Test circuit for improving test coverage rate and working method

Abstract

According to the test circuit and the working method for improving the test coverage rate, when DFT is carried out on a chip, under the condition that it is guaranteed that high-frequency clock domain logic at-speed fault and stack-at fault can be tested, the stack-at fault can be tested when a low-frequency logic circuit does not carry out at-speed test, and therefore the coverage rate of the whole chip stack-at test is improved. When the chip enters an at-speed test mode, a scan enable is used for controlling the second clock gating circuit, after the scan enable is pulled up, the scan enable is subjected to beat processing through the third register, the output clock of the second clock gating circuit is output for one cycle later, and the clock output is stopped when the scan enable is pulled down through the third AND gate.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a test circuit for improving test coverage, and a working method of the test circuit for improving test coverage. Background Art

[0002] The purpose of testing is to check for defects and faults generated during the chip manufacturing process. The core technology of DFT (Design For Test) is the design of the scan path. The basic principle is to convert the timing circuit that is not easy to test into a combinational circuit and a timing circuit with triggers that are easy to test. DFT will establish a corresponding fault model (Fault Model) based on the various faults generated during the chip manufacturing process. The most common fault models are stuck-at (static fault) and at-speed (high-speed fault). The stuck-at model is used to detect short circuits to ground or power caused by the manufacturing process, and the at-speed model is used to detect delays caused by the production process that cannot meet the timing requirements for implementing the function.

[0003] For stuck-at, during the period when scan_enable is low in the capture phase, one cycle of scan_clock is used for sampling and capture, and then in the load_unload phase, it is possible to observe whether there is an output that does not meet expectations on scan_out. For at-speed, it is necessary to be able to detect whether the delay information of the functional circuit meets the timing requirements of the function. During testing, the chip should be operated at the highest clock frequency. In the capture phase, two cycles of high-frequency clocks need to be generated, one as the launch clock and the other as the capture clock. If a fault exists, the capture clock will sample an unexpected result, which will be observed through scan_out in the load_unload phase.

[0004] When performing netlist-level DFT design, the EDA tools commonly used are Synopsys' DFT compiler or Mentor's Tessent. The solutions proposed by these two tools for at-speed testing are to insert OCC (On Chip Controller) logic circuits.

[0005] The basic principle of the OCC circuit is to select the low-speed scan_clock provided by ATE in the load_unload stage. In the capture stage, the functional clock generated by the on-chip PLL is selected for at-speed testing, and the low-speed scan_clock is still selected for stuck-at testing. When performing at-speed testing, the internal logic of the OCC will also control the generation of at least 2T functional clocks in the capture stage to meet the requirements of the launch clock and capture clock.

[0006] Generally speaking, there are multiple clock domains in a chip. Some of the internal clock frequencies are much higher than the scan clock frequency, and some are lower than the scan clock frequency. At-speed testing is to test the impact of the production environment on the path delay, resulting in the inability to observe the correct output results within the expected time. The logic circuits in the high-frequency clock domain are easily affected. At-speed testing of the low-frequency clock domain is relatively unimportant and may even increase the testing cost.

[0007] To complete the above two fault tests, the industry usually inserts an OCC circuit to switch between the two test modes through its internal logic, such as Figure 1 shown.

[0008] (i) When the OCC circuit is in at-speed test mode: scan_mode is high and pll_bypass is low (at_speed mode).

[0009] 1) In the load_unload phase, the scan_enable signal is in a high level state, the output of the OR gate U9 is high, the output of the OR gate U9 is connected to the S pin of the second dual selector U7, the scan_clock is output to the Y pin of the second dual selector U7 via the B pin of the second dual selector U7, the S pin of the third dual selector U8 is connected to the scan_mode, at this time the S pin of the third dual selector U8 is high level, the Y pin of the third dual selector U8 will output the scan_clock input from the Y pin of the second dual selector U7 to the B pin of the third dual selector U8; 2) In the capture phase, the scan_enable signal changes from high level to low level, and completes the synchronization of the scan_enable signal from the scan_clock to the function_clock clock domain through the first register U0 and the second register U1 to obtain a stable scan_enable low level state. After the cross-clock domain synchronization is completed, the scan_enable is inverted by the NOT gate U2 and output together with the Qn-1 output of the second register U1 to the first AND gate U3, and at the same time, it is given to the second AND gate U4 together with the Qn-2 output of the second register U1, and combined with the first dual-way selector U5. To realize the control of several cycles of the function_clock clock output of the first clock gating circuit U6, the output functional clock of the first clock gating circuit U6 passes through the second dual-way selector U7. At this time, the S pin of the second dual-way selector U7 is at a low level, so it is output from the A pin of the second dual-way selector U7 to the Y pin of the second dual-way selector U7. At this time, because it is still in the scan_mode state, the scan_mode is at a high level, so the Y pin of the third dual-way selector U8 comes from the B pin of the third dual-way selector U8, that is, the function_clock of several clocks through the first clock gating circuit U6.

[0010] (ii) When the OCC circuit is in stuck-at test mode: scan_mode is high level, pll_bypass is high level (stuck-at mode at this time). At this time, the output of the OR gate U9 is always high. Regardless of the load_unload stage or the capture stage, the second dual selector U7 will give the input of the B pin of the second dual selector U7 to the Y pin of the second dual selector U7. Because scan_mode is high, the output of the Y pin of the third dual selector U8 is always scan_clock.

[0011] For low-frequency logic in the chip, its operating frequency is even lower than scan_clock, so there is no need to insert OCC circuit to do at-speed test. If the clock of these low-frequency logic is not processed, all low-frequency logic will not be tracked and controlled by scan_clock in test mode, resulting in the stuck-at fault of this part of the circuit cannot be tested, thereby reducing the stuck-at test coverage of the entire chip.

[0012] If the low-frequency clock is processed in the conventional way of only doing stuck-at test on the whole chip, such as Figure 2As shown, the output pin Y of the second dual-way selector U10 will always output scan_clock in scan_mode. In this way, in the capture phase of the high-frequency logic at-speed test, because the scan_clock is always on, the low-frequency logic test in the capture phase has no OCC involved, and the cycle of scan_enable being pulled low is uncontrollable, resulting in unpredictable number of scan_clock cycles, and the tool will not be able to generate correct at-speed test stimulus. Summary of the invention

[0013] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a test circuit for improving test coverage, which can ensure that both at-speed fault and stuck-at fault of high-frequency clock domain logic can be tested when DFT is performed on the chip, so that stuck-at fault can be tested when low-frequency logic circuit is not subjected to at-speed test, thereby improving the stuck-at test coverage of the entire chip.

[0014] The technical solution of the present invention is: the test circuit for improving test coverage includes a third register U11, a third AND gate U12, a second clock gating circuit U13, and a fourth dual-way selector U14; During the static fault stuck-at test, the fourth dual-way selector is enabled to obtain a clock consistent with the scan clock scan_clock through the second clock gating circuit, and the second clock gating circuit is controlled to be in a transparent state through the stuck-at test mode signal pll_bypass high level, the scan mode scan_mode signal is high level, and the fourth dual-way selector outputs scan_clock to Function DFFs to obtain the expected scan_clock; When the chip enters the at-speed test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. The third AND gate is used to shut down the clock output when scan_enable is pulled low.

[0015] The beneficial technical effects of the present invention are as follows: 1. This circuit structure does not affect the insertion of the OCC circuit; 2. This circuit does not affect the output of the normal functional clock; 3. This circuit can ensure that scan_clock can be output with a delay of one cycle when scan_enable changes from low to high; 4. For low-frequency logic circuits that do not require at-speed testing, this circuit can be inserted to improve stuck-at related coverage.

[0016] A method for operating a test circuit for improving test coverage is also provided, comprising the following steps: (1) During the stuck-at test, the Y pin of the fourth dual selector obtains a clock consistent with scan_clock through the second clock gating circuit, and the EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state, and scan_clock reaches the B pin of the fourth dual selector through the second clock gating circuit. In the test mode, the scan_mode signal is high, and the fourth dual selector outputs scan_clock to the Function DFFs to obtain the expected scan_clock; (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low, the clock output is shut down through the third AND gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A structural schematic diagram of an OCC circuit is shown.

[0018] Figure 2 The clock selection circuit is shown for stuck-at testing only.

[0019] Figure 3 A schematic diagram of the structure of a circuit of a specific embodiment of a test circuit for improving test coverage according to the present invention is shown.

[0020] Figure 4 is with Figure 3 Matching timing diagrams of each signal. DETAILED DESCRIPTION

[0021] This test circuit for improving test coverage includes a third register U11, a third AND gate U12, a second clock gating circuit U13, and a fourth dual-way selector U14; During the static fault stuck-at test, the fourth dual-way selector is enabled to obtain a clock consistent with the scan clock scan_clock through the second clock gating circuit, and the second clock gating circuit is controlled to be in a transparent state through the stuck-at test mode signal pll_bypass high level, the scan mode scan_mode signal is high level, and the fourth dual-way selector outputs scan_clock to Function DFFs to obtain the expected scan_clock; When the chip enters the at-speed test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. The third AND gate is used to shut down the clock output when scan_enable is pulled low.

[0022] The beneficial technical effects of the present invention are as follows: 1. This circuit structure does not affect the insertion of the OCC circuit; 2. This circuit does not affect the output of the normal functional clock; 3. This circuit can ensure that scan_clock can be output with a delay of one cycle when scan_enable changes from low to high; 4. For low-frequency logic circuits that do not require at-speed testing, this circuit can be inserted to improve stuck-at related coverage.

[0023] Preferably, if Figure 3 As shown, scan_enable is connected to the D pin of the third register and is used as the input of the third AND gate together with the Q pin output of the third register. scan_clock is used as the input of the third register and is connected to the CK pin of the second clock gating circuit. The ECK pin of the second clock gating circuit is connected to the B pin of the fourth dual-way selector. The functional clock function_clock and scan_mode are respectively connected to the A pin and the S pin of the fourth dual-way selector. The Y pin of the fourth dual-way selector is connected to Function DFFs.

[0024] application Figure 3 The waveform of the low-frequency clock domain in at-speed test mode is as follows: Figure 4 shown.

[0025] A method for operating a test circuit for improving test coverage is also provided, comprising the following steps: (1) During the stuck-at test, the Y pin of the fourth dual selector obtains a clock consistent with scan_clock through the second clock gating circuit, and the EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state, and scan_clock reaches the B pin of the fourth dual selector through the second clock gating circuit. In the test mode, the scan_mode signal is high, and the fourth dual selector outputs scan_clock to the Function DFFs to obtain the expected scan_clock; (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low, the clock output is shut down through the third AND gate.

[0026] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A test circuit for improving test coverage, characterized in that: It includes a third register (U11), a third AND gate (U12), a second clock gating circuit (U13), and a fourth dual-way selector (U14); During the static fault stuck-at test, the fourth dual-way selector is enabled to obtain a clock consistent with the scan clock scan_clock through the second clock gating circuit, and the second clock gating circuit is controlled to be in a transparent state through the stuck-at test mode signal pll_bypass high level, the scan mode scan_mode signal is high level, and the fourth dual-way selector outputs scan_clock to the function register Function DFFs to obtain the expected scan_clock; When the chip enters the at-speed fault test mode, the scan enable scan_enable controls the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The second clock gating circuit outputs the clock one cycle later. The clock output is shut down when scan_enable is pulled low through the third AND gate.

2. The test circuit for improving test coverage according to claim 1, characterized in that: scan_enable is connected to the D pin of the third register and is used as the input of the third AND gate together with the Q pin output of the third register. scan_clock is used as the input of the third register and is connected to the CK pin of the second clock gating circuit. The ECK pin of the second clock gating circuit is connected to the B pin of the fourth dual-way selector. The functional clock function_clock and scan_mode are respectively connected to the A pin and S pin of the fourth dual-way selector. The Y pin of the fourth dual-way selector is connected to Function DFFs.

3. The working method of the test circuit for improving test coverage according to claim 2, characterized in that: It includes the following steps: (1) During the stuck-at test, the Y pin of the fourth dual selector obtains a clock consistent with scan_clock through the second clock gating circuit, and the EN pin of the second clock gating circuit is controlled by the high level of the stuck-at test mode signal pll_bypass. In the stuck-at mode, the second clock gating circuit is in a transparent state, and scan_clock reaches the B pin of the fourth dual selector through the second clock gating circuit. In the test mode, the scan_mode signal is high, and the fourth dual selector outputs scan_clock to the Function DFFs to obtain the expected scan_clock; (2) When the chip enters the at-speed test mode, scan_enable controls the SE pin of the second clock gating circuit. After scan_enable is pulled high, scan_enable is beat through the third register. The ECK pin of the second clock gating circuit outputs the clock one cycle later. When scan_enable is pulled low, the clock output is shut down through the third AND gate.

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