Satellite navigation baseband signal processing method and satellite navigation baseband signal processing device

Abstract

According to the satellite navigation baseband signal processing method and the satellite navigation baseband signal processing device provided by the invention, on the basis of the existing baseband signal processing device, the cache module and the system control module of the baseband signal processing device are improved, so that the acquisition and playback functions of baseband signals can be realized; therefore, the overall cost of the system is effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of satellite navigation technology, and in particular to a satellite navigation baseband signal processing method and a satellite navigation baseband signal processing device. Background Art

[0002] The Global Navigation Satellite System (GNSS) has played a key role in promoting the informatization of human society. The positioning, navigation, measurement and timing services it provides have penetrated into all walks of life and become a core component of the new generation of information technology. Especially in the field of intelligent transportation, the application of GNSS technology has realized functions such as vehicle positioning, anti-theft, anti-hijacking, driving route monitoring and call command.

[0003] GNSS receiver is a key device for receiving GNSS satellite signals and determining ground position. Its core component is a multi-mode multi-system satellite navigation SoC chip. The chip usually includes components such as radio frequency (RF) front-end circuit, baseband processor, microprocessor and SoC peripherals. The RF front-end is responsible for receiving the RF signal from the navigation satellite and performing low-noise amplification, power amplification, down-conversion, filtering, gain control and analog-to-digital conversion (ADC) processing. The baseband processor is responsible for processing the intermediate frequency digital signal of satellite navigation, including mixing, low-pass filtering, downsampling, multi-tone interference elimination, GNSS signal capture and tracking and other tasks. The microprocessor works with the baseband processor to complete the navigation positioning solution, while the SoC peripherals are responsible for realizing the external interface function.

[0004] However, the satellite navigation signal acquisition and playback equipment currently on the market is relatively expensive. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a satellite navigation baseband signal processing method and a satellite navigation baseband signal processing device to solve the problem of high cost of satellite navigation signal acquisition and playback equipment on the market.

[0006] A satellite navigation baseband signal processing method provided in an embodiment of the present application is applied to a satellite navigation baseband signal processing device, wherein the satellite navigation baseband signal processing device comprises: a preprocessing module, a cache module, a channel processing module, a system control module and a processor; the preprocessing module, the cache module and the channel processing module are connected in sequence, the preprocessing module, the cache module and the channel processing module are all connected to the system control module, and the system control module is connected to the processor;

[0007] Methods include:

[0008] The processor receives an instruction to enter the acquisition mode and configures the system control module to enter the acquisition mode;

[0009] The system control module sets the valid flag of the cache module to invalid, and configures the preprocessing module and the cache module to start collecting data;

[0010] The pre-processing module performs digital down-conversion, down-sampling and re-quantization on the intermediate frequency signal output by the radio frequency device to obtain processed data;

[0011] The cache module fills data into the first cache; after the first cache is filled, the system control module sets the valid flag of the first cache to valid, and the system control module initiates an interrupt to complete the collection of the first cache; then, the collection of the next cache is performed.

[0012] In the above technical solution, on the basis of the existing baseband signal processing device, the cache module and the system control module of the baseband signal processing device are improved, so that the acquisition function of the baseband signal can be realized, thereby effectively reducing the overall cost of the system. Specifically, after receiving the instruction to start the acquisition mode, the processor will configure the system control module to enter the acquisition mode. At this time, the system control module will set the valid flag of the cache module to invalid, and configure the preprocessing module and the cache module to start signal acquisition. The preprocessing module will perform digital down-conversion, downsampling and re-quantization processing on the intermediate frequency signal output by the radio frequency device to obtain data suitable for subsequent processing. The cache module will fill the processed data into the first cache, and in this process, the system control module will keep the valid flag of the first cache in an invalid state. When the first cache is completely filled, the system control module will set its valid flag to valid and trigger an interrupt, indicating that the acquisition work of the first cache is completed. Subsequently, the system will start the acquisition of the next cache according to the same process.

[0013] In some optional implementations, each time the collection of a cache is completed, the processor may start to read the data of the cache and transmit it back to the host computer.

[0014] In the above technical solution, at the same time, only one cache collects data, and other caches that have completed data collection transmit the cached data back to the host computer through the system control module and the processor.

[0015] In some optional implementations, after the cached data is transmitted back to the host computer, the system control module sets the valid flag of the cache to invalid, and the cache continues to be filled with data output by the preprocessing module.

[0016] In the above technical solution, when the cached data is successfully transmitted back to the host computer, the system control module will immediately reset the valid flag of the cache to an invalid state. This step indicates that the cache is ready to receive and store new data from the preprocessing module again. Subsequently, the preprocessing module will continue to fill the processed data it outputs into the cache that has been cleared and set to invalid, preparing for the next round of data collection. Such a design ensures the continuity and efficiency of the data collection and transmission process, and improves the operating efficiency of the entire satellite navigation baseband signal processing system.

[0017] In some optional embodiments, it also includes:

[0018] The processor receives an instruction to enter the playback mode and configures the system control module to enter the playback mode;

[0019] The processor receives the data to be played back and writes the data into each cache of the cache module in sequence;

[0020] The first data of the first buffer of the buffer module is output to the channel processing module for processing, and the first data is played back; after the playback of the first data is completed, the next buffer data is played back.

[0021] In the above technical solution, on the basis of the existing baseband signal processing device, the cache module and the system control module of the baseband signal processing device are improved, so that the playback function of the baseband signal can be realized, thereby effectively reducing the overall cost of the system. Specifically, when the processor receives an instruction to enter the playback mode, it will configure the system control module to switch to the playback mode. At this time, the processor will receive the data to be played back, and write these data into each cache of the cache module in sequence. In the playback mode, the first data in the first cache of the cache module will first be processed by the channel processing module, and then the processing result will be output to realize the playback of the first data. When the playback of the first data is completed, the system will automatically play back the data in the next cache until all the data to be played back have been processed.

[0022] In some optional implementations, each time playback of cached data is completed, the processor requests a host computer to fill the cache with new data.

[0023] In the above technical solution, in order to further optimize the data playback and processing flow, every time the data playback of a cache is completed, the processor will actively send a request to the host computer to apply for new data to fill the vacated cache, ensuring the continuity and real-time nature of the data. By applying for and filling new data in a timely manner, the system can maintain an uninterrupted data processing flow and avoid processing interruptions caused by data shortages. By dynamically managing the data in the cache, the system can ensure that each cache is fully utilized and avoid waste of resources.

[0024] In some optional implementations, during playback, the processor polls the valid flag of each cache in turn, and fills new data into the caches whose valid flags are invalid.

[0025] In some optional implementations, when the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor applies to the host computer for new data that is smaller than the capacity of the cache module to be filled into the cache module;

[0026] Or, when the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor requests the host computer to fill new data into the cache module; during the process of filling new data, when the processor receives an interrupt signal indicating that the entire cache module is about to be full, the processor stops requesting new data from the host computer to fill the cache module.

[0027] A satellite navigation baseband signal processing device provided in an embodiment of the present application includes: a preprocessing module, a cache module, a channel processing module, a system control module and a processor; the preprocessing module, the cache module and the channel processing module are connected in sequence, the preprocessing module, the cache module and the channel processing module are all connected to the system control module, and the system control module is connected to the processor.

[0028] In the above technical solution, the satellite navigation baseband signal processing device is based on the existing baseband signal processing device, and improves the cache module and system control module of the baseband signal processing device, thereby realizing the baseband signal acquisition function and effectively reducing the overall cost of the system. Specifically, the satellite navigation baseband signal processing device includes:

[0029] Preprocessing module: responsible for digital down-conversion, down-sampling and re-quantization of the intermediate frequency signal output by the RF device to obtain data suitable for subsequent processing.

[0030] Cache module: stores the data output by the preprocessing module or the data sent by the host computer as the data source for the channel processing module.

[0031] Channel processing module: In playback mode, it is responsible for processing and outputting the data in the buffer, which may include steps such as signal demodulation and decoding.

[0032] System control module: responsible for coordinating the work between various modules. It receives instructions from the processor, configures the device to enter acquisition or playback mode, and monitors the valid flag status of the cache to control the flow of data.

[0033] Processor: As the brain of the device, the processor is responsible for receiving instructions, configuring system control modules, reading cached data, and performing necessary calculations and processing.

[0034] In some optional implementations, the cache module of the satellite navigation baseband signal processing device includes at least two caches; each cache is set with a valid flag.

[0035] In the above technical solution, the cache module is composed of at least two caches, and each cache is provided with a valid flag. This valid flag is used to indicate whether the data in the cache is valid or has been processed. In the acquisition mode, when the cache is filled with data, the system control module sets the valid flag of the cache to valid, indicating that the data in the cache is ready to be processed or transmitted. In the playback mode, when the processor fills the cache with playback data, the system control module sets the valid flag of the cache to valid, indicating that the cache is ready to play back data. When a cached data is completely read or played back, it will be immediately cleared and set to an invalid state, and then ready to receive the next round of data.

[0036] In some optional implementations, the system control module of the satellite navigation baseband signal processing device includes a register for a mode word indicating an acquisition mode or a playback mode.

[0037] In the above technical solution, the system control module of the satellite navigation baseband signal processing device includes a register of a mode word for indicating the current working mode (acquisition mode or playback mode). The value in the mode word register directly reflects whether the satellite navigation baseband signal processing device is currently in acquisition mode or playback mode. This information is crucial for the system control module because it needs to configure the working status of other modules (such as cache module, etc.) according to the current working mode. In the acquisition mode, the system control module will ensure that the data flows correctly from the preprocessing module to the cache module according to the instructions of the mode word register, and trigger the operation of transmitting the data to the host computer when the cache is full. In the playback mode, the system control module will control the playback process of the data to ensure that the data first enters the cache module from the system control module and then flows into the channel processing module for processing.

[0038] In some optional implementations, the system control module includes an acquisition interrupt flag register and a playback interrupt flag register.

[0039] In the above technical solution, the acquisition interrupt flag register generates an interrupt when the cache is full; the playback interrupt flag register generates an interrupt signal when all buffers of the cache module are about to be empty or empty, or generates different interrupt signals when all buffers of the cache module are about to be full and about to be empty or empty.

[0040] Specifically, the main function of the acquisition interrupt flag register is to generate an interrupt signal when the cache is full. When the data output by the preprocessing module is continuously filled into the cache, the system control module will monitor the filling status of the cache in real time. Once the filling amount of the cache reaches the cache capacity (that is, when the cache is full), the acquisition interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will be received by the processor, and the processor will immediately start the data transmission process, transferring the data from the cache to the host computer, and the system control module will switch to another cache to continue collecting data.

[0041] The playback interrupt flag register is responsible for generating an interrupt signal when all the caches in the cache module are about to be empty or have been empty. In playback mode, the data in the cache will be read in sequence and sent to the channel processing module for processing. When the amount of data in all the caches in the cache module is reduced to a preset threshold (i.e., the cache is about to be empty), or the data in all the caches in the cache module has been completely read, the playback interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will also be received by the processor, and the processor can continue to fill the cache module with playback data, or if all the cached data has been played back, it may end the playback mode and switch to other working modes.

[0042] The playback interrupt flag register can also generate an interrupt signal when all the caches of the cache module are about to be full. When the data transmitted by the host computer is continuously filled into the cache through the processor, the system control module will monitor the filling status of the cache in real time. Once the filling amount of all the caches of the cache module reaches the preset threshold (that is, the cache is about to be full), the playback interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will be received by the processor, and the processor will immediately stop writing data to all the caches of the cache module. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A satellite navigation baseband signal processing device provided in an embodiment of the present application;

[0045] Figure 2 A flowchart of a method for collecting satellite navigation baseband signals provided in an embodiment of the present application;

[0046] Figure 3A flowchart of the steps of a satellite navigation baseband signal playback method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0048] Please refer to Figure 1 , Figure 1 A satellite navigation baseband signal processing device is provided in an embodiment of the present application. The satellite navigation baseband signal processing device includes: a preprocessing module, a cache module, a channel processing module, a system control module and a processor; the preprocessing module, the cache module and the channel processing module are connected in sequence, the preprocessing module, the cache module and the channel processing module are all connected to the system control module, and the system control module is connected to the processor.

[0049] Please refer to Figure 2 , Figure 2 A flowchart of a method for collecting satellite navigation baseband signals provided in an embodiment of the present application specifically includes:

[0050] Step S1, the processor receives an instruction to enter the acquisition mode, and configures the system control module to enter the acquisition mode;

[0051] Step S2: the system control module sets the valid flag of the cache module to invalid, and configures the preprocessing module and the cache module to start collecting data;

[0052] Step S3, the preprocessing module performs digital down-conversion, down-sampling and re-quantization on the intermediate frequency signal output by the radio frequency device to obtain processed data;

[0053] Step S4, the cache module fills the data into the first cache; after the first cache is filled, the system control module sets the valid flag of the first cache to valid, and the system control module initiates an interrupt to complete the collection of the first cache; then, the collection of the next cache is performed.

[0054] The cache includes storage media such as register files, FIFO (First In First Out), single-port SRAM (Static Random Access Memory), pseudo dual-port SRAM and true dual-port SRAM.

[0055] In the embodiment of the present application, on the basis of the existing baseband signal processing device, the cache module and the system control module of the baseband signal processing device are improved, so that the acquisition function of the baseband signal can be realized, thereby effectively reducing the overall cost of the system. Specifically, after receiving the instruction to start the acquisition mode, the processor will configure the system control module to enter the acquisition mode. At this time, the system control module will set the valid flag of the cache module to invalid, and configure the preprocessing module and the cache module to start signal acquisition. The preprocessing module will perform digital down-conversion, downsampling and requantization processing on the intermediate frequency signal output by the radio frequency device to obtain data suitable for subsequent processing. The cache module will fill the processed data into the first cache. During this process, the system control module will keep the valid flag of the first cache in an invalid state. When the first cache is completely filled, the system control module will set its valid flag to valid and trigger an interrupt, indicating that the acquisition work of the first cache is completed. Subsequently, the system will start the acquisition of the next cache according to the same process. Until the acquisition work of the last cache is completed, the data in the first cache has been uploaded to the host computer, and the system will restart the acquisition work of the first cache.

[0056] In some optional implementations, each time the collection of a cache is completed, the processor may start to read the data of the cache and transmit it back to the host computer.

[0057] The host computer and the processor are connected via protocols, including but not limited to USB (Universal Serial Bus) protocol, UART (Universal Asynchronous Receiver / Transmitter) serial port protocol, Ethernet protocol, etc.

[0058] In the embodiment of the present application, at the same time, only one cache is collecting data, and other caches that have completed data collection transmit the cached data back to the host computer through the system control module and the processor.

[0059] In some optional implementations, after the cached data is transmitted back to the host computer, the system control module sets the valid flag of the cache to invalid, and the cache continues to be filled with data output by the preprocessing module.

[0060] In the embodiment of the present application, when the cached data is successfully transmitted back to the host computer, the system control module will immediately reset the valid flag of the cache to an invalid state. This step indicates that the cache is ready to receive and store new data from the preprocessing module again. Subsequently, the preprocessing module will continue to fill the processed data it outputs into the cache that has been cleared and set to invalid, preparing for the next round of data collection. Such a design ensures the continuity and efficiency of the data collection and transmission process, and improves the operating efficiency of the entire satellite navigation baseband signal processing system.

[0061] Please refer to Figure 3 , Figure 3 A flowchart of a satellite navigation baseband signal playback method provided in an embodiment of the present application specifically includes:

[0062] Step S5: the processor receives an instruction to enter the playback mode and configures the system control module to enter the playback mode;

[0063] Step S6: The processor receives the data to be played back, and writes the data into each cache of the cache module in sequence;

[0064] Step S7: the first data of the first buffer of the buffer module is output to the channel processing module for processing, and the first data is played back; after the playback of the first data is completed, the next buffer data is played back.

[0065] In an embodiment of the present application, on the basis of the existing baseband signal processing device, the cache module and the system control module of the baseband signal processing device are improved, so that the playback function of the baseband signal can be realized, thereby effectively reducing the overall cost of the system. Specifically, when the processor receives an instruction to enter the playback mode, it will configure the system control module to switch to the playback mode. At this time, the processor will receive the data to be played back, and write these data into each cache of the cache module in sequence. In the playback mode, the first data in the first cache of the cache module will first be processed by the channel processing module, and then the processing result will be output to realize the playback of the first data. When the playback of the first data is completed, the system will automatically play back the data in the next cache until all the data to be played back have been processed.

[0066] In some optional implementations, during playback, the processor polls the valid flag of each cache in turn, and fills new data into the caches whose valid flags are invalid.

[0067] In some optional implementations, when the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor applies to the host computer for new data that is smaller than the capacity of the cache module to be filled into the cache module;

[0068] Or, when the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor requests the host computer to fill new data into the cache module; during the process of filling new data, when the processor receives an interrupt signal indicating that the entire cache module is about to be full, the processor stops requesting new data from the host computer to fill the cache module.

[0069] In this embodiment, by polling the playback interrupt flag register or receiving an interrupt signal, the processor can accurately determine whether the playback of a cached data is completed, thereby ensuring the continuity and accuracy of the data processing flow.

[0070] Finally, the host computer device can also determine whether the playback task is completed based on the user's stop command, configuration information or data information.

[0071] An embodiment of the present application provides a satellite navigation baseband signal processing device, which is used to implement any of the above methods.

[0072] In the embodiment of the present application, the satellite navigation baseband signal processing device is based on the existing baseband signal processing device, and improves the cache module and system control module of the baseband signal processing device, thereby realizing the baseband signal acquisition function, effectively reducing the overall cost of the system. Specifically, the satellite navigation baseband signal processing device includes:

[0073] Preprocessing module: responsible for digital down-conversion, down-sampling and re-quantization of the intermediate frequency signal output by the RF device to obtain data suitable for subsequent processing.

[0074] Cache module: stores the data output by the preprocessing module or the data sent by the host computer as the data source for the channel processing module.

[0075] Channel processing module: In playback mode, it is responsible for processing and outputting the data in the buffer, which may include steps such as signal demodulation and decoding.

[0076] System control module: responsible for coordinating the work between various modules. It receives instructions from the processor, configures the device to enter acquisition or playback mode, and monitors the valid flag status of the cache to control the flow of data.

[0077] Processor: As the brain of the device, the processor is responsible for receiving instructions, configuring system control modules, reading cached data, and performing necessary calculations and processing.

[0078] In some optional implementations, the cache module of the satellite navigation baseband signal processing device includes at least two caches; each cache is set with a valid flag.

[0079] In an embodiment of the present application, the cache module is composed of at least two caches, each of which is provided with a valid flag. This valid flag is used to indicate whether the data in the cache is valid or has been processed. In acquisition mode, when the cache is filled with data, the system control module sets the valid flag of the cache to valid, indicating that the data in the cache is ready to be processed or transmitted. In playback mode, when the processor fills the cache with playback data, the system control module sets the valid flag of the cache to valid, indicating that the cache is ready to replay data. When a cached data is completely read or played back, it will be immediately cleared and set to an invalid state, and then ready to receive the next round of data.

[0080] In some optional implementations, the system control module of the satellite navigation baseband signal processing device includes a register for a mode word indicating an acquisition mode or a playback mode.

[0081] In an embodiment of the present application, the system control module of the satellite navigation baseband signal processing device includes a register of a mode word for indicating the current working mode (acquisition mode or playback mode). The value in the mode word register directly reflects whether the satellite navigation baseband signal processing device is currently in acquisition mode or playback mode. This information is crucial for the system control module because it needs to configure the working status of other modules (such as cache modules, etc.) according to the current working mode. In the acquisition mode, the system control module will ensure that the data flows correctly from the preprocessing module to the cache module according to the instructions of the mode word register, and trigger the operation of transferring data to the host computer when the cache is full. In the playback mode, the system control module will control the playback process of the data to ensure that the data first enters the cache module from the system control module and then flows into the channel processing module for processing.

[0082] In some optional implementations, the system control module includes an acquisition interrupt flag register and a playback interrupt flag register.

[0083] In an embodiment of the present application, the acquisition interrupt flag register generates an interrupt when the cache is full; the playback interrupt flag register generates an interrupt signal when all buffers of the cache module are about to be empty or are empty, or generates different interrupt signals when all buffers of the cache module are about to be full and are about to be empty or are empty.

[0084] Specifically, the main function of the acquisition interrupt flag register is to generate an interrupt signal when the cache is full. When the data output by the preprocessing module is continuously filled into the cache, the system control module will monitor the filling status of the cache in real time. Once the filling amount of the cache reaches the cache capacity (that is, when the cache is full), the acquisition interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will be received by the processor, and the processor will immediately start the data transmission process, transferring the data from the cache to the host computer, and the system control module will switch to another cache to continue collecting data.

[0085] The playback interrupt flag register is responsible for generating an interrupt signal when all the caches in the cache module are about to be empty or have been empty. In playback mode, the data in the cache will be read in sequence and sent to the channel processing module for processing. When the amount of data in all the caches in the cache module is reduced to a preset threshold (i.e., the cache is about to be empty), or the data in all the caches in the cache module has been completely read, the playback interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will also be received by the processor, and the processor can continue to fill the cache module with playback data, or if all the cached data has been played back, it may end the playback mode and switch to other working modes.

[0086] The playback interrupt flag register can also generate an interrupt signal when all the caches of the cache module are about to be full. When the data transmitted by the host computer is continuously filled into the cache through the processor, the system control module will monitor the filling status of the cache in real time. Once the filling amount of all the caches of the cache module reaches the preset threshold (that is, the cache is about to be full), the playback interrupt flag register will be triggered and an interrupt signal will be generated. This interrupt signal will be received by the processor, and the processor will immediately stop writing data to all the caches of the cache module.

[0087] The embodiment of the present application is to transform the baseband signal processing device to realize the acquisition function, specifically including: if the original cache in the cache module has only 1 block, it is split into 2 blocks or more; if the original cache is greater than or equal to 2 blocks, the status quo is maintained. Add a register in the system control module to represent the mode words: acquisition mode, playback mode. In the cache module or the system control module, add a valid flag for the acquired data, and set a valid flag for each cache. The cache that is currently being filled with data or the cache that is not filled with data is marked as invalid, and the buffer that has been filled with data is marked as valid. Add an acquisition interrupt flag register in the system control module and connect it to the system interrupt module. Every time the acquisition of a cache is completed, the interrupt is pulled up once.

[0088] The embodiment of the present application is to transform the baseband signal processing device to realize the playback function, specifically including: if the original cache in the cache module has only 1 block, it is split into 2 blocks or more; if the original cache is greater than or equal to 2 blocks, the status quo is maintained. Add a register in the system control module to represent the mode words: acquisition mode, playback mode. In the system control module, the cache of the cache module is added to the address space accessible to the bus to participate in address decoding, and the cache write pointer and read pointer are maintained in the cache module according to the playback mode. Add a playback interrupt flag register in the system control module, and connect to the system interrupt module to add a playback interrupt. When the cache is about to be full, about to be empty, or is empty, an interrupt is initiated.

[0089] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0090] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0091] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0092] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0093] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A satellite navigation baseband signal processing method, characterized in that: Applicable to a satellite navigation baseband signal processing device, the satellite navigation baseband signal processing device comprises: a preprocessing module, a cache module, a channel processing module, a system control module and a processor; the preprocessing module, the cache module and the channel processing module are connected in sequence, the preprocessing module, the cache module and the channel processing module are all connected to the system control module, and the system control module is connected to the processor; The method comprises: The processor receives an instruction to enter a collection mode, and configures the system control module to enter the collection mode; The system control module sets the valid flag of the cache module to invalid, and configures the preprocessing module and the cache module to start acquisition; The preprocessing module performs digital down-conversion, down-sampling and re-quantization on the intermediate frequency signal output by the radio frequency device to obtain processed data; The cache module fills data into the first cache; after the first cache is filled, the system control module sets the valid flag of the first cache to valid, and the system control module initiates an interrupt to complete the collection of the first cache; then, the collection of the next cache is performed.

2. The method according to claim 1, characterized in that Each time the acquisition of a cache is completed, the processor may start to read the data of the cache and transmit it back to the host computer.

3. The method according to claim 2, characterized in that After the cached data is transmitted back to the host computer, the system control module sets the valid flag of the cache to invalid, and the cache continues to be filled with the data output by the preprocessing module.

4. The method according to claim 1, characterized in that Also includes: The processor receives an instruction to enter the playback mode, and configures the system control module to enter the playback mode; The processor receives the data to be played back, and writes the data into each cache of the cache module in sequence; The first data of the first buffer of the buffer module is output to the channel processing module for processing, and the first data is played back; after the playback of the first data is completed, the next buffer data is played back.

5. The method according to claim 4, characterized in that During playback, the processor polls the valid flag of each cache in turn, and fills new data into the cache whose valid flag is invalid.

6. The method according to claim 4, characterized in that When the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor applies to the upper computer for new data that is smaller than the capacity of the cache module to be filled into the cache module; Or, when the processor receives an interrupt signal indicating that the entire cache module is about to be empty or is empty, the processor applies to the host computer for new data to be filled into the cache module; during the process of filling new data, when the processor receives an interrupt signal indicating that the entire cache module is about to be full, the processor stops applying to the host computer for new data to be filled into the cache module.

7. A satellite navigation baseband signal processing device, characterized in that: include: Preprocessing module, cache module, channel processing module, system control module and processor; The preprocessing module, the cache module and the channel processing module are connected in sequence, and the preprocessing module, the cache module and the channel processing module are all connected to the system control module, and the system control module is connected to the processor.

8. The device according to claim 7, characterized in that The cache module of the satellite navigation baseband signal processing device includes at least two caches; each cache is set with a valid flag.

9. The device according to claim 7, characterized in that The system control module of the satellite navigation baseband signal processing device includes a register for a mode word indicating an acquisition mode or a playback mode.

10. The device according to claim 7, characterized in that The system control module includes an acquisition interrupt flag register and a playback interrupt flag register.

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