Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to improve the display uniformity. A fan-out area of the display panel comprises a first area, a second area and a third area. The display panel comprises a substrate, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are stacked on the substrate, and the resistivity of a material of the first conductive layer is larger than that of a material of the second conductive layer. The first conductive layer comprises a first data fan-out line arranged in the first area and a sixth data fan-out line arranged in the third area; the second conducting layer comprises a fourth data fan-out line arranged in the first area, a second data fan-out line and a fifth data fan-out line which are arranged in the second area, and a third data fan-out line arranged in the third area, and the first data fan-out line, the second data fan-out line and the third data fan-out line are connected in sequence; and the fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line are connected in sequence. The display panel can be used for displaying pictures.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel of a liquid crystal display (LCD), in order to narrow the border width, the data fan-out lines in the fan-out area of ​​the display panel are wired in an interleaved manner (Interleave), that is, the material of each data fan-out line is composed of low-resistivity material accounting for one-half and high-resistivity material accounting for one-half.

[0003] However, when the data fan-out lines on both sides of the fan-out area extend to the far end of the IC, the data line impedance (Source Loading) is too large and the impedance difference between adjacent data fan-out lines is also large, thereby affecting the display uniformity of the display panel located at the far end of the IC. Summary of the invention

[0004] The present application provides a display panel and a display device, aiming to improve display uniformity.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, a display panel is provided, which includes a display area and a fan-out area located on one side of the display area. The fan-out area includes a first wiring area and a second wiring area arranged along a first direction, the fan-out area includes a boundary close to the display area, and the first direction is parallel to the boundary. The second wiring area includes a first area, a second area, and a third area arranged in sequence along a second direction, the second direction intersects with the first direction, and the first area is closer to the display area than the third area. The display panel includes a substrate, and a first conductive layer and a second conductive layer stacked on the substrate, and the resistivity of the material of the first conductive layer is greater than the resistivity of the material of the second conductive layer. The first conductive layer includes a first data fan-out line arranged in the first area, the second conductive layer includes a second data fan-out line arranged in the second area, and a third data fan-out line arranged in the third area, and the first data fan-out line, the second data fan-out line and the third data fan-out line are connected in sequence. The second conductive layer also includes a fourth data fan-out line arranged in the first area, and a fifth data fan-out line arranged in the second area, and the first conductive layer also includes a sixth data fan-out line arranged in the third area, and the fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line are connected in sequence.

[0007] In an embodiment of the present application, the display panel includes a display area and a fan-out area located on one side of the display area, the fan-out area includes a boundary of the display area, and the fan-out area also includes a first wiring area and a second wiring area arranged along a first direction parallel to the boundary. Along a second direction intersecting the first direction, a first area, a second area, and a third area of ​​the second wiring area are sequentially arranged outside the display area. The display panel also includes a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate, and the resistivity of the material of the first conductive layer is greater than the resistivity of the material of the second conductive layer.

[0008] The first conductive layer includes a first data fan-out line arranged in the first area, the second conductive layer includes a second data fan-out line arranged in the second area, and a third data fan-out line arranged in the third area, and the first data fan-out line, the second data fan-out line and the third data fan-out line are sequentially connected to form a second fan-out line. It can be understood that the second fan-out line includes three sections, one of which uses a first conductive layer with a higher impedance, and the other two sections use a second conductive layer with a lower impedance. The proportion of low-impedance conductive layer materials in the second fan-out line is relatively high, and the resistance of the second fan-out line is relatively low, which is conducive to reducing the resistance of the data line connected to the second fan-out line, thereby reducing the load of the routing.

[0009] The second conductive layer also includes a fourth data fan-out line arranged in the first area, and a fifth data fan-out line arranged in the second area. The first conductive layer also includes a sixth data fan-out line arranged in the third area. The fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line are sequentially connected to form a first fan-out line. It can be understood that the first fan-out line includes three sections, one of which uses a first conductive layer with a higher impedance, and the other two sections use a second conductive layer with a lower impedance. The proportion of low-impedance conductive layer materials in the first fan-out line is relatively high, and the resistance of the first fan-out line is relatively low, which is conducive to reducing the resistance of the data line connected to the first fan-out line, thereby reducing the load of the routing.

[0010] Furthermore, in the first fan-out line and the second fan-out line, each fan-out line includes a section of the line located in the first conductive layer and two sections of the line located in the second conductive layer, so the resistance values ​​of the first fan-out line and the second fan-out line are also close, and the loads of the first fan-out line and the second fan-out line are close. When the first fan-out line and the second fan-out line are adjacent to each other, the data signal transmitted through the first fan-out line and the second fan-out line is transmitted to the pixels at the far end of the display area (the side of the display area away from the fan-out area), which can improve the uneven display phenomenon at the far end of the display area.

[0011] In some embodiments, the orthographic projection of the first data fan-out line on the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line on the substrate. The orthographic projection of the third data fan-out line on the substrate at least partially overlaps with the orthographic projection of the sixth data fan-out line on the substrate.

[0012] In some embodiments, the first conductive layer is a light shielding layer, and the second conductive layer is a gate conductive layer.

[0013] In some embodiments, the display panel further includes a first insulating layer disposed between the first conductive layer and the second conductive layer. The second data fan-out line penetrates the first insulating layer and is connected to the first data fan-out line. The fifth data fan-out line penetrates the first insulating layer and is connected to the sixth data fan-out line.

[0014] In some embodiments, the display panel includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a source-drain conductive layer stacked in sequence, and the source-drain conductive layer includes a first connecting electrode and a second connecting electrode. The first connecting electrode penetrates the second insulating layer and the first insulating layer to be connected to the first data fan-out line, and penetrates the second insulating layer to be connected to the second data fan-out line. The second connecting electrode penetrates the second insulating layer to be connected to the fifth data fan-out line, and penetrates the second insulating layer and the first insulating layer to be connected to the sixth data fan-out line.

[0015] In some embodiments, the source-drain conductive layer further includes a touch signal line, and an orthographic projection of the touch signal line on the substrate does not overlap with an orthographic projection of the first connection electrode on the substrate, and does not overlap with an orthographic projection of the second connection electrode on the substrate.

[0016] In some embodiments, the first conductive layer is a gate conductive layer, and the second conductive layer is a source-drain conductive layer.

[0017] In some embodiments, the display panel further includes a third insulating layer disposed between the first conductive layer and the second conductive layer. The second data fan-out line penetrates the third insulating layer and is connected to the first data fan-out line. The fifth data fan-out line penetrates the third insulating layer and is connected to the sixth data fan-out line.

[0018] In some embodiments, the display panel further includes a plurality of data lines disposed in the display area, and the plurality of data lines are arranged in sequence along the first direction. The plurality of data lines include adjacent first data lines and second data lines, the first data lines are sequentially connected to the first data fan-out lines, the second data fan-out lines, and the third data fan-out lines, and the second data lines are sequentially connected to the fourth data fan-out lines, the fifth data fan-out lines, and the sixth data fan-out lines. The difference between the sum of the resistances of the first data fan-out lines, the second data fan-out lines, and the third data fan-out lines and the sum of the resistances of the fourth data fan-out lines, the fifth data fan-out lines, and the sixth data fan-out lines is less than or equal to 20Ω.

[0019] In some embodiments, the first wiring area includes a fourth area and a fifth area arranged along the second direction, and the fourth area is closer to the display area than the fifth area;

[0020] The first conductive layer further includes a seventh data fan-out line disposed in the fourth region, the second conductive layer further includes an eighth data fan-out line disposed in the fifth region, and the seventh data fan-out line is connected to the eighth data fan-out line. The second conductive layer further includes a ninth data fan-out line disposed in the fourth region, the first conductive layer further includes a tenth data fan-out line disposed in the fifth region, and the ninth data fan-out line is connected to the tenth data fan-out line. The orthographic projection of the seventh data fan-out line on the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line on the substrate. The orthographic projection of the eighth data fan-out line on the substrate at least partially overlaps with the orthographic projection of the tenth data fan-out line on the substrate.

[0021] In some embodiments, the fan-out region includes a first wiring region and two second wiring regions. Along the first direction, the two second wiring regions are disposed on opposite sides of the first wiring region.

[0022] On the other hand, a display device is provided. The display device includes the display panel in any one of the above embodiments, and a controller electrically connected to the display panel.

[0023] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0025] Figure 1 A structural diagram of a display device provided in an embodiment of the present application;

[0026] Figure 2 for Figure 1 A local enlarged view of multiple routing lines in the second wiring area;

[0027] Figure 3 for Figure 1 A partial enlarged view of multiple routing lines in the first wiring area;

[0028] Figure 4 for Figure 1 A partial enlarged view of the second wiring area in FIG.

[0029] Figures 5 to 8 They are Figure 4 A partial enlarged view of the second wiring area in area A to area D;

[0030] Fig. 9 for Figure 5 A partial cross-sectional view of a jumper along section line PP';

[0031] Fig.10 for Figure 7 A partial cross-sectional view of a jumper along section line QQ';

[0032] Fig.11 A partial enlarged view of another second wiring area provided in an embodiment of the present application;

[0033] Fig.12 for Fig.11 A partial cross-sectional view of another jumper along the section line PP';

[0034] Fig.13 for Fig.11 A partial cross-sectional view of another jumper along the section line QQ';

[0035] Fig.14 is a partial cross-sectional view of another jumper along section line PP';

[0036] Fig.15 is a partial cross-sectional view of another jumper along section line QQ';

[0037] Fig.16 for Figure 1 A partial enlarged view of part of the wiring of the display panel at position N. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0042] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0043] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0044] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0045] An embodiment of the present application provides a display device, which may be a liquid crystal display (LCD). Figure 1 A structural diagram of a display device provided in an embodiment of the present application.

[0046] See also Figure 1 The display device 100 includes a display panel 10 and a controller 20 electrically connected to the display panel 10. The controller 20 may be disposed on a non-display side of the display panel 10 to control the display panel 10 to display a picture.

[0047] The display device 100 described above may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether textual or electronic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, aesthetic structures (e.g., displays of images of a piece of jewelry), laptop computers, and touch panel computers (TPCs), etc.

[0048] Continue to see Figure 1 The display panel 10 provided in the present application includes a display area (Active Area, AA) 11, and a fan-out area (fanout) 12 located on one side of the display area 11, for example, the fan-out area 12 is located below the display area 11, corresponding to the lower frame of the display device 100. The display panel 10 also includes a source driver circuit (source IC) 30 arranged in the fan-out area 12, and the source driver circuit 30 is used to transmit a data signal (data) to the display panel 10, so as to control the image display of the display panel 10. Exemplarily, the display panel 10 provided in the present application can be a display panel with touch and display driver integration (Touch and Display Driver Integration, TDDI), or it can also be a common display panel without touch.

[0049] The fan-out region 12 includes a boundary 120 close to the display region 11 , the first direction X is parallel to the boundary 120 , and the fan-out region 12 includes a first wiring region 1 and a second wiring region 2 arranged along the first direction X.

[0050] For example, see Figure 1 The fan-out region 12 includes a first wiring region 1 and two second wiring regions 2. Along the first direction X, the two second wiring regions 2 are arranged on opposite sides of the first wiring region 1.

[0051] Figure 2 for Figure 1 A local enlarged view of multiple routing lines in the second wiring area.

[0052] See also Figure 2The second wiring area 2 includes a first area 21, a second area 22, and a third area 23 arranged in sequence along a second direction Y. The second direction Y intersects with the first direction X. In the embodiment of the present application, the second direction Y is perpendicular to the first direction X. The first area 21 is closer to the display area 11 than the third area 23, that is, the first area 21, the second area 22, and the third area 23 are arranged in sequence outside the display area 11.

[0053] Continue to see Figure 2 The display panel 10 includes a substrate, and a first conductive layer M1 and a second conductive layer M2 stacked on the substrate. The resistivity of the material of the first conductive layer M1 is greater than the resistivity of the material of the second conductive layer M2. For example, the sheet resistance (sheet resistance) of the material of the first conductive layer M1 is greater than the sheet resistance of the material of the second conductive layer M2.

[0054] The first conductive layer M1 includes a first data fan-out line 41 arranged in the first area 21, the second conductive layer M2 includes a second data fan-out line 42 arranged in the second area 22, and a third data fan-out line 43 arranged in the third area 23. The first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 are connected in sequence to form a second fan-out line S2.

[0055] Exemplarily, among the first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43, the data fan-out lines located in the same conductive layer can be directly connected, and the data fan-out lines located in different conductive layers can be connected across the film layer (also called "jumper"). In the embodiment of the present application, the first data fan-out line 41 is arranged on the first conductive layer M1, and the second data fan-out line 42 is arranged on the second conductive layer M2, and the two are connected by means of a jumper, and the second data fan-out line 42 and the third data fan-out line 43 are both arranged on the second conductive layer M2, and the two are directly connected.

[0056] Continue to see Figure 2 The second conductive layer M2 also includes a fourth data fan-out line 44 arranged in the first area 21, and a fifth data fan-out line 45 arranged in the second area 22. The first conductive layer M1 also includes a sixth data fan-out line 46 arranged in the third area 23. The fourth data fan-out line 44, the fifth data fan-out line 45 and the sixth data fan-out line 46 are connected in sequence to form a first fan-out line S1.

[0057] Exemplarily, among the fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46, the data fan-out lines located in the same conductive layer can be directly connected, and the data fan-out lines located in different conductive layers can be connected by means of jumpers. In the embodiments of the present application, both the fourth data fan-out line 44 and the fifth data fan-out line 45 are disposed on the second conductive layer M2 and are directly connected to each other. The fifth data fan-out line 45 is disposed on the first conductive layer M1, and the sixth data fan-out line 46 is disposed on the second conductive layer M2, and the two are connected by means of jumpers.

[0058] In the above embodiments of the present application, the display panel 10 includes a display area 11 and a fan-out area 12 located on one side of the display area 11. The fan-out area 12 includes a boundary 120 of the display area 11. The fan-out area 12 further includes a first wiring area 1 and a second wiring area 2 arranged along a first direction X parallel to the boundary 120. Along a second direction Y intersecting with the first direction X, a first region 21, a second region 22, and a third region 23 of the second wiring area 2 are sequentially arranged outside the display area 11. The display panel 10 further includes a substrate and a first conductive layer M1 and a second conductive layer M2 sequentially stacked on the substrate. The resistivity of the material of the first conductive layer M1 is greater than the resistivity of the material of the second conductive layer M2.

[0059] The first conductive layer M1 includes a first data fan-out line 41 disposed in the first region 21. The second conductive layer M2 includes a second data fan-out line 42 disposed in the second region 22 and a third data fan-out line 43 disposed in the third region 23. The first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43 are sequentially connected to form a second fan-out line S2. It can be understood that the second fan-out line S2 includes three segments, one of which uses the first conductive layer M1 with a higher impedance, and the other two segments use the second conductive layer M2 with a lower impedance. The proportion of the low-impedance conductive layer material in the second fan-out line S2 is relatively high, and the resistance of the second fan-out line S2 is relatively low, which is beneficial to reducing the resistance of the data line (data line) connected to the second fan-out line S2, thereby reducing the load of the trace.

[0060] The second conductive layer M2 further includes a fourth data fan-out line 44 disposed in the first region 21 and a fifth data fan-out line 45 disposed in the second region 22. The first conductive layer M1 further includes a sixth data fan-out line 46 disposed in the third region 23. The fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46 are sequentially connected to form a first fan-out line S1. It can be understood that the first fan-out line S1 includes three segments, one of which uses the first conductive layer M1 with a higher impedance, and the other two segments use the second conductive layer M2 with a lower impedance. The proportion of the low-impedance conductive layer material in the first fan-out line S1 is relatively high, and the resistance of the first fan-out line S1 is relatively low, which is beneficial to reducing the resistance of the data line connected to the first fan-out line S1, thereby reducing the load of the trace.

[0061] Moreover, in the above-mentioned first fan-out line S1 and second fan-out line S2, each fan-out line includes a section of routing located in the first conductive layer M1 and two sections of routing located in the second conductive layer M2, therefore, the resistance value of the first fan-out line S1 and the second fan-out line S2 are also close, and the load of the first fan-out line S1 and the second fan-out line S2 are close. In the case where the first fan-out line S1 and the second fan-out line S2 are adjacent, the data signal transmitted through the first fan-out line S1 and the second fan-out line S2 is transmitted to the pixels at the far end of the display area 11 (the side of the display area 11 away from the fan-out area 12), which can improve the uneven display phenomenon at the far end of the display area 11.

[0062] In some embodiments, see Figure 2 The orthographic projection of the first data fan-out line 41 on the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line 44 on the substrate. The orthographic projection of the third data fan-out line 43 on the substrate at least partially overlaps with the orthographic projection of the sixth data fan-out line 46 on the substrate.

[0063] It can be understood that the first data fan-out line 41 and the fourth data fan-out line 44 located in the first area 21 are stacked in an interleaved wiring manner, and the third data fan-out line 43 and the sixth data fan-out line 46 located in the third area 23 are also stacked in an interleaved wiring manner, which can reduce the area occupied by the data fan-out lines in the second wiring area 2, which is beneficial to reducing the area of ​​the second wiring area 2, thereby helping to narrow the border width of the display device 100.

[0064] Figure 3 for Figure 1 A local enlarged view of multiple routing lines in the first wiring area.

[0065] In some embodiments, see Figure 3 , the first wiring area 1 includes a fourth area 24 and a fifth area 25 arranged along the second direction Y. The fourth area 24 is closer to the display area 11 than the fifth area 25 .

[0066] The first conductive layer M1 further includes a seventh data fan-out line 47 disposed in the fourth region 24, and the second conductive layer M2 further includes an eighth data fan-out line 48 disposed in the fifth region 25. The seventh data fan-out line 47 and the eighth data fan-out line 48 are connected to form a third fan-out line S3. Exemplarily, the seventh data fan-out line 47 and the eighth data fan-out line 48 are located in different conductive layers, and the two are connected by a jumper.

[0067] The second conductive layer M2 further includes a ninth data fan-out line 49 disposed in the fourth region 24, and the first conductive layer M1 further includes a tenth data fan-out line 40 disposed in the fifth region 25. The ninth data fan-out line 49 is connected to the tenth data fan-out line 40 to form a fourth fan-out line S4. Exemplarily, the ninth data fan-out line 49 and the tenth data fan-out line 40 are located in different conductive layers, and the two are connected by a jumper.

[0068] Continue to see Figure 3 , the orthographic projection of the seventh data fan-out line 47 on the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line 49 on the substrate. The orthographic projection of the eighth data fan-out line 48 on the substrate at least partially overlaps with the orthographic projection of the tenth data fan-out line 40 on the substrate. It can be understood that the seventh data fan-out line 47 and the ninth data fan-out line 49 located in the fourth area 24 are stacked and wired in an interlaced wiring manner, and the eighth data fan-out line 48 and the tenth data fan-out line 40 located in the fifth area 25 are also stacked and wired in an interlaced wiring manner, which reduces the occupied area of ​​the data fan-out line in the first wiring area 1, is conducive to reducing the area of ​​the first wiring area 1, and thus is conducive to narrowing the border width of the display device 100.

[0069] Understandably, see Figure 1 and Figure 3 Compared with the second wiring area 2, the first wiring area 1 is closer to the center line L of the display panel 10 along the first direction X, so the first wiring area 1 is called the "proximal area" and the second wiring area 2 is called the "distal area". Therefore, the length of the fan-out line of the first wiring area 1 is smaller than the length of the fan-out line of the second wiring area 2.

[0070] The fan-out line in the first wiring area 1 performs a "jump" at the junction of the fourth area 24 and the fifth area 25, that is, a fan-out line includes two sections, one section uses the first conductive layer M1 with higher impedance, and the other section uses the second conductive layer M2 with lower impedance.

[0071] Exemplarily, the jumper is at the middle position of the fan-out line, thereby dividing a fan-out line into two sections of equal length, that is, in each fan-out line, the low-impedance conductive material accounts for one-half and the high-impedance conductive material also accounts for one-half.

[0072] In the second wiring area 2, see Figure 2 A portion of the fan-out lines performs a first jump at the junction of the first area 21 and the second area 22, and another portion of the fan-out lines performs a second jump at the junction of the second area 22 and the third area 23. Each fan-out line includes three sections, one section uses the first conductive layer M1 with higher impedance, and two sections use the second conductive layer M2 with lower impedance.

[0073] Exemplarily, in the second wiring area 2, the length of each fan-out line is equal in the first area 21, the second area 22 and the third area 23. In the second fan-out line S2, the lengths of the first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 are equal, the proportion of high-impedance conductive material is one-third, and the proportion of low-impedance conductive material is two-thirds.

[0074] Similarly, in the first fan-out line S1 , the fourth data fan-out line 44 , the fifth data fan-out line 45 and the sixth data fan-out line 46 are of equal length, the high-impedance conductive material accounts for one third, and the low-impedance conductive material accounts for two thirds.

[0075] In the above-mentioned embodiments of the present application, the length of the fan-out line of the second wiring area 2 is greater than the length of the fan-out line of the first wiring area 1, that is, the length of the fan-out line located in the remote area is greater than the length of the fan-out line located in the proximal area, so that the wiring resistance in the remote area is larger and the load is higher.

[0076] Based on this, by improving the wiring design of the second wiring area 2, compared with the first wiring area 1, the proportion of low-impedance conductive material (second conductive material) in the fan-out line of the second wiring area 2 is increased from one half to two thirds, and the proportion of high-impedance conductive material (first conductive material) is reduced from one half to one third, thereby reducing the square resistance of multiple fan-out lines located in the second wiring area 2, reducing the load of the fan-out line, and helping to reduce the square resistance difference between adjacent fan-out lines, so as to improve the display uniformity of the display area 11 located at the far end of the source driver circuit 30.

[0077] Figure 4 for Figure 1 A partial enlarged view of the second wiring area in FIG. Figures 5 to 8 They are Figure 4 A local enlarged view of multiple routing lines in the second wiring area in area A to area D.

[0078] In some embodiments, see Figures 4 to 8 , the first conductive layer M1 is a light shield (Light Shield, LS), and the second conductive layer M2 is a gate conductive layer (Gate). Figure 4 , the second wiring area 2 is divided into four areas: area A, area B, area C and area D.

[0079] Among them, see Figure 5Compared with area B, area C and area D, area A is closest to the display area 11. Area A corresponds to the junction of the first area 21 and the second area 22. Multiple fan-out lines make a first jump in area A. Exemplarily, the second data fan-out line 42 located in the gate conductive layer crosses the film layer and is connected to the first data fan-out line 41 located in the light shielding layer. The fourth data fan-out line 44 and the fifth data fan-out line 45 located in the gate conductive layer are directly connected.

[0080] See also Figure 6 , region B corresponds to the second region 22 , and the plurality of fan-out lines after the first jump are all located in the gate conductive layer M2 , that is, the second data fan-out line 42 and the fifth data fan-out line 45 are arranged in the region B on the same layer.

[0081] See also Figure 7 , region C corresponds to the second region 22. In region C, multiple fan-out lines are jumped for the second time. For example, the second data fan-out line 42 and the third data fan-out line 43 located in the gate conductive layer M2 are directly connected, and the fifth data fan-out line 45 located in the gate conductive layer is connected to the sixth data fan-out line 46 located in the light shielding layer by crossing the film layer. Figure 8 Region D corresponds to the third region 23. In region D, the third data fan-out line 43 and the sixth data fan-out line 46 after the second jump are stacked to reduce the occupied area of ​​the data fan-out line in region D.

[0082] Exemplarily, the square resistance of the light-shielding layer (first conductive layer) M1 is approximately 0.33Ω / □ ("Ω / □" is "ohm per square", which refers to the resistance value from edge to edge of a square thin film conductive material), and the square resistance of the gate conductive layer (second conductive layer) M2 is approximately 0.1Ω / □. The square resistance of the light-shielding layer is approximately three times that of the gate conductive layer. In an embodiment of the present application, the second fan-out line S2 is composed of two-thirds of the gate conductive layer material (the second data fan-out line 42 and the third data fan-out line 43) and one-third of the shading layer material (the first data fan-out line 41), and the first fan-out line S1 is composed of two-thirds of the gate conductive layer material (the fourth data fan-out line 44 and the fifth data fan-out line 45) and one-third of the shading layer material (the sixth data fan-out line 46). Compared with the related art, each fan-out line of the fan-out area 12 of the present application increases the use of low-impedance material (gate conductive layer material), thereby reducing the resistance of the data line connected to the second fan-out line S2, thereby reducing the load of the routing, so as to optimize the display uniformity at the far end of the display area 11.

[0083] Fig. 9 for Figure 5 A partial cross-sectional view of a jumper along section line PP'; Fig.10 for Figure 7 A partial cross-sectional view of a jumper along section line QQ'.

[0084] In some embodiments, see Fig. 9 and Fig.10 The display panel 10 further includes a first insulating layer 5 disposed between the first conductive layer M1 and the second conductive layer M2. Exemplarily, the first insulating layer 5 includes a stacked buffer layer 51 and a gate insulating layer (Gate Insulator, GI) 52. The first insulating layer 5 is located between the light shielding layer (first conductive layer) M1 and the gate conductive layer (second conductive layer) M2. The first insulating layer 5 is used to isolate the gate conductive layer M2 from the light shielding layer M1. The buffer layer 51 is disposed on the substrate 7, and the light shielding layer M1 is disposed in the buffer layer 51. The gate insulating layer (GI) 52 and the buffer layer 51 are patterned by setting a mask plate, so that the first insulating layer 5 is provided with a first via 50, and the gate conductive layer M2 is electrically connected to the light shielding layer M1 through the first via 50.

[0085] In this embodiment, LS and Gate are used as data signal lines, and LS and Gate are jumpered through LS-GI-Gate. Fig. 9 The second data fan-out line 42 located in the second conductive layer M2 passes through the first insulating layer 5 and is electrically connected to the first data fan-out line 41 located in the first conductive layer M1, thereby realizing the first jump of multiple data fan-out lines. Fig.10 , the fifth data fan-out line 45 located in the second conductive layer M2 penetrates the first insulating layer 5 and is connected to the sixth data fan-out line 46 located in the first conductive layer M1, thereby realizing the second jump of multiple fan-out lines. Exemplarily, the resistance of multiple fan-out lines located in the second wiring area 2 can be reduced by about 12%, thereby reducing the charging loss of the display panel 10.

[0086] Fig.11 A partial enlarged view of another second wiring area provided in an embodiment of the present application; Fig.12 for Fig.11 A partial cross-sectional view of another jumper along the section line PP'; Fig.13 for Fig.11 A partial cross-sectional view of another jumper along section line QQ'.

[0087] In some embodiments, see Fig.11 The source-drain conductive layer M3 further includes a touch signal line (Touch Transmit Line, Tx) 9, and the touch signal line 9 is used to send a driving signal to the touch electrode to achieve touch positioning.

[0088] In some embodiments, see Fig.12 and Fig.13The display panel 10 includes a substrate 7, and a first conductive layer M1, a first insulating layer 5, a second conductive layer M2, a second insulating layer 8 and a source and drain conductive layer (Source, Drain, SD) M3 stacked in sequence on the substrate 7. Exemplarily, the first insulating layer 5 includes a stacked buffer layer 51 and a gate insulating layer (Gate Insulator, GI) 52. The second insulating layer 8 is an interlayer dielectric layer (Inter Layer Dielectric, ILD). The second insulating layer 8 is used to isolate the source and drain conductive layer M3 from the second conductive layer (gate conductive layer) M2. The source and drain conductive layer M3 includes a first connecting electrode 91 and a second connecting electrode 92. The second insulating layer 8 is provided with a second through hole 80 and a third through hole 81.

[0089] In this embodiment, there is no need to additionally set up a mask plate for patterning the GI. After forming the second via 80 and the third via 81 in the second insulating layer (ILD) 8 using the ILD mask plate, etching is continued downward along the second via 80 until a portion of the first conductive layer M1 located below the second via 80 is exposed. LS and Gate are used as data signal lines, and LS and Gate are jumpered through LS-ILD-SD-ILD-Gate.

[0090] For example, see Fig.10 , the first connection electrode 91 passes through the second insulating layer 8 through the second via hole 80, and passes through the first insulating layer 5 through the via hole to connect with the first data fan-out line 41, and the first connection electrode 91 passes through the second insulating layer 8 through the third via hole 81 to connect with the second data fan-out line 42. That is, the second data fan-out line 42 located in the gate conductive layer (Gate) M2 is electrically connected to the first data fan-out line 41 located in the light shielding layer (LS) M1 through the first connection electrode (SD) 91, thereby realizing the first jump of multiple fan-out lines.

[0091] For example, see Fig.11 The second connection electrode 92 passes through the second insulating layer 8 through the third via hole 81 and is connected to the fifth data fan-out line 45, and the second connection electrode 92 passes through the second insulating layer 8 through the second via hole 80, and passes through the first insulating layer 5 through the via hole of the first insulating layer 5 and is electrically connected to the sixth data fan-out line 46, thereby realizing the second jump of multiple fan-out lines.

[0092] In the embodiments of this application, see Fig.11The touch signal line 9 is located in the source-drain conductive layer M3, and the first connecting electrode 91 and the second connecting electrode 92 are also located in the source-drain conductive layer M3. To prevent a short circuit, it is necessary to ensure that the orthographic projection of the touch signal line 9 on the substrate 7 does not overlap with the orthographic projection of the first connecting electrode 91 on the substrate 7, and the orthographic projection of the touch signal line 9 and the second connecting electrode 92 on the substrate 7 do not overlap, that is, the touch signal line 9 needs to avoid the position where the fan-out line jumps twice.

[0093] Fig.14 is a partial cross-sectional view of another jumper along section line PP'; Fig.15 It is a partial cross-sectional view of another jumper along the section line QQ'.

[0094] In some embodiments, see Fig.14 and Fig.15 The first conductive layer M1 is a gate conductive layer, and the second conductive layer M2 is a source-drain conductive layer (SD).

[0095] The display panel 10 further includes a third insulating layer 8 disposed between the first conductive layer (Gate) M1 and the second conductive layer (SD) M1. Exemplarily, the third insulating layer 8 is an interlayer dielectric layer (ILD), and the ILD 8 is used to isolate the second conductive layer (SD) M2 from the first conductive layer (Gate) M1. The third insulating layer 8 is provided with a fourth through hole 82.

[0096] In this embodiment, there is no need to set up an additional mask plate for patterning GI. The fourth via 82 is formed in the third insulating layer (ILD) 8 using the ILD mask plate, and Gate and SD are used as data signal lines. Gate and SD are connected through Gate-ILD-SD to achieve a jumper.

[0097] For example, see Fig.14 The second data fan-out line 42 passes through the third insulating layer 8 through the fourth via hole 82 and is electrically connected to the first data fan-out line 41, thereby realizing the first jump of multiple fan-out lines.

[0098] For example, see Fig.15 The fifth data fan-out line 45 passes through the third insulating layer 8 through the fourth via hole 82 and is electrically connected to the sixth data fan-out line 46, thereby realizing the second jump of multiple fan-out lines.

[0099] Each fan-out line can be divided into three sections based on the positions of the above two jump lines. Exemplarily, the lengths of the above three sections of fan-out lines are equal, that is, the lengths of the first data fan-out line 41 and the fourth data fan-out line 44 are equal, the lengths of the second data fan-out line 42 and the fifth data fan-out line 45 are equal, and the lengths of the third data fan-out line 43 and the sixth data fan-out line 46 are equal.

[0100] The square resistance of the second conductive layer M2 is smaller than that of the first conductive layer M1. Exemplarily, the square resistance of the gate conductive layer is about 0.1Ω / □, and the square resistance of the source-drain conductive layer is about 0.06Ω / □. Through two jumpers, the SD lines account for about two-thirds of the multiple fan-out lines, and the Gate lines account for about one-third. Since the second wiring area 2 uses more SD lines with lower square resistance, the total impedance reduction effect of the multiple fan-out lines is more obvious, further improving the display uniformity at the far end of the display area 11.

[0101] Fig.16 for Figure 1 A partial enlarged view of part of the wiring of the display panel at position N.

[0102] In some embodiments, see Fig.16 , along the first direction X, the display panel 10 also includes a plurality of data lines arranged in sequence in the display area 11. Exemplarily, the plurality of data lines include a first data line S101, a second data line S102 ... a sixteenth data line S116 arranged in sequence, and the first data line S101 is adjacent to the second data line S102. The second data line S102 is connected to the first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 in sequence. The first data line S101 is connected to the fourth data fan-out line 44, the fifth data fan-out line 45 and the sixth data fan-out line 46 in sequence. Among them, the first data fan-out line 41 is adjacent to the fourth data fan-out line 44 and is located in different conductive layers.

[0103] The difference between the sum of the resistances of the first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 and the sum of the resistances of the fourth data fan-out line 44, the fifth data fan-out line 45 and the sixth data fan-out line 46 is less than or equal to 20Ω. Since the resistance values ​​of the first data line S101 and the second data line S102 are similar, it can be understood that the difference between the sum of the resistances of the second data line S102, the first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 and the sum of the resistances of the first data line S101, the fourth data fan-out line 44, the fifth data fan-out line 45 and the sixth data fan-out line 46 is less than or equal to 20Ω, that is, the resistance difference between adjacent data lines in the display panel 10 is less than or equal to 20Ω, thereby improving the display panel 10 and other display defects such as vertical stripes, thereby improving the display uniformity of the display panel 10 located at the far end area of ​​the source driving circuit 30.

[0104] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The device comprises a display area and a fan-out area located on one side of the display area; the fan-out area comprises a first wiring area and a second wiring area arranged along a first direction, the fan-out area comprises a boundary close to the display area, and the first direction is parallel to the boundary; The second wiring area includes a first area, a second area and a third area sequentially arranged along a second direction, the second direction intersects the first direction; the first area is closer to the display area than the third area; The display panel includes a substrate, and a first conductive layer and a second conductive layer stacked on the substrate, wherein the resistivity of a material of the first conductive layer is greater than the resistivity of a material of the second conductive layer; the first conductive layer includes a first data fan-out line arranged in the first area, the second conductive layer includes a second data fan-out line arranged in the second area, and a third data fan-out line arranged in the third area, and the first data fan-out line, the second data fan-out line and the third data fan-out line are connected in sequence; The second conductive layer also includes a fourth data fan-out line arranged in the first area, and a fifth data fan-out line arranged in the second area. The first conductive layer also includes a sixth data fan-out line arranged in the third area. The fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line are connected in sequence.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the first data fan-out line on the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line on the substrate; An orthographic projection of the third data fan-out line on the substrate at least partially overlaps with an orthographic projection of the sixth data fan-out line on the substrate.

3. The display panel according to claim 1, characterized in that: The first conductive layer is a light shielding layer, and the second conductive layer is a gate conductive layer.

4. The display panel according to claim 3, characterized in that: The display panel further includes a first insulating layer disposed between the first conductive layer and the second conductive layer; The second data fan-out line passes through the first insulating layer and is connected to the first data fan-out line, and the fifth data fan-out line passes through the first insulating layer and is connected to the sixth data fan-out line.

5. The display panel according to claim 3, characterized in that: The display panel comprises the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer and the source-drain conductive layer which are sequentially stacked; The source-drain conductive layer includes a first connecting electrode and a second connecting electrode; The first connecting electrode passes through the second insulating layer and the first insulating layer to be connected to the first data fan-out line, and passes through the second insulating layer to be connected to the second data fan-out line; the second connecting electrode passes through the second insulating layer to be connected to the fifth data fan-out line, and passes through the second insulating layer and the first insulating layer to be connected to the sixth data fan-out line.

6. The display panel according to claim 5, characterized in that: The source-drain conductive layer further includes a touch signal line, the orthographic projection of the touch signal line on the substrate does not overlap with the orthographic projection of the first connection electrode on the substrate, and does not overlap with the orthographic projection of the second connection electrode on the substrate.

7. The display panel according to claim 1, characterized in that: The first conductive layer is a gate conductive layer, and the second conductive layer is a source-drain conductive layer.

8. The display panel according to claim 7, characterized in that: The display panel further includes a third insulating layer disposed between the first conductive layer and the second conductive layer; The second data fan-out line passes through the third insulating layer and is connected to the first data fan-out line, and the fifth data fan-out line passes through the third insulating layer and is connected to the sixth data fan-out line.

9. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of data lines arranged in the display area, and the plurality of data lines are arranged in sequence along the first direction; The plurality of data lines include adjacent first data lines and second data lines, the first data line is connected to the first data fan-out line, the second data fan-out line and the third data fan-out line in sequence; the second data line is connected to the fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line in sequence; A difference between a sum of resistances of the first data fan-out line, the second data fan-out line, and the third data fan-out line and a sum of resistances of the fourth data fan-out line, the fifth data fan-out line, and the sixth data fan-out line is less than or equal to 20Ω.

10. The display panel according to claim 1, characterized in that: The first wiring area includes a fourth area and a fifth area arranged along the second direction, and the fourth area is closer to the display area than the fifth area; The first conductive layer further includes a seventh data fan-out line disposed in the fourth region, the second conductive layer further includes an eighth data fan-out line disposed in the fifth region, the seventh data fan-out line is connected to the eighth data fan-out line; the second conductive layer further includes a ninth data fan-out line disposed in the fourth region, the first conductive layer further includes a tenth data fan-out line disposed in the fifth region, the ninth data fan-out line is connected to the tenth data fan-out line; The orthographic projection of the seventh data fan-out line on the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line on the substrate; An orthographic projection of the eighth data fan-out line on the substrate at least partially overlaps with an orthographic projection of the tenth data fan-out line on the substrate.

11. The display panel according to claim 1, characterized in that: The fan-out area includes a first wiring area and two second wiring areas; Along the first direction, the two second wiring regions are disposed on opposite sides of the first wiring region.

12. A display device, characterized in that: include: The display panel according to any one of claims 1 to 11; A controller is electrically connected to the display panel.

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