Storage component, data writing method, data reading method and storage system

Abstract

The invention discloses a storage component, a data writing method, a data reading method and a storage system, and relates to the technical field of storage. The storage component comprises N memories, N write ports, N read ports and a storage controller, and N is an integer greater than or equal to 2; the N memories are connected with the N write ports in a one-to-one correspondence manner; each memory in the N memories is respectively connected with the N read ports; the N write ports and the N read ports are respectively connected with the storage controller; the N memories correspond to the same address space, mapping relation information is stored in the storage controller, and the mapping relation information is used for indicating the memories where the effective data stored in all the addresses in the address space are located.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage component, a data writing method, a data reading method and a storage system. Background Art

[0002] Random Access Memory (RAM) is usually used as a temporary data storage medium for the operating system or other running programs.

[0003] In the related art, in order to improve the read and write efficiency of the storage system, multiple read and write ports are usually set for the random access memory, so as to achieve simultaneous writing or reading of the random access memory, that is, the "multi-read and multi-write" function.

[0004] However, in order to resolve bank conflicts, the memory that implements “multiple read and multiple write” in the related art needs to add more peripheral circuits, thereby increasing circuit complexity. Summary of the invention

[0005] The embodiments of the present application provide a storage component, a data writing method, a data reading method and a storage system, which can simplify the circuit complexity when resolving bank conflicts. The technical solution is as follows.

[0006] In one aspect, a storage component is provided, the storage component comprising: N memories, N write ports, N read ports, and a storage controller, where N is an integer greater than or equal to 2;

[0007] The N memories are connected to the N write ports in a one-to-one correspondence;

[0008] Each of the N memories is connected to the N read ports respectively;

[0009] The N write ports and the N read ports are respectively connected to the storage controller;

[0010] The N memories correspond to the same address space, and mapping relationship information is stored in the storage controller, where the mapping relationship information is used to indicate the memory where the valid data stored in each address in the address space is located.

[0011] On the other hand, a data writing method is provided, the method being executed by a storage controller in a storage component, the storage component being the storage component described above; the method comprising:

[0012] Obtaining a first write request received by a first write port, where the first write port is any one of the N write ports;

[0013] Writing the data corresponding to the first write request into a first address in a first memory; the first memory is the memory corresponding to the first write port, and the first address is a write address of the first write request;

[0014] In the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory.

[0015] In some embodiments, the mapping relationship information includes mapping values ​​corresponding to each address in the address space;

[0016] The step of setting the memory where the valid data stored in the first address is located as the first memory in the mapping relationship information includes:

[0017] The mapping value corresponding to the first address in the mapping relationship information is set as a first mapping value, where the first mapping value is used to indicate that the valid data stored in the first address is located in the first memory.

[0018] In some embodiments, writing the data corresponding to the first write request to the first address in the first memory includes:

[0019] In response to the absence of the second write request, writing the data corresponding to the first write request to the first address in the first memory;

[0020] The second write request is a write request received by the second write port, the first write request and the second write request are received at the same time, and a write address of the second write request is the first address.

[0021] In some embodiments, the method further comprises:

[0022] In response to the existence of the second write request, and the write content of the second write request is different from the write content of the write request, performing one of the following operations:

[0023] not executing the first write request and the second write request; or,

[0024] executing one of the first write request and the second write request, and canceling the other of the first write request and the second write request; or,

[0025] Execute the first write request and the second write request, and in the mapping relationship information, set the memory where the valid data stored in the first address is located to one of the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0026] In some embodiments, the method further comprises:

[0027] In response to the existence of the second write request and the write content of the second write request is the same as the write content of the write request, the first write request and the second write request are executed, and in the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0028] In some embodiments, the method further includes: providing the mapping relationship information to an address generation unit so that the address generation unit generates multiple write requests with different write addresses according to the mapping relationship information, and the multiple write requests are used to be sent simultaneously to different write ports among the N write ports.

[0029] On the other hand, a data reading method is provided, the method being executed by a storage controller in a storage component, the storage component being the storage component described above; the method comprising:

[0030] Obtaining a first read request received by a first read port, where the first read port is any one of the N read ports;

[0031] Based on the mapping relationship information, query the memory where the valid data stored in the second address is located; the second address is the read address of the first read request;

[0032] Read data from the second address in the memory obtained by querying;

[0033] The read data is returned through the first read port.

[0034] In some embodiments, the mapping relationship information includes mapping values ​​corresponding to each address in the address space.

[0035] The querying, based on the mapping relationship information, of the memory where the valid data stored in the second address is located comprises:

[0036] Querying the mapping relationship information for a mapping value corresponding to the second address;

[0037] The memory corresponding to the mapping value is determined as the memory where the valid data stored in the second address is located.

[0038] In some embodiments, querying the memory where the valid data stored in the second address is located based on the mapping relationship information includes:

[0039] In response to the absence of the second read request, querying the memory where the valid data stored in the second address is located based on the mapping relationship information;

[0040] The second read request is a read request received by the second read port, the first read request and the second read request are received at the same time, and a read address of the second read request conflicts with the second address.

[0041] In some embodiments, the method further comprises:

[0042] In response to the second read request, one of the following operations is performed:

[0043] not executing the first read request and the second read request; or,

[0044] One of the first read request and the second read request is executed, and the other of the first read request and the second read request is canceled.

[0045] In some embodiments, the method further includes: providing the mapping relationship information to an address generation unit so that the address generation unit generates multiple read requests whose read addresses do not conflict based on the mapping relationship information, and the multiple read requests are used to be sent simultaneously to different read ports among the N read ports.

[0046] On the other hand, a storage system is provided, the storage system comprising at least one storage component as described above.

[0047] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0048] A storage component is composed of N memories, N write ports, N read ports, and a storage controller, where N is an integer greater than or equal to 2; wherein the N memories are connected to the N write ports in a one-to-one correspondence, and each of the N memories is connected to the N read ports respectively, and mapping relationship information is used to indicate the memory where the valid data stored in each address in the same address space of the N memories is located, thereby realizing a multi-read and multi-write storage system and saving the area occupied by the storage component. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1is a basic circuit diagram of a storage system involved in this application;

[0051] Figure 2 is a basic circuit diagram of another storage system involved in the present application;

[0052] Figure 3 is a basic circuit diagram of another storage system involved in the present application;

[0053] Figure 4 is a basic circuit diagram of another storage system involved in the present application;

[0054] Figure 5 is a schematic diagram of the structure of a storage component provided by an exemplary embodiment of the present application;

[0055] Figure 6 is a schematic diagram of the structure of another storage component provided by the present application;

[0056] Figure 7 It is a structural schematic diagram of a storage system involved in this application;

[0057] Figure 8 It is a structural schematic diagram of a storage system involved in this application;

[0058] Fig. 9 It is a structural schematic diagram of a storage system involved in this application;

[0059] Fig.10 It is a structural schematic diagram of a storage system involved in this application;

[0060] Fig.11 is a flow chart of a data writing method provided by an exemplary embodiment of the present application;

[0061] Fig.12 It is a flow chart of a data reading method provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0063] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0064] The following first introduces some concepts involved in this application:

[0065] 1) Static Random-Access Memory (SRAM)

[0066] SRAM is a type of random access memory. The so-called "static" means that the data stored in this memory can be kept constant as long as the power is kept on.

[0067] 2) Multi-read and multi-write storage system

[0068] To improve the parallel performance of storage system reading and writing, there are usually the following solutions:

[0069] ① Use registers to build a multi-read-one-write / multi-read-multi-write storage system, which is more common in the design of the central processing unit (CPU). However, the area consumed by the unit bit of the register is much larger than that of SRAM, which is not suitable for large-capacity storage.

[0070] ② Use multi-port SRAM to build a multi-read one-write / multi-read multi-write storage system. Take a "one-write two-read" SRAM as an example. Please refer to Figure 1 , which shows a basic circuit diagram of a storage system involved in the present application.

[0071] like Figure 1 As shown in the figure, in this design, each storage unit (bit cell) needs to support two parallel read operations, which requires two sets of read address decoding, two read request lines, and two sets of read data output buses. Although this can accurately provide dual-port read function, this method requires a lot of circuits to be copied, so the area will increase. And the bigger problem is that this SRAM is not a standard component. If it is necessary, it may have to be specially customized, which undoubtedly prolongs the construction period and increases the development cost.

[0072] ③ Copy multiple copies of memory to implement a multi-read and one-write storage system. Taking the "one-write and two-read" SRAM as an example, please refer to Figure 2 , which shows a basic circuit diagram of another storage system involved in the present application.

[0073] like Figure 2As shown in the figure, in this design, the data written through the write port is sent to two identical SRAMs for storage at the same time, and the contents of SRAM#1 and #2 are kept consistent at all times. In this way, all addresses of the SRAM can be accessed through the two read ports. This design can indeed use standard multiple read ports, but its disadvantages are also obvious: (1) It consumes a lot of power. A written data must not only be stored in one place, but also copied to another place to provide two read channels for the same data; (2) It can achieve "one write, multiple reads", but it cannot achieve "multiple writes, multiple reads".

[0074] ④ Implement multiple reads and multiple writes through multi-bank design, that is, divide a large memory into many small banks. Although each bank has only one (at most two) read and write ports, at a certain moment, read and write requests can be distributed on different banks, thus avoiding bank conflicts. Take the "two writes and two reads" 4-bank design as an example, please refer to Figure 3 , which shows a basic circuit diagram of another storage system involved in the present application; Figure 3 As shown, assuming that each bank has only one read / write port (at a certain moment, either read or write, not both), in this design, the addressing order is generally "big Z mode": SRAM#123412341234..., that is:

[0075]

[0076] Based on the above Figure 3 The design can avoid the read-write bank conflict by properly controlling the read and write addresses. For example, at the same time, the write address 0, 1 can be controlled, and the read address 2, 3 can be controlled. This is equivalent to: writing bank #1, 2, reading bank #3, 4, and there is no bank conflict at all. Of course, this is a very ideal situation. Let's consider the disadvantages of this design.

[0077] Assume that the access address is not perfect. For example, if at a certain moment, address 0,4 is written and address 3,7 is read, this is equivalent to: writing bank#1,1 and reading bank#3,3, which causes write-write conflict and read-read conflict of the bank. There are two ways to solve the bank conflict problem:

[0078] (1) If the memory access address can be calculated in advance, it is possible to predict whether a bank conflict will occur. If a bank conflict is detected, some read and write operations will be canceled. Let's look at the above example again. If it is known that "write address 0, 4, read address 3, 7" will be executed, then "write address 4, read address 7" will be canceled, and "write address 0, read address 3" will be retained. In this way, there will be no bank conflict, but the cost is that the memory access performance will be lost by half. Considering further, the data written to the memory often comes from upstream computing / data acquisition / network modules. If the memory cannot access data in time, it will inevitably cause performance loss to the entire system.

[0079] (2) If the memory access address cannot be calculated in advance, or if you do not want the upstream module to be blocked due to memory access problems, then the bank conflict problem must be handled at the memory entrance.

[0080] For write-write bank conflict issues, refer to Figure 4 , which shows a basic circuit diagram of another storage system involved in the present application, such as Figure 4 As shown, a buffer can be added to the second priority write port (write port 2 in this example) to cache data that cannot be written due to bank conflicts. After the bank conflicts are resolved, the data can be taken out of the buffer and written to the SRAM.

[0081] For example: Assume that the write address is 0, 4, which is equivalent to: writing bank #1, 1. At this time, the data of write port 2 write address 4 is cached in the buffer (at this time, write port 1 write address 0 is executed normally), and wait until the subsequent bank #1 is idle (no data access), then take out the data from the buffer and write it to address 4.

[0082] Through this method, bank write-write conflicts are alleviated, but the bank conflict problem cannot be fundamentally solved. Consider an extreme scenario, that is, continuous access to the same bank. For example: Assume that writing addresses 0, 4, 8, 12, ... is equivalent to continuously writing to bank #1. Data can be written to addresses 0 and 8 normally. The data to be written to address 4 is cached in the buffer, but note that the data to be written to address 12 has nowhere to go (because the buffer is already occupied by the data to be written to address 4). In this regard, although the buffer capacity can be increased to deal with it, it is impossible to increase it infinitely. As long as the same bank is continuously accessed for a period of time, the buffer will always be exhausted. At this time, the front end has to be back-pressured, resulting in performance degradation.

[0083] The read-read bank conflict problem can be solved by the replay mechanism. Consider the following example: Assuming that the read address is 3, 7, this is equivalent to: reading bank #3, 3. The standard single-port SRAM does not support simultaneous access to different addresses, so one address access must be canceled. Assuming that the read address 7 is canceled, the read address 3 can be executed normally. At the same time, the address 7 is recorded and notified to the relevant read request generation circuit (because the read of address 7 is not executed), and then the read request circuit can choose to send the read request of address 7 again (this is the reason why replay is named). Special attention should be paid to the fact that "writing address 7" is not allowed between "the first read address 7" and "the second replay reread address 7". Otherwise, the program intends to read the old data, but it is overwritten by the write operation in the middle, and the new data is read, which obviously violates the original intention of the program. It should also be noted that the replay mechanism is suitable for scenarios that are not sensitive to response delays. For scenarios that require immediate response, replay is not suitable. At this time, the aforementioned solution ② or ③ needs to be adopted to solve the "multiple read ports" requirement, at the cost of area and power consumption.

[0084] The second disadvantage of the multi-bank solution is the area expansion problem. Assuming that the area of ​​a memory system of a certain capacity is 1, in order to alleviate bank conflicts, it is divided into 8 banks (the more banks, the lower the probability of conflicts), it will be found that the sum of the areas of the 8 banks is ≈ 3. In other words, the cost is 200% more than the original cost (if the buffer is added, it will be even more).

[0085] The reason why the "capacity / area ratio" of a small-capacity bank is worse than that of a large-capacity bank is that in addition to the bit cell array used to store data, SRAM also requires supporting peripheral circuits, which have little to do with capacity. That is, regardless of whether it is a large-capacity bank or a small-capacity bank, the required peripheral circuit area is actually similar, so multi-bank design requires more peripheral circuits, which leads to an expansion of the total area.

[0086] Please refer to Figure 5 , which shows a schematic diagram of the structure of a storage component provided by an exemplary embodiment of the present application, and the storage component may include:

[0087] N memories 501 , N write ports 502 , N read ports 503 , and a storage controller 504 , where N is an integer greater than or equal to 2.

[0088] For example, the above Figure 5 The value of N shown in is 2. Optionally, the value of N can also be 3 or 4, etc.

[0089] The memory may be an SRAM, or may be another type of RAM, such as a dynamic random access memory (DRAM).

[0090] The N memories 501 are connected to the N write ports 502 in a one-to-one correspondence.

[0091] The N memories 501 are respectively connected to a corresponding write port 502 , and the write ports 502 connected to the memories 501 are different.

[0092] The connection between the memory 501 and the write port 502 may mean that the memory 501 and the write port 502 are electrically connected, that is, data may be written to the memory 501 through the write port 502 electrically connected to the memory 501 .

[0093] Each memory 501 in the N memories 501 is connected to N read ports 503 respectively.

[0094] Each of the above memories 501 is connected to each of the N read ports 503 , that is, there is not a one-to-one correspondence between the above N memories 501 and the N read ports 503 , but a cross-connected relationship.

[0095] The memory 501 being connected to the read port 503 may mean that the memory 501 is electrically connected to the read port 503 , that is, data can be read from any one of the N memories 501 through one read port 503 .

[0096] The N write ports 502 and the N read ports 503 are respectively connected to the storage controller 504 .

[0097] Among them, the above-mentioned N write ports 502 and N read ports 503 can be connected to the storage controller 504 respectively. The above-mentioned write port 502 or read port 503 is connected to the storage controller 504, which means that the write port 502 or the read port 503 is electrically connected to the storage controller 504. That is to say, any write request received by any write port 502 can be sent to the storage controller 504, and correspondingly, any read request received by any read port 503 can be sent to the storage controller 504, so that the storage controller 504 controls the reading and writing of the above-mentioned N memories.

[0098] The N memories 501 correspond to the same address space, and the storage controller 504 stores mapping relationship information, which is used to indicate the memory where the valid data stored in each address in the address space is located.

[0099] In the embodiment of the present application, N memories 501 correspond to the same address space, which means that the storage addresses in the N memories 501 are the same, for example, the addresses in the N memories 501 are all 0 to 81. In other words, the external addresses of the N memories 501 are the same.

[0100] The solution shown in the present application provides a "multi-write and multi-read" storage (memory) system, whose data bit width = Nbit / port, address depth = M, and its total capacity = M*N bit;

[0101] If a multi-bank solution is used, assuming 8 banks are used (8 banks are necessary to reduce the probability of bank conflicts), at least 8 SRAMs are required, each with a data bit width of N bit / port and an address depth of M / 8, which will lead to an area expansion problem.

[0102] In view of the shortcomings of the multi-bank solution, the solution shown in this application proposes a new storage system design, for example, Figure 5 For example, the above solution consists of two dual-port (one write and one read) SRAMs, each SRAM has a data bit width of N bit / port and an address depth of M, so the total capacity of the entire system is M*N*2bit, but the total capacity presented to the outside is M*N bit. In other words, this solution uses two SRAMs to achieve one storage space.

[0103] Optional, above Figure 5 The scheme shown can also be extended to the case where N = 3 or 4. For example, please refer to Figure 6 , which shows a schematic diagram of the structure of another storage component provided by the present application. Figure 6 As shown, the number of memory 501, write port 502, and read port 503 is equal to 4. This solution consists of three dual-port (one write and one read) SRAMs, each SRAM has a data bit width of N bit / port and an address depth of M, so the total capacity of the entire system is M*N*2bit, but the total capacity presented to the outside is M*Nbit. In other words, this solution uses three SRAMs to achieve one storage space.

[0104] Among them, since the address spaces of the above-mentioned N memories 501 are the same, that is, through the N write ports 502, data corresponding to N different write addresses can be written to a maximum of N memories 501 at the same time, thereby realizing a "multi-write" operation.

[0105] Correspondingly, since each memory 501 is respectively connected to N read ports 503, and mapping relationship information is stored in the storage controller 504, the mapping relationship information is used to indicate the memory where the valid data stored in each address in the address space is located. Therefore, for a read request received by any read port 503, it is possible to determine in which memory 501 the corresponding valid data is located through the above-mentioned mapping relationship information, and read the data from the corresponding memory 501. That is to say, through N read ports 503, data corresponding to N different addresses can be read from up to N memories 501 at the same time, thereby realizing a "multi-read" operation.

[0106] In addition, the solutions shown in the above embodiments of the present application can also save the area of ​​storage components.

[0107] Please refer to Table 1, which shows the relationship between the area and storage space of the circuit design involved in this application. The area comparison table shown in Table 1 below is from real data, reflecting the memory area required to store 96kbit data:

[0108] Table 1

[0109] SRAM address depth SRAM data width Number of SRAM chips Total SRAM area 768 128 1 1.0 (normalized area) 256 128 3 1.6 128 128 6 2.6 96 128 8 3.2

[0110] As shown in Table 1, even if "two pieces of 768*128 SRAM" are used, the area is still smaller than "one piece of 8 pieces of 96*128 SRAM".

[0111] That is to say, for the same storage capacity of 768*128, the normalized area required for two 768*128 SRAM structures through this solution is 2. If an 8-bank solution is formed by eight 96*128 SRAMs, the normalized area required is 3.2. In other words, the circuit involved in this application can save 37.5% of the area (the area occupied by the storage controller is ignored here, because the area occupied by the storage controller and the storage space required to store the mapping relationship information can be ignored compared to the area of ​​the SRAM).

[0112] To summarize, the solution shown in the embodiment of the present application consists of N memories, N write ports, N read ports, and a storage controller to form a storage component, where N is an integer greater than or equal to 2; wherein the N memories are connected to the N write ports in a one-to-one correspondence, and each of the N memories is connected to the N read ports respectively, and mapping relationship information is used to indicate the memory where the valid data stored in each address in the same address space of the N memories is located, thereby realizing a multi-read and multi-write storage system and saving the area occupied by the storage component.

[0113] Based on the above Figure 5 or Figure 6 In some implementations of the embodiment shown, the storage controller 504 is used to:

[0114] Obtain a first write request received by a first write port, where the first write port is any one of the N write ports 502;

[0115] Writing the data corresponding to the first write request into a first address in a first memory; the first memory is the memory 501 corresponding to the first write port, and the first address is the write address of the first write request;

[0116] In the mapping relationship information, the memory 501 where the valid data stored in the first address is located is set as the first memory.

[0117] Among them, during the writing process, for any write request received by the write port, the data and write address corresponding to the write request can be written to the write address in the corresponding memory. At the same time, the mapping relationship information and the memory where the valid data of the address is located are set to the corresponding memory, thereby ensuring the validity of the address mapping.

[0118] In some embodiments, the mapping relationship information includes mapping values ​​corresponding to each address in the address space;

[0119] The above-mentioned step of setting the memory where the valid data stored in the first address is located as the first memory in the mapping relationship information includes:

[0120] The mapping value corresponding to the first address in the mapping relationship information is set as a first mapping value, where the first mapping value is used to indicate that the valid data stored in the first address is located in the first memory.

[0121] In an embodiment of the present application, the above-mentioned mapping relationship information is represented by a mapping table, and a mapping value is set for each address. The mapping value is used to indicate in which memory the valid data stored in the corresponding address is located. This can simplify the indication method of the memory corresponding to the valid data of the address, control the data amount of the mapping relationship information, reduce the area occupied by the storage space of the mapping relationship information, and thus control the overall area of ​​the storage component.

[0122] In some embodiments, the storage controller is used to:

[0123] In response to the absence of the second write request, writing the data corresponding to the first write request to the first address in the first memory;

[0124] The second write request is a write request received by the second write port, the first write request and the second write request are received simultaneously, and the write address of the second write request is the first address.

[0125] In an embodiment of the present application, when the storage controller obtains the first write request received through the first write port, it can detect whether other write ports have received the write request at the same time. If so, it can further detect whether the write address of the write request received by the other write ports is the same as the write address of the first write request. If so, it is determined that the other write request is the second write request. Otherwise, it is determined that there is no second write request, that is, there is no write conflict for the first write request. When there is no write conflict for the first write request, the first write request can be executed, thereby avoiding write errors caused by writing when there is a write conflict, thereby ensuring the accuracy of data writing.

[0126] In some embodiments, the storage controller is further configured to:

[0127] In response to the second write request existing and the write content of the second write request being different from the write content of the write request, performing one of the following operations:

[0128] The first write request and the second write request are not executed; or,

[0129] executing one of the first write request and the second write request, and canceling the other of the first write request and the second write request; or,

[0130] The first write request and the second write request are executed, and in the mapping relationship information, the memory where the valid data stored in the first address is located is set to one of the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0131] For a canceled write request, the storage controller may also return an error response to the sender of the write request (such as an address generation unit) so that the sender of the write request may re-initiate the write or perform other processing.

[0132] In the embodiment of the present application, when a write conflict exists in the first write request, data write errors can be avoided by not executing either write request or executing one of the write requests or executing both write requests but only marking the data of the corresponding address in one memory as valid.

[0133] In one possible implementation, within one cycle, N write requests are first sent to the storage controller through N write ports, and the storage controller detects whether there is a conflict in the write addresses of the N write requests. If there is a conflict in the write addresses of two or more write requests, one of the write requests is taken to execute, or neither of the two or more write requests is executed.

[0134] When the storage controller determines to execute a certain write request, it can generate a write instruction corresponding to the write request, send the write instruction to the memory corresponding to the valid data, and the memory stores the corresponding data.

[0135] In some embodiments, the storage controller is further configured to:

[0136] In response to the existence of a second write request, and the write content of the second write request is the same as the write content of the write request, the first write request and the second write request are executed, and in the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0137] In an embodiment of the present application, when there is a write conflict in the first write request, but the write content is the same, both can be executed, and the storage where the valid data is located can be set to multiple memories, thereby avoiding returning an error response to the sender of the write request, and also avoiding the subsequent sender of the write request to resend the write request, thereby improving write efficiency.

[0138] In some embodiments, the storage controller is further used to provide mapping relationship information to the address generation unit so that the address generation unit generates multiple write requests with different write addresses according to the mapping relationship information, and the multiple write requests are used to be sent to different write ports among the N write ports at the same time.

[0139] In an embodiment of the present application, the above-mentioned mapping relationship information can also be provided to the address generation unit so that the address generation unit can avoid write conflicts when generating write requests, thereby further reducing the situation of write conflicts and improving write efficiency.

[0140] by Figure 5 Take the two SRAMs shown as an example:

[0141] Write port 0 to SRAM#0, the available address space is: 0~(M-1);

[0142] Write port 1 to SRAM#1, and the available address space is also: 0~(M-1);

[0143] Therefore, no matter which write port is used, the entire address space can be written, and there will be no bank write-write conflict between the two write ports (because for one write port, it is "almost" always writable).

[0144] Consider a special case: writing to port 0 and port 1 at the same time to the same address, but with different contents. In this case, there are multiple processing strategies, including but not limited to:

[0145] 1) No writing is allowed;

[0146] 2) Allow writing to port 0, cancel writing to port 1, and report an error;

[0147] 3) Both are allowed to be written, but only SRAM#0 is recorded as valid in the mapping table.

[0148] Consider a special case: writing to port 0 and port 1 at the same time to the same address, but with the same content. This is equivalent to initializing the memory system. The recommended processing strategy can be:

[0149] Both are allowed to be written, and the records in the mapping table that SRAM#0 and #1 are both valid.

[0150] Among them, there is no crossover between the above-mentioned write ports, and all are directly connected, which is more friendly to the physical implementation of the back-end layout and wiring, that is, it is easy to wire.

[0151] The above mapping relationship information can be implemented as a re-mapping table, which is used to record which SRAM the valid data of each address is located in. Taking N=2 as an example, each address is allocated 2 bits, and the definition is shown in the following Table 2:

[0152] Table 2

[0153]

[0154] Each entry in the above remapping table only requires 2 bits, which is much smaller than a large-capacity buffer. At the same time, compared with the area of ​​SRAM, the area of ​​the storage space required for the remapping table can also be ignored.

[0155] Based on the above Figure 5 or Figure 6 In some implementations of the embodiment shown, the storage controller is used to:

[0156] Obtaining a first read request received by a first read port, where the first read port is any one of the N read ports;

[0157] Based on the mapping relationship information, query the memory where the valid data stored in the second address is located; the second address is the read address of the first read request;

[0158] Read data from the second address in the queried memory;

[0159] The read data is returned through the first read port.

[0160] In the reading process, for any read request received by the read port, the memory where the valid data corresponding to the read address is located can be queried from the mapping relationship information, and the data can be read from the corresponding memory, thereby ensuring the accuracy of data query.

[0161] In some implementations, the mapping relationship information includes mapping values ​​corresponding to each address in the address space.

[0162] Based on the mapping relationship information, querying the memory where the valid data stored in the second address is located includes:

[0163] Query the mapping relationship information for a mapping value corresponding to the second address;

[0164] The memory corresponding to the mapping value is determined as the memory where the valid data stored in the second address is located.

[0165] In an embodiment of the present application, the above-mentioned mapping relationship information is represented by a mapping table, and a mapping value is set for each address. The mapping value is used to indicate in which memory the valid data stored in the corresponding address is located. This can simplify the indication method of the memory corresponding to the valid data of the address, control the data amount of the mapping relationship information, reduce the area occupied by the storage space of the mapping relationship information, and thus control the overall area of ​​the storage component. At the same time, the memory where the valid data is located can be determined through a simple mapping value, which can simplify the determination process of the valid data and ensure the efficiency of data reading.

[0166] In some implementations, a storage controller is configured to:

[0167] In response to the absence of the second read request, querying the memory where the valid data stored in the second address is located based on the mapping relationship information;

[0168] The second read request is a read request received by the second read port, the first read request and the second read request are received at the same time, and a read address of the second read request conflicts with the second address.

[0169] In an embodiment of the present application, when the storage controller obtains the first read request received through the first read port, it can detect whether other read ports have received the read request at the same time. If so, it can further detect whether the read address of the read request received by the other read ports conflicts with the read address of the first read request. If so, it is determined that the other read request is the second read request. Otherwise, it is determined that there is no second read request, that is, there is no read conflict for the first read request. When there is no read conflict for the first read request, the first read request can be executed, thereby avoiding read errors caused by reading when there is a read conflict, thereby ensuring the accuracy of data reading.

[0170] In the embodiment of the present application, a read address conflict of two or more read requests means that the memory where the valid data stored in the respective read addresses of the two or more read requests is located is the same memory.

[0171] In some implementations, the storage controller is further configured to:

[0172] In response to the second read request, one of the following operations is performed:

[0173] The first read request and the second read request are not executed; or,

[0174] One of the first read request and the second read request is executed, and the other of the first read request and the second read request is canceled.

[0175] For a canceled read request, the storage controller may also return an error response to the sender of the read request (such as an address generation unit) so that the sender of the read request may re-initiate the read or perform other processing.

[0176] In the embodiment of the present application, when a read conflict exists in the first read request, a data read error can be avoided by not executing or executing one of the read requests.

[0177] In one possible implementation, within one cycle, N read requests are first sent to the storage controller through N read ports, and the storage controller detects whether there is a conflict in the read addresses of the N read requests. If there is a conflict in the read addresses of two or more read requests, one of the read requests is taken to execute, or neither of the two or more read requests is executed.

[0178] When the storage controller determines to execute a read request, it can generate a read instruction corresponding to the read request, send the read instruction to the memory where the valid data is located, and the memory reads the corresponding data and outputs the read data through the read port that receives the read request.

[0179] In some implementations, the storage controller is further used to provide mapping relationship information to the address generation unit so that the address generation unit generates multiple read requests with non-conflicting read addresses according to the mapping relationship information, and the multiple read requests are used to be sent to different read ports among the N read ports at the same time.

[0180] In an embodiment of the present application, the above-mentioned mapping relationship information can also be provided to the address generation unit, so that the address generation unit can avoid read conflicts when generating read requests, thereby further reducing the read conflicts and improving the reading efficiency.

[0181] by Figure 5 Take the two SRAMs shown as an example:

[0182] Read port 0 can fetch data from SRAM#0 or #1;

[0183] Read port 1 can fetch data from SRAM#0 or #1.

[0184] That is, there is an intersection between the read ports, and which SRAM to fetch the required data from depends on the result of querying the remapping table based on the read address. As long as the valid value results of the read address resolution of the two read ports are distributed on two different SRAMs, there will be no bank read-read conflict.

[0185] If the valid value results of the two read ports' read address resolution are distributed on the same SRAM, possible solutions include but are not limited to:

[0186] 1) Cooperate with the address generation unit AGU to query the remapping table in advance, predict the occurrence of bank read-read conflicts before actually initiating a read request, and avoid read conflicts from the source by replacing one of the read requests to a non-conflicting address. This method is suitable for large-block memory transfer operations;

[0187] 2) If a read conflict is discovered when reaching the memory entry, the conflict is inevitable. In this case, one of the read requests (such as reading port 1) must be canceled and a feedback signal must be given to the AGU to inform it that the read port 1 request has failed. The AGU will then try to initiate the read request again through the replay mechanism.

[0188] In some embodiments, the storage system where the above storage component is located further includes an address generation unit; the address generation unit includes an address generator and a request controller.

[0189] The address generator is used to generate N read requests and write the N read requests into the request controller; the N read requests correspond to the N read ports one by one.

[0190] The request controller is used to send a first conflict query request to the storage controller, where the first conflict query request is used to query whether read addresses between N read requests conflict.

[0191] The storage controller is used to detect whether there is a conflict in the read addresses between N read requests, and return a first query result to the request controller.

[0192] The request controller is used to send the N read requests to corresponding read ports respectively when the first query result indicates that the read addresses between the N read requests do not conflict.

[0193] The request controller is also used to send one of the two or more read requests to the corresponding read port and send a retransmission indication to the address generator when the first query result indicates that the memory where the valid data stored in the read address between two or more read requests among N read requests is the same, and the retransmission indication is used to instruct the address generator to retransmit the read request that has not been sent to the read port among the two or more read requests.

[0194] Please refer to Figure 7 , which shows a schematic diagram of the structure of a storage system involved in this application. Figure 7 As shown, the storage system includes, in addition to the above storage components, an address generation unit 702; the address generation unit includes an address generator 702a and a request controller 702b; the above storage components include a storage controller 704, and N memories ( Figure 7 In the example, N=2 is used for explanation. Figure 7 In the solution shown, the value of N may also be 3 or 4, etc.), and what is not shown in the figure is that the storage component also includes N write ports and N read ports. Figure 7 In the address generation unit 702 (i.e. Figure 7 After generating read request 1 and read request 2, the AGU in the storage component queries the storage controller 704 to inquire whether there is a read-read conflict between the two read requests. The storage controller 704 returns the query result to the request controller 702b (RequestController) of the AGU:

[0195] 1) If there is no conflict, both read requests 1 and 2 are sent to the storage component;

[0196] 2) If there is a conflict, read request 1 is sent to the storage component, and read request 2 is canceled (this read request goes to read port 1 in the next beat, so there will be no continuous blocking). At the same time, the AG is notified that read request 2 has failed, and the AG is required to resend read request 2 in the next beat (optionally, the resent read request 2 can be sent to port 1, that is, to the read port of the previous read request 1).

[0197] For example: Assuming that addresses 1, 2, 3, 4, 5, and 6 are to be read, and the read-read conflict persists, the read process is as shown in Table 3 below:

[0198] Table 3

[0199]

[0200] It can be seen that even in the worst case, the read performance can reach 50% of the peak value.

[0201] In some embodiments, the storage system where the above storage component is located further includes an address generation unit; the address generation unit includes an address generator, a read request queue, and a request selector.

[0202] The address generator is used for generating a read request and writing the read request into a read request queue.

[0203] The request selector is used to send a second conflict query request to the storage controller, where the second conflict query request is used to query whether the read addresses of the read requests in the read request queue conflict with each other.

[0204] The storage controller is used to detect whether there is a conflict in the read addresses between the read requests in the read request queue, and return a second query result to the request controller.

[0205] Among them, the above-mentioned second conflicting query request may be a query request for two read requests among the multiple read requests already in the read request queue, and correspondingly, the above-mentioned second query result may be a query result for two read requests among the multiple read requests already in the read request queue; in this case, there may be multiple queries within one beat / clock cycle.

[0206] Alternatively, the second conflicting query request may be a query request for two read requests among the multiple read requests already in the read request queue, and correspondingly, the second query result may be a query result for two read requests among the multiple read requests already in the read request queue; in this case, a single query may exist within one beat / clock cycle.

[0207] A request selector is used to select at most N read requests without read address conflicts from the read request queue based on the second query result, and send the selected read requests to a read port respectively. Optionally, the address generation unit can remove the selected read request from the read request queue, for example, the request selector or the read request queue in the address generation unit can remove the selected read request from the read request queue.

[0208] Regarding the above Figure 7 The structure shown can be further considered as follows: if there are multiple read requests, two or more read requests without conflict can be found and sent to the storage component.

[0209] Essentially, this is to shuffle a series of read operations, which can improve the performance of block operations (block read), for example:

[0210] If you want to read addresses 1, 2, 3, 4, 5, and 6, and if this series of reads is considered as an atomic operation (for example, the entire block read is a complete and indivisible operation, and no other operations can be inserted in the middle), then the following two possible read orders will achieve the same final effect:

[0211] 1)1->2->3->4->5->6.

[0212] 2)1->3->2->4->5->6.

[0213] Please refer to Figure 8 , which shows a schematic diagram of the structure of a storage system involved in this application. Figure 8As shown, the storage system includes, in addition to the above storage components, an address generation unit 802; the address generation unit includes an address generator 802a, a read request queue 802b, and a request selector 802c; the above storage components include a storage controller 804, and N memories ( Figure 8 In the example, N=2 is used for explanation. Figure 8 In the solution shown, the value of N may also be 3 or 4, etc.), and what is not shown in the figure is that the storage component also includes N write ports and N read ports. Figure 8 In the address generation unit 802 (i.e. Figure 8 The address generated by the AGU in the memory first enters the read request queue 802b (Read Request Queue, RRQ), and the request selector 802c (Request Selector) selects two read requests from the queue according to certain rules and sends them to the storage controller in the storage component for query to inquire whether there is a read-read conflict between the two read requests. The storage controller returns the query result to the Request Selector of the AGU:

[0214] 1) If there is no conflict, both read requests 1 and 2 are sent to the storage component, and read requests 1 and 2 leave the RRQ at the same time;

[0215] 2) If there is a conflict, read request 1 is sent to the storage component and at the same time, read request 1 leaves the RRQ.

[0216] For conflicting read request 2, the following processing strategies are available:

[0217] 1) Send request 1 and cancel read request 2, maintain read request 2 in RRQ, and wait for the next selection by request selector 802c (for example, the next beat, or the next clock cycle);

[0218] 2) In the current beat / clock cycle, another read request 3 is selected and sent to the storage component together with request 1 to query whether there is a conflict. If there is a conflict, the replacement-query process is repeated until two non-conflicting requests are found, or until all read requests are queried;

[0219] 3) Alternatively, the above step 2) can also be replaced by: querying multiple read requests at one time, that is, sending multiple read requests to the storage component for query at one time, and the probability of finding two non-conflicting requests is very high. Even if two non-conflicting requests cannot be found, the read request of port 2 can be canceled and wait for the next selection of the selector. Therefore, multiple read requests (such as read requests 1, 2, 3, 4) can be sent to the storage component at one time to query conflicts, and two non-conflicting read requests are selected for sending according to the query results.

[0220] In some embodiments, the value of N is 2, and the storage system where the storage component is located further includes an address generation unit, a read request retransmission buffer, and a selection circuit.

[0221] The address generation unit is used to send a first read request to a first read port at a first moment, send a third read request to a third read port in a storage component through a selection circuit, and write the third read request into a read request retransmission buffer; the third read port is another read port in the storage component except the first read port.

[0222] The storage controller is used to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and execute the first read request when it is detected that the read addresses of the first read request and the third read request have a conflict.

[0223] The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict.

[0224] The read request retransmission buffer is used to remove the third read request from the read request retransmission buffer when the first conflict response indicates that the read addresses of the first read request and the third read request have no conflict.

[0225] The read request retransmission buffer is further used to send the third read request to the third read port through the selection circuit at a second moment after the first moment when the first conflict response indicates that the read addresses of the first read request and the third read request conflict. Optionally, at the second moment, the address generation unit may stop sending the read request to the first read port; or, at the second moment, the address generation unit may continue to send a new read request to the first read port.

[0226] In another implementation of the present application, the read request may also be resent through a resending mechanism, for example, please refer to Fig. 9 , which shows a schematic diagram of the structure of a storage system involved in this application. Fig. 9 As shown, when N is equal to 2, the storage system includes, in addition to the above storage components, an address generation unit 902, a read request retransmission buffer 903, and a selection circuit 904. The above storage components include a storage controller 905 and two memories. What is not shown in the figure is that the storage components also include two write ports and two read ports.

[0227] like Fig. 9As shown, in one beat / clock cycle, the read request 1 generated by the address generation unit 902 (AGU) is directly sent to the storage component. The read request 2 generated by the address generation unit 902 is sent to the storage component through the selection circuit 904, and a backup is stored in the read request resend buffer 903 (Read Replay Buffer, RRB) (RRB can be a FIFO (first-in-first-out stack)).

[0228] After the read request reaches the storage component, the storage controller 905 performs a read-read conflict check:

[0229] 1) If there is no conflict, read requests 1 and 2 are both executed normally and fed back to RRB. The backup read request 2 leaves RRB and is discarded.

[0230] 2) If there is a conflict, read request 1 is executed normally and RRB is fed back. At this time, there are two strategies for handling the conflict:

[0231] ① Process immediately. RRB can immediately notify AGU to stop generating new read requests. MUX selects the RRB path and sends the backup read request 2 to the storage component. At this time, read port 2 can monopolize the memory, so no conflict will occur.

[0232] ② Delayed processing: In fact, as long as there is still cache space in the RRB, the conflict problem can be delayed. After the AGU generates and sends all read requests, it checks whether the RRB is empty:

[0233] a) If it is empty, it means that there is no conflict in this read operation, there is no request that needs to be replayed, and the operation ends;

[0234] b) If it is not empty, it means that there is a conflict in this read operation and some read requests need to be replayed. Then MUX selects the RRB path and pops the backup read request from the RRB to the storage component. At this time, read port 2 can monopolize the memory, so no conflict will occur.

[0235] In some embodiments, the value of N is 2, and the storage system where the storage component is located further includes an address generation unit, a read request retransmission buffer, a first selection circuit, and a second selection circuit;

[0236] The address generation unit is used to, at a first moment, send a first read request to a first read port through a first selection circuit, send a third read request to a third read port in the storage component through a second selection circuit, and write the third read request into a read request retransmission buffer; the third read port is another read port in the storage component except the first read port;

[0237] A storage controller, configured to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and to execute the first read request when it is detected that the read addresses of the first read request and the third read request conflict;

[0238] The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict;

[0239] a read request retransmission buffer, configured to remove the third read request from the read request retransmission buffer if the first conflict response indicates that the read addresses of the first read request and the third read request do not conflict;

[0240] The read request retransmission buffer is also used to extract the fourth read request and the fifth read request from the read request retransmission buffer at a third moment after the first moment when the first conflict response indicates a read address conflict between the first read request and the third read request, send the fourth read request to the first read port through the first selection circuit, and send the fifth read request to the third read port through the second selection circuit.

[0241] For example, please refer to Fig.10 , which shows a schematic diagram of the structure of a storage system involved in this application. Fig.10 As shown, when N is equal to 2, the storage system includes, in addition to the above storage components, an address generation unit 1002, a read request retransmission buffer 1003, a first selection circuit 1004, and a first selection circuit 1005. The above storage components include a storage controller 1006 and two memories. What is not shown in the figure is that the storage components also include two write ports and two read ports.

[0242] like Fig.10 As shown in Fig. 9 The following improvements have been made based on the scheme shown:

[0243] 1) In the case of immediate processing, RRB immediately notifies AGU to stop generating new read request 2, but continues to generate read request 1. MUX selects the RRB path and sends the backup read request 2 to the storage component. At this time, read request 2 cannot leave RRB immediately and can only leave after no feedback conflict occurs. Otherwise, it needs to be replayed again in the next beat. In this case, you can continue to use Fig. 9 The circuit structure shown;

[0244] 2) In the case of deferred processing, if the RRB is not empty, MUX select selects the RRB path, takes out two read requests from the RRB and sends them to read ports 1 and 2 respectively. At this time, read request 2 cannot leave the RRB immediately. It can only leave after waiting for the feedback conflict to occur. Otherwise, it needs to be replayed again in the next beat.

[0245] Through the above Fig. 9 or Fig.10 With the scheme shown, the replay performance can be improved from 50% to between 50% and 100%.

[0246] In some embodiments, the read address of the read request simultaneously received by the N read ports at a first moment is the same as the write address of the write request simultaneously received by the N write ports at a second moment;

[0247] Among them, the first moment is later than the second moment.

[0248] The solution shown in the embodiment of the present application can be used in conjunction with the following projects: a read request always adapts to a write request. Taking N=2 as an example, "the addresses read by the two read ports" are always "the addresses written by the previous two write ports". For example, the storage component shown in the above embodiment of the present application can be used in projects in various scenarios such as cloud technology, artificial intelligence (AI), smart transportation, and assisted driving.

[0249] For example, the storage components shown in the above embodiments of the present application can be used in offline training scenarios of AI models, or the storage components shown in the above embodiments of the present application can be used in cloud-based reasoning scenarios of AI models, such as providing online reasoning services in the cloud for smart transportation, assisted driving and other systems.

[0250] As explained above for the memory structure, the data written from the two write ports are naturally distributed to two different SRAMs, so the data read from the two read ports are also naturally read from two different SRAMs, which means that from the outside, there is no bank read-read conflict. If a bank read-read conflict does occur, the replay mechanism can also ensure that the data can be read in the end.

[0251] This application Figure 5 or Figure 6 The circuit design involved in the embodiment shown has the following advantages:

[0252] 1) Completely avoid bank write-write conflicts, two write ports are always available (performance advantage), and no large-capacity buffer is required (cost advantage);

[0253] 2) There are no bank read-read conflicts in a specific calculation sequence;

[0254] 3) Compared with the multi-bank solution, the write port has no cross-wires and saves a lot of area (construction time and cost advantages).

[0255] Please refer to Fig.11 , which shows a flow chart of a data writing method provided by an exemplary embodiment of the present application. The method is used for a storage component and is executed by a storage controller in the storage component. The storage component may be as follows: Figure 5 or Figure 6 Any storage component shown, such as Fig.11 As shown, the method includes:

[0256] Step 1110: Obtain a first write request received by a first write port, where the first write port is any one of the N write ports.

[0257] Step 1120: Write data corresponding to the first write request into a first address in a first memory; the first memory is a memory corresponding to a first write port, and the first address is a write address of the first write request.

[0258] Step 1130: In the mapping relationship information, set the memory where the valid data stored in the first address is located as the first memory.

[0259] In some embodiments, the mapping relationship information includes mapping values ​​corresponding to respective addresses in the address space;

[0260] The step of setting the memory where the valid data stored in the first address is located as the first memory in the mapping relationship information includes:

[0261] The mapping value corresponding to the first address in the mapping relationship information is set as a first mapping value, where the first mapping value is used to indicate that the valid data stored in the first address is located in the first memory.

[0262] In some embodiments, writing the data corresponding to the first write request to the first address in the first memory includes:

[0263] In response to the absence of the second write request, writing the data corresponding to the first write request to the first address in the first memory;

[0264] The second write request is a write request received by the second write port, the first write request and the second write request are received at the same time, and a write address of the second write request is the first address.

[0265] In some embodiments, the method further comprises:

[0266] In response to the existence of the second write request, and the write content of the second write request is different from the write content of the write request, performing one of the following operations:

[0267] not executing the first write request and the second write request; or,

[0268] executing one of the first write request and the second write request, and canceling the other of the first write request and the second write request; or,

[0269] Execute the first write request and the second write request, and in the mapping relationship information, set the memory where the valid data stored in the first address is located to one of the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0270] In some embodiments, the method further comprises:

[0271] In response to the existence of the second write request and the write content of the second write request is the same as the write content of the write request, the first write request and the second write request are executed, and in the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory and the second memory; the second memory is the memory corresponding to the second write port.

[0272] In some embodiments, the method further includes: providing the mapping relationship information to an address generation unit so that the address generation unit generates multiple write requests with different write addresses according to the mapping relationship information, and the multiple write requests are used to be sent simultaneously to different write ports among the N write ports.

[0273] Please refer to Fig.12 , which shows a flow chart of a data reading method provided by an exemplary embodiment of the present application. The method is used for a storage component and is executed by a storage controller in the storage component. The storage component may be as follows: Figure 5 or Figure 6 Any storage component shown, such as Fig.12 As shown, the method includes:

[0274] Step 1210: Obtain a first read request received by a first read port, where the first read port is any one of the N read ports.

[0275] Step 1220: Based on the mapping relationship information, query the memory where the valid data stored in the second address is located; the second address is the read address of the first read request.

[0276] Step 1230: Read data from the second address in the queried memory.

[0277] Step 1240: Return the read data through the first read port.

[0278] In some embodiments, the mapping relationship information includes mapping values ​​corresponding to each address in the address space.

[0279] Based on the mapping relationship information, querying the memory where the valid data stored in the second address is located includes:

[0280] Querying the mapping relationship information for a mapping value corresponding to the second address;

[0281] The memory corresponding to the mapping value is determined as the memory where the valid data stored in the second address is located.

[0282] In some embodiments, querying the memory where the valid data stored in the second address is located based on the mapping relationship information includes:

[0283] In response to the absence of the second read request, querying the memory where the valid data stored in the second address is located based on the mapping relationship information;

[0284] The second read request is a read request received by the second read port, the first read request and the second read request are received at the same time, and a read address of the second read request is the second address.

[0285] In some embodiments, the method further comprises:

[0286] In response to the second read request, one of the following operations is performed:

[0287] not executing the first read request and the second read request; or,

[0288] One of the first read request and the second read request is executed, and the other of the first read request and the second read request is canceled.

[0289] In some embodiments, the method further includes: providing the mapping relationship information to an address generation unit so that the address generation unit generates multiple read requests with different read addresses according to the mapping relationship information, and the multiple read requests are used to be sent simultaneously to different read ports among the N read ports.

[0290] For ease of understanding, Figure 5 Taking the circuit structure shown in FIG. 1 (N=2) as an example, the following example illustrates the writing and reading process of the memory system designed by the present application:

[0291] Step 1: Initialization (optional).

[0292] A 1-bit signal is used to prompt the memory to enter the initialization mode. The same initialization value (such as 0) is written to the same address simultaneously through write port 0 and write port 1. Initialization starts from address 0 and ends at address (M-1).

[0293] After initialization, each entry value in the remapping table is set to 11, indicating that valid data exists in both SRAM#0 and #1.

[0294] Step 2: Read.

[0295] After initialization, read port 0 and read port 1 can read any address, and the data can be read normally, for example, read port 0 to read address 2, and read port 1 to read address 3.

[0296] Step 3: Write back.

[0297] After the data is processed / calculated, it is written back to memory, for example, writing to port 0 is writing to address 2, and writing to port 1 is writing to address 3. After writing is completed, the content of the remapping table is shown in Table 4 below:

[0298] Table 4

[0299] Table No. Table Value 0 11 1 11 2 01 3 10 ... ...

[0300] Among them, Table 3 shows that the valid value of address 2 is in SRAM#0, and the valid value of address 3 is in SRAM#1.

[0301] Step 4: Read again.

[0302] Read port 0 reads address 2, and read port 1 reads address 3; first query the remapping table to determine the valid value position, and then initiate the SRAM read operation. The data taken out of SRAM#0 is sent back to read port 0, and the data taken out of SRAM#1 is sent back to read port 1.

[0303] On the contrary, if read port 0 reads address 3 and read port 1 reads address 2; then similarly, first query the remapping table to determine the valid value position, and then initiate the SRAM read operation. The difference is that the data taken out of SRAM#0 is sent back to read port 1, and the data taken out of SRAM#1 is sent back to read port 0.

[0304] In the above, steps 1 and 2 can be omitted, and the operation can be started directly from step 3, that is, writing directly to memory. The writing process is also the process of initializing the remapping table.

[0305] The embodiment of the present application also provides a storage system, which includes at least one Figure 5 or Figure 6Any of the storage components shown.

[0306] In some embodiments, the above storage system further includes an address generation unit; the address generation unit includes an address generator and a request controller;

[0307] An address generator is used to generate N read requests and write the N read requests into a request controller; the N read requests correspond one to one with the N read ports;

[0308] A request controller, used for sending a first conflict query request to the storage controller, where the first conflict query request is used for querying whether read addresses between N read requests conflict;

[0309] The storage controller is used to detect whether the read addresses of the N read requests conflict, and return a first query result to the request controller;

[0310] A request controller, configured to send the N read requests to corresponding read ports respectively when the first query result indicates that the read addresses between the N read requests do not conflict;

[0311] The request controller is also used to send one of the two or more read requests to the corresponding read port and send a retransmission indication to the address generator when the first query result indicates that the memory where the valid data stored in the read address between two or more read requests among N read requests is the same, and the retransmission indication is used to instruct the address generator to retransmit the read request that has not been sent to the read port among the two or more read requests.

[0312] In some embodiments, the storage component further includes an address generation unit; the address generation unit includes an address generator, a read request queue, and a request selector;

[0313] An address generator, used for generating a read request and writing the read request into a read request queue;

[0314] A request selector, used for sending a second conflict query request to the storage controller, where the second conflict query request is used for querying whether read addresses of various read requests in the read request queue conflict with each other;

[0315] The storage controller is used to detect whether the read addresses of the read requests in the read request queue conflict with each other, and return a second query result to the request controller;

[0316] The request selector is used to select at most N read requests without read address conflicts from the read request queue based on the second query result, and send the selected read requests to a read port respectively.

[0317] In some embodiments, the value of N is 2, and the storage system further includes an address generation unit, a read request retransmission buffer, and a selection circuit;

[0318] The address generation unit is used to send the first read request to the first read port at a first moment, send the third read request to the third read port in the storage component through the selection circuit, and write the third read request into the read request retransmission buffer; the third read port is another read port in the storage component except the first read port;

[0319] A storage controller, configured to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and to execute the first read request when it is detected that the read addresses of the first read request and the third read request conflict;

[0320] The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict;

[0321] a read request retransmission buffer, configured to remove the third read request from the read request retransmission buffer if the first conflict response indicates that the read addresses of the first read request and the third read request do not conflict;

[0322] The read request retransmission buffer is further used to send the third read request to the third read port through the selection circuit at a second time after the first time when the first conflict response indicates that the read addresses of the first read request and the third read request conflict.

[0323] In some embodiments, the value of N is 2, and the storage system further includes an address generation unit, a read request retransmission buffer, a first selection circuit, and a second selection circuit;

[0324] The address generation unit is used to, at a first moment, send a first read request to a first read port through a first selection circuit, send a third read request to a third read port in the storage component through a second selection circuit, and write the third read request into a read request retransmission buffer; the third read port is another read port in the storage component except the first read port;

[0325] A storage controller, configured to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and to execute the first read request when it is detected that the read addresses of the first read request and the third read request conflict;

[0326] The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict;

[0327] a read request retransmission buffer, configured to remove the third read request from the read request retransmission buffer if the first conflict response indicates that the read addresses of the first read request and the third read request do not conflict;

[0328] The read request retransmission buffer is also used to extract the fourth read request and the fifth read request from the read request retransmission buffer at a third moment after the first moment when the first conflict response indicates a read address conflict between the first read request and the third read request, send the fourth read request to the first read port through the first selection circuit, and send the fifth read request to the third read port through the second selection circuit.

[0329] The embodiment of the present application further provides a computer device, the computer device comprising the above storage system, or comprising at least one of the above Figure 5 or Figure 6 Any of the storage components shown.

[0330] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0331] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A storage component, It is characterized in that The storage component includes: N memories, N write ports, N read ports, and a storage controller, where N is an integer greater than or equal to 2; The N memories are connected to the N write ports in a one-to-one correspondence; Each of the N memories is connected to the N read ports respectively; The N write ports and the N read ports are respectively connected to the storage controller; The N memories correspond to the same address space, and mapping relationship information is stored in the storage controller, where the mapping relationship information is used to indicate the memory where the valid data stored in each address in the address space is located.

2. The storage component according to claim 1, It is characterized in that The storage controller is used to: Obtaining a first write request received by a first write port, where the first write port is any one of the N write ports; Writing the data corresponding to the first write request into a first address in a first memory; the first memory is the memory corresponding to the first write port, and the first address is a write address of the first write request; In the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory.

3. The storage component according to claim 2, It is characterized in that The mapping relationship information includes mapping values ​​corresponding to each address in the address space; The storage controller is used to set the mapping value corresponding to the first address in the mapping relationship information to a first mapping value, wherein the first mapping value is used to indicate that the valid data stored in the first address is located in the first memory.

4. The storage component according to claim 2, It is characterized in that The storage controller is used to: In response to the absence of the second write request, writing the data corresponding to the first write request to the first address in the first memory; The second write request is a write request received by the second write port, the first write request and the second write request are received at the same time, and a write address of the second write request is the first address.

5. The storage assembly according to claim 4, It is characterized in that The storage controller is further configured to: In response to the existence of the second write request, and the write content of the second write request is different from the write content of the write request, performing one of the following operations: not executing the first write request and the second write request; or, executing one of the first write request and the second write request, and canceling the other of the first write request and the second write request; or, Execute the first write request and the second write request, and in the mapping relationship information, set the memory where the valid data stored in the first address is located to one of the first memory and the second memory; the second memory is the memory corresponding to the second write port.

6. The storage assembly according to claim 4, It is characterized in that The storage controller is further configured to: In response to the existence of the second write request and the write content of the second write request is the same as the write content of the write request, the first write request and the second write request are executed, and in the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory and the second memory; the second memory is the memory corresponding to the second write port.

7. The storage assembly according to claim 2, It is characterized in that The storage controller is further used to provide the mapping relationship information to the address generation unit so that the address generation unit generates multiple write requests with different write addresses according to the mapping relationship information, and the multiple write requests are used to be sent to different write ports among the N write ports at the same time.

8. The storage assembly according to claim 1, It is characterized in that The storage controller is used to: Obtaining a first read request received by a first read port, where the first read port is any one of the N read ports; Based on the mapping relationship information, query the memory where the valid data stored in the second address is located; The second address is a read address of the first read request; Read data from the second address in the memory obtained by querying; The read data is returned through the first read port.

9. The storage assembly according to claim 8, It is characterized in that The mapping relationship information includes mapping values ​​corresponding to each address in the address space. The storage controller is used to: Querying the mapping relationship information for a mapping value corresponding to the second address; The memory corresponding to the mapping value is determined as the memory where the valid data stored in the second address is located.

10. The storage assembly according to claim 8, It is characterized in that The storage controller is used to: In response to the absence of the second read request, querying the memory where the valid data stored in the second address is located based on the mapping relationship information; The second read request is a read request received by the second read port, the first read request and the second read request are received at the same time, and a read address of the second read request conflicts with the second address.

11. The storage assembly according to claim 10, It is characterized in that The storage controller is further configured to: In response to the second read request, one of the following operations is performed: not executing the first read request and the second read request; or, One of the first read request and the second read request is executed, and the other of the first read request and the second read request is canceled.

12. The storage assembly according to claim 8, It is characterized in that The storage controller is also used to provide the mapping relationship information to the address generation unit so that the address generation unit generates multiple read requests with non-conflicting read addresses according to the mapping relationship information, and the multiple read requests are used to be sent to different read ports among the N read ports at the same time.

13. The storage component according to any one of claims 1 to 12, It is characterized in that The read address of the read request simultaneously received by the N read ports at the first moment is the same as the write address of the write request simultaneously received by the N write ports at the second moment; The first moment is later than the second moment.

14. A method for writing data, It is characterized in that The method is executed by a storage controller in a storage component, and the storage component is a storage component according to any one of claims 1 to 13; the method comprises: Obtaining a first write request received by a first write port, where the first write port is any one of the N write ports; Writing the data corresponding to the first write request into a first address in a first memory; the first memory is the memory corresponding to the first write port, and the first address is a write address of the first write request; In the mapping relationship information, the memory where the valid data stored in the first address is located is set as the first memory.

15. A data reading method, It is characterized in that The method is executed by a storage controller in a storage component, and the storage component is a storage component according to any one of claims 1 to 13; the method comprises: Obtaining a first read request received by a first read port, where the first read port is any one of the N read ports; Based on the mapping relationship information, query the memory where the valid data stored in the second address is located; the second address is the read address of the first read request; Read data from the second address in the memory obtained by querying; The read data is returned through the first read port.

16. A storage system, It is characterized in that The storage system comprises at least one storage component according to any one of claims 1 to 13.

17. The storage system according to claim 16, It is characterized in that The storage system further includes an address generation unit; the address generation unit includes an address generator and a request controller; The address generator is used to generate N read requests and write the N read requests into the request controller; The N read requests correspond one-to-one to the N read ports; The request controller is used to send a first conflict query request to the storage controller, where the first conflict query request is used to request to query whether the read addresses between the N read requests conflict; The storage controller is used to detect whether the read addresses of the N read requests conflict, and return a first query result to the request controller; The request controller is configured to send the N read requests to the corresponding read ports respectively when the first query result indicates that the read addresses between the N read requests do not conflict; The request controller is further configured to send one of the two or more read requests to the corresponding read port and send a retransmission indication to the address generator when the first query result indicates that the memory where valid data stored in the read addresses between two or more read requests among the N read requests is the same, wherein the retransmission indication is used to instruct the address generator to retransmit the read request that has not been sent to the read port among the two or more read requests.

18. The storage system according to claim 16, It is characterized in that The storage component further includes an address generation unit; the address generation unit includes an address generator, a read request queue, and a request selector; The address generator is used to generate a read request and write the read request into the read request queue; The request selector is used to send a second conflict query request to the storage controller, where the second conflict query request is used to query whether read addresses of the read requests in the read request queue conflict with each other; The storage controller is used to detect whether the read addresses of the read requests in the read request queue conflict with each other, and return a second query result to the request controller; The request selector is used to select at most N read requests without read address conflicts from the read request queue based on the second query result, and send the selected read requests to one of the read ports respectively.

19. The storage system according to claim 16, It is characterized in that The value of N is 2, and the storage component further includes an address generation unit, a read request retransmission buffer, and a selection circuit; The address generation unit is used to send a first read request to the first read port at a first moment, send a third read request to a third read port in the storage component through the selection circuit, and write the third read request into the read request retransmission buffer; The third read port is another read port in the storage component except the first read port; The storage controller is configured to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and execute the first read request when it is detected that the read addresses of the first read request and the third read request conflict; The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict; The read request retransmission buffer is configured to remove the third read request from the read request retransmission buffer when the first conflict response indicates that there is no conflict between the read addresses of the first read request and the third read request; The read request retransmission buffer is further used to send the third read request to the third read port through the selection circuit at a second moment after the first moment when the first conflict response indicates that the read addresses of the first read request and the third read request conflict.

20. The storage system according to claim 16, It is characterized in that The value of N is 2, and the storage component further includes an address generation unit, a read request retransmission buffer, a first selection circuit and a second selection circuit; The address generation unit is used to, at a first moment, send a first read request to the first read port through the first selection circuit, send a third read request to the third read port in the storage component through the second selection circuit, and write the third read request into the read request retransmission buffer; The third read port is another read port in the storage component except the first read port; The storage controller is configured to execute the first read request and the second request when it is detected that the read addresses of the first read request and the third read request have no conflict, and execute the first read request when it is detected that the read addresses of the first read request and the third read request conflict; The storage controller is further used to send a first conflict response to the read request retransmission buffer, where the first conflict response is used to indicate whether the read addresses of the first read request and the third read request conflict; The read request retransmission buffer is configured to remove the third read request from the read request retransmission buffer when the first conflict response indicates that there is no conflict between the read addresses of the first read request and the third read request; The read request retransmission buffer is also used to extract a fourth read request and a fifth read request from the read request retransmission buffer at a third moment after the first moment when the first conflict response indicates a read address conflict between the first read request and the third read request, send the fourth read request to the first read port through the first selection circuit, and send the fifth read request to the third read port through the second selection circuit.

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