Memory system, operating method thereof, and memory controller

Abstract

The invention provides a memory system and an operation method thereof, a memory controller, and a computer readable storage medium. The memory system includes a memory device and a memory controller coupled to the memory device; the memory controller comprises a buffer, and the memory controller supports a host performance enhancement mode; the memory controller is configured to: in response to the memory controller entering a power saving mode, back-up data related to a host performance enhancement mode in a first storage area of the buffer to a second storage area; the first storage area is in a power-down state when the memory controller is in a power-saving mode, and the second storage area can retain data stored in the second storage area when the memory controller is in the power-saving mode; and in response to quitting the power saving mode, recovering the data related to the host performance enhancement mode in the second storage area to the first storage area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory system and an operating method thereof, a memory controller, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices used by people, such as solid state drives (SSDs). SSDs have been widely used in military, automotive, industrial, medical and aviation fields due to their fast read and write speed, vibration resistance, low power consumption, no noise, low heat and light weight. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a memory system and an operating method thereof, a memory controller, and a computer-readable storage medium to solve at least one problem existing in the prior art.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory system, which includes a memory device and a memory controller coupled to the memory device; the memory controller includes a cache, and the memory controller supports a host performance enhancement mode; the memory controller is configured to: in response to the memory controller entering a power saving mode, back up data related to the host performance enhancement mode in a first storage area of ​​the cache to a second storage area; the first storage area is in a power-off state when the memory controller is in the power saving mode, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode; in response to exiting the power saving mode, restore the data related to the host performance enhancement mode in the second storage area to the first storage area.

[0005] In an optional implementation, the second storage area includes an area in the cache that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in the memory device.

[0006] In an optional embodiment, the memory controller is further configured to: when the memory controller is in a power saving mode and the capacity of the area in the cache that is in a non-power-off state is greater than or equal to the capacity required to store data related to the host performance enhancement mode, back up the data related to the host performance enhancement mode in the first storage area to the area in the cache that is in a non-power-off state when the memory controller is in the power saving mode; when the memory controller is in a power saving mode and the capacity of the area in the cache that is in a non-power-off state is less than the capacity required to store data related to the host performance enhancement mode, back up the data related to the host performance enhancement mode in the first storage area to a portion of the area in the memory device.

[0007] In an optional implementation, the memory controller is configured to: compress the data related to the host performance enhancement mode in the first storage area; and store the compressed data related to the host performance enhancement mode in the second storage area.

[0008] In an optional embodiment, the memory controller is configured to: in response to exiting the power saving mode, decompress the compressed data related to the host performance enhancement mode stored in the second storage area; and store the decompressed data related to the host performance enhancement mode in the first storage area.

[0009] In an optional embodiment, the memory controller is configured to: generate a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address is an address of data related to the host performance enhancement mode in the first storage area before being backed up to the second storage area, and the second address is an address of data related to the host performance enhancement mode in the second storage area after being backed up to the second storage area; in response to exiting the power saving mode, obtain the data related to the host performance enhancement mode stored in the second address of the second storage area; according to the data mapping table, restore the data related to the host performance enhancement mode in the second storage area to the first address in the first storage area.

[0010] In an optional implementation, the memory controller is configured to enter a power saving mode after backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache to the second storage area.

[0011] In an optional implementation, the data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

[0012] In an optional implementation, the memory system includes a memory card, a solid state drive, or a universal flash memory storage.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory controller, which includes a cache and supports a host performance enhancement mode; the memory controller is configured to: in response to the memory controller entering a power saving mode, back up data related to the host performance enhancement mode in a first storage area of ​​the cache to a second storage area; the first storage area is in a power-off state when the memory controller is in the power saving mode, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode; in response to exiting the power saving mode, restore the data related to the host performance enhancement mode in the second storage area to the first storage area.

[0014] In an optional embodiment, the second storage area includes an area in the cache that is in a non-power-off state when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in a memory device coupled to the memory controller.

[0015] In a third aspect, an embodiment of the present disclosure provides an operating method for a memory system, the operating method comprising: in response to a memory controller entering a power saving mode, backing up data related to a host performance enhancement mode in a first storage area of ​​a cache of the memory controller to a second storage area; the first storage area is in a power-off state when the memory controller is in the power saving mode, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode; in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area.

[0016] In an optional implementation, the second storage area includes an area in the cache that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in the memory device.

[0017] In an optional embodiment, backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: when the memory controller is in the power saving mode and the capacity of the area in the cache that is in a non-power-off state is greater than or equal to the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to the area in the cache that is in a non-power-off state when the memory controller is in the power saving mode; when the memory controller is in the power saving mode and the capacity of the area in the cache that is in a non-power-off state is less than the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to a portion of the area in the memory device.

[0018] In an optional embodiment, backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: compressing the data related to the host performance enhancement mode in the first storage area; and storing the compressed data related to the host performance enhancement mode in the second storage area.

[0019] In an optional embodiment, in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: in response to exiting the power saving mode, decompressing the compressed data related to the host performance enhancement mode stored in the second storage area; and storing the decompressed data related to the host performance enhancement mode in the first storage area.

[0020] In an optional embodiment, in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: generating a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address is the address of the data related to the host performance enhancement mode in the first storage area before being backed up to the second storage area, and the second address is the address of the data related to the host performance enhancement mode in the second storage area after being backed up to the second storage area; in response to exiting the power saving mode, obtaining the data related to the host performance enhancement mode stored in the second address of the second storage area; and restoring the data related to the host performance enhancement mode in the second storage area to the first address of the first storage area according to the data mapping table.

[0021] In an optional implementation, the operation method further includes: after backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area, the memory controller enters the power saving mode.

[0022] In an optional implementation, the data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

[0023] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method as described in any of the above-mentioned embodiments can be implemented.

[0024] In the technical solution provided by the embodiment of the present disclosure, in response to the memory controller entering the power saving mode, the data related to the host performance enhancement mode in the first storage area of ​​the cache is backed up to the second storage area, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode, and when exiting the power saving mode, the backed-up data related to the host performance enhancement mode is restored to the first storage area. On the one hand, the integrity and continuity of the data related to the host performance enhancement mode before and after the power saving mode are guaranteed, thereby maintaining the stability of the performance of the host performance enhancement mode; on the other hand, since the memory controller does not need to re-recommend the host performance enhancement mode sub-area to the host performance enhancer after exiting the power saving mode, the performance of the memory controller can be improved; on the third hand, the time consumption of data reading and writing can be reduced, and the performance of data reading and writing can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an exemplary system having a memory system provided for embodiments of the present disclosure.

[0026] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for embodiments of the present disclosure.

[0027] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system provided for an embodiment of the present disclosure.

[0028] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for embodiments of the present disclosure.

[0029] Figure 5 A cross-sectional schematic diagram of a memory array including memory strings provided for an embodiment of the present disclosure.

[0030] Figure 6A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for embodiments of the present disclosure.

[0031] Figure 7 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure Figure 1 .

[0032] Figure 8 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure Figure 2 .

[0033] Fig. 9 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure Figure 3 .

[0034] Fig.10 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure Figure 4 .

[0035] Fig.11 A flowchart of an operating method of a memory system provided for a specific example of the present disclosure. DETAILED DESCRIPTION

[0036] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0038] In the drawings, like reference numerals refer to like elements throughout.

[0039] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system including a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking the memory system including a three-dimensional NAND memory as an example.

[0042] Figure 1 Schematic diagram of an exemplary system with a memory system provided for an embodiment of the present disclosure. In the embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , the system 100 may include a host device 101 and a memory system 102, and the memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to the memory system 102 or receive data from the memory system 102.

[0043] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101, and is configured to control the memory device 103. The memory controller 104 can manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (Compact Flash Card, CFC), a universal serial bus (Universal Serial BUS, USB) flash drive, or in other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as a solid state drive or an embedded multimedia card (EmbeddedMulti-MediaCard, eMMC).

[0044] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0045] In such Figure 2 In one example shown in , the memory controller 104 and the single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1The host device 101 in the embodiment of the present invention is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD203 is greater than the storage capacity and / or operating speed of memory card 201.

[0046] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided for an embodiment of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 103 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0047] In some embodiments, each memory cell 305 is a single level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0048] like Figure 4As shown in , each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled through a common source line (CSL) 310. In other words, all memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data can be read or written from the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0049] like Figure 4 As shown in , the memory string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or programming operation.

[0050] Figure 5 A cross-sectional schematic diagram of a memory array including memory strings provided in an embodiment of the present disclosure. Figure 5As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 that are alternately stacked in sequence, and a channel structure 403 that vertically penetrates the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0051] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as an upper selection gate line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a lower selection gate line, and the gate layer 401 extending laterally between the upper selection gate line and the lower selection gate line can serve as a word line layer.

[0052] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0053] It should be noted that, in some other embodiments, the memory array may only include the stacked structure 400 but not a substrate, and the present disclosure does not limit whether the memory array includes a substrate.

[0054] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polycrystalline silicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge capture / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0055] Return to reference Figure 4 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0056] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic unit 505, and select one or more memory strings by applying a bit line voltage generated from the voltage generator 504.

[0057] The row decoder / word line driver 503 may be configured to be controlled by the control logic unit 505, and select / deselect a memory block of the memory array 301 and select / deselect a word line of the memory block. The row decoder / word line driver 508 may also be configured to drive a word line using a word line voltage generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 may also select / deselect and drive a lower selection line and an upper selection line. As described in detail below, the row decoder / word line driver 503 is configured to perform a programming operation on a memory cell coupled to (one or more) selected word lines. The voltage generator 504 may be configured to be controlled by the control logic unit 505, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0058] The control logic unit 505 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 506 may be coupled to the control logic unit 505, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The flash memory interface 507 may be coupled to the control logic unit 505, and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic unit 505, and to buffer status information received from the control logic unit 505 and relay them to the memory controller. The flash memory interface 507 may also be coupled to the column decoder / bit line driver 502 via the data bus 508, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0059] Figure 7 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the memory system 600 includes a memory controller 601 and a memory device 602. The memory controller 601 is used to control the memory device 602 to perform read and write operations. Here, the memory controller 601 and the memory device 602 can be coupled in any suitable manner. The memory controller 601 includes a control unit 605, a buffer 607, a host I / F interface 606, a memory I / F interface 609, etc. The memory device 602 may include Figures 4 to 6 The three-dimensional NAND type memory shown.

[0060] In some embodiments, the host I / F interface 606 outputs commands, valid data (write data), etc. received from the host 700 to the internal bus 610, and sends valid data (read data) read from the memory device 602, responses from the control unit 605, etc. to the host 700. The memory I / F interface 609 controls the process of writing data, etc. to the memory device 602 and the process of reading data from the memory device 602 based on the instructions of the control unit 605. The control unit 605 controls the memory system 600 as a whole, and the control unit 605 is, for example, a central processing unit, a microprocessor unit (MPU), etc. When the control unit 605 receives a command from the host 700 via the host I / F interface 606, it performs control according to the command. For example, the control unit 605 instructs the memory I / F interface 609 to write data to the memory device 602 according to the command from the host 700. In addition, the control unit 605 instructs the memory I / F interface 609 to read data from the memory device 602 according to the command from the host 700.

[0061] In some embodiments, the memory controller 601 is configured to perform mapping management on the data stored in the memory device 602. Specifically, the memory controller 601 can update and maintain a logical address to physical address (Logical address To Physical address, L2P) mapping table, i.e., an L2P table. Each L2P entry in the L2P table can represent a mapping relationship between a logical address and a physical address. When the host 700 sends a read command including a logical address to the memory controller 601, the memory controller 601 can obtain the corresponding physical address based on the L2P table and the logical address in the read command, and read the data from the memory device 602 according to the physical address and send it to the host 700.

[0062] In some embodiments, the memory controller 601 includes a cache 607, which may include but is not limited to a static random access memory (SRAM). At the same time, the memory system 600 also includes a memory for storing the L2P table, such as a dynamic random access memory (DRAM). The memory controller 601 can quickly obtain the L2P table from the DRAM, thereby achieving higher reading efficiency.

[0063] In other embodiments, DRAM may not be set as a cache space in the memory system 600 due to considerations of package size, power consumption, and cost. In this case, since the storage space in the memory controller 601 is limited, the memory controller 601 is configured to store the L2P table, which is a secondary mapping table and occupies a large storage space, in the memory device, and only store the primary mapping table, which occupies a small storage space, in the cache 607. When the memory controller 601 receives a read command packet including a read command and a logical address, the memory controller 601 can obtain the storage location of the L2P table to be used in the memory device 602 according to the primary mapping table, and read the part of the L2P table to be used from the memory device 602, and then obtain the physical address according to the logical address and the read part of the L2P table and perform a read operation, that is, two read operations are required to read the data, resulting in low efficiency of the read operation, especially for random read operations, one random read operation may require a large number of L2P tables to be read from the memory device 602, resulting in poor performance of the random read operation.

[0064] In some embodiments, continue to refer to Figure 8 In order to solve the problems of low read operation efficiency and poor random read operation performance in the above embodiments, a system architecture including a host performance booster (HPB) 701 is proposed. Specifically, part of the storage space in the host 700 can be divided into the host performance booster 701 as a cache space for mapping data, and the memory controller 601 can send part of the mapping data to the host 700, and the host 700 can cache the mapping data in the host performance booster 701. Here, the mapping data includes an L2P table. Therefore, the host 700 can send an HPB read command packet to the memory system 600 to read data. The HPB read command packet can include a physical address of the pre-read data of the host 700, and the physical address can be obtained according to the mapping data cached in the host performance booster 701. The memory controller 601 can directly read data from the memory device 602 according to the physical address in the HPB read command packet, without reading the mapping data from the memory device 602, thereby effectively improving the efficiency of the read operation and improving the performance of the random read operation. The cache of the memory controller stores data related to the HPB. The data related to the HPB stored in the cache can be used to determine whether the mapping data cached in the host performance enhancer 701 is valid.

[0065] However, the memory controller frequently enters / exits the power saving mode during operation. When entering the power saving mode, most of the data in the cache will be lost due to power failure, including data related to the HPB. When exiting the power saving mode, due to the loss of data related to the HPB, it will be impossible to determine whether the mapping data in the host performance enhancer is valid, which may cause the mapping data in the memory device 602 to be re-recommended to the host through the memory controller in a short period of time, affecting the performance of the memory controller. In addition, frequent entry / exit of the power saving mode will also affect the performance of the HPB and the reading and writing speed of the data.

[0066] The present disclosure provides a memory system. Fig. 9 As shown, the memory system 600 includes a memory device 602 and a memory controller 601 coupled to the memory device 602; the memory controller 601 includes a cache 607, and the memory controller 601 supports a host performance enhancement mode; the memory controller 601 is configured to: in response to the memory controller 601 entering a power saving mode, back up data related to the host performance enhancement mode in a first storage area 603 of the cache 607 to a second storage area 604; the first storage area 603 is in a power-off state when the memory controller 601 is in the power saving mode, and the second storage area 604 can retain the data stored in the second storage area 604 when the memory controller 601 is in the power saving mode; in response to exiting the power saving mode, restore the data related to the host performance enhancement mode in the second storage area 604 to the first storage area 603.

[0067] In some specific examples, the memory controller 601 may be connected to a host 700 including a host performance enhancer 701. The host performance enhancer 701 may be a portion of storage space in the host 700 that is specifically reserved for caching mapping data.

[0068] In the embodiment of the present disclosure, the mapping data includes a mapping relationship from a logical address to a physical address. The logical address may be a logical block address (LBA), and the physical address may be a physical block address (PBA). The physical block address of the data corresponds to the location of the storage block where the data is located in the memory device 602.

[0069] In the embodiment of the present disclosure, under the HPB system architecture, the logical address space can be divided into multiple HPB regions, each HPB region can be divided into multiple HPB sub-regions, each HPB sub-region stores multiple L2P entries, and the HPB sub-regions cached in the host performance enhancer 701 are activated HPB sub-regions in the memory device 602, and the memory device 602 also includes unactivated HPB sub-regions. The mapping data in the HPB sub-regions in the host performance enhancer 701 corresponds to the mapping data in the activated HPB sub-regions in the memory device 602, and there is a one-to-one correspondence between the HPB sub-regions in the host performance enhancer 701 and the activated HPB sub-regions in the memory device 602.

[0070] In some embodiments, the data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

[0071] The host performance enhancement mode area list and the host performance enhancement mode sub-area list here can be understood as that the HPB areas and HPB sub-areas in the memory device 602 can be numbered, and an HPB area list corresponding to the HPB areas in the memory device 602 and an HPB sub-area list corresponding to the HPB sub-areas in the memory device 602 are formed in the buffer 607 of the memory controller 601.

[0072] The dirty unit bitmap here is used to mark whether the mapping data in the HPB sub-region in the host performance enhancer 701 is valid. One bit in the dirty unit bitmap corresponds to one HPB sub-region. In some specific examples, when the mapping data in the HPB sub-region in the memory device 602 is cached in the host performance enhancer 701, the memory controller 601 can set each bit position in the dirty unit bitmap of the HPB sub-region in the memory device 602 to 0, indicating that the mapping data in the HPB sub-region in the host performance enhancer 701 is the same as the mapping data in the corresponding HPB sub-region in the memory device 602, and the mapping data in the host performance enhancer 701 is valid. In this case, when the host 700 sends an HPB read command packet including a physical address according to the mapping data in the HPB sub-region of the host performance enhancer 701, the memory controller 601 can directly read data from the memory device 602 according to the physical address in the HPB read command packet, that is, the HPB read operation can be performed.

[0073] In some specific examples, the memory controller 601 can perform background operations such as garbage collection operations, data migration operations of the SLC buffer, read recovery operations, and wear leveling operations without a request from the host 700. The above background operations will change the physical address of the data. After the physical address of the data is changed, the mapping relationship between the logical address and the physical address will also change accordingly, and the mapping data in the corresponding HPB sub-region in the memory device 602 needs to be updated. The memory controller 601 will set the bit position corresponding to the corresponding HPB sub-region to 1 to mark the HPB sub-region as a dirty unit. When the HPB sub-region has been cached in the host performance enhancer 701, it means that the mapping data in the HPB sub-region in the host performance enhancer 701 is different from the mapping data in the corresponding HPB sub-region in the memory device 602, and the mapping data in the host performance enhancer 701 is invalid. In this case, when the host 700 sends an HPB read command packet including mapping data according to the mapping data in the HPB sub-region in the host performance enhancer 701, if the mapping data in the HPB read command packet belongs to the first HPB sub-region of the host performance enhancer 701, and the HPB sub-region in the memory device 602 corresponding to the first HPB sub-region is marked as a dirty unit, the mapping data in the first HPB sub-region is invalid, and the memory controller 601 needs to obtain the mapping data from the HPB sub-region in the memory device 602 corresponding to the first HPB sub-region to obtain the physical address corresponding to the logical address, and perform a read operation.

[0074] In the embodiment of the present disclosure, the memory controller 601 entering the power saving mode can also be understood as the memory system 600 entering the power saving mode. The memory controller 601 enters the automatic power saving (auto power saving), sleep (sleep), deep sleep (saving / sleep / deep sleep) and other states. Some firmware functions in the memory controller 601 are restricted. At this time, only a small part of the area in the cache 607 is configured to be in a non-power-off state, which can be used to continuously save data, while the data in most other areas of the cache 607 will lose power, and the data stored thereon will be lost, affecting the performance of the memory controller 601 and the HPB performance, and affecting the reading and writing speed of the data.

[0075] In the embodiment of the present disclosure, in response to the memory controller 601 entering the power saving mode, the data related to the host performance enhancement mode in the first storage area 603 of the buffer 607 is backed up to the second storage area 604, and the second storage area 604 can retain the data stored in the second storage area 604 when the memory controller 601 is in the power saving mode, and when exiting the power saving mode, the backed up data related to the host performance enhancement mode is restored to the first storage area 603. On the one hand, the integrity and continuity of the data related to the host performance enhancement mode before and after the power saving mode are guaranteed, thereby maintaining the stability of the performance of the host performance enhancement mode; on the other hand, since the memory controller 601 does not need to re-recommend the host performance enhancement mode sub-area to the host performance enhancer 701 after exiting the power saving mode, the performance of the memory controller 601 can be improved; on the other hand, the time consumption of data reading and writing can be reduced, and the performance of data reading and writing can be improved.

[0076] In some embodiments, Fig. 9 As shown, the second storage area 604 includes an area in the cache 607 that is not powered off when the memory controller 601 is in power saving mode, or Fig.10 As shown, the second storage area 604 includes a portion of the area in the memory device 602 .

[0077] It is understandable that when the memory controller 601 is in the power saving mode, not all areas in the buffer 607 are in the power-off state, and some areas remain in the non-power-off state. Therefore, when the memory controller 601 is in the power saving mode, the data related to the host performance enhancement mode in the buffer 607 can be temporarily stored in the area in the non-power-off state in the buffer 607. Alternatively, since the memory device 602 in the embodiment of the present disclosure may include a non-volatile memory device 602, the memory device 602 can retain the data stored therein even in the power-off state. Therefore, when the memory controller 601 is in the power saving mode, the data related to the host performance enhancement mode in the buffer 607 can also be temporarily stored in the memory device 602.

[0078] In some embodiments, the memory controller 601 is further configured to: when the memory controller 601 is in a power saving mode and the capacity of the area in the cache 607 that is in a non-power-off state is greater than or equal to the capacity required to store data related to the host performance enhancement mode, back up the data related to the host performance enhancement mode in the first storage area 603 to the area in the cache 607 that is in a non-power-off state when the memory controller 601 is in the power saving mode; when the memory controller 601 is in a power saving mode and the capacity of the area in the cache 607 that is in a non-power-off state is less than the capacity required to store data related to the host performance enhancement mode, back up the data related to the host performance enhancement mode in the first storage area 603 to a portion of the area in the memory device 602.

[0079] In some specific examples, when the memory controller 601 is in a power saving mode and the capacity of the area in the cache 607 that is not powered off is greater than or equal to the capacity required to store data related to the host performance enhancement mode, the data related to the host performance enhancement mode in the first storage area 603 can also be backed up to the memory device 602.

[0080] The present disclosure provides multiple embodiments for backing up the data related to the host performance enhancement mode to the buffer 607 or to the memory device 602. It is understandable that when the memory controller 601 is in the power saving mode, the capacity of the area in the buffer 607 that is not powered off is greater than or equal to the capacity required to store the data related to the host performance enhancement mode, if the data related to the host performance enhancement mode in the first storage area 603 is backed up to the area in the buffer 607 that is not powered off when the memory controller 601 is in the power saving mode, when the memory controller 601 exits the power saving mode, when it is necessary to restore the data related to the host performance enhancement mode to its position in the buffer 607 before entering the power saving mode, since it is directly transferred from a part of the buffer 607 to another part of the buffer 607, the time for data recovery can be saved and the efficiency of data recovery can be improved.

[0081] In some embodiments, the memory controller 601 is configured to: compress the data related to the host performance enhancement mode in the first storage area 603; and store the compressed data related to the host performance enhancement mode in the second storage area 604.

[0082] In the disclosed embodiment, before backing up the data related to the host performance enhancement mode to the second storage area 604, the data related to the host performance enhancement mode in the first storage area 603 is compressed, so as to save the storage space occupied by the data.

[0083] In some embodiments, the memory controller 601 is configured to: generate a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address being the address of the data related to the host performance enhancement mode in the first storage area 603 before being backed up to the second storage area 604, and the second address being the address of the data related to the host performance enhancement mode in the second storage area 604 after being backed up to the second storage area 604.

[0084] The first address and the second address here can be logical addresses or physical addresses.

[0085] In some specific examples, the specific process of compressing and backing up the data related to the host performance enhancement mode in the first storage area 603 may include: reading the data related to the host performance enhancement mode from the first storage area 603; compressing the read data related to the host performance enhancement mode; and writing the compressed data related to the host performance enhancement mode to a specified location in the second storage area 604 according to the data mapping table.

[0086] In some embodiments, the memory controller 601 is configured to: in response to exiting the power saving mode, decompress the compressed data related to the host performance enhancement mode stored in the second storage area 604; and store the decompressed data related to the host performance enhancement mode in the first storage area 603.

[0087] In some embodiments, in response to exiting the power saving mode, data related to the host performance enhancement mode stored in the second address of the second storage area 604 is obtained; according to the data mapping table, the data related to the host performance enhancement mode in the second storage area 604 is restored to the first address in the first storage area 603.

[0088] In some specific examples, the specific process of decompressing the data related to the host performance enhancement mode backed up in the second storage area 604 and restoring it to the first storage area 603 in the cache 607 includes: reading the previously backed-up data related to the host performance enhancement mode from the specified address in the second storage area 604 according to the backup situation when entering the power saving mode; decompressing the data related to the host performance enhancement mode and restoring the original data according to the data compression situation when entering the power saving mode; and restoring the decompressed data related to the host performance enhancement mode to the specified address space of the first storage area 603 according to the data mapping table.

[0089] In some embodiments, the memory controller 601 is configured to enter a power saving mode after backing up the data related to the host performance enhancement mode in the first storage area 603 of the cache 607 to the second storage area 604 .

[0090] In the embodiment of the present disclosure, the data related to the host performance enhancement mode in the first storage area 603 needs to be backed up to the second area before entering the power saving mode to avoid the loss of the data related to the host performance enhancement mode. In some specific examples, there is a waiting time after the memory controller 601 receives the command to enter the power saving mode, and the corresponding backup task can be completed during this waiting time.

[0091] In some embodiments, the memory system includes a memory card or a solid state drive or a general purpose flash storage.

[0092] Based on the similar concept as the above memory system, Figure 8 as well as Fig. 9 As shown, the present disclosure provides a memory controller 601, which includes a cache 607, and the memory controller 601 supports a host performance enhancement mode; the memory controller 601 is configured to: in response to the memory controller 601 entering a power saving mode, back up data related to the host performance enhancement mode in a first storage area 603 of the cache 607 to a second storage area 604; the first storage area 603 is in a power-off state when the memory controller 601 is in the power saving mode, and the second storage area 604 can retain the data stored in the second storage area 604 when the memory controller 601 is in the power saving mode; in response to exiting the power saving mode, restore the data related to the host performance enhancement mode in the second storage area 604 to the first storage area 603.

[0093] In some embodiments, the second storage area 604 includes an area in the cache 607 that is not powered off when the memory controller 601 is in power saving mode, or the second storage area 604 includes a portion of an area in a memory device coupled to the memory controller 601.

[0094] Other specific details about the memory controller 601 have been introduced in detail on the memory system side and will not be repeated here.

[0095] Based on a concept similar to the above-mentioned memory system, the present disclosure provides an operation method of a memory system. Fig.11 A flowchart of the operation method provided by the embodiment of the present disclosure is shown in FIG. Fig.11As shown, the operating method of the memory system includes the following steps: step S10: in response to the memory controller entering a power saving mode, backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area; the first storage area is in a power-off state when the memory controller is in the power saving mode, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode; step S20: in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area.

[0096] In some embodiments, the second storage area includes an area in the cache that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in the memory device.

[0097] In some embodiments, backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: when the memory controller is in the power saving mode and the capacity of the area in the cache that is in a non-power-off state is greater than or equal to the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to the area in the cache that is in a non-power-off state when the memory controller is in the power saving mode; when the memory controller is in the power saving mode and the capacity of the area in the cache that is in a non-power-off state is less than the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to a portion of the area in the memory device.

[0098] In some embodiments, backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: compressing the data related to the host performance enhancement mode in the first storage area; and storing the compressed data related to the host performance enhancement mode in the second storage area.

[0099] In some embodiments, in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: in response to exiting the power saving mode, decompressing the compressed data related to the host performance enhancement mode stored in the second storage area; and storing the decompressed data related to the host performance enhancement mode in the first storage area.

[0100] In some embodiments, in response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: generating a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address being the address of the data related to the host performance enhancement mode in the first storage area before being backed up to the second storage area, and the second address being the address of the data related to the host performance enhancement mode in the second storage area after being backed up to the second storage area; in response to exiting the power saving mode, obtaining the data related to the host performance enhancement mode stored in the second address of the second storage area; and restoring the data related to the host performance enhancement mode in the second storage area to the first address of the first storage area according to the data mapping table.

[0101] In some embodiments, the operating method further includes: after backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area, the memory controller entering the power saving mode.

[0102] In some embodiments, the data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

[0103] In the embodiments of the present disclosure, the operating method of the memory system can be executed by the memory controller in the memory system in any of the aforementioned embodiments. The technical effects that can be achieved by the memory system in the aforementioned embodiments can also be achieved by the operating method of the memory system, which will not be described in detail here.

[0104] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. In some embodiments, when the computer program is executed by a processor, the operating method of the memory system in any of the above embodiments can be executed.

[0105] Here, in order to implement all or part of the processes in the operation method of the above-mentioned embodiment, it can be completed by hardware related to computer program instructions, and the computer program can be stored in a computer-readable storage medium, and the execution of the computer program can include the process of the operation method in any of the above-mentioned embodiments. Among them, the computer-readable storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (HDD) or a solid state drive, etc., and the computer-readable storage medium can also include a combination of the above-mentioned multiple storage media.

[0106] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0107] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0108] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, It is characterized in that The memory system includes a memory device and a memory controller coupled to the memory device; the memory controller includes a buffer, and the memory controller supports a host performance enhancement mode; The memory controller is configured to: In response to the memory controller entering a power saving mode, backing up data related to the host performance enhancement mode in a first storage area of ​​the cache to a second storage area; The first storage area is in a power-off state when the memory controller is in a power-saving mode, and the second storage area can retain data stored in the second storage area when the memory controller is in a power-saving mode; In response to exiting the power saving mode, the data related to the host performance enhancement mode in the second storage area is restored to the first storage area.

2. The memory system according to claim 1, It is characterized in that The second storage area includes an area in the buffer that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in the memory device.

3. The memory system according to claim 1, It is characterized in that The memory controller is further configured to: When the memory controller is in the power saving mode and the capacity of the area in the buffer that is in the non-power-off state is greater than or equal to the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to the area in the buffer that is in the non-power-off state when the memory controller is in the power saving mode; When the memory controller is in power saving mode and the capacity of the area in the cache that is not powered off is smaller than the capacity required to store data related to the host performance enhancement mode, the data related to the host performance enhancement mode in the first storage area is backed up to a portion of the area in the memory device.

4. The memory system according to claim 1, It is characterized in that The memory controller is configured to: compressing the data related to the host performance enhancement mode in the first storage area; The compressed data related to the host performance enhancement mode is stored in the second storage area.

5. The memory system according to claim 4, It is characterized in that The memory controller is configured to: In response to exiting the power saving mode, decompressing the compressed data related to the host performance enhancement mode stored in the second storage area; The decompressed data related to the host performance enhancement mode is stored in the first storage area.

6. The memory system according to claim 1, It is characterized in that The memory controller is configured to: Generate a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address is an address of the data related to the host performance enhancement mode in the first storage area before being backed up to the second storage area, and the second address is an address of the data related to the host performance enhancement mode in the second storage area after being backed up to the second storage area; In response to exiting the power saving mode, acquiring data related to the host performance enhancement mode stored in the second address of the second storage area; According to the data mapping table, the data related to the host performance enhancement mode in the second storage area is restored to the first address in the first storage area.

7. The memory system according to claim 1, It is characterized in that The memory controller is configured to: After backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache to the second storage area, the memory controller enters a power saving mode.

8. The memory system according to claim 1, It is characterized in that The data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

9. The memory system according to claim 1, It is characterized in that The memory system includes a memory card or a solid state drive or a universal flash memory storage.

10. A memory controller, It is characterized in that The memory controller includes a buffer, and the memory controller supports a host performance enhancement mode; the memory controller is configured to: In response to the memory controller entering a power saving mode, backing up data related to the host performance enhancement mode in a first storage area of ​​the cache to a second storage area; The first storage area is in a power-off state when the memory controller is in a power-saving mode, and the second storage area can retain data stored in the second storage area when the memory controller is in a power-saving mode; In response to exiting the power saving mode, the data related to the host performance enhancement mode in the second storage area is restored to the first storage area.

11. The memory controller according to claim 10, It is characterized in that The second storage area includes an area in the buffer that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in a memory device coupled to the memory controller.

12. A method of operating a memory system, It is characterized in that The operation method comprises: In response to the memory controller entering a power saving mode, backing up data related to the host performance enhancement mode in a first storage area of ​​a cache of the memory controller to a second storage area; the first storage area is in a power-off state when the memory controller is in the power saving mode, and the second storage area can retain the data stored in the second storage area when the memory controller is in the power saving mode; In response to exiting the power saving mode, the data related to the host performance enhancement mode in the second storage area is restored to the first storage area.

13. The operating method according to claim 12, It is characterized in that The second storage area includes an area in the buffer that is not powered off when the memory controller is in a power saving mode, or the second storage area includes a portion of an area in the memory device.

14. The operating method according to claim 12, It is characterized in that The step of backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: When the memory controller is in the power saving mode and the capacity of the area in the buffer that is in the non-power-off state is greater than or equal to the capacity required to store the data related to the host performance enhancement mode, backing up the data related to the host performance enhancement mode in the first storage area to the area in the buffer that is in the non-power-off state when the memory controller is in the power saving mode; When the memory controller is in power saving mode and the capacity of the area in the cache that is not powered off is smaller than the capacity required to store data related to the host performance enhancement mode, the data related to the host performance enhancement mode in the first storage area is backed up to a portion of the area in the memory device.

15. The operating method according to claim 12, It is characterized in that The step of backing up the data related to the host performance enhancement mode in the first storage area of ​​the cache of the memory controller to the second storage area includes: compressing the data related to the host performance enhancement mode in the first storage area; The compressed data related to the host performance enhancement mode is stored in the second storage area.

16. The operating method according to claim 15, It is characterized in that In response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: In response to exiting the power saving mode, decompressing the compressed data related to the host performance enhancement mode stored in the second storage area; The decompressed data related to the host performance enhancement mode is stored in the first storage area.

17. The operating method according to claim 12, It is characterized in that In response to exiting the power saving mode, restoring the data related to the host performance enhancement mode in the second storage area to the first storage area includes: Generate a data mapping table; the data mapping table includes a mapping relationship between a first address and a second address, the first address is an address of the data related to the host performance enhancement mode in the first storage area before being backed up to the second storage area, and the second address is an address of the data related to the host performance enhancement mode in the second storage area after being backed up to the second storage area; In response to exiting the power saving mode, acquiring data related to the host performance enhancement mode stored in the second address of the second storage area; According to the data mapping table, the data related to the host performance enhancement mode in the second storage area is restored to the first address in the first storage area.

18. The operating method according to claim 12, It is characterized in that The operation method further includes: After backing up the data related to the host performance enhancement mode in the first storage area of ​​the buffer of the memory controller to the second storage area, the memory controller enters the power saving mode.

19. The operating method according to claim 12, It is characterized in that The data related to the host performance enhancement mode includes: a host performance enhancement mode area list, a host performance enhancement mode sub-area list, and a dirty unit bitmap.

20. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 12 to 19 can be implemented.

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