Data writing method, flash memory device and computer readable storage medium

Abstract

The embodiment of the invention relates to the field of storage device application, and discloses a data writing method, a flash memory device and a computer readable storage medium. According to the data writing method, user data written into a flash memory space is cached by setting a second cache space in a high-speed cache space; and determining the release bandwidth of the second cache space by using the average write bandwidth of the flash memory space, so that the second cache space releases the user data by using the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host, improving the write performance consistency of the host, and further improving the service quality of the flash memory device.

Description

Technical Field

[0001] The present application relates to the application field of storage devices, and in particular to a data writing method, a flash memory device and a computer-readable storage medium. Background Art

[0002] Flash memory devices refer to storage devices manufactured based on flash memory technology. Flash memory is an electronic storage medium that uses electric current to store and read data in semiconductor transistors. For example, NAND flash memory is a type of flash memory composed of multiple storage cells, each of which can store a data bit (0 or 1). Flash memory devices can be independent storage units, such as USB flash drives, solid state drives (SSDs), etc., or they can be storage modules embedded in other devices, such as eMMC or UFS storage in smartphones.

[0003] When the host writes user data to the flash memory device, the user data is usually cached through the cache space. Since the write speed and read speed of the cache space are both greater than the write speed of the flash memory space, when the host continues to write user data, the cache space will be filled with user data written by the host. At this time, since the size of the cache space is limited, it is necessary to obtain cache space by releasing user data in the cache space so that the host can continue to write user data. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0004] At present, the release of cache space is usually performed after the flash memory space is programmed. However, within the physical block, the programming time of each word line fluctuates, which causes the release speed of the cache space to fluctuate, resulting in a large fluctuation in the host write bandwidth. In addition, due to other data writing such as garbage collection within the SSD, the bandwidth fluctuation is further aggravated, resulting in insufficient consistency in the host's write performance, which in turn leads to low quality of service (QoS) of the flash memory device. Summary of the invention

[0005] The embodiment of the present application provides a data writing method to improve the write performance consistency of a host, thereby improving the service quality of a flash memory device.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a data writing method, which is applied to a flash memory device, wherein the flash memory device includes a cache space and a flash memory space, wherein the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data sent by a host, and the second cache space is used to cache user data written into the flash memory space;

[0008] Methods include:

[0009] Obtain user data sent by the host, and store the user data in the first cache space;

[0010] Writing the user data in the first cache space into the flash memory space;

[0011] After the user data is written into the flash memory space, the user data written into the flash memory space is cached in the second cache space;

[0012] Smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space;

[0013] Determine a first release bandwidth according to an average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth;

[0014] The user data in the second cache space is released according to the first released bandwidth.

[0015] In some embodiments,

[0016] The write bandwidth of the flash memory space is smoothed to obtain the average write bandwidth of the flash memory space, including:

[0017] Real-time statistics of the amount of data successfully written into the flash memory space;

[0018] After each sampling time, the data increment of the written data volume is counted to calculate the first write bandwidth corresponding to each sampling time, wherein the first write bandwidth=data increment / sampling time;

[0019] The plurality of first write bandwidths are smoothed by a smoothing algorithm to obtain an average write bandwidth.

[0020] In some embodiments,

[0021] The method also includes:

[0022] Get the current bandwidth of the flash space;

[0023] Determine whether the average write bandwidth is less than the current bandwidth of the flash memory space;

[0024] If the average write bandwidth is less than the current bandwidth, the average write bandwidth is used as the first released bandwidth;

[0025] If the average write bandwidth is greater than or equal to the current bandwidth, the sum of the current bandwidth and the feedback bandwidth is used as the first release bandwidth, where feedback bandwidth=first coefficient*user data space, where the user data space is the size of user data in the second cache space.

[0026] In some embodiments,

[0027] The method also includes:

[0028] Determine the feedback bandwidth based on the user data space, including:

[0029] Setting a waterline threshold, wherein the waterline threshold is smaller than the second cache space;

[0030] Determine whether the user data space is less than or equal to the waterline threshold;

[0031] If so, the feedback bandwidth is set to zero;

[0032] If not, the feedback bandwidth is set to the second coefficient*(user data space-waterline threshold).

[0033] In some embodiments,

[0034] Obtaining user data sent by the host and storing the user data in the first cache space includes:

[0035] Obtaining a cache application command corresponding to a write request of the host, wherein the cache application command corresponds to the current application space;

[0036] According to the cache application command, the cache space is applied for the current application space to store the user data in the first cache space, wherein the first cache space = the applied first cache space + the current application space.

[0037] In some embodiments,

[0038] After releasing the user data in the second cache space, the method further includes:

[0039] Determining a current released space, wherein the current released space is used to compensate the first cache space;

[0040] If the released space is less than the currently applied space, the cache application command is determined to be an application failure;

[0041] If the released space is greater than or equal to the current applied space, it is determined that the cache application command is successfully applied.

[0042] In some embodiments,

[0043] The method also includes:

[0044] Determine the smoothing status of the flash device based on the current conditions of the flash device and the host, including:

[0045] If the current condition satisfies the first condition, it is determined that the smoothing state of the flash memory device is the closed state, wherein the first condition includes: the write bandwidth of the host is zero, or, when the host applies for cache space from the cache space, the number of successful applications is greater than the number of failed applications, or, the write bandwidth of the host is less than the target bandwidth of the flash memory device;

[0046] If the current condition satisfies the second condition, it is determined that the smoothing state of the flash memory device is a sampling state, wherein the second condition includes: the write bandwidth of the host is not zero, and when the host applies for cache space from the cache space, the number of successful applications is less than the number of failed applications, or the write bandwidth of the host is greater than the target bandwidth of the flash memory device;

[0047] If the current condition satisfies the third condition, it is determined that the smoothing state of the flash memory device is a working state, wherein the third condition includes: a sampling time of the sampling state is greater than a preset time threshold.

[0048] In some embodiments,

[0049] The method also includes:

[0050] Switch the smooth state of the flash device, including:

[0051] When the smoothing state of the flash memory device is in the off state, if the current condition satisfies the second condition, switching the smoothing state of the flash memory device to the sampling state;

[0052] When the smoothing state of the flash memory device is in the sampling state, if the current condition satisfies the first condition, the smoothing state of the flash memory device is switched to the off state; or, if the current condition satisfies the third condition, the smoothing state of the flash memory device is switched to the working state;

[0053] When the smoothing state of the flash memory device is in the working state, if the current condition satisfies the first condition, the system state of the flash memory device is switched to the closed state.

[0054] In some embodiments,

[0055] Switching the smooth state of the flash device also includes:

[0056] When the flash device is in smooth operation,

[0057] In a first sampling period, calculating a first average write bandwidth of the flash memory space;

[0058] In a second sampling period, calculating a second average write bandwidth of the flash memory space, wherein the second sampling period is greater than the first sampling period;

[0059] If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold, the working state is switched to the closed state.

[0060] In a second aspect, an embodiment of the present application provides a flash memory device, including:

[0061] A processor and a memory, the processor is used to execute the executable program code in the memory, and when the executable program code is executed, the processor executes the instructions of the data writing method of the first aspect.

[0062] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the data writing method of the first aspect is implemented.

[0063] The beneficial effects of the embodiments of the present application are as follows: different from the prior art, the embodiments of the present application provide a data writing method, which is applied to a flash memory device, the flash memory device includes a cache space and a flash memory space, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data sent by the host, and the second cache space is used to cache user data written to the flash memory space; the method includes: obtaining user data sent by the host, and storing the user data in the first cache space; writing the user data in the first cache space to the flash memory space; after the user data is written to the flash memory space, caching the user data written to the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain the average write bandwidth of the flash memory space; determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; releasing the user data in the second cache space according to the first release bandwidth.

[0064] By setting a second cache space in the cache space to cache user data that has been written to the flash memory space, and using the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, the second cache space releases user data with the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host. The present application can improve the write performance consistency of the host, thereby improving the service quality of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0066] Figure 1 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0067] Figure 2 is a schematic diagram of a programming time provided by an embodiment of the present application;

[0068] Figure 3 It is a schematic diagram of host data writing provided by an embodiment of the present application;

[0069] Figure 4 It is a flowchart of a data writing method provided in an embodiment of the present application;

[0070] Figure 5 yes Figure 4 A detailed flow chart of step S401 in FIG.

[0071] Figure 6 is a schematic diagram of another host data writing provided by an embodiment of the present application;

[0072] Figure 7 It is a flowchart of determining whether a cache application command corresponding to a write request of a host is successfully applied, provided by an embodiment of the present application;

[0073] Figure 8 yes Figure 4 A detailed flow chart of step S404 in FIG.

[0074] Fig. 9 is a schematic diagram of a cache space release provided by an embodiment of the present application;

[0075] Fig.10 is a schematic diagram of a bandwidth feedback mechanism provided in an embodiment of the present application;

[0076] Fig.11 It is a schematic diagram of a process of determining a first released bandwidth provided by an embodiment of the present application;

[0077] Fig.12 is a schematic diagram of a waterline threshold provided in an embodiment of the present application;

[0078] Fig.13 is a schematic diagram of a flow chart of determining a feedback bandwidth provided by an embodiment of the present application;

[0079] Fig.14 It is a schematic diagram of a flow chart of determining a smoothing state of a flash memory device provided by an embodiment of the present application;

[0080] Fig.15 is a schematic diagram of a switching smoothing state provided in an embodiment of the present application;

[0081] Fig.16 It is a schematic diagram of the structure of another flash memory device provided in an embodiment of the present application.

[0082] Description of Figure Numbers:

[0083] Label name Label name 100 Flash memory devices 200 Host 110 Flash Media 120 Controller 121 processor 122 Memory 123 Flash Memory Controller 124 interface DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0085] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0086] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0087] The data writing method in the embodiment of the present application is applied to flash memory devices, such as USB flash drives, SD cards, microSD cards, CF cards, solid state drives (SSDs), etc. Flash memory devices are storage devices that use semiconductor flash memory (NAND Flash) as a medium, and their main components include flash memory media, flash memory controllers, dynamic random access memory (DRAM), etc. Among them, an important function of the flash memory controller is to perform storage operations as a driver of the flash memory chip, and its main operations include erasing, writing, and reading.

[0088] See also Figure 1 , Figure 1 It is a structural schematic diagram of a flash memory device provided in an embodiment of the present application.

[0089] like Figure 1 As shown, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 is connected to the host 200 in a wired or wireless manner to achieve data interaction.

[0090] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, NAND Flash, Flash memory or Flash particles. It is a type of storage device and a non-volatile memory that can store data for a long time even without current supply. Its storage characteristics are equivalent to those of a hard disk, making flash memory medium 110 the basis of storage media for various portable digital devices.

[0091] The controller 120 includes a processor 121 , a memory 122 , a flash memory controller 123 and an interface 124 .

[0092] The processor 121 is connected to the memory 122, the flash controller 123 and the interface 124 respectively, wherein the processor 121 and the memory 122, the flash controller 123 and the interface 124 can be connected via a bus or other means, and the processor is used to run the non-volatile software program, instructions and modules stored in the memory 122, so as to implement any one of the method embodiments of the present application. On this basis, through firmware development, it is also responsible for the core processing of the flash translation layer (FTL).

[0093] The memory 122 is mainly used to cache the read / write instructions sent by the host 200 , and to cache the read data or write data obtained from the flash memory medium 110 according to the read / write instructions sent by the host 200 .

[0094] The flash memory controller 123 is connected to the flash memory medium 110 , the processor 121 and the memory 122 , and is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110 .

[0095] Interface 124 connects the host 200, the processor 121 and the memory 122, and is used to receive data sent by the host 200, or receive data sent by the processor 121 to realize data transmission between the host 200 and the processor 121. Interface 124 can be a SATA-2 interface, a SATA-3 interface, a SAS interface, an MSATA interface, a PCI-E interface, a NGFF interface, a CFast interface, an SFF-8639 interface and an M.2NVME / SATA protocol.

[0096] At present, with the development of NAND Flash manufacturing technology, the number of Flash stacking layers is increasing, and the number of physical pages (Page) inside the physical block (Block) is increasing. For example, a physical block of mainstream Flash includes more than 4,000 Pages.

[0097] It is understandable that since Flash is programmed according to word lines, a word line contains multiple pages, for example: SLC contains one page; MLC contains 2 pages; TLC contains 3 pages; QLC contains 4 pages. Therefore, for a block including more than 4,000 pages, a block needs to be programmed more than 1,000 times to complete. In addition, for some NAND, such as QLC NAND, a word line needs to be programmed twice before the data is programmed, making the number of programming times to complete a block even higher.

[0098] Assume that the program time of a word line is tProgram, and tProgram is in milliseconds. For example, the tProgram of TLC Nand is between 1 and 2ms, and the tProgram of QLC Nand is between 6 and 9ms. At this time, it takes seconds to write a block. TLC Nand needs to program 1000 times, and tProgram is 1.5ms. It takes 1.5s to write a block. QLC Nand needs to program 2000 times, and tProgram is 7ms. It takes 10.5s to write a block.

[0099] When the host writes user data to the flash memory device, the user data is usually cached through the cache space. Since the write speed and read speed of the cache space are both greater than the write speed of the flash memory space, when the host continues to write user data, the cache space will be filled with user data written by the host. At this time, since the size of the cache space is limited, it is necessary to obtain cache space by releasing user data in the cache space so that the host can continue to write user data. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0100] At present, the release of cache space is usually performed after the flash memory space is programmed. However, within the physical block, the Program time of each word line fluctuates, that is, the tProgram of each word line fluctuates. Taking QLC Nand as an example, assuming that a block includes 5544 pages, each word line needs to be programmed twice.

[0101] See also Figure 2 , Figure 2 It is a schematic diagram of programming time provided in an embodiment of the present application.

[0102] like Figure 2 As shown, the horizontal axis is the number of Pages, and the vertical axis is the programming time (tProgram), where Figure 2 The statistics of tProgram for the second program show that tProgram is between 4.6ms and 6ms, which causes periodic fluctuations in the performance bandwidth of the Host, even with a fluctuation range of more than 20%.

[0103] That is to say, within the physical block, the Program time of each word line fluctuates, which causes the release speed of the cache space to fluctuate, resulting in large fluctuations in the host write bandwidth. In addition, due to other data writing such as garbage collection within the SSD, the bandwidth fluctuation is further aggravated, resulting in insufficient consistency in the host's write performance, which in turn leads to low service quality of the flash memory device.

[0104] Please refer to Figure 3 , Figure 3 This is a schematic diagram of host data writing provided by an embodiment of the present application.

[0105] like Figure 3 As shown, host data is written into a cache space. For example, the host writes data A into the cache space, and the cache space writes data A into a flash memory space, i.e., a flash array. After data A is successfully written into the flash array, data A' in the cache space corresponding to data A is released.

[0106] Specifically, the host data writing includes the following steps (1) to (3):

[0107] Step (1): Host data is written to the cache space.

[0108] Among them, the cache space (Cache) includes storage media such as synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDRAM), and single-level cell NAND flash (Single-Level Cell NAND Flash, SLC NAND Flash).

[0109] Step (2): Write the host data to the flash memory space.

[0110] Specifically, the data in the cache space is written to the flash memory space through firmware processing. The flash memory space includes a flash array (Flash Array), and the flash array includes storage media such as MLC NAND Flash, TLC NAND Flash, and QLC NAND Flash.

[0111] Step (3): After the data is successfully written into the flash memory space, the cache space is released.

[0112] Specifically, after data A is successfully written into the Flash Array, data A' in the cache space corresponding to data A is released.

[0113] It is understandable that when the host writes user data to the flash memory device, the user data is usually cached through the cache space. Since the write speed and read speed of the cache space are greater than the write speed of the flash memory space, when the host continues to write user data, the cache space will be filled with user data written by the host. At this time, since the size of the cache space is limited, it is necessary to obtain cache space by releasing user data in the cache space so that the host can continue to write user data. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0114] The above method is to release the cache space after the data is successfully written into the flash memory space and the programming is completed. However, within the physical block, the Program time of each word line fluctuates, which causes the release speed of the cache space to fluctuate, resulting in a large fluctuation in the host write bandwidth. In addition, due to other data writing such as garbage collection within the SSD, the bandwidth fluctuation is further aggravated, resulting in insufficient consistency in the host's write performance, which in turn leads to low quality of service (QoS) of the flash memory device.

[0115] Based on this, an embodiment of the present application provides a data writing method, which caches user data that has been written to the flash memory space by setting a second cache space in the cache space, and uses the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, so that the second cache space releases user data with the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuations of the host. The present application can improve the write performance consistency of the host, thereby improving the service quality of the flash memory device.

[0116] For details, please refer to Figure 4 , Figure 4It is a flowchart of a data writing method provided in an embodiment of the present application.

[0117] The data writing method is applied to a flash memory device, and specifically, to at least one processor of the flash memory device. The execution subject of the data writing method is at least one processor of the flash memory device.

[0118] like Figure 4 As shown, the data writing method includes the following steps S401 to S406:

[0119] Step S401: Obtain user data sent by the host, and store the user data in a first cache space.

[0120] Specifically, the flash memory device obtains user data sent by the host, and the flash memory device includes a cache space, and the cache space includes a first cache space. After receiving the user data sent by the host, the flash memory device caches the user data in the cache space. Specifically, the user data is cached in the first cache space of the cache space, wherein the first cache space is used to cache the user data sent by the host.

[0121] Please refer to Figure 5 , Figure 5 yes Figure 4 A detailed flowchart of step S401 in FIG.

[0122] like Figure 5 As shown, the step S401, obtaining the user data sent by the host and storing the user data in the first cache space, includes the following steps S4011-S4012:

[0123] Step S4011: Obtain a cache application command corresponding to the host's write request.

[0124] Specifically, the host sends a write request, which corresponds to a cache application command, so that the flash memory device receives the cache application command, wherein the cache application command is used to apply for cache space to cache user data corresponding to the write request, wherein the cache application command corresponds to the current application space.

[0125] Step S4012: According to the cache application command, apply for the current application space from the cache space to store the user data in the first cache space.

[0126] Specifically, after receiving the cache application command, the flash memory device applies to the cache space for the current application space corresponding to the cache application command, wherein the first cache space=the applied first cache space+the current application space.

[0127] Step S402: writing the user data in the first cache space into the flash memory space.

[0128] Specifically, after the flash memory device caches the user data sent by the host in the first cache space, the user data in the first cache space is written into the flash memory space, that is, the user data in the first cache space is sent to the flash memory space, so that the flash memory space stores the user data.

[0129] Step S403: After the user data is written into the flash memory space, the user data written into the flash memory space is cached in the second cache space.

[0130] Specifically, the cache space also includes a first cache space. After the user data is flushed from the first cache space to the flash memory space, the flash memory space needs to program the data to write it to the flash memory array of the flash memory space. After the user data is successfully written to the flash memory array of the flash memory space, the user data written to the flash memory space is cached in the second cache space of the cache space, wherein the second cache space is used to cache the user data written to the flash memory space.

[0131] In the embodiment of the present application, the Flashprogram completion status can be checked through the Ready / busy pin of the Nand flash, or the status of the Nand flash can be checked through the register to determine whether the user data is successfully written into the flash array (Flash Array) of the flash space.

[0132] See also Figure 6 , Figure 6 This is a schematic diagram of another host data writing provided by an embodiment of the present application.

[0133] like Figure 6 As shown, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data written by the host, and the second cache space is used to cache user data written into the flash memory space. For example, user data A written by the host is stored in the first cache space, and then the user data A in the first cache space is programmed (Program) and written into the flash memory array of the flash memory space. After the user data A is successfully written into the flash memory array, the user data A' in the second cache space is released from the second cache space to supplement the released cache space to the first cache space.

[0134] Specifically, assume that the first cache space is Cache total The space requested by the cache request command corresponding to the host's write request is recorded as Cache alloc , that is, the space requested by the host is recorded as Cache alloc , the space not requested by the host is recorded as Cache free, the cache in the second cache space (Rsv cache) is recorded as Cache rsv .

[0135] The following describes the change process of the cache space, including the following steps (1) to (3):

[0136] (1) When a host write request occurs, the host applies for cache to store user data. Assume that the size of the user data is denoted as Size. data At this time, Cache alloc Increase Size data , Cache free Reduce Size data , Cache alloc +Cache free =Cache total .

[0137] (2) As user data is continuously written, the cache free The write speed of the Flash is lower than the write speed of the Cache, that is, the write speed of the Flash space is lower than the write speed of the Cache space. free The rate of increase is equal to the host write rate.

[0138] (3) In Size data The corresponding data is successfully written to the flash memory space, that is, after Program is done, Cache rsv Increase Size data , Cache free No change, still satisfying Cache alloc +Cache free =Cache total .

[0139] (4) Based on the smoothed average bandwidth, the user data in the second cache space is released to compensate for the first cache space, that is, the cache is released. rsv To add to the Cache free , making Cache rsv Reduce, Cache free Increase, and realize the release from cache A' to buffer A".

[0140] Furthermore, in Cache freeWhen it decreases to 0, the second cache space needs to release user data to compensate the first cache space, so that the first cache space can continue to be used to meet the cache application of the host.

[0141] For details, please refer to Figure 7 , Figure 7 It is a flowchart provided by an embodiment of the present application for determining whether a cache application command corresponding to a write request of a host is successfully applied.

[0142] like Figure 7 As shown, the process of determining whether the cache application command corresponding to the host's write request is successfully applied includes the following steps S701 to S703:

[0143] Step S701: Determine the current freed space.

[0144] Specifically, after the user data in the second cache space is released, the current released space is determined, wherein the current released space is used to compensate the first cache space, so that the first cache space continues to be used to satisfy the cache application of the host.

[0145] Step S702: Determine whether the released space is smaller than the currently applied space.

[0146] If the released space is smaller than the currently applied space, the process proceeds to step S703.

[0147] If the released space is greater than or equal to the currently applied space, the process proceeds to step S704.

[0148] Step S703: Determine that the cache application command is an application failure;

[0149] It is understandable that if the current application space corresponding to the cache application command is larger than the released space of the second cache space, the free space in the first cache space is insufficient to satisfy the cache application command, and the cache application command is determined to be an application failure.

[0150] Step S704: Determine whether the cache application command is successfully applied.

[0151] If the released space is greater than or equal to the current applied space, it is determined that the cache application command is successfully applied.

[0152] Step S404: smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space.

[0153] It can be understood that the write bandwidth of the flash memory space is real-time, and the corresponding write bandwidth at different times is different. Therefore, the embodiment of the present application smoothes the write bandwidth of the flash memory space to obtain the average write bandwidth of the flash memory space, and characterizes the write bandwidth of the flash memory space by the average write bandwidth of the flash memory space.

[0154] Please refer to Figure 8 , Figure 8 yes Figure 4 A detailed flowchart of step S404 in FIG.

[0155] like Figure 8 As shown, step S404: smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space includes the following steps S4041 to S4043:

[0156] Step S4041: Real-time statistics of the amount of data written into the flash memory space successfully;

[0157] Specifically, the amount of data written successfully to the flash memory space is sampled, that is, the amount of data completed by the Program is sampled. It can be understood that as data is continuously written, the amount of written data increases over time.

[0158] Step S4042: after each sampling time, counting the data increment of the written data amount to calculate the first write bandwidth corresponding to each sampling time;

[0159] Specifically, the first write bandwidth = data increment / sampling time. For example, at the first moment, the statistical amount of written data is X 1 After 100ms, the amount of written data is X 2 , then within 100ms, the data increment of the written data volume is X 2 -X 1 , at this time, the first write bandwidth is (X 2 -X 1 ) / 100ms.

[0160] For example: In the recent period of time T 1 Inside, T 1 It includes multiple sampling times, that is, sampling periods. For example, if the sampling time is 100 ms, the first write bandwidth is calculated every 100 ms. Through the multiple sampling times, the first write bandwidths corresponding to the multiple sampling times are continuously calculated, thereby obtaining multiple write bandwidths.

[0161] Step S4043: smoothing the plurality of first write bandwidths using a smoothing algorithm to obtain an average write bandwidth.

[0162] Specifically, multiple first write bandwidths are smoothed by a smoothing algorithm, and the smoothing algorithm includes a moving average method (Moving Average), a median filter (Median Filtering), a local weighted regression smoothing, a Gaussian smoothing (Gaussian Smoothing), a weighted regression, a box smoothing (Box Smoothing), an exponential smoothing method (Exponential Smoothing) and the like. For example, the smoothing algorithm is a first-order lag filtering algorithm in the exponential smoothing method, wherein the calculation method of the first-order lag filtering algorithm is as follows:

[0163] BW avg =BW avg *(1-a)+BW*a

[0164] Among them, BW avg is the average write bandwidth, a is the coefficient, and BW is the first write bandwidth.

[0165] Alternatively, a ring queue is used to record bandwidth data of the last period of time, that is, multiple first write bandwidths of the last period of time, and an average of the multiple first write bandwidths is taken to obtain an average write bandwidth.

[0166] It is understandable that the smaller the value of a is, the better the smoothing effect is and the longer the sampling period is. However, at this time, the average value change of the first write bandwidth BW will respond more slowly to the fluctuation of BW. For example, if a block takes 10 seconds to be fully written and the sampling period is 100ms, a=1 / 64 can be taken.

[0167] In the embodiment of the present application, historical bandwidths are sampled and a smoothing algorithm is used to smooth multiple historical bandwidths, so that the released bandwidth of the cache space can be better determined.

[0168] Step S405: determining a first release bandwidth according to the average write bandwidth of the flash memory space.

[0169] Specifically, the first release bandwidth is equal to the average write bandwidth BW avg That is, the average write bandwidth of the flash memory space is used as the first release bandwidth, wherein the first release bandwidth is used to characterize the release speed of the user data in the second cache space.

[0170] Step S406: releasing the user data in the second cache space according to the first released bandwidth.

[0171] Specifically, the user data in the second cache space is released using the first released bandwidth.

[0172] In an embodiment of the present application, a second cache space is set in the cache space to cache user data that has been written to the flash memory space, and the average write bandwidth of the flash memory space is used to determine the release bandwidth of the second cache space, so that the second cache space releases user data with the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host. The present application can improve the write performance consistency of the host, thereby improving the service quality of the flash memory device.

[0173] It is understandable that the Flash bandwidth BW is reduced by the smoothing algorithm. Flash Take samples and calculate the average write bandwidth BW avg , with the average write bandwidth BW avg As the release bandwidth, the second cache space is released, so that the host's write bandwidth BW host =BW avg .

[0174] See also Fig. 9 , Fig. 9 This is a schematic diagram of cache space release provided in an embodiment of the present application.

[0175] like Fig. 9 As shown, the host writes user data to the first cache space (Cache), writes the user data in the first cache space (Cache) to the Flash Array, and samples the bandwidth BW of the Flash Array in real time. Flash , and calculate the average write bandwidth BW avg , with the average write bandwidth BW avg To release the second cache space (Rsv Cache), and compensate the released space to the first cache space (Cache).

[0176] However, when sampling Flash bandwidth BW Flash When the bandwidth is released, a sampling error may occur, resulting in the performance of the entire disk being lower than the actual performance of the flash memory space. Based on this, the present application further proposes a feedback mechanism to adjust the released bandwidth to obtain the adjusted released bandwidth.

[0177] For details, please refer to Fig.10 , Fig.10 It is a schematic diagram of a bandwidth feedback mechanism provided in an embodiment of the present application.

[0178] like Fig.10 As shown, the bandwidth BW of the flash array is sampled in real time. Flash , and calculate the average write bandwidth BW avg Then, using the feedback bandwidth (BW fd) compensates the average write bandwidth to obtain the adjusted first released bandwidth, so that the host's write bandwidth (BW host ) is equal to the first released bandwidth after adjustment.

[0179] For details, please refer to Fig.11 , Fig.11 This is a schematic diagram of a process for determining a first released bandwidth provided by an embodiment of the present application.

[0180] like Fig.11 As shown, the process of determining the first released bandwidth includes the following steps S1101 to S1104:

[0181] Step S1101: obtaining the current bandwidth of the flash memory space;

[0182] Specifically, the current bandwidth of the flash memory space is the current write bandwidth of the flash memory space. The data increment of the amount of data written within the sampling time is counted in real time, and the current bandwidth BW of the flash memory space is calculated within the sampling time. Flash , where current bandwidth = BW Flash = Data increment of the amount of data written within the sampling time / sampling time.

[0183] Step S1102: determine whether the average write bandwidth is less than the current bandwidth of the flash memory space.

[0184] Specifically, determine the average write bandwidth BW avg Is it less than the current bandwidth BW of the flash space? Flash , if so, proceed to step S1103; if not, proceed to step S1104.

[0185] It is understandable that if the average write bandwidth BW avg Greater than or equal to the current bandwidth BW of the flash space Flash , then the average write bandwidth BW avg Will converge to BW through the smoothing algorithm Flash .

[0186] If the average write bandwidth BW avg Less than the current bandwidth BW Flash , since the second cache space uses the average write bandwidth as the release bandwidth, the amount of data written will be greater than the amount of data released, and the user data space in the second cache space will be greater than the released space compensated to the first cache space, so that part of the user data space (program done cache) still exists in the second cache space, that is, BW flash -BW avg The program done cache will first be stored in the second cache space (Rsv cache), and the amount of stored data will increase over time.

[0187] In view of this, the average write bandwidth BW avg Greater than the current bandwidth BW Flash Under the condition of Flash Based on this, a feedback bandwidth (FeedBack BW, BW fd ) to adjust the current bandwidth BW Flash Compensation is performed, and the compensated bandwidth is used as the first released bandwidth.

[0188] Step S1103: taking the average write bandwidth as the first released bandwidth.

[0189] It is understandable that the average write bandwidth BW avg Less than the current bandwidth BW Flash When the average write bandwidth is directly used as the first release bandwidth, the user data in the second cache space is released through the first release bandwidth.

[0190] Step S1104: taking the sum of the current bandwidth and the feedback bandwidth as the first released bandwidth.

[0191] Specifically, if the average write bandwidth BW avg Greater than or equal to the current bandwidth BW Flash , then the sum of the current bandwidth and the feedback bandwidth is taken as the first released bandwidth, that is, the first released bandwidth = current bandwidth BW Flash +Feedback Bandwidth BW fd , so as to release the user data in the second cache space through the updated first release bandwidth.

[0192] In the embodiment of the present application, feedback bandwidth=first coefficient*user data space, where the user data space is the size of the user data in the second cache space.

[0193] Specifically, the user data space is the user data in the second cache space that has been successfully written into the flash memory space, that is, the user data of the completed program stored in the Rsv cache. The first coefficient can be set according to actual needs, or calibrated according to experimental results.

[0194] In an embodiment of the present application, through a feedback mechanism, that is, under the condition that the average write bandwidth is greater than or equal to the current bandwidth of the flash memory space, the current bandwidth is compensated by feedback bandwidth, which can better solve the performance problems caused by sampling errors and correct smaller performance evaluation errors, thereby better improving the host's write performance consistency and further improving the service quality of the flash memory device.

[0195] Furthermore, based on the feedback mechanism, the embodiment of the present application provides a waterline mechanism.

[0196] It can be understood that the user data in the second cache space will be released. Therefore, the size of the user data in the second cache space is dynamically changed, that is, the user data space is dynamically changed. The user data space is the size of the data successfully written to the flash memory space, that is, the cache stored in the second cache space (Rsv cache) of the completed program, recorded as Cache rsv .

[0197] In the embodiment of the present application, through the user data space Cache rsv The feedback bandwidth is determined by the relationship with the waterline threshold.

[0198] Please refer to Fig.12 , Fig.12 is a schematic diagram of a waterline threshold provided in an embodiment of the present application;

[0199] like Fig.12 As shown, the waterline threshold (water line) is smaller than the size of the second cache space (Rsv cache).

[0200] For details, please refer to Fig.13 , Fig.13 This is a flow chart of determining feedback bandwidth provided in an embodiment of the present application.

[0201] like Fig.13 As shown, the process of determining the feedback bandwidth includes the following steps S1301 to S1304:

[0202] Step S1301: Setting the waterline threshold.

[0203] Among them, Cache waterLine The waterline threshold is smaller than the size of the second cache space.

[0204] Step S1302: Determine whether the user data space is less than or equal to the waterline threshold.

[0205] Specifically, determine whether the user data space is less than or equal to the waterline threshold. If so, proceed to step S1303; if not, proceed to step S1304.

[0206] Step S1303: Set the feedback bandwidth to zero.

[0207] Specifically, if the user data space is less than or equal to the waterline threshold, the feedback bandwidth is set to zero.

[0208] Step S1304: Set the feedback bandwidth to the second coefficient*(user data space-waterline threshold).

[0209] Specifically, if the user data space is larger than the waterline threshold, the feedback bandwidth is set to the second coefficient*(user data space-waterline threshold).

[0210] In the embodiment of the present application, the feedback bandwidth BW fd = b*MAX(0, Cache rsv -Cache waterLine ), where b is the second coefficient, MAX(0, Cache rsv -Cache waterLine ) refers to 0 and (Cache rsv -Cache waterLine ), for example:

[0211] If the difference between the user data space and the waterline threshold is greater than 0, that is, Cache rsv -Cache waterLine > 0, then feedback bandwidth = b*(Cache rsv -Cache waterLine ).

[0212] If the difference between the user data space and the waterline threshold is less than or equal to 0, the Cache rsv -Cache waterLine ≤0, then feedback bandwidth = b*0 = 0.

[0213] In the embodiment of the present application, the second coefficient may be equal to the first coefficient, or may not be equal to the first coefficient. The second coefficient may be set according to actual needs, or may be calibrated according to experimental results.

[0214] It is understandable that without a waterline threshold Cache waterLine Cache rsv It is based on 0, that is, BW fd =a*Cache rsv , in Cache rsv When it is 0, no feedback compensation is required, and when the performance drops, the cache for compensation is limited. waterLine , making BW fd = b*MAX(0, Cache rsv -Cache waterLine ), when the current bandwidth is less than the average bandwidth, Cache rsv There will be more Cache to compensate.

[0215] For example: Fig.12 As shown, Cache waterLine Take 10MB. If the current bandwidth is greater than the average bandwidth, when the cachersv When the size is less than 10MB, that is, the user data space does not exceed the dotted line, no feedback compensation is required and the data will be stored in the cache. rsv Inside; and in Cache rsv When the user data space exceeds the dotted line, feedback compensation is performed to increase the cache. rsv The speed of release.

[0216] It is understandable that the waterline threshold Cache waterLine The bigger the better, which can compensate for more performance degradation, but the cache is also constrained by cost. The waterline threshold needs to be selected based on cost and smoothing effect in actual use.

[0217] In the embodiment of the present application, the Cache is implemented through the waterline mechanism. rsv Smaller than Cache waterLine No feedback compensation is needed, so that more cache can be stored in the second cache space (Rsv cache), which can better achieve the performance lower than BW avg Compensation is made when.

[0218] It is understandable that before sampling the current bandwidth of the flash memory space, due to the lack of evaluation of the write bandwidth of the flash memory space, it is temporarily impossible to smooth the write bandwidth of the flash memory space. However, in the application scenario of the flash memory device, there is a situation where the write bandwidth of the host is lower than the bandwidth capacity of the flash memory device. For example, the write bandwidth capacity of the SSD is 2GB / s, but the write bandwidth of the host is only 300MB / s. In this case, no smoothing is required.

[0219] Therefore, the embodiment of the present application further determines the smoothing state of the flash memory device according to the current conditions of the flash memory device and the host to adapt to different application scenarios, thereby enabling fast response to different IO models to complete sampling (ramp up).

[0220] For details, please refer to Fig.14 , Fig.14 It is a flowchart of determining the smoothing state of a flash memory device provided in an embodiment of the present application.

[0221] like Fig.14 As shown, determining the smoothing state of the flash memory device includes the following steps S1401 to S1404:

[0222] Step S1401: Obtain the current conditions of the flash memory device and the host.

[0223] Specifically, the smoothing state of the flash memory device includes a closed state, a sampling state, and a working state.

[0224] Step S1402: If the current condition satisfies the first condition, it is determined that the smoothing state of the flash memory device is an off state.

[0225] It is understandable that if the smoothing state of the flash memory device is off (State off ), then no smoothing is required.

[0226] Specifically, the first condition includes that the host's write bandwidth is zero, or, when the host applies for cache space from the cache space, the number of successful applications is greater than the number of failed applications, or, the host's write bandwidth is less than the target bandwidth of the flash memory device.

[0227] The first condition includes the following three situations, and only at least one of the following three situations needs to be met:

[0228] (1) The host's write bandwidth is zero.

[0229] Specifically, the host's write bandwidth is zero, which means that the host does not send a write request to the flash memory device, so that the host does not need to write user data to the flash memory device. At this time, the host's write bandwidth is zero, that is, Host write is 0.

[0230] (2) When the host applies for cache space from the cache space, the number of successful applications is greater than the number of failed applications.

[0231] Specifically, when the host sends a cache application command to the flash memory device, the number of successful applications and failed applications is counted. If the number of successful applications is greater than the number of failed applications, the first condition is met.

[0232] Further, if the number of successes is much greater than the number of failures, the first condition is met, for example: a first ratio of the number of successes to the number of failures is calculated, the first ratio = number of successes / number of failures, if the first ratio is greater than a preset coefficient, it is determined that the first condition is met. In the embodiment of the present application, the preset coefficient can be set according to actual needs, or calibrated according to experimental results, for example: the preset coefficient is set to 100.

[0233] (3) The host's write bandwidth is less than the target bandwidth of the flash device.

[0234] Specifically, the target bandwidth of the flash memory device refers to the maximum bandwidth of the flash memory device. If the host's write bandwidth is less than the target bandwidth of the flash memory device, it means that the host's write speed cannot keep up with the write speed of the flash memory space. At this time, there is no need to smooth the write bandwidth of the flash memory device.

[0235] Step S1403: If the current condition satisfies the second condition, it is determined that the smoothing state of the flash memory device is a sampling state.

[0236] It is understandable that if the smoothing state of the flash memory device is the sampling state (State ramp ), the bandwidth is not limited, and the write bandwidth of the flash memory space needs to be sampled.

[0237] Specifically, the second condition includes that the host's write bandwidth is not zero, and when the host applies for cache space from the cache space, the number of successful applications is less than the number of failed applications, or the host's write bandwidth is greater than the target bandwidth of the flash memory device.

[0238] The first condition includes the following three conditions, and the following three conditions need to be met at the same time:

[0239] (1) The host's write bandwidth is not zero.

[0240] Specifically, the host write bandwidth is not zero, which means that the host sends a write request to the flash memory device, so that the host needs to write user data to the flash memory device. At this time, the host write bandwidth is not zero, that is, Host write is not 0.

[0241] (2) When the host applies for cache space from the cache space, the number of successful applications is less than the number of failed applications.

[0242] Specifically, when the host sends a cache request command to the flash memory device, the number of successful requests and failed requests is counted. If the number of successful requests is less than the number of failed requests, point (2) is satisfied.

[0243] Further, if the first ratio of the number of successes to the number of failures is less than the preset coefficient, point (2) is satisfied. Wherein, the first ratio = number of successes / number of failures. In the embodiment of the present application, the preset coefficient can be set according to actual needs, or calibrated according to experimental results, for example, the preset coefficient is set to 100.

[0244] (3) The host's write bandwidth is greater than the target bandwidth of the flash device.

[0245] Specifically, the target bandwidth of the flash memory device refers to the maximum bandwidth of the flash memory device. If the write bandwidth of the host is greater than the target bandwidth of the flash memory device, it means that the write speed of the host is greater than the write speed of the flash memory space. At this time, the write bandwidth of the flash memory device needs to be smoothed.

[0246] Step S1404: If the current condition satisfies the third condition, it is determined that the smoothing state of the flash memory device is a working state.

[0247] It is understandable that if the smoothing state of the flash memory device is the working state (State on ), the write bandwidth of the flash memory device needs to be smoothed.

[0248] Specifically, the third condition includes that the sampling time of the sampling state is greater than a preset time threshold. The preset time threshold can be set according to specific needs, for example, set to 10s. After the sampling time is greater than 10s, the write bandwidth of the flash memory space is smoothed to obtain an average write bandwidth of the flash memory space.

[0249] It is understandable that when the current conditions of the flash memory device and the host change, the smoothing state of the flash memory device needs to be switched.

[0250] For details, please refer to Fig.15 , Fig.15 It is a schematic diagram of a switching smoothing state provided in an embodiment of the present application.

[0251] like Fig.15 As shown, switching the smooth state of the flash memory device includes:

[0252] When the smoothing state of the flash memory device is in the off state, if the current condition satisfies the second condition, switching the smoothing state of the flash memory device to the sampling state;

[0253] When the smoothing state of the flash memory device is in the sampling state, if the current condition satisfies the first condition, the smoothing state of the flash memory device is switched to the off state; or, if the current condition satisfies the third condition, the smoothing state of the flash memory device is switched to the working state;

[0254] When the smoothing state of the flash memory device is in the working state, if the current condition satisfies the first condition, the system state of the flash memory device is switched to the closed state.

[0255] It should be noted that the first condition, the second condition and the third condition can refer to the above description and will not be repeated here.

[0256] In the embodiment of the present application, switching the smoothing state of the flash memory device also includes:

[0257] When the flash device is in smooth operation,

[0258] In a first sampling period, calculating a first average write bandwidth of the flash memory space;

[0259] In a second sampling period, calculating a second average write bandwidth of the flash memory space, wherein the second sampling period is greater than the first sampling period;

[0260] If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold, the working state is switched to the closed state.

[0261] It can be understood that the first sampling period is a short period, and the second sampling period is a long period. The long period sampling represents the average bandwidth over a long period, and the short period represents the average bandwidth over a short period. When the long period and the short period are not equal, it means that the flash memory device is not in a stable bandwidth state, and the working state needs to be switched to the off state to adjust the flash memory device to a stable bandwidth state and achieve bandwidth balance.

[0262] Specifically, assuming that the first sampling period is T 1 , the second sampling period is T 2 , where T 2 >T 1 , by the first sampling period T 1 , to obtain a plurality of first write bandwidths, and smooth the plurality of first write bandwidths by a smoothing algorithm to obtain a first average write bandwidth corresponding to the first sampling period; similarly, by sampling the first average write bandwidth corresponding to the second sampling period T 2 Sampling is performed at each sampling time within a period to obtain a plurality of first write bandwidths, and the plurality of first write bandwidths are smoothed by a smoothing algorithm to obtain a second average write bandwidth corresponding to a second sampling period.

[0263] If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold, the working state is switched to the off state. off ).

[0264] In the embodiment of the present application, the first sampling period T 1 The second sampling period is T 2 All can be set according to specific needs, for example: setting the first sampling period T 1 =5s, the second sampling period T 2 =8s.

[0265] In the embodiment of the present application, the difference threshold can be set according to specific needs. For example, the difference threshold is set to the larger value of the preset bandwidth threshold and (average write bandwidth*third coefficient), that is, the difference threshold=Max(preset bandwidth threshold, average write bandwidth*third coefficient). For example, if the preset bandwidth threshold is 50MB / s and the third coefficient is 0.1, then the difference threshold=Max(50MB / s, BW avg *0.1).

[0266] In an embodiment of the present application, by determining the smoothing state of the flash memory device and switching the smoothing state of the flash memory device in real time according to current conditions, state management can be better implemented, thereby quickly responding to changes in the IO model and improving the stability of the flash memory device.

[0267] In an embodiment of the present application, a data writing method is provided, which is applied to a flash memory device, wherein the flash memory device includes a cache space and a flash memory space, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data sent by the host, and the second cache space is used to cache user data that has been written to the flash memory space; the method includes: obtaining user data sent by the host, and storing the user data in the first cache space; writing the user data in the first cache space to the flash memory space; after the user data is written to the flash memory space, caching the user data that has been written to the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; determining a first release bandwidth based on the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; and releasing the user data in the second cache space based on the first release bandwidth.

[0268] By setting a second cache space in the cache space to cache user data that has been written to the flash memory space, and using the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, the second cache space releases user data with the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host. The present application can improve the write performance consistency of the host, thereby improving the service quality of the flash memory device.

[0269] Please refer to Fig.16 , Fig.16 It is a schematic diagram of the structure of another flash memory device provided in an embodiment of the present application.

[0270] like Fig.16 As shown, the flash memory device 100 includes one or more processors 121 and a memory 122. Fig.16 A processor 121 is taken as an example.

[0271] The processor 121 and the memory 122 may be connected via a bus or other means. Fig.16 The example of connecting through bus is taken in the following.

[0272] The processor 121 is used to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to perform a data writing method in any one of the above method embodiments, the data writing method is applied to a flash memory device, the flash memory device includes a cache space and a flash memory space, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data sent by the host, and the second cache space is used to cache user data written into the flash memory space; the method includes: obtaining user data sent by the host, and storing the user data in the first cache space; writing the user data in the first cache space to the flash memory space; after the user data is written to the flash memory space, caching the user data written into the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; releasing the user data in the second cache space according to the first release bandwidth.

[0273] By setting a second cache space in the cache space to cache user data that has been written to the flash memory space, and using the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, the second cache space releases user data with the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host. The present application can improve the write performance consistency of the host, thereby improving the service quality of the flash memory device.

[0274] The processor 121 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0275] The memory 122, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the data writing method in the embodiment of the present application. The processor 121 can implement the data writing method in any of the following method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 122. Specifically, the memory 122 may include a volatile memory (VM), such as a random access memory (RAM); the memory 122 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 122 may also include a combination of the above-mentioned types of memories.

[0276] The memory 122 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 122 may optionally include a memory remotely arranged relative to the processor 121, and these remote memories may be connected to the processor 121 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0277] One or more modules are stored in the memory 122, and when executed by one or more processors 121, the data writing method in any of the above method embodiments is executed, for example, the data writing method described above is executed. Figure 3 The steps shown.

[0278] In the embodiment of the present application, the flash memory device 100 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 100 may also include other components for realizing device functions, which will not be described in detail here.

[0279] The present application also provides a computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the data writing method in the above embodiment. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0280] The present application also provides a computer program product, which includes one or more program codes stored in a computer-readable storage medium. The processor of the flash memory device reads the program code from the computer-readable storage medium, and the processor executes the program code to complete the method steps of the data writing method provided in the above embodiment.

[0281] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0282] Through the description of the above implementation methods, ordinary technicians in this field can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Ordinary technicians in this field can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0283] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that: Applied to a flash memory device, the flash memory device includes a cache space and a flash memory space, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data sent by a host, and the second cache space is used to cache user data written into the flash memory space; The method comprises: Acquire user data sent by the host, and store the user data in the first cache space; Writing the user data in the first cache space into the flash memory space; After the user data is written into the flash memory space, cache the user data written into the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; Determine a first release bandwidth according to an average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; The user data in the second cache space is released according to the first released bandwidth.

2. The method according to claim 1, characterized in that The smoothing of the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space includes: Real-time statistics of the amount of data written successfully into the flash memory space; After each sampling time, counting the data increment of the written data amount to calculate the first write bandwidth corresponding to each sampling time, wherein the first write bandwidth=data increment / sampling time; The plurality of first write bandwidths are smoothed by using a smoothing algorithm to obtain the average write bandwidth.

3. The method according to claim 2, characterized in that The method further comprises: Obtaining the current bandwidth of the flash memory space; Determining whether the average write bandwidth is less than the current bandwidth of the flash memory space; If the average write bandwidth is less than the current bandwidth, using the average write bandwidth as the first released bandwidth; If the average write bandwidth is greater than or equal to the current bandwidth, the sum of the current bandwidth and the feedback bandwidth is used as the first release bandwidth, wherein the feedback bandwidth=first coefficient*user data space, wherein the user data space is the size of the user data in the second cache space.

4. The method according to claim 3, characterized in that The method further comprises: Determining the feedback bandwidth according to the user data space includes: Setting a waterline threshold, wherein the waterline threshold is smaller than the second cache space; Determine whether the user data space is less than or equal to the waterline threshold; If yes, setting the feedback bandwidth to zero; If not, the feedback bandwidth is set to the second coefficient*(user data space-waterline threshold).

5. The method according to claim 1, characterized in that The acquiring the user data sent by the host and storing the user data in the first cache space includes: Obtaining a cache application command corresponding to a write request of the host, wherein the cache application command corresponds to a current application space; According to the cache application command, the currently applied space is applied to the cache space to store the user data in the first cache space, wherein the first cache space = the applied first cache space + the currently applied space.

6. The method according to claim 5, characterized in that After releasing the user data in the second cache space, the method further includes: Determining a current released space, wherein the current released space is used to compensate the first cache space; If the released space is smaller than the currently applied space, determining that the cache application command is an application failure; If the released space is greater than or equal to the currently applied space, it is determined that the cache application command is successfully applied.

7. The method according to claim 1, characterized in that The method further comprises: Determining a smoothing state of the flash memory device according to current conditions of the flash memory device and the host includes: If the current condition satisfies the first condition, it is determined that the smoothing state of the flash memory device is the closed state, wherein the first condition includes: the write bandwidth of the host is zero, or, when the host applies for cache space from the cache space, the number of successful applications is greater than the number of failed applications, or, the write bandwidth of the host is less than the target bandwidth of the flash memory device; If the current condition satisfies the second condition, determining that the smoothing state of the flash memory device is a sampling state, wherein the second condition includes: the write bandwidth of the host is not zero, and when the host applies for cache space from the cache space, the number of successful applications is less than the number of failed applications, or the write bandwidth of the host is greater than the target bandwidth of the flash memory device; If the current condition satisfies a third condition, it is determined that the smoothing state of the flash memory device is a working state, wherein the third condition includes: a sampling time of the sampling state is greater than a preset time threshold.

8. The method according to claim 7, characterized in that The method further comprises: Switching the smoothing state of the flash memory device includes: When the smoothing state of the flash memory device is in the off state, if the current condition satisfies the second condition, switching the smoothing state of the flash memory device to the sampling state; When the smoothing state of the flash memory device is in the sampling state, if the current condition satisfies the first condition, the smoothing state of the flash memory device is switched to the off state; or, if the current condition satisfies the third condition, the smoothing state of the flash memory device is switched to the working state; When the smoothing state of the flash memory device is in the working state, if the current condition satisfies the first condition, the system state of the flash memory device is switched to the closed state.

9. The method according to claim 8, characterized in that The switching of the smooth state of the flash memory device further includes: When the smoothing state of the flash memory device is in a working state, In a first sampling period, calculating a first average write bandwidth of the flash memory space; In a second sampling period, calculating a second average write bandwidth of the flash memory space, wherein the second sampling period is greater than the first sampling period; If the difference between the first average write bandwidth and the second average write bandwidth is greater than a difference threshold, the working state is switched to a closed state.

10. A flash memory device, characterized in that: include: A processor and a memory, wherein the processor is used to execute an executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the data writing method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the data writing method according to any one of claims 1 to 9 is implemented.

Images