Lookup device applied to lookup table, lookup table control method, chip and equipment

Abstract

The invention discloses a lookup device applied to a lookup table, a lookup control method, a chip and equipment, and the lookup device applied to the lookup table comprises an addressing module which is configured to receive a lookup address based on an initial lookup table and determine a reconstruction address according to the lookup address; the lookup table module is configured to receive the reconstruction address and output a lookup value to the mean value module according to the reconstruction address and a target lookup table; wherein the reconstruction address comprises at least two address values, and the lookup values are in one-to-one correspondence with the reconstruction address; a target lookup table is pre-stored in the lookup table module, and the target lookup table is obtained by compressing the initial lookup table; and the mean value module is configured to perform mean value calculation on the lookup value and determine an obtained calculation result as a target lookup value. Therefore, the target lookup table stored in the lookup table module is obtained by compressing the initial lookup table, so that the area of the lookup table can be reduced, and the overall performance can be improved.

Description

Technical Field

[0001] The present application relates to the field of image display technology, and in particular to a lookup device, a lookup control method, a chip and a device applied to a lookup table. Background Art

[0002] In computer science, a look-up table (LUT) is a data structure such as an array or associative array or map that replaces runtime calculations with simple query operations, thereby avoiding complex calculations and increasing processing speed.

[0003] However, when storing a lookup table, corresponding storage space is required. Taking image quality development as an example, it is often necessary to use a lookup table to obtain data, especially when a larger-scale lookup table is needed. At this time, a large number of registers and logic circuits for setting registers are required, which leads to a significant increase in circuit area and consumes more system resources, resulting in a decrease in overall performance. Summary of the invention

[0004] The present application proposes a lookup device, a lookup control method, a chip and a device applied to a lookup table, which can reduce the area of ​​the lookup table, thereby saving circuit costs and improving overall performance.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a search device applied to a lookup table, the search device includes a lookup table control device, the lookup table control device includes an addressing module, a lookup table module and an average module, wherein:

[0007] An addressing module is configured to receive a table lookup address based on an initial table lookup, and determine a reconstructed address according to the table lookup address;

[0008] A lookup table module is configured to receive a reconstructed address and output a lookup value to the average module according to the reconstructed address and a target lookup table; wherein the reconstructed address includes at least two address values, and the lookup value corresponds to the reconstructed address one by one; the lookup table module pre-stores a target lookup table, and the target lookup table is obtained by compressing the initial lookup table;

[0009] The mean module is configured to perform mean calculation on the search value and determine the obtained calculation result as the target search value.

[0010] In a second aspect, an embodiment of the present application provides a table lookup control method, the method comprising:

[0011] receiving a table lookup address based on an initial lookup table, and determining a reconstructed address according to the table lookup address;

[0012] Outputting a lookup value according to the reconstructed address and the target lookup table; wherein the reconstructed address includes at least two address values, and the lookup value corresponds to the reconstructed address one by one; and the target lookup table is obtained by compressing the initial lookup table;

[0013] The mean of the search value is calculated, and the obtained calculation result is determined as the target search value.

[0014] In a third aspect, an embodiment of the present application provides a display chip, which includes the search device as described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a register controller and a display chip as described in the third aspect.

[0016] The embodiment of the present application provides a search device, a table search control method, a chip and a device for a lookup table. In the search device, the addressing module is configured to receive a table search address based on an initial table search, and determine a reconstruction address according to the table search address; the table search module is configured to receive the reconstruction address, and output a search value to the mean module according to the reconstruction address and the target table search; wherein the reconstruction address includes at least two address values, and the search value corresponds to the reconstruction address one by one; the table search module pre-stores a target table search, and the target table search is obtained by compression based on the initial table search; the mean module is configured to perform mean calculation on the search value, and determine the obtained calculation result as the target search value. In this way, for the target table search stored in the table search module, it is obtained by compression of the initial table search, so that the area of ​​the table search can be reduced, and the number of registers and the area of ​​the related logic circuit can be reduced accordingly, so that the circuit cost can be saved; in addition, by reducing the area of ​​the table search, the query speed can be accelerated, the consumption of system resources can be saved, and the overall performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 1 ;

[0018] Figure 2 A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 2 ;

[0019] Figure 3 A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 3 ;

[0020] Figure 4A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 4 ;

[0021] Figure 5 A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 5 ;

[0022] Figure 6 A flowchart of a table lookup control method provided in an embodiment of the present application Figure 1 ;

[0023] Figure 7 A flowchart of a table lookup control method provided in an embodiment of the present application Figure 2 ;

[0024] Figure 8 A schematic diagram of the structure of a display chip provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] It should also be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0029] It should also be noted that in the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0030] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application.

[0031] A Look Up Table (LUT) is a data structure that speeds up the calculation process by pre-calculating and storing function values. LUT is widely used in computer science, image processing, and other fields. The basic principle of LUT is to pre-calculate function values ​​and store them in an array or dictionary. When the function value needs to be calculated, the approximate value is quickly obtained by looking up this table, thus avoiding the complex calculation process. Since extracting values ​​from memory is usually much faster than calculation, LUT can significantly improve calculation efficiency.

[0032] In the field of display technology, the development of picture quality intellectual property (IP) often requires the use of lookup tables to obtain data. However, when a larger-scale lookup table is needed, a large number of registers and logic circuits for setting the registers are required, resulting in a significant increase in circuit area. At the same time, as the size of the lookup table increases, the complexity of the lookup table also increases. When processing large-scale data, the consumption of system resources such as the central processing unit (CPU) and memory will also increase significantly, resulting in a decrease in overall system performance.

[0033] Based on this, the present embodiment provides a search device, a table search control method, a chip and a device applied to a lookup table. Among them, the addressing module is configured to receive a table search address based on an initial lookup table, and determine a reconstruction address according to the table search address; the table search module is configured to receive a reconstruction address, and output a search value to the mean module according to the reconstruction address and the target lookup table; the mean module is configured to perform mean calculation on the search value, and determine the obtained calculation result as the target lookup value. In this way, for the target lookup table pre-stored in the lookup table module, it is obtained by compressing the initial lookup table, so that the area of ​​the lookup table can be reduced, and the number of registers and the area of ​​the related logic circuit can be reduced accordingly, so that the circuit cost can be saved; in addition, by reducing the area of ​​the lookup table, the query speed can be accelerated, the consumption of system resources can be saved, and the overall performance can be improved.

[0034] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0035] In one embodiment of the present application, Figure 1 A schematic diagram of the structure of a search device provided in an embodiment of the present application Figure 1 .like Figure 1As shown, a lookup device 100 applied to a lookup table may include a lookup table control device 11, and the lookup table control device 11 may include an addressing module 101, a lookup table module 102 and an average module 103, wherein:

[0036] The addressing module 101 is configured to receive a table lookup address based on an initial table lookup, and determine a reconstructed address according to the table lookup address;

[0037] A lookup table module 102, configured to receive a reconstructed address and output a lookup value to the mean value module according to the reconstructed address and a target lookup table;

[0038] The mean module 103 is configured to perform mean calculation on the search value and determine the obtained calculation result as the target search value.

[0039] Here, the reconstructed address may include at least two address values, and the lookup value corresponds to the reconstructed address one by one. In addition, the lookup table module 102 pre-stores a target lookup table, and the target lookup table is obtained by compressing the initial lookup table.

[0040] It should be noted that in the embodiments of the present application, the lookup table here (such as the initial lookup table, the target lookup table, etc.) can be implemented in a variety of ways, including but not limited to arrays, dictionaries, mapping tables, hash tables and other data structures. In addition, the types of lookup tables can be divided into one-dimensional (One Dimensions, 1D) lookup tables, two-dimensional (Two Dimensions, 2D) lookup tables, three-dimensional (Three Dimensions, 3D) lookup tables, etc. Among them, the 1D lookup table only needs to input one variable to query the corresponding output value; the 2D lookup table needs to input two unrelated variables to get the corresponding output value, for example, input a set of coordinate information (x, y), then you can get an output value; the 3D lookup table needs to input three unrelated variables to get the corresponding output value, for example, input the color values ​​of the three channels of R, G, and B, and then return an RGB value. In the embodiments of the present application, whether it is the initial lookup table or the target lookup table, this article takes the 2D lookup table as an example for relevant description.

[0041] It should also be noted that in the embodiment of the present application, the initial lookup table may refer to the lookup table before compression, and the size of the initial lookup table is relatively large. For example, assuming that the number of nodes in the x-axis direction of the initial lookup table before compression is 2 m , the number of nodes in the y-axis direction is 2 n , where m,n∈N. Then the number of nodes contained in the initial lookup table can be 2 m+n , as shown in Table 1. In Table 1, L(y, x) represents the node value of the yth row and the xth column.

[0042] Table 1

[0043]

[0044]

[0045] In an embodiment of the present application, the number of nodes included in the target lookup table is less than the number of nodes included in the initial lookup table. In a possible implementation, the number of nodes included in the target lookup table may be one-fourth the number of nodes included in the initial lookup table. In this implementation, the target lookup table can be viewed as being obtained by deleting all odd rows and odd columns in the initial lookup table.

[0046] For example, taking the initial lookup table shown in Table 1 as an example, all odd rows and columns in Table 1 are deleted, and the number of nodes in the x-axis direction can be obtained as 2 m-1 , the number of nodes in the y-axis direction is 2 n-1 , at this time, the number of nodes contained in the target lookup table can be 2 m+n-2 , as shown in Table 2.

[0047] Table 2

[0048] addr 0 2 4 6 …… <![CDATA[2 m -2]]> 0 L(0,0) L(0,2) L(0,4) L(0,6) …… <![CDATA[L(0,2 m -2)]]> 2 L(2,0) L(2,2) L(2,4) L(2,6) …… <![CDATA[L(2,2 m -2)]]> 4 L(4,0) L(4,2) L(4,4) L(4,6) …… <![CDATA[L(4,2 m -2)]]> 6 L(6,0) L(6,2) L(6,4) L(6,6) …… <![CDATA[L(6,2 m -2)]]> …… …… …… …… …… …… …… <![CDATA[2 n -2]]> <![CDATA[L(2 n -2,0)]]> <![CDATA[L(2 n -2,2)]]> <![CDATA[L(2 n -2,4)]]> <![CDATA[L(2 n -2,6)]]> …… <![CDATA[L(2 n -2,2 m -2)]]>

[0049] It should be noted that in the embodiment of the present application, considering that when generating the reconstructed address according to the lookup address of the initial lookup table, some of the reconstructed addresses may fall into a row or a column outside the boundary of Table 2. Therefore, after dividing the coordinates of the x-axis direction and the y-axis direction of Table 2 by 2 to complete the coordinate mapping, it is necessary to add an additional second m-1 Column and 2 n-1 The final target lookup table can be obtained by performing the following operations, as shown in Table 3.

[0050] Table 3

[0051]

[0052]

[0053] Thus, assuming that the initial lookup table is represented by LUT, the target lookup table can be represented by 1 / 4 LUT. In other words, the embodiment of the present application can achieve compression of the initial lookup table and reduce the area of ​​the lookup table.

[0054] In some embodiments, Figure 1 Based on the search device 100 shown, see Figure 2 , the search device 100 may further include a target register set 104, wherein:

[0055] The target register group 104 is configured to write and store the node value of the target lookup table according to the write instruction after receiving the write instruction.

[0056] In an embodiment of the present application, the target register set 104 may include a plurality of registers, each register being used to store a node value. Here, the number of registers included in the target register set 104 is less than the number of nodes included in the initial lookup table. Alternatively, it can be said that the number of registers included in the target register set 104 is related to the number of nodes included in the target lookup table.

[0057] In a possible implementation, the number of registers included in the target register set 104 is equal to the number of nodes included in the target lookup table. If the target lookup table is a compressed 1 / 4 of the initial lookup table, then the number of registers included in the target register set 104 can be reduced to 1 / 4 relative to the number of registers required for the initial lookup table; that is, the number of registers included in the target register set 104 is approximately equal to 1 / 4 of Table 1. Therefore, the target register set 104 can also be called a "1 / 4LUT register set".

[0058] In the embodiment of the present application, for the target register group 104, the target register group 104 can be set inside the lookup table control device 11, such as Figure 2 Alternatively, the target register group 104 may also be set outside the lookup table control device 11, such as Figure 3 shown.

[0059] It should be noted that in the embodiment of the present application, whether the target register group 104 is set inside or outside the lookup table control device 11, the target register group 104 and the lookup table control device 11 are integrated into the display chip, specifically, they can be integrated into the display driver chip (Display Driver Integrated Circuit, DDIC).

[0060] In some embodiments, Figure 1 Based on the search device 100 shown in FIG. Figure 2 or Figure 3 , the search device 100 may further include a register controller 12, wherein:

[0061] The register controller 12 is configured to send a write instruction to the target register group 104 , where the write instruction is used to write the node value of the target lookup table into the target register group 104 and store it.

[0062] In an embodiment of the present application, the register controller 12 may be arranged outside the display chip, and the register controller 12 is located outside the lookup table control device 11. In this way, by sending a write instruction to the target register group 104 through the register controller 12, the node values ​​of the target lookup table can be written into the corresponding registers in the target register group 104, and the target register group 104 is used to store the node values ​​of the target lookup table. Among them, the node value here may refer to the LUT node value. Exemplarily, the LUT node value in Table 3 may be written into the target register group 104 and stored, thereby reducing the number of registers in the target register group.

[0063] In one possible implementation, Figure 2 As shown, the target register set 104 is set inside the LUT control device 11. The register controller 12 establishes a communication connection with the target register set 104 inside the LUT control device 11, and the register controller 12 can write the LUT node value of the target LUT into the target register set 104 and store it.

[0064] In another possible implementation, Figure 3 As shown, the target register set 104 is set outside the LUT control device 11. The register controller 12 establishes a communication connection with the target register set 104 outside the LUT control device 11, and the register controller 12 can also write the LUT node value of the target LUT into the target register set 104 and store it.

[0065] In some embodiments, Figure 2 or Figure 3 As shown, the target register group 104 is further configured to read the node values ​​of the stored target lookup table to the lookup table module 102 .

[0066] It should be noted that, in the embodiment of the present application, the lookup table module 102 may load the node values ​​of the target lookup table from the target register group 104. For example, the lookup table module 102 may load the LUT node values ​​shown in Table 3.

[0067] It should also be noted that, in the embodiment of the present application, the target register group 104 may read the node values ​​of the stored target lookup table to the lookup table module 102 when the image frame is refreshed. Alternatively, it can be said that the node values ​​of the stored target lookup table are read to the lookup table module 102 when the field synchronization information is at a low level.

[0068] In electronic display technology, the field synchronization signal, also known as the vertical synchronization signal (VerticalSynchronization, VSYNC), plays a vital role, especially in progressive scan display devices. The change of the field synchronization signal marks the beginning or end of a new frame of the image, thereby triggering the refresh process of the display. Among them, the main function of the field synchronization signal is to synchronize the refresh rate of the display with the data output rate of the video source. It ensures that the display starts and ends the scanning of each frame at the correct time point, thereby avoiding image tearing and display asynchrony. In the standard progressive scanning process, the field synchronization signal usually becomes a low level (or negative pulse) at the beginning of each frame and lasts for a period of time. This low-level pulse is the signal that triggers the display to start a new frame scan. When the signal changes back to a high level, it means that the scan of the frame has ended and is ready to start the scan of the next frame.

[0069] Simply put, in an embodiment of the present application, the node values ​​of the target lookup table can be written to the target register group 104 at any time, that is, the register controller can write the node values ​​of the target lookup table into the target register group 104 at any time; however, the target register group 104 will only load its stored LUT node values ​​into the lookup table module 102 when the field synchronization signal becomes a low level (that is, a new image frame starts to refresh).

[0070] It can be understood that in the embodiment of the present application, since the reconstructed address includes at least two address values, accordingly, the number of lookup table modules can also be at least two, and each address value can query and output the corresponding lookup value from a lookup table module.

[0071] In one possible implementation, taking the case where the reconstructed address includes two address values ​​(e.g., a first reconstructed address and a second reconstructed address) as an example, the lookup table module 102 may include a first lookup table module and a second lookup table module, so that the lookup table module 102 can output two lookup values ​​(e.g., a first lookup value and a second lookup value) to the mean module 103.

[0072] In a specific embodiment, Figure 2 Based on the search device 100 shown, see Figure 4 , the lookup table module 102 may include a first lookup table module a1 and a second lookup table module a2, and the target lookup tables stored in the first lookup table module a1 and the second lookup table module a2 are the same; wherein:

[0073] A first lookup table module a1, configured to receive a first reconstructed address and output a first lookup value to the average module according to the first reconstructed address and a target lookup table;

[0074] The second lookup table module a2 is configured to receive a second reconstructed address and output a second lookup value to the average module according to the second reconstructed address and the target lookup table.

[0075] In another specific embodiment, Figure 3 Based on the search device 100 shown, see Figure 5 , the lookup table module 102 may include a first lookup table module a1 and a second lookup table module a2, and the target lookup tables stored in the first lookup table module a1 and the second lookup table module a2 are the same; wherein:

[0076] A first lookup table module a1, configured to receive a first reconstructed address and output a first lookup value to the average module according to the first reconstructed address and a target lookup table;

[0077] The second lookup table module a2 is configured to receive a second reconstructed address and output a second lookup value to the average module according to the second reconstructed address and the target lookup table.

[0078] It should be noted that whether Figure 4 or Figure 5 , the first lookup table module a1 and the second lookup table module a2 store the same target lookup table. It should also be noted that Figure 4 or Figure 5 Only an application example including two lookup table modules is provided, but the invention is not limited thereto. If more number of lookup table modules are included here, the target lookup tables stored in these lookup table modules are also all the same.

[0079] It should also be noted that the first lookup table module a1 and the second lookup table module a2 can be node values ​​loaded into the target lookup table from the target register group 104, and the node values ​​stored in the first lookup table module a1 and the second lookup table module a2 are exactly the same. Exemplarily, the first lookup table module a1 and the second lookup table module a2 can both be LUT node values ​​loaded as shown in Table 3.

[0080] That is to say, in an embodiment of the present application, the register controller 12 is used to write the node values ​​of the target lookup table obtained by compressing the initial lookup table into the target register group 104 and store them; then the target register group 104 is used to load the stored node values ​​of the target lookup table into the first lookup table module a1 and the second lookup table module a2.

[0081] Thus, in the embodiment of the present application, assuming that the target lookup table is compressed to 1 / 4 of the initial lookup table, the number of registers included in the target register group 104 will be reduced to 1 / 4, but the area of ​​the lookup table will be reduced to 1 / 2. Because the first lookup table module a1 is loaded with 1 / 4LUT, and the second lookup table module a2 is loaded with 1 / 4LUT, for the lookup table, although the target lookup table is compressed to 1 / 4 of the initial lookup table, the area of ​​the lookup table is only reduced to 1 / 2.

[0082] It can also be understood that in the embodiment of the present application, for the addressing module 101, the addressing mode here can refer to the way in which the processor finds the effective address according to the coordinate information given in the instruction, which is a method for determining the data address of the current instruction and the address of the next instruction to be executed. In computer science, addressing is a mechanism for locating and accessing data storage locations in a computer system. Data may be stored in registers, memory, hard disks, or other forms of storage devices. Here, the addressing mode mainly affects how to read data from these storage devices, such as how to read the corresponding node value from the first lookup table module a1 or the second lookup table module a2.

[0083] In a possible implementation, the addressing mode may be L(y, x), or the addressing mode may also be L(x, y). Exemplarily, in combination with the aforementioned Tables 1 to 3, the addressing mode used in the embodiment of the present application is L(y, x), but is not specifically limited thereto.

[0084] In the embodiment of the present application, for the addressing module 101, the received table lookup address may include the initial coordinates of the first direction and the initial coordinates of the second direction. Accordingly, in some embodiments, the addressing module 101 is configured to perform binary bit division on the initial coordinates of the first direction to determine the first part of the bit value and the second part of the bit value of the first direction; and perform binary bit division on the initial coordinates of the second direction to determine the third part of the bit value and the fourth part of the bit value of the second direction; determine the first reconstructed address and the second reconstructed address according to the first part of the bit value, the second part of the bit value, the third part of the bit value and the fourth part of the bit value.

[0085] It should be noted that, in the embodiment of the present application, the first direction and the second direction are respectively one of the horizontal axis direction and the vertical axis direction, and the first direction and the second direction are different. For example, the first direction may refer to the horizontal axis direction (or referred to as the "x-axis direction"), and the second direction may refer to the vertical axis direction (or referred to as the "y-axis direction"). Accordingly, the initial coordinates of the first direction can be represented by addr x Indicates that the initial coordinates of the second direction can be obtained using addr yIn which, the initial coordinates of the first direction and the initial coordinates of the second direction are both expressed in binary, so addr x The bit width is m bits, addr y The bit width is n bits.

[0086] It should also be noted that, in the embodiment of the present application, for the initial coordinates of the first direction, the first part of the bit value may refer to addr x [m-1:1], that is, select addr x The second part of the bit value can refer to addr x [0], that is, select addr x For the initial coordinates of the second direction, the third bit value may refer to addr y [n-1:1], that is, select addr y The n-1th bit to the 1st bit of the binary number; the fourth bit value can refer to addr y [0], that is, select addr y The 0th bit of the binary number.

[0087] Thus, according to the first part of the bit value addr x [m-1:1], the second part bit value addr x [0], the third part bit value addr y [n-1:1] and the fourth part bit value addr y [0], which can be used to determine the first reconstruction address and the second reconstruction address.

[0088] In an embodiment of the present application, the first reconstructed address may include a first reconstructed coordinate in the first direction and a first reconstructed coordinate in the second direction, and the second reconstructed address may include a second reconstructed coordinate in the first direction and a second reconstructed coordinate in the second direction. Accordingly, in some embodiments, the addressing module 101 is further configured to set the first reconstructed coordinate in the first direction to be equal to the sum of the first partial bit value and the second partial bit value, and to set the first reconstructed coordinate in the second direction to be equal to the sum of the third partial bit value and the fourth partial bit value; and to set the second reconstructed coordinate in the first direction to be equal to the difference between the first partial bit value and the second partial bit value, and to set the second reconstructed coordinate in the second direction to be equal to the difference between the third partial bit value and the fourth partial bit value.

[0089] It should be noted that, in the embodiment of the present application, for the first reconstructed address, the first reconstructed coordinate in the first direction can be represented by addr x1 Indicates that the first reconstructed coordinates in the second direction can be expressed as addr y1For the second reconstructed address, the second reconstructed coordinates in the first direction can be represented by addr x2 Indicates that the second reconstructed coordinates in the second direction can be expressed using addr y2 express.

[0090] In one possible implementation, the four reconstruction coordinates addr x1 、addr y1 、addr x2 、addr y2 , as shown below:

[0091] addr x1 = addr x [m-1:1]+addr x [0] (1)

[0092] addr y1 = addr y [n-1:1]+addr y [0] (2)

[0093] addr x2 = addr x [m-1:1]-addr x [0] (3)

[0094] addr y2 = addr y [n-1:1]-addr y [0] (4)

[0095] Here, according to the external input table address addr x and addr y The first reconstructed address generated by the addressing module 101 is (addr y1 ,addr x1 ), the second reconstructed address is (addr y2 ,addr x2 ). Then the first reconstructed address (addr y1 ,addr x1 ) is input into the first lookup table module a1, and the first lookup table module a1 outputs a first lookup value L (addr y1 ,addr x1 ); the second reconstructed address (addr y2 ,addr x2 ) is input into the second lookup table module a2, and the second lookup table module a2 outputs a second lookup value L (addr y2,addr x2 ).

[0096] For example, assuming that the external input table lookup address addr x is 7 (111 in binary), addr y is 10 (1010 in binary); then addr x The bit width is 3 bits, addr y The bit width is 4 bits. x The value of [0] is 1, addr x The value of [m-1:1] is 3 (11 in binary); addr y The value of [0] is 0, addr y The value of [n-1:1] is 5 (101 in binary). Thus, according to the above formulas (1) to (4), the first reconstructed address is (5, 4) and the second reconstructed address is (5, 2); accordingly, the first search value output by the first lookup table module a1 is L(5, 4) and the second search value output by the second lookup table module a2 is L(5, 2).

[0097] It can also be understood that in the embodiment of the present application, upon receiving the first search value L(addr y1 ,addr x1 ) and the second lookup value L(addr y2 ,addr x2 ), the average module 103 can be configured to calculate the first search value L(addr y1 ,addr x1 ) and the second lookup value L(addr y2 ,addr x2 ) is used to calculate the average value, and the calculated result is determined as the target search value, that is, the final LUT value, which can be recorded as Lut_o.

[0098] In one possible implementation, the mean operation can be implemented using division. y1 ,addr x1 ) and the second lookup value L(addr y2 ,addr x2 ) to calculate the mean, which can be shown as follows:

[0099]

[0100] In another possible implementation, the mean operation may be implemented using a right shift operation. In some embodiments, the mean module 103 may also be configured to perform a right shift operation on the first search value L (addr y1 ,addrx1 ) and the second lookup value L(addr y2 ,addr x2 ) is shifted right by one position, and the obtained calculation result is determined as the target search value.

[0101] Exemplarily, “>>” represents a binary right shift operator. Here, for the first search value L (addr y1 ,addr x1 ) and the second lookup value L(addr y2 ,addr x2 ) is shifted right by one position, which can be shown as follows:

[0102] Lut_o=(L(addr y1 ,addr x1 )+L(addr y2 ,addr x2 ))>>1 (6)

[0103] The embodiment of the present application provides a search device, wherein the addressing module can determine the reconstruction address according to the received table lookup address; the table lookup module can output the search value to the mean module according to the reconstruction address and the pre-stored target table lookup; since the reconstruction address includes at least two address values, the number of search values ​​here can be at least two, and then the mean module is used to calculate the mean of these search values ​​to determine the final target search value. In this way, since the target table lookup stored in the table lookup module is obtained by compressing the initial table lookup, the area of ​​the table lookup can be reduced, and the number of registers and the area of ​​the related logic circuit can be reduced accordingly, so that the circuit cost can be saved; in addition, by reducing the area of ​​the table lookup, the query speed can be accelerated, the consumption of system resources can be saved, and the overall performance can be improved.

[0104] In another embodiment of the present application, based on the search device 100 described in the aforementioned embodiment, a technical solution for lookup table compression is proposed, which may be a 2D lookup table compression solution, which can reduce the circuit area of ​​the lookup table and related logic.

[0105] In a possible implementation, in order to reduce the area of ​​the 2D lookup table, a search device provided herein may be as follows: Figure 4 or Figure 5 As shown. The search device comprises a register controller and a lookup table control device (also referred to as a "LUT controller").

[0106] In an embodiment of the present application, the LUT controller may further include a target register group, an addressing module, a first lookup table module, a second lookup table module, and an average module in the aforementioned embodiment. Here, it is assumed that the initial lookup table LUT is compressed to 1 / 4, that is, the target lookup table may be 1 / 4LUT, then the target register group may be referred to as a "1 / 4LUT register group", and both the first lookup table module and the second lookup table module are used to load 1 / 4LUT, so they may also be referred to as "1 / 4LUT modules".

[0107] That is, the register controller is used to write the register value into the 1 / 4LUT register group. The 1 / 4LUT register group is used to store the node value in the 1 / 4LUT. The addressing module is used to construct two reconstruction addresses for searching in the 1 / 4LUT module. The 1 / 4LUT module can load the node value from the 1 / 4LUT register group and output the table lookup result according to the reconstruction address constructed by the addressing module. After obtaining the two table lookup results, the mean module can output the table lookup mean, that is, the final target search value.

[0108] In some embodiments, the working principle of the search device is as follows:

[0109] Assume that the number of nodes in the x-axis direction of the initial lookup table before compression is 2 m , the number of nodes in the y-axis direction is 2 n , where m,n∈N. Then the total number of nodes in the initial lookup table is 2 m+n , as shown in Table 1. Here, in Table 1, L(y,x) represents the LUT node value of the yth row and the xth column.

[0110] Delete all odd rows and columns in Table 1, and the number of nodes in the x-axis direction is 2. m-1 , the number of nodes in the y-axis direction is 2 n-1 , the total number of nodes at this time is 2 m+n-2 , as shown in Table 2.

[0111] Finally, divide the horizontal and vertical coordinates of Table 2 by 2 to complete the coordinate mapping, and add an additional second m-1 Column and 2 n-1 Then, we can get 1 / 4LUT, as shown in Table 3.

[0112] It should be noted that the L(y,x) values ​​in Table 3 are all loaded from the 1 / 4LUT register set. According to the above content, the number of registers included in the 1 / 4LUT register set is approximately equal to 1 / 4 of that in Table 1.

[0113] In addition, the addressing module receives the x and y coordinates passed in from the outside, which are recorded as addr x and addr y, where addr x The bit width is m bits, addr y The bit width is n bits. This can generate 4 reconstruction coordinates addr x1 、addr y1 、addr x2 and addr y2 , calculated according to the above formulas (1) to (4). In the formula, addr[m-1:1] means selecting the m-1th bit to the 1st bit of the binary number addr. addr[0] means selecting the 0th bit of the binary number addr.

[0114] In this way, addr can be calculated x1 、addr y1 、addr x2 and addr y2 , to form two reconstructed addresses (addr y1 ,addr x1 ) and (addr y2 ,addr x2 ); then the two reconstructed addresses (addr y1 ,addr x1 ) and (addr y2 ,addr x2 ) are input into two 1 / 4LUT modules respectively. The 1 / 4LUT modules output L(addr) according to the input reconstruction address. y1 ,addr x1 ) and L(addr y2 ,addr x2 ). Then the mean module can calculate the final target search value according to the above formula (5) or (6), which is recorded as Lut_o.

[0115] It should also be noted that, in the embodiment of the present application, the addressing mode of the LUT may be L(y, x), or the addressing mode of the LUT may also be L(x, y). In addition, the 1 / 4LUT register group may be set inside the LUT controller, or the 1 / 4LUT register group may also be set outside the LUT controller, and no limitation is made here.

[0116] In the embodiments of the present application, the specific implementation of the aforementioned embodiments is elaborated in detail through the above embodiments, from which it can be seen that through the technical scheme of the aforementioned embodiments, not only the overall structure of the LUT controller is provided here, but also the structure of the compressed 1 / 4LUT and the addressing method of the addressing module are provided; thereby, by compressing the 2D lookup table, the number of registers of the 2D lookup table can be reduced to 1 / 4, and the area of ​​the lookup table can be reduced to 1 / 2; this not only saves circuit costs, but also speeds up the query speed, saves the consumption of system resources, and thus improves the overall performance.

[0117] In yet another embodiment of the present application, Figure 6 A flowchart of a table lookup control method provided in an embodiment of the present application Figure 1 .like Figure 6 As shown, the process may include:

[0118] S601, receiving a table lookup address based on an initial table lookup, and determining a reconstructed address according to the table lookup address.

[0119] S602, outputting a lookup value according to the reconstructed address and the target lookup table.

[0120] S603, performing mean calculation on the search value, and determining the obtained calculation result as the target search value.

[0121] It should be noted that in the embodiment of the present application, the table lookup control method can be applied to the search device 100 described in the above embodiment. Here, the reconstructed address includes at least two address values, the search value corresponds to the reconstructed address one by one; and the target lookup table is obtained by compressing the initial lookup table.

[0122] It should also be noted that, in the embodiment of the present application, the number of nodes included in the target lookup table is less than the number of nodes included in the initial lookup table. In a possible implementation, the number of nodes included in the target lookup table can be one-fourth of the number of nodes included in the initial lookup table. In this implementation, the target lookup table can be regarded as the result of deleting all the odd rows and odd columns in the initial lookup table. In this way, the compression of the initial lookup table can be achieved, reducing the area of ​​the lookup table.

[0123] In some embodiments, before receiving the table lookup address based on the initial lookup table, the method may further include: the register controller writes and stores the node values ​​of the target lookup table obtained by compressing the initial lookup table into the target register group.

[0124] It should be noted that, in an embodiment of the present application, the target register group may include multiple registers, each register being used to store a node value. Here, the number of registers included in the target register group is less than the number of nodes included in the initial lookup table. Alternatively, it can be said that the number of registers included in the target register group is related to the number of nodes included in the target lookup table.

[0125] In a possible implementation, the number of registers included in the target register group is equal to the number of nodes included in the target lookup table. If the target lookup table is a compressed 1 / 4 of the initial lookup table, then the number of registers included in the target register group can be reduced to 1 / 4 relative to the number of registers required for the initial lookup table; that is, the number of registers included in the target register group is approximately equal to 1 / 4 of Table 1.

[0126] In some embodiments, the method may further include: the target register group reading the node value of the stored target lookup table to the lookup table module.

[0127] It should be noted that, in the embodiment of the present application, the target register group may read the node values ​​of the stored target lookup table into the lookup table module when the image frame is refreshed (or when the field synchronization information is at a low level).

[0128] That is to say, in the embodiment of the present application, the node values ​​of the target lookup table can be written into the target register group at any time, that is, the register controller can write the node values ​​of the target lookup table into the target register group at any time; however, the target register group will load the stored LUT node values ​​into the lookup table module only when the field synchronization signal becomes a low level (that is, the new image frame starts to refresh).

[0129] It can be understood that in the embodiment of the present application, since the reconstructed address includes at least two address values, accordingly, the number of the lookup table modules can also be at least two, and each address value can query and output the corresponding lookup value from a lookup table module. Exemplarily, assuming that the reconstructed address includes two address values ​​(e.g., a first reconstructed address and a second reconstructed address), the lookup table module can include a first lookup table module and a second lookup table module, so that the two lookup table modules can output two lookup values ​​(e.g., a first lookup value and a second lookup value) to the average module.

[0130] In a specific embodiment, taking the reconstructed address including the first reconstructed address and the second reconstructed address as an example, see Figure 7 , the process may include:

[0131] S701, receiving a table lookup address based on an initial lookup table, and determining a first reconstructed address and a second reconstructed address according to the table lookup address.

[0132] S702: Output a first lookup value according to the first reconstructed address and the target lookup table.

[0133] S703: Output a second lookup value according to the second reconstructed address and the target lookup table.

[0134] S704, performing mean calculation on the first search value and the second search value, and determining the obtained calculation result as the target search value.

[0135] It should be noted that after receiving the first reconstruction address, the first lookup table module can output the first lookup value to the average module according to the first reconstruction address and the target lookup table; after receiving the second reconstruction address, the second lookup table module can output the second lookup value to the average module according to the second reconstruction address and the target lookup table. Here, the first lookup table module and the second lookup table module can be node values ​​loaded from the target register group into the target lookup table, and the node values ​​stored in the first lookup table module and the second lookup table module are exactly the same. Exemplarily, both the first lookup table module and the second lookup table module can be LUT node values ​​loaded as shown in Table 3.

[0136] In some embodiments, the table lookup address includes an initial coordinate in the first direction and an initial coordinate in the second direction. Accordingly, determining the reconstructed address according to the table lookup address may include:

[0137] Performing binary bit division on the initial coordinates of the first direction to determine a first part of bit values ​​and a second part of bit values ​​in the first direction; and performing binary bit division on the initial coordinates of the second direction to determine a third part of bit values ​​and a fourth part of bit values ​​in the second direction;

[0138] A first reconstructed address and a second reconstructed address are determined according to the first part of the bit value, the second part of the bit value, the third part of the bit value and the fourth part of the bit value.

[0139] It should be noted that, in the embodiment of the present application, the first direction and the second direction are respectively one of the horizontal axis direction and the vertical axis direction, and the first direction and the second direction are different. For example, the first direction may refer to the horizontal axis direction (or referred to as the "x-axis direction"), and the second direction may refer to the vertical axis direction (or referred to as the "y-axis direction"). Accordingly, the initial coordinates of the first direction can be represented by addr x Indicates that the initial coordinates of the second direction can be obtained using addr y In which, the initial coordinates of the first direction and the initial coordinates of the second direction are both expressed in binary, so addr x The bit width is m bits, addr y The bit width is n bits.

[0140] It should also be noted that, in the embodiment of the present application, for the initial coordinates of the first direction, the first part of the bit value may refer to addr x [m-1:1], the second part of the bit value can refer to addr x [0]. For the initial coordinates of the second direction, the third bit value may refer to addr y [n-1:1], the fourth bit value can refer to addr y [0]. Thus, according to the first part of the bit value addr x [m-1:1], the second part bit value addr x [0], the third part bit value addr y [n-1:1] and the fourth part bit value addr y [0], which can be used to determine the first reconstruction address and the second reconstruction address.

[0141] In some embodiments, the first reconstructed address includes a first reconstructed coordinate in a first direction and a first reconstructed coordinate in a second direction, and the second reconstructed address includes a second reconstructed coordinate in the first direction and a second reconstructed coordinate in the second direction. Accordingly, according to the first partial bit value, the second partial bit value, the third partial bit value and the fourth partial bit value, determining the first reconstructed address and the second reconstructed address may include:

[0142] The first reconstructed coordinate in the first direction is set to be equal to the sum of the first part bit value and the second part bit value, and the first reconstructed coordinate in the second direction is set to be equal to the sum of the third part bit value and the fourth part bit value;

[0143] The second reconstructed coordinates in the first direction are set to be equal to the difference between the first and second partial bit values, and the second reconstructed coordinates in the second direction are set to be equal to the difference between the third and fourth partial bit values.

[0144] It should be noted that, in the embodiment of the present application, for the first reconstructed address, the first reconstructed coordinate in the first direction can be represented by addr x1 Indicates that the first reconstructed coordinates in the second direction can be expressed as addr y1 For the second reconstructed address, the second reconstructed coordinates in the first direction can be represented by addr x2 Indicates that the second reconstructed coordinates in the second direction can be expressed using addr y2 express.

[0145] In one possible implementation, the four reconstruction coordinates addr x1 、addr y1 、addr x2 、addr y2They are calculated according to the above formulas (1) to (4) respectively.

[0146] In this way, according to the external input table address addr x and addr y , the addressing module generates the first reconstruction address (addr y1 ,addr x1 ) and the second reconstructed address (addr y2 ,addr x2 ). Then the first reconstructed address (addr y1 ,addr x1 ) is input to the first lookup table module and outputs the first lookup value L(addr y1 ,addr x1 ); the second reconstructed address (addr y2 ,addr x2 ) is input to the second lookup table module and outputs the second lookup value L(addr y2 ,addr x2 ).

[0147] In some embodiments, for the mean value module, performing mean calculation on the lookup value and determining the obtained calculation result as the target lookup value may include:

[0148] A shift operation of shifting right one bit is performed on the sum of the first search value and the second search value, and the obtained calculation result is determined as the target search value.

[0149] In the embodiment of the present application, the mean value calculation can be implemented by right shift operation, and “>>” represents a binary right shift operator. y1 ,addr x1 ) and the second lookup value L(addr y2 ,addr x2 ) is shifted right by one position, as shown in the above formula (6).

[0150] The embodiment of the present application provides a table lookup control method, which is applied to the search device described in the above embodiment. Since the target lookup table stored in the lookup table module is obtained by compressing the initial lookup table, the area of ​​the lookup table can be reduced, and the number of registers and the area of ​​related logic circuits can be reduced accordingly, which can save circuit costs; in addition, by reducing the area of ​​the lookup table, the query speed can be accelerated, the consumption of system resources can be saved, and the overall performance can be improved.

[0151] In yet another embodiment of the present application, Figure 8The following is a schematic diagram of the structure of a display chip provided in an embodiment of the present application. Figure 8 As shown, the display chip 80 may include the lookup table control device 11 described in the above embodiment.

[0152] It should be noted that, for the target register group 104 in the aforementioned embodiment, if it is set outside the lookup table control device 11, then the display chip 80 may also include the target register group 104. That is to say, for the lookup device 100 in the aforementioned embodiment, except for the register controller 12 located outside the display chip 80, other modules (such as the modules inside the lookup table control device 11, the target register group 104, etc.) are all integrated in the display chip 80.

[0153] In yet another embodiment of the present application, Fig. 9 The following is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig. 9 As shown, the electronic device 90 may include a register controller 12 and a Figure 8 The display chip 80 is shown.

[0154] In the embodiment of the present application, the electronic device may be a device with a display function such as a smart phone, a notebook, a PDA, a personal digital assistant, etc. This can be applied to the field of display technology, for example, an organic light-emitting diode (OLED) may be used for display, that is, the lookup table compression scheme of the embodiment of the present application may be applied to the field of OLED display driver chip (OLED Display Driver Integrated Circuit, ODDI).

[0155] It should also be noted that in the embodiment of the present application, the register controller 12 is disposed outside the display chip 80, for example, it can be disposed in a processing chip (such as a CPU). Here, the register controller 12 can write the node values ​​of the target lookup table obtained by compressing the initial lookup table into the target register group in the display chip 80; then, in the display chip 80, the module inside the lookup table control device 11 is used to implement the lookup table compression scheme.

[0156] In the embodiment of the present application, taking the case where the reconstruction address includes the first reconstruction address and the second reconstruction address, and the lookup table module includes the first lookup table module and the second lookup table module as an example, the addressing module in the lookup table control device 11 can determine the first reconstruction address and the second reconstruction address according to the received lookup table address; the first lookup table module can output the first lookup value to the mean module according to the first reconstruction address, and the second lookup table module can output the second lookup value to the mean module according to the second reconstruction address, and then the mean module is used to calculate the mean of the first lookup value and the second lookup value to determine the final target lookup value. In this way, since the target lookup table stored in the first lookup table module and the second lookup table module is obtained by compressing the initial lookup table, the area of ​​the lookup table can be reduced, and the number of registers and the area of ​​the related logic circuit can be reduced accordingly, so that the circuit cost can be saved; in addition, by reducing the area of ​​the lookup table, the query speed can be accelerated, the consumption of system resources can be saved, and the overall performance can be improved.

[0157] In another embodiment of the present application, a computer-readable storage medium is provided for storing a computer program. The computer-readable storage medium can be applied to the search device, chip or electronic device in the embodiment of the present application, and the computer program is executed by at least one processor to implement the corresponding process implemented by the search device, chip or electronic device in each method of the embodiment of the present application, which will not be described in detail for the sake of brevity.

[0158] In another embodiment of the present application, a computer program product is provided, including computer program instructions. The computer program product can be applied to the search device, chip or electronic device in the embodiment of the present application, and the computer program instructions enable the computer to execute the corresponding process implemented by the search device, chip or electronic device in each method of the embodiment of the present application, which will not be described in detail for the sake of brevity.

[0159] Those of ordinary skill in the art will appreciate that the devices, systems, and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0160] Those skilled in the art should also understand that the devices, chips, equipment and methods disclosed in the present application can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0161] It should also be noted that in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0162] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0163] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0164] The features disclosed in several system or method embodiments provided in this application can be arbitrarily combined without conflict to obtain new system embodiments or method embodiments.

[0165] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A search device applied to a lookup table, characterized in that: The search device includes a lookup table control device, and the lookup table control device includes an addressing module, a lookup table module and an average module, wherein: The addressing module is configured to receive a table lookup address based on an initial lookup table, and determine a reconstructed address according to the table lookup address; The lookup table module is configured to receive the reconstructed address and output a lookup value to the average module according to the reconstructed address and the target lookup table; wherein the reconstructed address includes at least two address values, and the lookup value corresponds to the reconstructed address one by one; the lookup table module pre-stores the target lookup table, and the target lookup table is obtained by compressing the initial lookup table; The mean value module is configured to perform mean calculation on the search value and determine the obtained calculation result as the target search value.

2. The search device according to claim 1, characterized in that: The reconstructed address includes a first reconstructed address and a second reconstructed address, the lookup table module includes a first lookup table module and a second lookup table module, and the target lookup table stored in the first lookup table module and the second lookup table module is the same; The first lookup table module is configured to receive the first reconstructed address and output a first lookup value to the average module according to the first reconstructed address and the target lookup table; The second lookup table module is configured to receive the second reconstructed address and output a second lookup value to the average module according to the second reconstructed address and the target lookup table.

3. The search device according to claim 2, characterized in that: The mean value module is configured to perform mean calculation on the first search value and the second search value, and determine the obtained calculation result as the target search value, including: A shift operation of shifting right by one bit is performed on the sum of the first search value and the second search value, and the obtained calculation result is determined as the target search value.

4. The search device according to claim 2, characterized in that: The table lookup address includes an initial coordinate in a first direction and an initial coordinate in a second direction; wherein the first direction and the second direction are respectively one of a horizontal axis direction and a vertical axis direction, and the first direction and the second direction are different; The addressing module is configured to perform binary bit division on the initial coordinates of the first direction to determine the first part bit value and the second part bit value of the first direction; and perform binary bit division on the initial coordinates of the second direction to determine the third part bit value and the fourth part bit value of the second direction; determine the first reconstruction address and the second reconstruction address according to the first part bit value, the second part bit value, the third part bit value and the fourth part bit value.

5. The search device according to any one of claims 1 to 4, characterized in that: The search device also includes a target register group, wherein: The target register group is configured to write and store the node value of the target lookup table according to the write instruction after receiving the write instruction.

6. The search device according to claim 5, characterized in that: The search device further comprises a register controller, wherein: The register controller is configured to send a write instruction to the target register group, wherein the write instruction is used to write the node value of the target lookup table into the target register group and store it.

7. The search device according to any one of claims 1 to 4, characterized in that: The number of nodes included in the target lookup table is one quarter of the number of nodes included in the initial lookup table.

8. A table lookup control method, characterized in that: The method comprises: Receiving a table lookup address based on an initial lookup table, and determining a reconstruction address according to the table lookup address; Outputting a lookup value according to the reconstructed address and the target lookup table; wherein the reconstructed address includes at least two address values, and the lookup value corresponds to the reconstructed address one by one; and the target lookup table is obtained by compressing the initial lookup table; The mean value of the search value is calculated, and the obtained calculation result is determined as the target search value.

9. The method according to claim 8, characterized in that The reconstructed address includes a first reconstructed address and a second reconstructed address, and outputting a search value according to the reconstructed address includes: outputting a first lookup value according to the first reconstructed address and the target lookup table; A second lookup value is output according to the second reconstructed address and the target lookup table.

10. The method according to claim 9, characterized in that The performing mean calculation on the search value and determining the obtained calculation result as the target search value includes: A shift operation of shifting right by one bit is performed on the sum of the first search value and the second search value, and the obtained calculation result is determined as the target search value.

11. The method according to claim 9, characterized in that The table lookup address includes an initial coordinate in a first direction and an initial coordinate in a second direction, wherein the first direction and the second direction are respectively one of a horizontal axis direction and a vertical axis direction, and the first direction and the second direction are different; The determining the reconstruction address according to the table lookup address comprises: Performing binary bit division on the initial coordinates of the first direction to determine a first part of bit values ​​and a second part of bit values ​​of the first direction; Performing binary bit division on the initial coordinates of the second direction to determine a third part of bit values ​​and a fourth part of bit values ​​of the second direction; The first reconstructed address and the second reconstructed address are determined according to the first part bit value, the second part bit value, the third part bit value and the fourth part bit value.

12. A display chip, characterized in that: The display chip includes a search device as described in any one of claims 1 to 5 and 7.

13. An electronic device, characterized in that: The electronic device comprises a register controller and the display chip as claimed in claim 12.

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