Memory management method and memory storage device

Abstract

The invention provides a memory management method and a memory storage device, the memory management method is used for a rewritable nonvolatile memory module comprising a plurality of memory submodules, and the method comprises the following steps: respectively obtaining a plurality of load values of a plurality of command queues corresponding to the plurality of memory submodules; selecting a first command queue from the plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to a first memory sub-module in the plurality of memory sub-modules; and pushing a first to-be-processed command corresponding to the first memory sub-module in the to-be-processed commands to the first command queue. Therefore, the command pushing probability of each memory sub-module is balanced according to the load value, so that the problem of load imbalance caused by non-uniform distribution of recycled data or read-write conflict with a host is solved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a memory storage device. Background Art

[0002] Flash Memory is a non-volatile memory widely used in electronic devices such as memory cards, solid-state drives and portable multimedia players.

[0003] Currently, memories usually use multi-channel and multi-memory dies and read and write data in an interleaved read and write mode to improve the overall throughput of the memory end. However, in some scenarios, there may be an unbalanced load between multiple dies, which in turn affects the efficiency of memory interleaving (flash interleave). Summary of the invention

[0004] The present invention provides a single buffer queue memory management method and a memory storage device, which balance the command push probability of each memory sub-module through the load value, thereby solving the load imbalance problem caused by uneven distribution of recovered data or read-write conflicts with the host in a garbage collection scenario.

[0005] In an exemplary embodiment of the present invention, a memory management method is provided for a rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of memory sub-modules, including: respectively obtaining a plurality of load values ​​of a plurality of command queues corresponding to the plurality of memory sub-modules; selecting a first command queue from the plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to a first memory sub-module; and pushing a first pending command among pending commands corresponding to the first memory sub-module to the first command queue.

[0006] In an exemplary embodiment of the present invention, a memory storage device is provided, comprising a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to electrically connect to a host system. The rewritable non-volatile memory module includes a plurality of memory sub-modules. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to respectively obtain a plurality of load values ​​of a plurality of command queues corresponding to the plurality of memory sub-modules. The memory control circuit unit is used to select a first command queue from a plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to the first memory sub-module. The memory control circuit unit is used to push a first pending command corresponding to the first memory sub-module in the pending commands to the first command queue.

[0007] In an exemplary embodiment of the present invention, a memory control circuit unit is provided for controlling a rewritable non-volatile memory module, wherein the memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to be electrically connected to a host system. The memory interface is used to be electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory sub-modules. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used to respectively obtain a plurality of load values ​​of a plurality of command queues corresponding to the plurality of memory sub-modules. The memory management circuit is used to select a first command queue from a plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to a first memory sub-module among the plurality of memory sub-modules. The memory management circuit is used to push a first pending command corresponding to the first memory sub-module among the pending commands to the first command queue.

[0008] Based on the above, the present invention provides a memory management method and a memory storage device, which can determine the priority of pushing to the command queue according to the time required to execute all commands in each command queue as the initial load value corresponding to the command queue. The command queue with a small load will get more command pushing opportunities, thereby ensuring the load balance of all command queues, thereby realizing flash interleave under the condition of load balance of each command queue, effectively improving the throughput and efficiency of data processing.

[0009] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0011] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0012] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to another exemplary embodiment of the present invention;

[0013] Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

[0014] Figure 4is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0015] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0016] Figure 6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0017] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention;

[0018] Figure 8 FIG. 4 is a schematic diagram showing selecting a command queue to push commands according to a load value according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0021] The ordinal numbers used in the specification and claims of this application, such as "first", "second", etc., are used to modify elements. They themselves do not imply or represent any previous ordinal numbers of the element or elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims. It should be noted that the following embodiments can replace, reorganize, and mix the technical features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure.

[0022] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device is usually used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0023] Figure 1is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to another exemplary embodiment of the present invention.

[0024] Please refer to Figure 1 and Figure 2 The host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 are all electrically connected to a system bus 110.

[0025] In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 can store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is electrically connected to the I / O device 12 via the system bus 110. For example, the host system 11 can transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0026] In the present exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be electrically connected to the memory storage device 10 via a wired or wireless manner. The memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203 or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be electrically connected to various I / O devices such as a global positioning system (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0027] In an exemplary embodiment, the host system mentioned is any system that can actually cooperate with the memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, however, Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Figure 3 In another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33 or an embedded storage device 34 or other non-volatile memory storage devices used therein. The embedded storage device 34 includes various types of embedded storage devices such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342 that directly and electrically connect a memory module to a substrate of the host system.

[0028] Figure 4is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0029] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

[0030] The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In the present exemplary embodiment, the connection interface unit 402 complies with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard and is compatible with the fast non-volatile memory (NVM express) interface standard. Specifically, the fast non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a cache interface, an instruction set and a function set between a controller of a memory storage device and an operating system of a host system, and promotes the data access speed and data transfer rate of a memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in another exemplary embodiment, the connection interface unit 402 may also comply with other suitable standards. In addition, the connection interface unit 402 may be packaged in a chip with the memory control circuit unit 404, or the connection interface unit 402 may be arranged outside a chip including the memory control circuit unit 404.

[0031] The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 .

[0032] The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single level cell (SLC) NAND memory module (i.e., a memory module in which one memory cell can store one bit), a multi-level cell (MLC) NAND memory module (i.e., a memory module in which one memory cell can store two bits), a triple level cell (TLC) NAND memory module (i.e., a memory module in which one memory cell can store three bits), other memory modules or other memory modules with the same characteristics.

[0033] Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0034] In the present exemplary embodiment, the storage cells of the rewritable non-volatile memory module 406 constitute a plurality of physical programming cells, and these physical programming cells constitute a plurality of physical erasing cells. Specifically, the storage cells on the same character line constitute one or more physical programming cells. If each storage cell can store more than 2 bits, the physical programming cells on the same character line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a storage cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a storage cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND type memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0035] In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units usually include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erase. That is, each physical erase unit contains one of the minimum number of storage cells that are erased. For example, the physical erase unit is a physical block.

[0036] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0037] Please refer to Figure 5 The memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

[0038] The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

[0039] In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0040] In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of ​​the rewritable non-volatile memory module 406 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 502. Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

[0041] In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are electrically connected to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 502 may also issue other types of command sequences to the rewritable non-volatile memory module 406 to instruct the execution of corresponding operations.

[0042] The host interface 504 is electrically connected to the memory management circuit 502 and is used to receive and identify the instructions and data transmitted by the host system 11. In other words, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the SATA standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0043] The memory interface 506 is electrically connected to the memory management circuit 502 and is used to access the rewritable non-volatile memory module 406. That is, the data to be written to the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These command sequences are, for example, generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506. These command sequences may include one or more signals, or data on a bus. These signals or data may include scripts or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0044] In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508 , a buffer memory 510 , and a power management circuit 512 .

[0045] The error checking and correction circuit 508 is electrically connected to the memory management circuit 502 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 508 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0046] The buffer memory 510 is electrically connected to the memory management circuit 502 and used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and used to control the power of the memory storage device 10.

[0047] Figure 6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0048] This application scheme takes 8 memory sub-modules as an example for illustration. Figure 6, the rewritable non-volatile memory module 406 includes a first memory submodule 310, a second memory submodule 320, a third memory submodule 330, a fourth memory submodule 340, a fifth memory submodule 350, a sixth memory submodule 360, a seventh memory submodule 370 and an eighth memory submodule 380. For example, the first, second, third, fourth, fifth, sixth, seventh and eighth memory submodules 310, 320, 330, 340, 350, 360, 370 and 380 are memory dies, respectively. The first memory submodule 310 has physical erase units 410(0)-410(N). The second memory submodule 320 has physical erase units 420(0)-420(N). The third memory submodule 330 has physical erase units 430(0)-430(N). The fourth memory submodule 340 has physical erase units 440(0)-440(N). The fifth memory submodule 350 has physical erasing units 450(0)-450(N). The sixth memory submodule 360 ​​has physical erasing units 460(0)-460(N). The seventh memory submodule 370 has physical erasing units 470(0)-470(N). The eighth memory submodule 380 has physical erasing units 480(0)-480(N).

[0049] For example, the first, second, third, fourth, fifth, sixth, seventh and eighth memory submodules 310, 320, 330, 340, 350, 360, 370 and 380 are electrically connected to the memory control circuit unit 404 through independent data buses 316, 326, 336, 346, 356, 366, 376 and 386, respectively. Therefore, the memory management circuit 502 can write data to the first, second, third, fourth, fifth, sixth, seventh and eighth memory submodules 310, 320, 330, 340, 350, 360, 370 and 380 through the data buses 316, 326, 336, 346, 356, 366, 376 and 386 in parallel.

[0050] However, it should be understood that in another exemplary embodiment of the present invention, the first, second, third, fourth, fifth, sixth, seventh and eighth memory sub-modules 310, 320, 330, 340, 350, 360, 370 and 380 may also be electrically connected to the memory control circuit unit 404 via only one data bus. Here, the memory management circuit 502 may write data to the first, second, third, fourth, fifth, sixth, seventh and eighth memory sub-modules 310, 320, 330, 340, 350, 360, 370 and 380 via a single data bus in an interleave manner.

[0051] It is worth mentioning that although the exemplary embodiment of the present invention is described by taking the rewritable non-volatile memory module 406 including eight memory sub-modules as an example, the present invention is not limited thereto, and in other embodiments, the rewritable non-volatile memory module 406 may also include two, four, six or ten memory sub-modules.

[0052] In the traditional mode, each memory submodule corresponds to a command queue, and the scheduling algorithm between command queues is usually a polling algorithm. When the load of each command queue is very balanced, the polling algorithm can better implement the flash interleave of the memory. For the mode of pushing the issued commands to the command queue in sequence according to the order in which the host issues commands under the single buffer architecture, it will lead to some scenarios, such as the conflict between the garbage collection (GC) operation and the read and write operation of the host system 11, resulting in a certain memory submodule being blocked for a long time, and the commands corresponding to other memory submodules cannot be pushed to the idle command queue due to the later issuance time, resulting in inability to execute. At this time, the efficiency of flash interleave will be greatly reduced.

[0053] For example, when executing a GC operation, it is necessary to read recycled data from eight memory sub-modules. If the amount of recycled data distributed in each memory sub-module varies greatly, if commands are pushed in the traditional order of command generation, it is possible that a certain memory sub-module is already fully loaded while other memory sub-modules are always idle. They can only receive and execute the corresponding commands when the command push order reaches the corresponding command of the memory sub-module, thereby wasting memory resources due to unnecessary waiting.

[0054] Alternatively, if it is necessary to read recovered data from 8 memory sub-modules when performing a GC operation, and at the same time, performing host read and write operations requires operating a certain memory sub-module, if the traditional mode of pushing the issued commands to the command queue in the order in which the host issues the commands is followed, the read command may be blocked by the read and write operations of the host system 11 when performing the GC operation, thereby reducing the overall garbage collection efficiency.

[0055] If the above commands are pushed into the command queue in the order of the commands or the order in which the host sends the commands, it is not friendly to the overall command execution efficiency and causes the command waiting time to be too long. Therefore, this solution provides a memory management method to solve the above problem.

[0056] The following takes the rewritable non-volatile memory module 406 including eight memory sub-modules as an example and combines Figure 7 and Figure 8The memory management method of the present invention is described in detail with reference to the embodiments of the present invention. Each process of the method can be adjusted according to the implementation situation, and is not limited thereto.

[0057] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Figure 8 FIG. 4 is a schematic diagram showing selecting a command queue to push commands according to a load value according to an exemplary embodiment of the present invention.

[0058] Combination Figure 7 and Figure 8 As shown, in step S701 , the memory management circuit 502 may put the to-be-processed command into the pre-processed command pool 800 .

[0059] In one embodiment, the pending commands may include a read command and a write command for a certain memory submodule issued by the host system 11, and a read command for the memory management circuit 502 to read the recovered data of each memory submodule when performing a GC operation, etc., but the present invention is not limited thereto. And the status of the pre-processing command pool 800 is updated in real time, that is, there is a new pending command added or the pending command in the pre-processing command pool 800 is removed.

[0060] like Figure 8 As shown, the pending commands may include pending commands corresponding to each memory sub-module respectively. For example, the first pending command 801 in the pre-processed command pool 800 corresponds to the first memory sub-module 310, the second pending command 802 corresponds to the second memory sub-module 320, the third pending command 803 corresponds to the third memory sub-module 330, the fourth pending command 804 corresponds to the fourth memory sub-module 340, the fifth pending command 805 corresponds to the fifth memory sub-module 350, the sixth pending command 806 corresponds to the sixth memory sub-module 360, the seventh pending command 807 corresponds to the seventh memory sub-module 370, and the eighth pending command 808 corresponds to the eighth memory sub-module 380.

[0061] In step S702 , the memory management circuit 502 respectively obtains the initial load value of each command queue corresponding to each memory sub-module.

[0062] In one embodiment, the commands to be processed may be classified into read commands, write commands, and erase commands according to the command type. Specifically, since the execution time of commands of different command types is different, the weights may be set according to the ratio of the command execution time of each command type, or different priority weights may be set for different types of commands. In actual applications, the weights may be set according to specific needs, and are not specifically limited here.

[0063] The memory management circuit 502 may obtain the execution completion time of each command according to the command type of each command included in each command queue, and sum up the execution completion time of each command according to the weight of each command type to serve as the load value or initial load value of each command queue.

[0064] The following description is made by taking the calculation of the load value or initial load value of a certain command queue (the first command queue and the second command queue) as an example. A similar method can be applied to other command queues.

[0065] The memory management circuit 502 can obtain the load value or initial load value of a command queue by using the following formula 1, which is as follows:

[0066] Ln-1=k1×Tread+k2×Tprog+k3×Terase

[0067] Among them, Ln-1 is the load value or initial load value of the nth command queue, k1 is the number of read commands in the nth command queue, k2 is the number of write commands in the nth command queue, k3 is the number of erase commands in the nth command queue, Tread is the execution completion time of executing a read command, Tprog is the execution completion time of executing a write command, and Terase is the execution completion time of executing an erase command. In the calculation process here, the priority of each type of command is regarded as the same priority. In actual applications, the corresponding priority weights can be set according to specific needs.

[0068] In one embodiment, if the first command queue includes 2 read commands, 1 write command and 1 erase command, the execution completion time of each command is summed up according to the above formula 1 to serve as the load value or initial load value of the first command queue: L0=2×Tread+1×Tprog+1×Terase.

[0069] In another embodiment, if the second command queue includes 1 read command and 1 write command, the execution completion time of each command is summed up according to the above formula 1 to serve as the load value or initial load value of the second command queue: L1=1×Tread+1×Tprog.

[0070] Therefore, the memory management circuit 502 can obtain the following equation through the above formula 1: Figure 8 The initial load values ​​L0, L1, L2, L3, L4, L5, L6, L7 shown correspond to the first, second, third, fourth, fifth, sixth, seventh and eighth command queues respectively.

[0071] In step S703 , the memory management circuit 502 may sort the initial load values ​​of each command queue in order of the load value from small to large.

[0072] In one embodiment, the memory management circuit 502 may sort the initial load values ​​of the command queues in ascending order as L5, L1, L7, L0, L2, L4, L3, and L6, where L5 has the smallest load value.

[0073] In step S704 , the memory management circuit 502 selects a command queue with the smallest load value from each command queue as a target command queue to push the to-be-processed command.

[0074] In one embodiment, the memory management circuit 502 selects a target command queue with the smallest load value ( L5 ) from each command queue, and the target command queue is the sixth command queue corresponding to the sixth memory sub-module 360 ​​.

[0075] In step S705 , the memory management circuit 502 may determine whether the target command queue (ie, the sixth command queue) is not full and whether there is a pending command (ie, the sixth processing command 806 ) corresponding to the target command queue in the pre-processing command pool 800 .

[0076] Furthermore, if the target command queue is full, it indicates that the load value of the current memory submodule has reached the maximum, and unless at least one command is dequeued from the target command queue, the pending command cannot be pushed into the target command queue.

[0077] In one embodiment, the memory management circuit 502 may learn the threshold of the number of commands that the target command queue corresponding to the memory submodule may include through the model of the memory submodule. When the number of commands included in the target command queue is greater than or equal to the threshold, the memory management circuit 502 may determine that the target command queue is full; when the number of commands included in the target command queue is less than the threshold, the memory management circuit 502 may determine that the target command queue is not full. The present invention is not limited thereto.

[0078] In one embodiment, the threshold is related to the model of the memory sub-module.

[0079] When the target command queue is not full and there are pending commands corresponding to the target command queue in the pre-processed command pool 800 , in step S706 , the memory management circuit 502 may push the pending commands corresponding to the target command queue to the target command queue and update the load value of the target command queue.

[0080] In this embodiment, the target command queue is the sixth command queue. If the sixth command queue is not full and there is a sixth pending command 806 corresponding to the sixth command queue in the pre-processing command pool 800, the memory management circuit 502 can push the sixth pending command 806 to the sixth command queue and update the load value of the sixth command queue. At this time, the updated load value L5′ corresponding to the sixth command queue is L5′=L5+1×T, where T is the execution completion time of the sixth pending command 806.

[0081] The load value of each command queue corresponding to each memory sub-module is determined by the command execution time, and the target command queue corresponding to the memory sub-module is selected for priority execution based on the load value, and the command is pushed to the target command queue, so that the load of each command queue is in a relatively balanced state, thereby improving the overall command processing efficiency.

[0082] In step S707 , the memory management circuit 502 determines whether the pre-processing command pool 800 is empty.

[0083] When the pre-processing command pool 800 is empty, that is, there are no commands to be processed in the pre-processing command pool 800, the process ends.

[0084] When the pre-processing command pool 800 is not empty, that is, there are still pending commands in the pre-processing command pool 800, return to step S703, the memory management circuit 502 can re-sort the updated load value of the target command queue and the initial load values ​​of each command queue except the target command queue in order from small to large, and continue to execute the subsequent process of reselecting the target command queue to push the pending commands until each command queue is full or the pre-processing command pool 800 is empty.

[0085] In this embodiment, if the target command queue is full and there is no pending command corresponding to the target command queue among the pending commands, or there is no corresponding GC operation in the memory sub-module corresponding to the target command queue, in step S708, the memory management circuit 502 removes the target command queue from the command queue and removes the load value corresponding to the target command queue from the load value.

[0086] In one embodiment, if the target command queue is full and there are no pending commands corresponding to the target command queue in the pre-processing command pool 800 (for example, there is no garbage collection operation on the target memory sub-module corresponding to the target command queue), the above steps S704, S705 and S706 are performed on the remaining memory sub-modules except the target memory sub-module, so as to facilitate the load of the command queue corresponding to each memory sub-module to be in a relatively balanced state.

[0087] After removing the target command queue from the command queues and removing the load value corresponding to the target command queue from the load value, in step S709 , the memory management circuit 502 determines whether there is a command queue to be selected.

[0088] If the memory management circuit 502 determines that there is still a command queue to be selected, the process returns to step S704 to continue selecting the command queue with the smallest load value from among the command queues.

[0089] The above-mentioned pushing of pending commands to the target command queue that is not full and has the smallest load value is conducive to ensuring that the loads of the command queues corresponding to the memory sub-modules are relatively balanced, which not only improves the overall command processing performance, but also effectively avoids the situation where the host's read and write operations and GC operations are performed on the same memory sub-module at the same time, resulting in the read command being blocked by the host's read and write operations when performing GC operations, thereby reducing the overall garbage collection efficiency. It effectively solves the problem of load imbalance caused by uneven distribution of recovered data or read and write conflicts with the host.

[0090] If the memory management circuit 502 determines that there is no command queue to be selected, it means that each command queue is full, or the pre-processing command pool 800 is empty, and the process ends.

[0091] Based on the above, the present invention provides a memory management method and a memory storage device, which can use the time required to execute all commands in each command queue as the load value corresponding to the command queue, thereby determining the priority of pushing to the command queue according to the load value of each command queue. The command queue with a small load will get more command pushing opportunities, thereby ensuring the load balance of all command queues, thereby realizing flash interleave when each command queue is load balanced, and effectively improving the throughput and efficiency of data processing.

[0092] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory sub-modules, characterized in that: include: Respectively acquiring a plurality of load values ​​of a plurality of command queues corresponding to the plurality of memory submodules; selecting a first command queue from the plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to a first memory submodule; as well as Pushing a first to-be-processed command corresponding to the first memory submodule among the to-be-processed commands to the first command queue.

2. The memory management method according to claim 1, characterized in that: The step of respectively acquiring the multiple load values ​​of the multiple command queues corresponding to the multiple memory sub-modules further includes: Obtaining the execution completion time of each command according to the command type of each command in each command queue; The execution completion time of each of the commands is summed up to serve as the load value of each of the command queues.

3. The memory management method according to claim 1, characterized in that: The step of selecting the first command queue from the multiple command queues according to the multiple load values, wherein the first command queue corresponds to the first memory submodule among the multiple memory submodules, further includes: Sorting the multiple load values ​​in ascending order of the load values ​​to obtain a sorting result; and The first command queue is selected from the multiple command queues according to the sorting result, wherein the first load value corresponding to the first command queue is the smallest.

4. The memory management method according to claim 3, characterized in that: After the step of selecting the first command queue from the multiple command queues according to the sorting result, the method further includes: determining whether the first command queue is not full and whether there is a first pending command in the pending commands corresponding to the first command queue; When the first command queue is not full and there is a first to-be-processed command corresponding to the first command queue among the to-be-processed commands, the first to-be-processed command is pushed into the first command queue.

5. The memory management method according to claim 3, characterized in that: After the step of selecting the first command queue from the multiple command queues according to the sorting result, the method further includes: determining whether the first command queue is not full and whether there is a first pending command in the pending commands corresponding to the first command queue; When the first command queue is full and / or there is no first pending command in the pending commands corresponding to the first command queue, the first command queue is removed from the multiple command queues, and the first load value corresponding to the first command queue is removed from the multiple load values.

6. The memory management method according to claim 4 or 5, characterized in that: The step of determining whether the first command queue is not full and whether there is a first to-be-processed command in the to-be-processed commands corresponding to the first command queue further includes: Whether the first command queue is not full is determined according to whether the number of commands in the first command queue is less than a threshold.

7. The memory management method according to claim 1, characterized in that: The method further comprises: After pushing the first to-be-processed command to the first command queue, updating a first load value corresponding to the first command queue.

8. The memory management method according to claim 1, characterized in that: The pending commands include the pending commands corresponding to the plurality of memory sub-modules, respectively.

9. A memory storage device, characterized in that: include: A connection interface unit for electrically connecting to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory sub-modules; as well as A memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to respectively obtain multiple load values ​​of multiple command queues corresponding to the multiple memory sub-modules, wherein the memory control circuit unit is used to select a first command queue from the plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to the first memory submodule, and The memory control circuit unit is used for pushing a first to-be-processed command corresponding to the first memory sub-module among the to-be-processed commands to the first command queue.

10. The memory storage device according to claim 9, characterized in that: In the operation of the memory control circuit unit respectively acquiring the multiple load values ​​of the multiple command queues corresponding to the multiple memory sub-modules, it also includes: The memory control circuit unit is further used to obtain the execution completion time of each command according to the command type of each command in each command queue, and sum up the execution completion time of each command to serve as the load value of each command queue.

11. The memory storage device according to claim 9, characterized in that: The memory control circuit unit selects the first command queue from the plurality of command queues according to the plurality of load values, wherein the first command queue corresponds to the operation of the first memory sub-module among the plurality of memory sub-modules, further comprising: The memory control circuit unit is further used to sort the multiple load values ​​in order from small to large to obtain a sorting result, and The memory control circuit unit is further configured to select the first command queue from the plurality of command queues according to the sorting result, wherein a first load value corresponding to the first command queue is the smallest.

12. The memory storage device according to claim 11, characterized in that After the memory control circuit unit selects the first command queue from the plurality of command queues according to the sorting result, The memory control circuit unit is further used to determine whether the first command queue is not full and whether there is a first pending command corresponding to the first command queue among the pending commands; When the first command queue is not full and there is a first to-be-processed command corresponding to the first command queue among the to-be-processed commands, the memory control circuit unit is further configured to push the first to-be-processed command into the first command queue.

13. The memory storage device according to claim 11, characterized in that After the memory control circuit unit selects the first command queue from the plurality of command queues according to the sorting result, The memory control circuit unit is further configured to determine whether the first command queue is not full and whether there is a first pending command corresponding to the first command queue among the pending commands. When the first command queue is full and / or there is no first pending command corresponding to the first command queue among the pending commands, the memory control circuit unit is also used to remove the first command queue from the multiple command queues and remove the first load value corresponding to the first command queue from the multiple load values.

14. The memory storage device according to claim 12 or 13, characterized in that: In the operation of the memory control circuit unit determining whether the first command queue is not full and whether there is a first to-be-processed command corresponding to the first command queue among the to-be-processed commands, the method further includes: The memory control circuit unit is further configured to determine whether the first command queue is not full according to whether the number of commands in the first command queue is less than a threshold.

15. The memory storage device according to claim 9, characterized in that After the memory control circuit unit pushes the first to-be-processed command to the first command queue, the memory control circuit unit is further configured to update a first load value corresponding to the first command queue.

16. The memory storage device according to claim 9, characterized in that The pending commands include the pending commands corresponding to the plurality of memory sub-modules, respectively.

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