BIOS parameter debugging method, program product, electronic device and storage medium

Abstract

The present application discloses a BIOS parameter debugging method, program product, electronic device and storage medium, which relate to the field of BIOS tuning technology, including inputting each group of candidate BIOS parameter combinations into a hybrid model respectively; obtaining at least one of the CPU utilization sub-score, memory bandwidth sub-score, delay sub-score and power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output by the hybrid model when running in a target business scenario; and determining the target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, memory bandwidth sub-score, delay sub-score and power consumption sub-score. The BIOS parameter debugging method of the present application comprehensively considers the synergistic effect between various hardwares and has the technical effects of high tuning efficiency, good tuning effect and dynamic tuning capability.

Description

Technical Field

[0001] The present application relates to the technical field of BIOS tuning, and in particular to a BIOS parameter debugging method, program product, electronic device, and storage medium. Background Art

[0002] With the development of cloud computing and data centers, server performance tuning has become critical for improving computing resource utilization. Currently, one of the core methods for server performance tuning is to optimize hardware behavior by adjusting BIOS parameters. Related technologies primarily use manual experience-based tuning to adjust BIOS parameters. For example, to adjust different workloads such as AI training and database transactions, manual switching of BIOS configurations is required, which is inefficient, error-prone, and results in poor tuning. Furthermore, it struggles to cope with complex and changing workload environments. Summary of the Invention

[0003] The present application provides a BIOS parameter debugging method, program product, electronic device and storage medium to at least solve the problems of low efficiency and poor tuning effect in related technologies.

[0004] This application provides a BIOS parameter debugging method, including:

[0005] Inputting each set of candidate BIOS parameter combinations into a hybrid model, the hybrid model comprising: at least two of a pre-built CPU load model, a memory load model, and a GPU load model for simulating server operation;

[0006] Obtaining at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model when running in the target business scenario;

[0007] Based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, a target BIOS parameter combination corresponding to the target business scenario is determined from each group of the candidate BIOS parameter combinations.

[0008] The present application also provides a computer program product, comprising:

[0009] A first processing module is configured to input each set of candidate BIOS parameter combinations into a hybrid model, wherein the hybrid model includes at least two of a pre-built CPU load model, a memory load model, and a GPU load model;

[0010] a second processing module, configured to obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model when running in a target business scenario;

[0011] A third processing module is configured to determine, from each group of the candidate BIOS parameter combinations, a target BIOS parameter combination corresponding to the target business scenario based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned BIOS parameter debugging methods when executing the computer program.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned BIOS parameter debugging methods are implemented.

[0014] Through this application, different candidate BIOS parameter combinations are input into a hybrid model that can simulate hardware collaborative efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, and the target BIOS parameter combination is obtained by screening based on these sub-scores. Therefore, the technical problems of low efficiency and poor tuning effect can be solved, and the technical effect of responding to load fluctuations, comprehensively considering the synergy between various hardware, and having high tuning efficiency, good tuning effect and dynamic tuning capability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 This is a flowchart of a BIOS parameter debugging method provided in an embodiment of the present application;

[0017] Figure 2 A second flow chart of a BIOS parameter debugging method provided in an embodiment of the present application;

[0018] Figure 3 The third flowchart of a BIOS parameter debugging method provided in an embodiment of the present application;

[0019] Figure 4 A fourth flowchart of a BIOS parameter debugging method provided in an embodiment of the present application;

[0020] Figure 5 A schematic diagram of the structure of a computer program product provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the BIOS parameter debugging method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0026] like Figure 2 As shown, the execution device of the BIOS parameter debugging method of the present application includes: a device main program, a test device, a database, and a server. Among them, the device main program is used to schedule data and various models, the test device is responsible for calculating data acquisition and executing tasks; and the database is used for data storage and parameter storage.

[0027] The overall architecture of the BIOS parameter debugging method of the present application includes: a BIOS data acquisition layer, a BIOS parameter modeling layer, a load generation layer, a performance dynamic evaluation and modeling layer, and a dynamic performance adjustment layer.

[0028] Among them, the main program uses the SCE tool to batch obtain the Map String and configuration path of BIOS options, supports atomic setting and checksum verification of parameter groups, builds a BIOS parameter library based on the I, II, and III rule bases, and obtains multiple sets of candidate BIOS parameter combinations.

[0029] Atomic configuration of BIOS options is achieved through the SCELNX_64 tool, supporting transactional operations of configuration groups (all successful or rollback to the last stable state).

[0030] After starting the GPU bandwidth test (nvqual tool) based on the priority policy, superimpose the CPU / memory stress model (stress-ng, stressapptest) to simulate the resource contention in real business scenarios and run the hybrid model.

[0031] Real-time monitoring of CPU IPC, memory bandwidth, GPU memory utilization, and overall machine power consumption, achieving millisecond-level sampling.

[0032] A state-action space model is constructed. The state vector includes the BIOS configuration code and the real-time score value, and the action space is the BIOS option adjustment instruction (such as HyperThreading: 0→1). A performance and BIOS parameter evaluation model is constructed to determine the target BIOS parameter combination corresponding to the target business scenario from multiple sets of candidate BIOS parameter combinations based on CPU utilization sub-scores, memory bandwidth sub-scores, latency sub-scores, and power consumption sub-scores.

[0033] During the application process, BIOS parameters are dynamically adjusted according to business needs to ensure a balance between server performance and resources.

[0034] The specific implementation method will be described in detail below.

[0035] An embodiment of the present application provides a BIOS parameter debugging method, and the method is described in detail in conjunction with the execution process of the BIOS parameter debugging method.

[0036] like Figure 1 As shown, the BIOS parameter debugging method includes: step 110, step 120 and step 130.

[0037] Step 110: Input each set of candidate BIOS parameter combinations into the hybrid model respectively;

[0038] In this step, BIOS (Basic Input / Output System) parameters are configuration options used to configure hardware and system behavior when the computer starts, including but not limited to: boot settings, CPU and overclocking, memory, storage, power management, security, and monitoring parameters.

[0039] The candidate BIOS parameter combination is a combination of state values ​​of one or more adjustable BIOS parameters. Different candidate BIOS parameter combinations correspond to different BIOS parameters and / or different state values ​​of BIOS parameters.

[0040] The hybrid model is established for each component and link of the server. It can simulate the hardware collaborative efficiency, hardware resource competition and dynamic load characteristics during the operation of the server. It includes simulation models, algorithm models, data acquisition models and other categories of models.

[0041] The hybrid model may include: at least two of a pre-built CPU load model, a memory load model, and a GPU load model for simulating server operation.

[0042] The CPU load model is a model used to simulate CPU load, the memory load model is a model used to simulate memory load, and the GPU load model is a model used to simulate GPU load.

[0043] In some embodiments, the hybrid model may also include other types of load models, such as a graphics card load model and a PCIe link load model, and the load models dynamically collaborate with each other during operation.

[0044] The BIOS parameter combination is used to configure the hybrid model so that it can simulate the server's operation under the corresponding BIOS parameter configuration and output corresponding performance indicators. It is understood that different candidate adjustable parameters input to the hybrid model may also result in different performance indicators output by the hybrid model.

[0045] Step 120: Obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each set of candidate BIOS parameter combinations output by the hybrid model when running in the target business scenario;

[0046] In this step, the target business scenario can be any business scenario, such as the current business scenario, or can be user-defined. For each business scenario, the corresponding BIOS parameter debugging method is similar. The following takes a business scenario as an example for explanation.

[0047] CPU utilization, memory bandwidth, latency, and power consumption are performance indicators used to evaluate server performance and computing power. Sub-scores are quantitative scores of each performance indicator. The higher the sub-score, the better the corresponding performance indicator.

[0048] Different combinations of candidate BIOS parameters may result in different server performance and computing power after configuration.

[0049] In some embodiments, the performance indicators may also include other indicators, such as graphics card related indicators, etc., which may be based on user-defined settings and are not limited in this application.

[0050] During the actual execution process, the hybrid model can run according to the given BIOS parameters, such as obtaining the BIOS option combination and BIOS option path from the BIOS parameter library, obtaining the Map String of the BIOS options, and constructing a parameter relationship map. To configure the BIOS options, multiple transactions are established through the thread pool, and each transaction sets the option values ​​of the BIOS options in batches through the SCE. The BIOS parameter path is traversed in a loop on the control machine side, and after setting the parameter path of each BIOS, the server is restarted to make the BIOS parameters take effect. At the same time, the hybrid model of the server is started. During this process, performance indicators are dynamically collected, including but not limited to CPU utilization, memory bandwidth, latency, power consumption and other performance indicators, and converted into scores to obtain corresponding sub-scores.

[0051] Step 130: Determine a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0052] In this step, the target BIOS parameter combination is a screened BIOS parameter combination that can best match the server performance of the server with the requirements in the target business scenario, and may include one or more candidate BIOS parameter combinations.

[0053] For example, the server performance computing power value corresponding to each set of candidate BIOS parameter combinations can be obtained by summing the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score, and the set of candidate BIOS parameter combinations with the highest server performance computing power value can be selected as the target BIOS parameter combination.

[0054] For the sub-scores not obtained in step 120 , they may be assigned a value of 0 for calculation in step 130 .

[0055] During their research and development, the inventors discovered that the following BIOS tuning methods exist in the relevant art: 1) Manual BIOS tuning: Administrators set BIOS parameters based on experience (e.g., disabling hyperthreading, enabling Turbo Boost), and verify the results using performance testing tools. This method relies on manual experience and cannot cover complex parameter combinations (e.g., a server BIOS has over 500 options, with a combination space of 10^100). Furthermore, the tuning cycle is long and it cannot respond to load fluctuations in real time. 2) Static performance testing tools: Using tools like Prime95 (CPU stress testing) and FIO (storage I / O testing) to independently test the performance of each component. This method only tests a single component and ignores hardware synergy effects (e.g., CPU cache contention leading to reduced memory bandwidth). Furthermore, it lacks the ability to simulate business scenarios (e.g., mixed computing and I / O loads). 3) Threshold-based monitoring and alarming: Fixed thresholds are set (e.g., CPU utilization >90% triggers an alarm), and manual tuning is required. This method requires a passive response, triggering corrections only after performance degradation occurs, resulting in a high risk of business jitter. Furthermore, it cannot predict potential bottlenecks (e.g., future performance degradation due to an increase in PCIe link bit error rates).

[0056] In the present application, a hybrid model capable of simulating hardware collaborative efficiency and dynamic load characteristics is pre-constructed, and multiple groups of candidate BIOS parameter combinations corresponding to different BIOS parameter combination forms are respectively input into the hybrid model. The hybrid model simulates the operation status under the influence of hardware collaborative efficiency and dynamic load characteristics in the target business scenario, and obtains the server performance computing power value corresponding to the server under different BIOS parameter combination forms. According to the server performance computing power value, one or more groups of candidate BIOS parameter combinations that can enable the server performance to reach a higher level in the target business scenario are screened to achieve BIOS parameter tuning. The dynamic tuning capability is achieved by combining the dynamic load model with the real-time performance score. It can comprehensively consider the synergy between various hardware, such as the CPU cache contention leading to the decrease in memory bandwidth and other problems, realize the rapid location of cross-component resource conflicts, reduce invalid configuration paths, and obtain the target BIOS parameter combination that is most suitable for the current business scenario. It is suitable for complex and changeable load environments and has a good tuning effect.

[0057] In addition, the server performance computing power is quantitatively evaluated through the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output by the hybrid model. It can combine multi-dimensional performance indicators for comprehensive evaluation to achieve coordinated optimization of energy efficiency and performance. For example, considering the natural contradiction between high-performance modes (such as CPU Turbo Boost) and energy-saving strategies (such as C-state), dynamically balancing instantaneous computing power requirements and long-term energy consumption costs, and predicting the optimal BIOS parameter combination through reinforcement learning algorithms, reducing traditional manual traversal and tuning time, and improving tuning efficiency and tuning effects.

[0058] According to the BIOS parameter debugging method provided in the embodiment of the present application, different candidate BIOS parameter combinations are respectively input into a hybrid model that can simulate hardware collaborative efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, so as to obtain the target BIOS parameter combination based on these sub-scores. The method can respond to load fluctuations, comprehensively consider the synergy between various hardware, and has high tuning efficiency, good tuning effect and dynamic tuning capability.

[0059] In some embodiments, step 130 may include:

[0060] Based on the weight sequence, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score are weighted and summed to obtain the server performance computing power score corresponding to each set of candidate BIOS parameter combinations;

[0061] Based on the server performance computing power score, a target BIOS parameter combination is determined from each group of candidate BIOS parameter combinations.

[0062] In this embodiment, the server performance computing power score is used to represent the level of the server performance computing power. The higher the score, the higher the computing power value.

[0063] The weight sequence is a sequence consisting of weights corresponding to various performance indicators such as CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score.

[0064] The weight sequence can be user-defined or initialized. For example, the weight sequence can be set to: CPU utilization (CPU_IPC): 0.4; memory bandwidth (Mem_BW): 0.3; latency (Latency): 0.2; power consumption (Power): 0.1.

[0065] During the actual execution process, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score can be weighted and summed based on the weight sequence to obtain the server performance computing power score.

[0066] For each set of candidate BIOS parameter combinations, a server performance computing power score can be calculated, and the set of candidate BIOS parameter combinations with the highest scores among these server performance computing power scores is determined as the target BIOS parameter combination.

[0067] According to the BIOS parameter debugging method provided in the embodiment of the present application, by dynamically collecting performance indicators and converting them into sub-scores, a weighted score is used to obtain a server performance computing power score to quantify the performance of the server under different BIOS parameter combinations, which has better tuning precision and accuracy.

[0068] In some embodiments, the weight sequence may be determined using a hierarchical analysis method.

[0069] In this embodiment, the Analytic Hierarchy Process (AHP) constructs a hierarchical structure, compares two-by-two judgment matrices, calculates weights, and performs consistency checks.

[0070] In the actual implementation process, a weighted evaluation function can be constructed based on the hierarchical analysis method to calculate the server performance computing power value. For example, the server performance computing power score Score can be calculated using the following formula:

[0071] Score = 0.4 * CPU utilization sub-score + 0.3 * memory bandwidth sub-score + 0.2 * latency sub-score + 0.1 * power consumption sub-score.

[0072] According to the BIOS parameter debugging method provided in the embodiment of the present application, a multi-dimensional performance scoring model is constructed by adopting the hierarchical analysis method, and the target BIOS parameter combination is obtained by comprehensive screening of CPU IPC, memory bandwidth, latency and power consumption indicators to achieve BIOS parameter tuning, which can reduce energy efficiency fluctuations and improve the tuning effect.

[0073] In some embodiments, the weight sequence may be adjusted based on target business requirements of a target business scenario.

[0074] In this embodiment, the target business demand may be the demand for server performance under the target business scenario. It is understandable that for different business scenarios, the emphasis on the demand for server computing, latency and other performance may be different. Based on the emphasis of the target business demand, the initial weight sequence corresponding to the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score and power consumption sub-score may be adjusted.

[0075] In some embodiments, when the target business demand focuses on computing, the weight corresponding to the CPU utilization sub-score in the weight sequence is increased;

[0076] When the target business demand focuses on latency, the weight corresponding to the latency sub-score in the weight sequence is increased.

[0077] For example, if the target business requirement focuses more on calculation, the weight sequence can be adjusted to: [0.4, 0.3, 0.2, 0.1];

[0078] If the target business requirement focuses more on latency, the weight sequence can be adjusted to: [0.2, 0.2, 0.5, 0.1].

[0079] According to the BIOS parameter debugging method provided in the embodiment of the present application, the weight sequence is dynamically adjusted according to the target business needs, and various performance indicators of the server computing power can be monitored according to the business type to achieve adaptive scoring, thereby screening the target BIOS parameter combination that best matches the current business scenario, which is suitable for complex and changeable business scenarios.

[0080] In some embodiments, parameter combinations can also be predicted based on the PPO algorithm, and the state-action space can be modeled to calculate the server performance computing power score corresponding to each group of candidate BIOS parameter combinations.

[0081] The State is the current BIOS configuration code (binary vector) plus the real-time performance score (Score). The Action is used to adjust the value of a specified BIOS option (e.g., HyperThreading: 0→1).

[0082] Use PyTorch to build a three-layer MLP that takes in a state vector and outputs a probability distribution for actions. Execute the policy in parallel across multiple servers to accelerate convergence. Record the candidate BIOS parameter combinations corresponding to the top-N server performance and computing power scores, and output the corresponding relationship between the candidate BIOS parameter combinations and server performance and computing power.

[0083] This allows the target BIOS parameter combination corresponding to the actual business scenario to be automatically matched in the subsequent application process, such as TurboBoost=Enabled in the HPC scenario and SR-IOV=Enable in the virtualization scenario.

[0084] In some embodiments, inputting each set of candidate BIOS parameter combinations into the hybrid model may include:

[0085] The hybrid model is configured based on each group of candidate BIOS parameter combinations. When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected in combination with the target business scenario to run the hybrid model.

[0086] In this embodiment, whether a steady state is reached may be determined based on the size of the processor (SM) utilization. If the SM utilization is greater than or equal to a preset threshold, such as SM utilization ≥ 85% or SM utilization ≥ 90%, it is considered that a steady state is reached.

[0087] During the actual execution process, the GPU load model can be activated to a stable state based on the simulation of hardware resource competition, and allocated in advance according to the load size, thread size, and CPU utilization; then the CPU load model or memory load model can be dynamically injected for concurrency control, thereby avoiding the situation where the GPU cannot be executed due to CPU priority startup, and improving the stability of server operation.

[0088] The BIOS option combinations (i.e., candidate BIOS parameter combinations) and BIOS option paths are then retrieved from the BIOS parameter library, and a BIOS option map string is obtained to construct a parameter relationship graph. To configure BIOS options, multiple transactions are established through the thread pool. Each transaction uses the SCE to batch-set the BIOS option values. The control machine loops through the BIOS parameter paths, setting each BIOS parameter path. The server is then restarted to make the BIOS parameters effective. Simultaneously, the server's hybrid dynamic model is activated. During this process, performance metrics such as CPU utilization, memory bandwidth, latency, and power consumption are dynamically collected. By weighting the sub-scores corresponding to each performance metric, the server's computing power performance under each BIOS parameter configuration is quantitatively evaluated.

[0089] According to the BIOS parameter debugging method provided in the embodiment of the present application, by hybrid dynamic load model and adopting priority-driven hybrid load superposition strategy, it can support rapid adaptation of heterogeneous computing power scenarios and improve business performance.

[0090] In some embodiments, after inputting each set of candidate BIOS parameter combinations into the hybrid model, the method may further include:

[0091] In the event that any parameter setting in the candidate BIOS parameter combination fails, the hybrid model is controlled to recover to the last stable state.

[0092] In this embodiment, a failure rollback mechanism can be set. If any setting in the parameter group fails, it will automatically recover to the last stable state. The execution instruction is: SCELNX_64 / i / ms HyperThreading / qv 0x00.

[0093] According to the BIOS parameter debugging method provided in the embodiment of the present application, by setting an atomic rollback mechanism, it can ensure that the BIOS configuration automatically recovers to a stable state when it fails, thereby improving the reliability of the system.

[0094] In some embodiments, the CPU load model may be constructed based on the following steps:

[0095] Constructing a dynamic power-aware model for executing workloads;

[0096] Simulate mixed load scenarios and construct business scenario simulation models;

[0097] A CPU load model is obtained based on at least one of a dynamic power consumption awareness model and a business scenario simulation model.

[0098] In this embodiment, the CPU load model may include one or more of a dynamic power consumption awareness model and a business scenario simulation model. In actual application, a corresponding model may be selected according to the target business scenario.

[0099] To build a dynamic power consumption awareness model, you can use the Intel PTU tool to perform real-time TDP calibration. Execute the load: ptu-ct 1 -t 172800 -log-logname ptu_stress–csv. Combined with the RAPL interface, you can monitor the thermal power consumption TDP in real time (with an accuracy of ±2%).

[0100] To build a business scenario simulation model, you can use stress-ng to simulate a mixed load scenario. The execution strategy is: input the business state thread / kernel state thread ratio of 3 / 1, and use stress-ng -c [business state thread] -i [kernel state thread] -t48H [duration].

[0101] In some embodiments, the memory load model may be constructed based on the following steps:

[0102] Perform full memory channel scans and build a joint bandwidth-latency model based on the collected correctable error rates.

[0103] Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model;

[0104] A memory load model is obtained based on at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model.

[0105] In this embodiment, the memory load model may include one or more of a bandwidth-delay joint model and a dynamic pressure adjustment algorithm model. In actual application, the corresponding model may be selected according to the target business scenario.

[0106] To build a joint bandwidth-delay model, use stressapptest to scan all memory channels. Use the Error Detection and Correction (EDAC) module to collect the correctable error rate. Then, run the stressapptest -M [value] -s [time] reliability model to obtain the joint bandwidth-delay model.

[0107] To build a dynamic pressure regulation algorithm model, you can use an adaptive thread control strategy to set the dynamic pressure regulation algorithm. For example, when the actual pressure is less than 90% of the target value, use stress-ng --vm 16 [working threads; if the reserved pressure cannot be reached, increase the number of threads appropriately] vm-bytes 90% [load size] -t 48H [duration], obtain the PSI indicator through / proc / pressure / memory, and dynamically maintain the 90% load threshold.

[0108] In some embodiments, an Nvqual depth test can be executed, using the command / nvqual --test [duration] --index<0~num-1> --loops n to perform bandwidth performance testing, collect memory bandwidth and SM, etc., perform memory bandwidth bottleneck detection, and build a GPU load model.

[0109] According to the BIOS parameter debugging method provided in the embodiment of the present application, by constructing multiple load models to simulate the synergistic effect between various hardware, dynamically respond to load fluctuations, such as considering the difference between burst traffic and steady-state load, as well as delay fluctuations or power consumption mutations in high-concurrency scenarios, thereby improving the tuning effect.

[0110] The following describes how to obtain candidate BIOS parameter combinations.

[0111] In some embodiments, before step 110, the method may further include:

[0112] According to the correlation between BIOS parameters, BIOS parameters are classified to obtain multiple parameter sets;

[0113] Based on a combination mechanism corresponding to a target class parameter set among the multiple parameter types, combining the state values ​​of the parameters in the target class parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set;

[0114] The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

[0115] In this embodiment, the association relationship is used to indicate whether there is a correlation between different categories of BIOS parameters, and can be obtained by analyzing the correlation between server hardware components (CPU, memory, PCIe devices) and BIOS options. For example, BIOS parameters can be divided into two categories: unrelated and related, or divided into multiple categories such as mutually exclusive or non-mutually exclusive, or even more categories. The specific division can be based on needs and is not limited in this application.

[0116] In actual implementation, the BIOS configuration file can be exported using the SCE tool. Using the Map String feature matching algorithm, the BIOS option fields can be precisely located to obtain the current BIOS default values ​​and BIOS adjustable options. A BIOS option structured data table is constructed, containing basic BIOS parameters and their relationships. The BIOS parameters are then categorized based on these relationships.

[0117] After the BIOS parameters are divided into different major categories, a combination mechanism adapted to the major category is adopted to combine the status values ​​of the BIOS parameters of each subcategory under the major category to obtain multiple groups of candidate sub-BIOS parameter combinations.

[0118] Then, the candidate sub-BIOS parameter combinations corresponding to each major category are arranged and combined to obtain multiple groups of candidate BIOS parameter combinations.

[0119] During the research and development process, the inventors also discovered that in the related technology, the traditional method of manually traversing BIOS parameters is time-consuming and difficult to enumerate all possibilities. Especially when it comes to multi-parameter dependencies (such as the linkage adjustment of CPU hyperthreading and memory timing), the combination space grows exponentially, resulting in low tuning efficiency.

[0120] According to the BIOS parameter debugging method provided in the embodiment of the present application, the BIOS parameters are graded according to the correlation relationship between the BIOS parameters, and the BIOS parameters are combined based on the combination mechanism corresponding to each level to obtain multiple groups of candidate BIOS parameter combinations. This can reduce the traditional manual traversal and tuning time, cover as many BIOS combination methods as possible, improve the feasibility of each group of candidate BIOS parameter combinations, and thus improve the subsequent tuning efficiency.

[0121] In some embodiments, BIOS parameters are classified based on associations between them to obtain multiple parameter sets, which may include:

[0122] According to the association relationship between BIOS parameters, the BIOS parameters are divided into an unrelated parameter set, a related parameter set, or a mutually exclusive parameter set.

[0123] In this embodiment, there is no dependency between the various BIOS options included in the irrelevant parameter set, such as Turbo Boost and NUMA Configuration.

[0124] Among the BIOS parameters included in the related parameter set, there is an association relationship between at least two BIOS options, such as a tree relationship.

[0125] Among the BIOS parameters included in the mutually exclusive parameter set, at least two BIOS options are mutually exclusive. For example, virtualization technology conflicts with a specific energy-saving mode, and C-States and Hyper-Threading cannot be disabled at the same time.

[0126] In actual implementation, BIOS options can be divided into Level I (i.e., unrelated parameter sets), Level II (i.e., related parameter sets), and Level III (i.e., mutually exclusive parameter sets) based on the hierarchical principle shown in Table 1. A hierarchical BIOS parameter relationship library can be constructed and the BIOS parameter library can be calculated.

[0127] Table 1

[0128]

[0129] According to the BIOS parameter debugging method provided in the embodiment of the present application, by dividing BIOS parameters into unrelated parameter sets, related parameter sets or mutually exclusive parameter sets, multi-parameter dependencies can be considered, and the risk of system startup failure or performance abnormality caused by logical mutual exclusion between BIOS parameters can be reduced, parameter configuration conflicts and stability risks can be reduced, and the subsequent parameter tuning effect can be further improved, thereby improving the stability of the system.

[0130] The following describes how to construct candidate sub-BIOS parameter combinations corresponding to different class sets.

[0131] In some embodiments, based on a combination mechanism corresponding to a target parameter set among multiple parameter types, the state values ​​of the parameters in the target parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, which may include:

[0132] In the case that the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0133] In this embodiment, in the level I model corresponding to the irrelevant parameter set, since there is no dependency between the various BIOS options, the number N of candidate sub-BIOS parameter combinations can be calculated as: the product of the total number of BIOS options of each option, as shown in Table 2.

[0134] Table 2

[0135]

[0136] The total number of candidate sub-BIOS parameter combinations is obtained: N=i=1∏kOptionCounti (k is the total number of level I options), and the BIOS parameters included in each combination and the corresponding status values ​​of the parameters are obtained; an example is shown in Table 3:

[0137] Table 3

[0138]

[0139] In some embodiments, based on a combination mechanism corresponding to a target parameter set among multiple parameter types, the state values ​​of the parameters in the target parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, which may include:

[0140] When the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0141] In this embodiment, since there is a tree relationship between the BIOS parameters in the level II model corresponding to the related class parameter set, all paths of the tree structure can be calculated by a recursive algorithm, such as Figure 3 shown.

[0142] After obtaining each path, traverse each path to obtain the total number M of level II model BIOS option combinations and a list of combination paths. Each combination path corresponds to a candidate sub-BIOS parameter combination, and the BIOS parameters included in each combination and the corresponding status values ​​of the parameters are obtained.

[0143] In some embodiments, traversing each path to obtain the total number M of Level II model BIOS option combinations and a list of combination paths may include:

[0144] If the current node has a child node, add one to the total number of combinations M and record the combination path;

[0145] If the current node has no child nodes, jump to the next node.

[0146] like Figure 4As shown, in the actual execution process, the initial value of the total number of combinations M can be set to 0 first, and then the node is checked to see if it is empty. If it is not empty, the node is added to the path, and the current node is checked to see if there is a child node. If there is no child node, jump to the next node and continue to check if the next node has a child node. If there is a child node, the total number of combinations M is added by one, and the combination path is recorded.

[0147] In some embodiments, based on a combination mechanism corresponding to a target parameter set among multiple parameter types, the state values ​​of the parameters in the target parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, which may include:

[0148] In the case where the target parameter set is a mutually exclusive parameter set, the parameters in the mutually exclusive parameter set that have a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and the state values ​​of the parameters corresponding to the same mutually exclusive group are obtained;

[0149] The state values ​​corresponding to the mutually exclusive groups are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0150] In this embodiment, there is a mutually exclusive relationship between the BIOS parameters in the level III model corresponding to the mutually exclusive parameter set, and the BIOS options of the level III model can be grouped according to the mutually exclusive relationship between the BIOS options.

[0151] The grouping rules are as follows:

[0152] Divide mutually exclusive BIOS parameters into independent mutually exclusive groups (a total of X groups, where X is a positive integer).

[0153] In each group, the maximum number of optional values ​​Y (i.e., the maximum number of adjustable state values) is taken as the valid number of combinations of the group.

[0154] The formula for the total number of combinations is as follows:

[0155] XY=i=1∏xOptionCounti(i=max(GroupOptions1,GroupOptions2,...,GroupOptionsX)); where XY is the total number of candidate sub-BIOS parameter combinations finally obtained; an example is shown in Table 4.

[0156] Table 4

[0157]

[0158] After obtaining the candidate sub-BIOS parameter combinations corresponding to the major categories, the candidate sub-BIOS parameter combinations corresponding to the major categories can be combined to obtain multiple groups of candidate BIOS parameter combinations.

[0159] In some embodiments, after step 130, the method may further include:

[0160] Control server operation based on target BIOS parameter combinations and obtain real-time performance indicator data;

[0161] When a change in the target business scenario is detected and server performance degradation is determined based on real-time performance indicator data, the target BIOS parameter combination is adjusted based on the changed target business scenario.

[0162] In this embodiment, Figure 2 An example of an overall logical control block diagram of the method of the present application is provided. In actual application, if a target BIOS parameter combination under a target business scenario is predicted in advance and the server is configured and operated based on the target BIOS parameter combination, various performance indicators of the server computing power can be monitored according to the business type and business information; if the performance is too low, the BIOS parameters can be dynamically adjusted according to the current business scenario, such as steps 110 to 130, to perform performance tuning, thereby achieving real-time tuning.

[0163] According to the BIOS parameter debugging method provided in the embodiment of the present application, by providing a closed-loop feedback mechanism of real-time load, it is possible to dynamically switch the BIOS configuration mode according to business pressure, realize dynamic BIOS voltage regulation, and be better used in complex and changeable business scenarios.

[0164] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0165] like Figure 5 As shown, an embodiment of the present application further provides a computer program product, including: a first processing module 510 , a second processing module 520 and a third processing module 530 .

[0166] A first processing module 510 is configured to input each set of candidate BIOS parameter combinations into a hybrid model, where the hybrid model includes at least two of a pre-built CPU load model, a memory load model, and a GPU load model;

[0167] The second processing module 520 is configured to obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each set of candidate BIOS parameter combinations output by the hybrid model when running in the target business scenario;

[0168] The third processing module 530 is configured to determine a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0169] According to the computer program product provided in the embodiment of the present application, different candidate BIOS parameter combinations are respectively input into a hybrid model that can simulate hardware collaborative efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, so as to obtain the target BIOS parameter combination based on these sub-scores. The product can respond to load fluctuations, comprehensively consider the synergistic effects between various hardware, and has high tuning efficiency, good tuning effect, and dynamic tuning capabilities.

[0170] In some embodiments, the third processing module 530 may also be used to:

[0171] Based on the weight sequence, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score are weighted and summed to obtain the server performance computing power score corresponding to each set of candidate BIOS parameter combinations;

[0172] Based on the server performance computing power score, a target BIOS parameter combination is determined from each group of candidate BIOS parameter combinations.

[0173] In some embodiments, the third processing module 530 may also be configured to determine a weight sequence using a hierarchical analysis method.

[0174] In some embodiments, the first processing module 510 may also be used to:

[0175] When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected into the target business scenario to run the hybrid model.

[0176] Each set of candidate BIOS parameter combinations is input into the hybrid model respectively.

[0177] In some embodiments, the computer program product may further include a fourth processing module configured to:

[0178] After each set of candidate BIOS parameter combinations is input into the hybrid model, if any parameter setting in the candidate BIOS parameter combination fails, the hybrid model is controlled to recover to the last stable state.

[0179] In some embodiments, the computer program product may further include a fifth processing module configured to:

[0180] Constructing a dynamic power-aware model for executing workloads;

[0181] Simulate mixed load scenarios and construct business scenario simulation models;

[0182] A CPU load model is obtained based on at least one of a dynamic power consumption awareness model and a business scenario simulation model.

[0183] In some embodiments, the computer program product may further include a sixth processing module configured to:

[0184] Perform full memory channel scans and build a joint bandwidth-latency model based on the collected correctable error rate;

[0185] Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model;

[0186] A memory load model is obtained based on at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model.

[0187] In some embodiments, the computer program product may further include a seventh processing module configured to:

[0188] Before inputting each set of candidate BIOS parameter combinations into the hybrid model, the BIOS parameters are classified according to the correlation between the BIOS parameters to obtain multiple parameter sets;

[0189] Based on a combination mechanism corresponding to a target class parameter set among the multiple parameter types, combining the state values ​​of the parameters in the target class parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set;

[0190] The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

[0191] In some embodiments, the seventh processing module may further be configured to:

[0192] According to the association relationship between BIOS parameters, the BIOS parameters are divided into an unrelated parameter set, a related parameter set, or a mutually exclusive parameter set.

[0193] In some embodiments, the seventh processing module may further be configured to:

[0194] In the case that the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0195] In some embodiments, the seventh processing module may further be configured to:

[0196] When the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0197] In some embodiments, the seventh processing module may further be configured to:

[0198] In the case where the target parameter set is a mutually exclusive parameter set, the parameters in the mutually exclusive parameter set that have a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and the state values ​​of the parameters corresponding to the same mutually exclusive group are obtained;

[0199] The state values ​​corresponding to the mutually exclusive groups are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0200] In some embodiments, the computer program product may further include an eighth processing module configured to:

[0201] After determining a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score, the server operation is controlled based on the target BIOS parameter combination and real-time performance indicator data is obtained;

[0202] When a change in the target business scenario is detected and server performance degradation is determined based on real-time performance indicator data, the target BIOS parameter combination is adjusted based on the changed target business scenario.

[0203] For descriptions of features in the embodiments corresponding to the computer program product, reference can be made to the relevant descriptions of the embodiments corresponding to the BIOS parameter debugging method, which will not be detailed here.

[0204] like Figure 6 As shown, an embodiment of the present application further provides an electronic device 600, comprising a memory 602 and a processor 601, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned BIOS parameter debugging method embodiments.

[0205] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned BIOS parameter debugging method embodiments when running.

[0206] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0207] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned BIOS parameter debugging method embodiments are implemented.

[0208] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned BIOS parameter debugging method embodiments.

[0209] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0210] The above is a detailed introduction to a BIOS parameter debugging method provided by this application. This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand the method and core ideas of this application. It should be pointed out that for those skilled in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A BIOS parameter debugging method, characterized in that: include: Inputting each set of candidate BIOS parameter combinations into a hybrid model, the hybrid model comprising: at least one of a CPU load model and a memory load model pre-built for simulating server operation, and a GPU load model; Obtaining the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score corresponding to each set of the candidate BIOS parameter combinations output by the hybrid model when running in the target business scenario; assigning a value of 0 to any sub-score that is not obtained; Determining, from each group of the candidate BIOS parameter combinations, a target BIOS parameter combination corresponding to the target business scenario based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score; The hybrid model is established for each component and link of the server, and can simulate the hardware coordination efficiency, hardware resource competition and dynamic load characteristics during the operation of the server; The CPU load model includes one or more of a dynamic power consumption awareness model and a business scenario simulation model; The GPU load model is used to detect the bottleneck of video memory bandwidth; The memory load model includes at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model; Determining a target BIOS parameter combination from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score includes: Performing a weighted summation of the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score according to the weight sequence to obtain a server performance computing power score corresponding to each group of candidate BIOS parameter combinations; Determining the target BIOS parameter combination from each group of candidate BIOS parameter combinations based on the server performance computing power score; After determining the target BIOS parameter combination corresponding to the target business scenario from each group of the candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, the method further includes: Controlling server operation based on the target BIOS parameter combination and obtaining real-time performance indicator data; When a change in the target business scenario is detected and it is determined based on the real-time performance indicator data that the server performance has degraded, the target BIOS parameter combination is adjusted based on the changed target business scenario.

2. The BIOS parameter debugging method according to claim 1, wherein: The weight sequence is determined by using the hierarchical analysis method.

3. The BIOS parameter debugging method according to claim 1 or 2, wherein: Inputting each set of candidate BIOS parameter combinations into the hybrid model separately includes: The hybrid model is configured separately based on each group of candidate BIOS parameter combinations. When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected in combination with the target business scenario to run the hybrid model.

4. The BIOS parameter debugging method according to claim 1 or 2, wherein: After inputting each set of candidate BIOS parameter combinations into the hybrid model, the method further includes: In the event that any parameter in the candidate BIOS parameter combination fails to be set, the hybrid model is controlled to recover to a previous stable state.

5. The BIOS parameter debugging method according to claim 1 or 2, wherein: The CPU load model is constructed based on the following steps: Constructing a dynamic power-aware model for executing workloads; Simulate mixed load scenarios and construct business scenario simulation models; The CPU load model is obtained based on at least one of the dynamic power consumption awareness model and the business scenario simulation model.

6. The BIOS parameter debugging method according to claim 1 or 2, characterized in that: The memory load model is constructed based on the following steps: Perform full memory channel scans and build a joint bandwidth-latency model based on the collected correctable error rate; Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model; The memory load model is obtained based on at least one of the bandwidth-delay joint model and the dynamic pressure regulation algorithm model.

7. The BIOS parameter debugging method according to claim 1 or 2, wherein: Before inputting each set of candidate BIOS parameter combinations into the hybrid model, the method further includes: According to the correlation between BIOS parameters, BIOS parameters are classified to obtain multiple parameter sets; combining, based on a combination mechanism corresponding to a target parameter set in the plurality of parameter sets, state values ​​of the parameters in the target parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set; The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

8. The BIOS parameter debugging method according to claim 7, wherein: The BIOS parameters are classified according to the association relationship between the BIOS parameters to obtain multiple parameter sets, including: According to the association relationship between the BIOS parameters, the BIOS parameters are divided into an unrelated parameter set, a related parameter set or a mutually exclusive parameter set.

9. The BIOS parameter debugging method according to claim 7, wherein: The combining mechanism corresponding to the target parameter set in the multiple parameter sets, combining the state values ​​of the parameters in the target parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, includes: In a case where the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain the at least one set of candidate sub-BIOS parameter combinations.

10. The BIOS parameter debugging method according to claim 7, wherein: The combining mechanism corresponding to the target parameter set in the multiple parameter sets, combining the state values ​​of the parameters in the target parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, includes: When the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain the at least one set of candidate sub-BIOS parameter combinations.

11. The BIOS parameter debugging method according to claim 7, wherein: The combining mechanism corresponding to the target parameter set in the multiple parameter sets, combining the state values ​​of the parameters in the target parameter set to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target parameter set, includes: In a case where the target parameter set is a mutually exclusive parameter set, parameters in the mutually exclusive parameter set that have a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and state values ​​of the parameters corresponding to the same mutually exclusive group are obtained; The state values ​​corresponding to the mutually exclusive groups are combined to obtain the at least one group of candidate sub-BIOS parameter combinations.

12. A computer program product, characterized in that include: a first processing module, configured to input each set of candidate BIOS parameter combinations into a hybrid model, wherein the hybrid model includes: at least one of a CPU load model and a memory load model pre-built for simulating server operation, and a GPU load model; a second processing module, configured to obtain a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each set of the candidate BIOS parameter combinations output by the hybrid model when running in the target business scenario; and assign a value of 0 to any sub-score that is not obtained; a third processing module, configured to determine, from each group of the candidate BIOS parameter combinations, a target BIOS parameter combination corresponding to the target business scenario based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score; The hybrid model is established for each component and link of the server, and can simulate the hardware coordination efficiency, hardware resource competition and dynamic load characteristics during the operation of the server; The CPU load model includes one or more of a dynamic power consumption awareness model and a business scenario simulation model; The GPU load model is used to detect the bottleneck of video memory bandwidth; The memory load model includes at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model; The third processing module is configured to perform a weighted summation of the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score according to a weight sequence to obtain a server performance computing power score corresponding to each group of candidate BIOS parameter combinations; Determining the target BIOS parameter combination from each group of candidate BIOS parameter combinations based on the server performance computing power score; a fourth processing module, configured to, after determining a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, control server operation based on the target BIOS parameter combination and obtain real-time performance indicator data; When a change in the target business scenario is detected and it is determined based on the real-time performance indicator data that the server performance has degraded, the target BIOS parameter combination is adjusted based on the changed target business scenario.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the BIOS parameter debugging method according to any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the BIOS parameter debugging method according to any one of claims 1 to 11 are implemented.

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