DDR (Double Data Rate) write data eye diagram training system and method based on standard delay unit

Abstract

The invention provides a DDR data writing eye diagram training system and method based on a standard delay unit and a computer storage medium, the DDR data writing eye diagram training system comprises a DDR training control module, a delay module and an IO module, and the DDR training control module comprises a command generation unit which sends a read-write command through the IO module and generates a WDQS signal and a WDQ signal; the delay control unit adjusts the delay module so as to adjust the delay time of the WDQS signal and the WDQ signal; and the detection judgment unit judges whether read data returned by the IO interface is correct or not and records related delay information. The DDR training control module generates commands and signals in an instruction control mode and controls adjustment of delay time in the eye diagram training process, so that the system is simple in structure and low in hardware resource consumption, the delay amount can be flexibly adjusted according to the actual situation, the training precision and stability are improved, and meanwhile the training efficiency is improved. The training complexity is reduced, the training time is saved, and the problems of high hardware consumption and poor training effect of the existing DDR data writing eye pattern training are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a DDR write data eye diagram training system and method based on a standard delay unit, and a computer storage medium. Background Art

[0002] Double Data Rate (DDR) system is the customary abbreviation of double data rate synchronous dynamic random access memory system. Its advantages are large storage capacity, low cost, mature interface, and high access rate during parallel burst access. The external signal interface of DDR mainly includes: clock signal (CK), data signal (DQ), select signal (DQS) and command / address signal (CA).

[0003] In order to complete the normal DDR write function, it is necessary to ensure that the write direction strobe signal (write datastrobe, WDQS) of the DDR system has a certain correspondence with the write direction data signal (write data, WDQ), so as to ensure the correct sampling of WDQ by WDQS. However, due to the deviation of the wiring length of different signals, DDR needs to train WDQS and WDQ before performing the normal write function.

[0004] Among them, the WDQ eye diagram training process requires that the control logic of DDR must have the ability to adjust the WDQ delay. The delay scale mainly includes the delay of integer multiples of the DDR clock cycle (tCK) and the delay of non-integer multiples. For the delay of non-integer multiples, the common practice is to divide a tCK into fixed equal parts, for example, to divide tCK into 32 or 64 parts, that is, for each increase in the delay unit, the delay time will increase by 1 / 32 tCK or 1 / 64 tCK. Since the applicable frequency range of DDR3 / 4 is relatively wide (800MTS~3200MTS), if this delay method is adopted, each equally divided delay unit needs to use different numbers of hardware delay resources at different frequencies, and the hardware delay module needs to perform complex calculations and processing. Moreover, for different frequencies, the training error will also be different. Taking DDR3-800 as an example, each DDR clock cycle is 2.5ns. In the case of 64 equal divisions, the delay time of each equally divided delay unit is 39ps, and the training error will also reach 39ps.

[0005] In addition, since the current DDR address signal lines usually adopt a fly-by structure, different DDR particles receive commands at different times. Therefore, during write leveling and write delay training, the training results of different particle WDQS will be quite different. At the same time, in the DDR system, the wiring lengths of WDQ and WDQS are generally close, which makes the training results of different particle WDQs also quite different during the write data eye diagram training process.

[0006] In addition, in the traditional write data eye diagram training method, the initial delay of all particle WDQ starts from the same position, which will cause the overall training time to be longer; although some training methods synchronize the training results of write balance and write delay to the write data eye diagram training process as the initial position based on hardware logic or algorithms, it requires additional hardware overhead and has poor flexibility. Summary of the invention

[0007] The object of the present invention is to provide a DDR write data eye diagram training system and method, and a computer storage medium based on a standard delay unit, so as to solve the problem that the existing DDR write data eye diagram training hardware consumes a lot and has a poor training effect.

[0008] In order to solve the above technical problems, the present invention provides a DDR write data eye diagram training system based on a standard delay unit, comprising a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module comprises: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal and a WDQ signal; A delay control unit, used to adjust the delay module during the eye diagram training process so that the delay module adjusts the delay time of the WDQS signal and the WDQ signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the eye diagram training process and the final delay information after the eye diagram training is completed.

[0009] Optionally, in the DDR write data eye diagram training system based on the standard delay unit, the DDR training control module also includes a whole UI delay unit; the whole UI delay unit is used to delay the WDQS signal and the WDQ signal by UI units through digital logic.

[0010] Optionally, in the DDR write data eye diagram training system based on the standard delay unit, the delay module includes a WDQS delay unit and a WDQ delay unit; the WDQS delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the WDQ delay unit is used to adjust the delay time of the WDQ signal under the control of the delay control unit.

[0011] Optionally, in the DDR write data eye diagram training system based on the standard delay unit, the WDQS delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series; the WDQ delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series.

[0012] Optionally, in the DDR write data eye diagram training system based on the standard delay unit, whenever the delay time of the WDQS delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the WDQS delay unit is cleared; whenever the delay time of the WDQ delay unit increases to 1 UI, the generation time of the WDQ signal is delayed by 1 UI, and the setting of the WDQ delay unit is cleared.

[0013] In order to solve the above technical problems, the present invention further provides a DDR write data eye diagram training method based on a standard delay unit, which is applied to the DDR write data eye diagram training system based on a standard delay unit as described in any one of the above items, and the DDR write data eye diagram training method based on a standard delay unit comprises: Set the initial position of the WDQ signal according to the WDQS signal; Update the delay setting of WDQ signal; Send read and write commands; Determine whether the current WDQ signal position meets the reading and writing requirements; If the current WDQ signal position meets the read and write requirements, the current WDQ signal position is divided into the success interval, otherwise, the current WDQ signal position is divided into the failure interval; The delay setting of the WDQ signal is updated until a complete success interval is found between two failure intervals.

[0014] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, the method of setting the initial position of the WDQ signal according to the WDQS signal includes: In a command configuration manner, the delay configuration of the WDQS signal of each DDR particle is reduced by a preset value to serve as the initial delay configuration of the WDQ signal of the DDR particle.

[0015] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, the method for updating the delay setting of the WDQ signal includes: Starting from the initial position of the WDQ signal, each time it is updated, the WDQ signal is delayed by one step according to the step size set in the instruction.

[0016] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, the method for determining whether the current WDQ signal position meets the read and write requirements includes: If the read-back data is consistent with the written data at the current WDQ signal position, it is determined that the current WDQ signal position meets the read and write requirements.

[0017] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, the DDR write data eye diagram training method based on the standard delay unit further includes: If a complete success interval is not found between two failure intervals from the initial position of the WDQ signal until the position of the WDQ signal reaches the maximum position set in the instruction, the training is marked as failed.

[0018] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, the DDR write data eye diagram training method based on the standard delay unit further includes: The middle value of the success interval is used as the final delay configuration of the WDQ signal so that the rising edge of the WDQS signal is aligned with the center of the WDQ signal.

[0019] Optionally, in the DDR write data eye diagram training method based on the standard delay unit, before the delay setting of the update WDQ signal, the DDR write data eye diagram training method based on the standard delay unit includes: Determine whether the signal skew between the WDQS signal and the WDQ signal of each DDR particle is within a preset range; If so, a fixed delay time is added based on the delay configuration of the WDQS signal of each DDR particle in the form of instruction configuration to serve as the final delay configuration of the WDQ signal of the DDR particle, and the subsequent eye diagram training process is omitted.

[0020] In order to solve the above technical problems, the present invention also provides a computer storage medium, wherein the computer storage medium stores an executable program; when the executable program is executed, the DDR write data eye diagram training method based on the standard delay unit as described in any one of the above items is implemented.

[0021] The present invention provides a DDR write data eye diagram training system and method based on a standard delay unit, and a computer storage medium, comprising a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module comprises: a command generation unit, used to send read and write commands to the DDR particle through the IO module, and generate a WDQS signal and a WDQ signal; a delay control unit, used to adjust the delay module during the eye diagram training process, so that the delay module adjusts the delay time of the WDQS signal and the WDQ signal; a detection and judgment unit, used to judge whether the read data returned by the IO interface is correct, and used to record boundary information during the eye diagram training process and final delay information after the eye diagram training is completed. The DDR training control module generates commands and signals in an instruction-controlled manner and controls the adjustment of the delay time during the eye diagram training process. Not only is the system structure simple and consumes less hardware resources, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. This improves the training accuracy and stability while reducing the training complexity. It also ensures that each DDR particle completes the training in the same time, saving training time and solving the problem of high hardware consumption and poor training effect in the existing DDR write data eye diagram training. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A structural block diagram of a DDR write data eye diagram training system based on a standard delay unit provided in this embodiment; Figure 2 A schematic diagram of the specific structure of the DDR write data eye diagram training system based on the standard delay unit provided in this embodiment; Figure 3 A schematic diagram of the initial correspondence between the WDQ signal and the WQDS signal provided in this embodiment; Figure 4 A flow chart of a DDR write data eye diagram training method based on a standard delay unit provided in this embodiment; Figure 5 Schematic diagram of signal delay between particle 0 and particle 1 during existing eye diagram training; Figure 6 A schematic diagram of signal delay between particle 0 and particle 1 during eye diagram training provided in this embodiment; Figure 7 A timing diagram showing that the WDQ signal and the WQDS signal provided in this embodiment have the same delay. DETAILED DESCRIPTION

[0023] The DDR write data eye diagram training system and method based on the standard delay unit and the computer storage medium proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0024] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] In order to better explain the DDR write data eye diagram training system and method based on the standard delay unit provided by the present application, the relevant terms are first explained as follows: Eye diagram training: also known as data eye diagram training (Data Eye Training), is a key technology in memory interfaces (such as DDR, LPDDR, etc.), which aims to optimize the quality and reliability of data transmission; as the clock frequency continues to increase, the width of the data eye diagram becomes narrower and narrower, which increases the difficulty of data sampling; data eye diagram training ensures that the data signal is accurately captured and transmitted within the optimal time window through a series of automatic or manual adjustment processes; FPGA: Field Programmable Gate Array, a field programmable gate array is an integrated circuit with programmable features pre-designed and implemented on a silicon chip; DDR: Double Data Rate, double data transmission rate; DDR particles: DDR SDRAM, synchronous dynamic random access memory with double data transfer rate; DQ: data, bidirectional data signal line of DDR particles; DQS: data strobe, equivalent to the reference clock of the data signal, used to sample the data signal line; WDQ: write data, data signal line in the write direction, referred to as write data signal in this application; WDQS: write data strobe, used to sample the data signal line in the write direction, referred to as write strobe signal in this application, including a pair of differential signals WDQS_t and WDQS_c; RDQ: read data, data signal line in the read direction, referred to as read data signal in this application; CK: clock, the clock of DDR particles, including a pair of differential clocks CK_t and CK_c; SDL: Standard Cell Delay Line, a standard delay cell with fixed delay function composed of combinational logic cascade, with a simple structure and a fixed delay time of about 20ps; CDL: Customer delay line, a user-defined standard delay unit composed of analog circuits, with a fixed delay time of about 5ps; WRITE LEVELING: Write leveling is a DDR particle training process used to align the rising edge of WDQS_t and the rising edge of CK_t received by the DDR particle; Skew: Different signals have transmission delay deviations due to wiring problems, so that the signals at the receiving end cannot be completely aligned. tCK: DDR clock cycle; UI: Half of the DDR particle clock cycle, that is, 1 / 2CK.

[0026] WRITE LATENCY: write delay. After receiving a write command, the DDR particle needs to go through a fixed number of tCK delays before it can accept WDQS. This delay is the write delay. CS: Chip select, chip select signal, one of the standard interface signals of DDR particles and one of the command signals.

[0027] This embodiment provides a DDR write data eye diagram training system based on a standard delay unit, such as Figure 1 As shown, it includes a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal and a WDQ signal; A delay control unit, used to adjust the delay module during the eye diagram training process so that the delay module adjusts the delay time of the WDQS signal and the WDQ signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the eye diagram training process and the final delay information after the eye diagram training is completed.

[0028] The DDR write data eye diagram training system based on the standard delay unit provided in this embodiment generates commands and signals in an instruction-controlled manner through the DDR training control module, and controls the adjustment of the delay time during the eye diagram training process. Not only is the system structure simple and the hardware resource consumption low, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. Therefore, while improving the training accuracy and stability, it not only reduces the training complexity, but also ensures that the time to complete the training of each DDR particle is the same, saving training time, and solving the problem of high hardware consumption and poor training effect of the existing DDR write data eye diagram training.

[0029] Specifically, in this embodiment, the delay module includes a WDQS delay unit and a WDQ delay unit; the WDQS delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the WDQ delay unit is used to adjust the delay time of the WDQ signal under the control of the delay control unit.

[0030] In practical applications, such as Figure 2 As shown, the WDQS delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series; the WDQ delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series. Among them, the series connection of the 96 levels of SDL units can be configured by setting configuration information thereof by means of instruction configuration, thereby adjusting the number of SDL units passed during the transmission of the WDQS signal and the WDQ signal, and further adjusting the length of the delay time of the WDQS signal and the WDQ signal; the series connection of the 4 levels of CDL units can also be configured by setting configuration information thereof by means of instruction configuration, thereby adjusting the number of CDL units passed during the transmission of the WDQS signal and the WDQ signal, and further adjusting the length of the delay time of the WDQS signal and the WDQ signal.

[0031] Since the delay time of each CDL level is about 5ps and the delay time of SDL is about 20ps, the delay time of 4-level CDL in series is approximately equal to the delay time of 1-level SDL. When the delay time of the used CDL reaches 4 levels, one level of SDL will be added and the value of CDL will be cleared. During the training process, if the delay accuracy requirement is relatively low, CDL can be omitted.

[0032] Better, such as Figure 2As shown, in order to reduce the resource consumption of the delay module and further improve the training efficiency and accuracy, in this embodiment, the DDR training control module also includes a whole UI delay unit; the whole UI delay unit is used to delay the WDQS signal and the WDQ signal by UI units through digital logic.

[0033] Specifically, the WDQS delay unit and the WDQ delay unit correspond to one whole UI delay unit respectively, so that the WDQS signal and the WDQ signal are delayed by UI units respectively by two whole UI delay units, and then the WDQS signal is transmitted to the WDQS delay unit and the WDQ signal is transmitted to the WDQ delay unit.

[0034] Since 2 UIs are equal to 1 CK, the minimum unit of the whole UI delay unit is 1UI. Whenever the delay time of the WDQS delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the WDQS delay unit is cleared; and whenever the delay time of the WDQ delay unit increases to 1 UI, the generation time of the WDQ signal is delayed by 1 UI, and the setting of the WDQ delay unit is cleared. It should be noted that the delay time here mainly refers to the delay time of SDL, that is, when the delay time of SDL increases to 1 UI, 1UI will be added to the whole UI delay unit, so that the generation time of the signal is delayed by 1 UI, and the delay configuration of SDL is cleared at the same time. It should be noted that the signal generation time here refers to the time when the WDQS signal and the WDQ signal are sent from the DDR training control module.

[0035] like Figure 2 As shown, the DDR write data eye diagram training system based on the standard delay unit provided in this embodiment is implemented based on FPGA, and uses its internal resources to build an instruction set-based DDR training platform. By combining and calling FPGA resources, the training of DDR write data eye diagram can be realized.

[0036] Of course, in practical applications, in addition to being used on an FPGA platform, the DDR write data eye diagram training system based on a standard delay unit provided in this embodiment can also be applied to various integrated circuit systems and SOCs using DDR particles.

[0037] And, in this embodiment, DDR particles select DDR3 / 4 particles. Of course, in practical applications, DDR particles are not limited to DDR3 / 4, and can also be applied to various memory particles such as DDR5 or LPDDR, and this application does not limit this.

[0038] And, in this embodiment, when implemented based on FPGA, the IO module can be specifically IOB (input / output buffer), which is the external interface resource of FPGA. Of course, in actual applications, the IO module can select other interface resources according to actual needs, and this application does not limit this.

[0039] Although the delay setting of the WDQS signal has met the requirements of the write operation after completing the write leveling and write delay training, the correspondence between the WDQ signal and the WDQS signal still needs further training due to the skew problem. Figure 3 For example, there may be a certain deviation in the initial corresponding relationship between the WDQ signal and the WQDS signal, so it is necessary to adjust the relative position of the WDQ signal and the WDQS signal by continuously delaying the WDQ signal.

[0040] Specifically, a read / write command can be sent at the position of each WDQ signal to determine whether the position meets the read / write requirements. That is, in the process of moving the WDQ signal, the read / write operation will fail → succeed → fail. The training process of writing the data eye diagram is the process of determining the center position of the successful interval. After the delay information of the WDQ signal at this position is determined, the WDQS signal will be aligned with the center position of the WDQ signal, thereby achieving the best sampling requirements.

[0041] Based on this, this embodiment also provides a DDR write data eye diagram training method based on a standard delay unit, which is applied to the DDR write data eye diagram training system based on a standard delay unit as described above. Figure 4 As shown, the DDR write data eye diagram training method based on the standard delay unit includes: S1, setting the initial position of the WDQ signal according to the WDQS signal; S2, update the delay setting of the WDQ signal; S3, send read and write commands; S4, judging whether the current WDQ signal position meets the reading and writing requirements; S5, if the current WDQ signal position meets the read and write requirements, the current WDQ signal position is divided into a success interval, otherwise, the current WDQ signal position is divided into a failure interval; S6, updating the delay setting of the WDQ signal until a complete success interval is found between the two failure intervals.

[0042] The present embodiment provides a DDR write data eye diagram training method based on a standard delay unit, and a DDR write data eye diagram training system based on a standard delay unit, thereby generating commands and signals in an instruction-controlled manner through a DDR training control module, and updating the delay setting of the WDQ signal during the eye diagram training process. Not only is the training process simple and consumes less hardware resources, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference, thereby improving the training accuracy and stability while ensuring that each DDR particle completes the training in the same time, saving training time, and solving the problem of high hardware consumption and poor training effect in the existing DDR write data eye diagram training.

[0043] Specifically, in this embodiment, step S1, the method of setting the initial position of the WDQ signal according to the WDQS signal includes: reducing the delay configuration of the WDQS signal of each DDR particle by a preset value in an instruction configuration manner to serve as the initial delay configuration of the WDQ signal of the DDR particle.

[0044] Since the current DDR system usually adopts a fly-by structure, different DDR particles will receive different CS times. Figure 5 For example, the CS time received by particle 0 and particle 1 differs by 2UI, so the delay time of the WDQS signal of particles 0 and 1 obtained by write equalization and write delay training differs by 2UI. When performing WDQ eye diagram training, if the initial delay of the WDQ signal of particles 0 and 1 is set to the same value, the range that the WDQ signal of particle 1 needs to scan will be 2UI more than that of particle 0, resulting in an overall long training time.

[0045] To solve this problem, this embodiment reduces the delay configuration of the WDQS signal of each particle by a fixed delay unit through instruction configuration, which serves as the initial delay setting of the WDQ signal of the corresponding particle. Figure 6 For example, at this time, the starting position of each particle WDQ signal is about 1UI ahead of the WDQS signal of the particle. Then the time required for each particle WDQ signal to complete the training is roughly the same, thereby shortening the overall training time.

[0046] In actual applications, the preset value of the delay configuration reduction of the WDQS signal of each DDR particle can be adjusted according to the frequency, so that the offset of the starting position of the WDQ signal can be flexibly adjusted. Usually, it is necessary to ensure that the initial position of the WDQ signal is before the left boundary of the eye diagram success (pass) interval, so that the WDQ signal can sweep the entire failure (fail) → success (pass) → failure (fail) interval during the movement. For example, at low frequency, the initial position of the WDQ signal can be advanced by only about 0.5UI relative to the WDQS signal.

[0047] In addition, the logic of the instruction configuration method adopted in this embodiment is the logic shared by the entire system, so it does not require too much additional logic overhead, thereby saving hardware resource consumption.

[0048] Further, in this embodiment, step S2, the method for updating the delay setting of the WDQ signal includes: starting from the initial position of the WDQ signal, each time it is updated, the WDQ signal is delayed by one step according to the step set in the instruction, wherein the step can be reasonably set in the instruction according to actual needs.

[0049] And, in this embodiment, step S3, sends a read / write command. Specifically, the read / write command may include a read command and a write command, and the WDQS signal and the WDQ signal are generated according to the write command. The RDQ returned by the particle is generated according to the read command. Multiple writes and reads can be performed at each delay position as required. The methods of generating read / write commands, WDQS signals and WDQ signals, and sending read / write commands are well known to those skilled in the art, and this application will not be repeated here.

[0050] Further, in this embodiment, step S4, the method for determining whether the current WDQ signal position meets the read and write requirements includes: if at the current WDQ signal position, the data read back each time is consistent with the data written, then determining that the current WDQ signal position meets the read and write requirements.

[0051] Specifically, multiple write and read operations are performed under the delay setting of each WDQ signal, and the read and write data results are determined. If the read data is consistent with the written data, then the read and write are correct, and it is determined that the current WDQ signal position meets the read and write requirements.

[0052] And, in this embodiment, in step S5, if the current WDQ signal position meets the read and write requirements, the current WDQ signal position is divided into a success interval, otherwise, the current WDQ signal position is divided into a failure interval.

[0053] Furthermore, in this embodiment, in step S6, the delay setting of the WDQ signal is updated until a complete success interval is found between the two failure intervals. That is, before a complete success (pass) interval is found and the delay setting of the WDQ signal has not reached the maximum setting, the delay of the WDQ signal is continuously increased according to the step size set in the instruction, and the reading and writing process is repeated, that is, steps S2 to S5 are repeated.

[0054] When a complete success (pass) interval is found, that is, a complete failure (fail) → success (pass) → failure (fail) process occurs, the training is completed, and the start and end positions of the success (pass) interval are recorded.

[0055] If a complete success interval is not found between two failure intervals from the initial position of the WDQ signal until the position of the WDQ signal reaches the maximum position set in the instruction, the training is considered to have failed and the training failure is marked as fail.

[0056] Furthermore, in this embodiment, the DDR write data eye diagram training method based on the standard delay unit further includes: S7, taking the middle value of the success interval as the final delay configuration of the WDQ signal, so that the rising edge of the WDQS signal is aligned with the center of the WDQ signal, thereby achieving optimal sampling.

[0057] In addition, in this embodiment, each bit of the WDQ signal has a corresponding delay line. During the training process, the training result is recorded for each bit (per bit) of the WDQ signal, and the calculation result is configured on the corresponding delay line, so as to further compensate for the skew between the bits of different WDQ signals.

[0058] Preferably, in order to further reduce the complexity of training and save training time, in this embodiment, before updating the delay setting of the WDQ signal in step S2, it can be determined based on the actual wiring whether the signal skew between the WDQS signal and the WDQ signal of each DDR particle is within a preset range; if so, a fixed delay time is added on the basis of the delay configuration of the WDQS signal of each DDR particle in an instruction configuration manner as the final delay configuration of the WDQ signal of the DDR particle, and the subsequent eye diagram training process is omitted.

[0059] Specifically, Figure 7 As shown in the figure, if the wiring delay of the WDQ signal is the same as that of the WDQS signal, the right edge of the eye diagram of the WDQ signal is aligned with the rising edge of the WDQS signal. Through the instruction, 0.5UI is added to the training result of the WDQS signal as the delay setting of the WDQ signal. At this time, the center position of the eye diagram of the WDQ signal is aligned with the upper edge of the WDQS signal, and correct sampling can be achieved. In this way, the WDQ signal delay configuration can be quickly implemented without complete eye diagram training, thereby greatly simplifying the training complexity of the DDR system.

[0060] The DDR write data eye diagram training method based on the standard delay unit provided in this embodiment can flexibly adjust the delay amount according to the frequency and the routing delay gap through instruction control, and does not require an additional register to store the value to be reduced in advance, thereby increasing flexibility while minimizing the hardware logic overhead as much as possible. In addition, if the DDR system can ensure that the routing delay gap between the WDQ signal and the WDQS signal is within a certain range, the training result of the WDQS signal can be directly increased or decreased by a fixed time as the training result of the WDQ signal through instructions, thereby omitting the write data eye diagram training process, greatly simplifying the complexity of DDR system training, and saving training time.

[0061] Furthermore, this embodiment further provides a computer storage medium storing an executable program; when the executable program is executed, the DDR write data eye diagram training method based on the standard delay unit as described above is implemented.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0063] The DDR write data eye diagram training system and method based on the standard delay unit and the computer storage medium provided in this embodiment include a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: a command generation unit, used to send read and write commands to the DDR particle through the IO module, and generate a WDQS signal and a WDQ signal; a delay control unit, used to adjust the delay module during the eye diagram training process so that the delay module adjusts the delay time of the WDQS signal and the WDQ signal; a detection and judgment unit, used to judge whether the read data returned by the IO interface is correct, and used to record the boundary information during the eye diagram training process and the final delay information after the eye diagram training is completed. The DDR training control module generates commands and signals in an instruction-controlled manner and controls the adjustment of the delay time during the eye diagram training process. Not only is the system structure simple and consumes less hardware resources, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. This improves the training accuracy and stability while reducing the training complexity. It also ensures that each DDR particle completes the training in the same time, saving training time and solving the problem of high hardware consumption and poor training effect in the existing DDR write data eye diagram training.

[0064] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DDR write data eye diagram training system based on a standard delay unit, characterized in that: It includes a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal and a WDQ signal; A delay control unit, used to adjust the delay module during the eye diagram training process so that the delay module adjusts the delay time of the WDQS signal and the WDQ signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the eye diagram training process and the final delay information after the eye diagram training is completed.

2. The DDR write data eye diagram training system based on the standard delay unit according to claim 1, characterized in that: The DDR training control module further includes an integral UI delay unit; the integral UI delay unit is used to delay the WDQS signal and the WDQ signal by UI units through digital logic.

3. The DDR write data eye diagram training system based on the standard delay unit according to claim 1, characterized in that: The delay module includes a WDQS delay unit and a WDQ delay unit; the WDQS delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the WDQ delay unit is used to adjust the delay time of the WDQ signal under the control of the delay control unit.

4. The DDR write data eye diagram training system based on the standard delay unit according to claim 3, characterized in that: The WDQS delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series; the WDQ delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series.

5. The DDR write data eye diagram training system based on the standard delay unit according to claim 4, characterized in that: Whenever the delay time of the WDQS delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the WDQS delay unit is cleared; whenever the delay time of the WDQ delay unit increases to 1 UI, the generation time of the WDQ signal is delayed by 1 UI, and the setting of the WDQ delay unit is cleared.

6. A DDR write data eye diagram training method based on a standard delay unit, applied to a DDR write data eye diagram training system based on a standard delay unit as claimed in any one of claims 1 to 5, characterized in that: The DDR write data eye diagram training method based on the standard delay unit includes: Set the initial position of the WDQ signal according to the WDQS signal; Update the delay setting of WDQ signal; Send read and write commands; Determine whether the current WDQ signal position meets the reading and writing requirements; If the current WDQ signal position meets the read and write requirements, the current WDQ signal position is divided into the success interval, otherwise, the current WDQ signal position is divided into the failure interval; The delay setting of the WDQ signal is updated until a complete success interval is found between two failure intervals.

7. The DDR write data eye diagram training method based on the standard delay unit according to claim 6, characterized in that: The method for setting the initial position of the WDQ signal according to the WDQS signal includes: In a command configuration manner, the delay configuration of the WDQS signal of each DDR particle is reduced by a preset value to serve as the initial delay configuration of the WDQ signal of the DDR particle.

8. The DDR write data eye diagram training method based on the standard delay unit according to claim 7, characterized in that: The method for updating the delay setting of the WDQ signal includes: Starting from the initial position of the WDQ signal, each time it is updated, the WDQ signal is delayed by one step according to the step size set in the instruction.

9. The DDR write data eye diagram training method based on the standard delay unit according to claim 8, characterized in that: The method for determining whether the current WDQ signal position meets the read and write requirements includes: If the read-back data is consistent with the written data at the current WDQ signal position, it is determined that the current WDQ signal position meets the read and write requirements.

10. The DDR write data eye diagram training method based on the standard delay unit according to claim 6, characterized in that: The DDR write data eye diagram training method based on the standard delay unit also includes: If a complete success interval is not found between two failure intervals from the initial position of the WDQ signal until the position of the WDQ signal reaches the maximum position set in the instruction, the training is marked as failed.

11. The DDR write data eye diagram training method based on the standard delay unit according to claim 6, characterized in that: The DDR write data eye diagram training method based on the standard delay unit also includes: The middle value of the success interval is used as the final delay configuration of the WDQ signal so that the rising edge of the WDQS signal is aligned with the center of the WDQ signal.

12. The DDR write data eye diagram training method based on the standard delay unit according to claim 6, characterized in that: Before the delay setting of the updating WDQ signal, the DDR write data eye diagram training method based on the standard delay unit includes: Determine whether the signal skew between the WDQS signal and the WDQ signal of each DDR particle is within a preset range; If so, a fixed delay time is added based on the delay configuration of the WDQS signal of each DDR particle in the form of instruction configuration to serve as the final delay configuration of the WDQ signal of the DDR particle, and the subsequent eye diagram training process is omitted.

13. A computer storage medium, characterized in that: The computer storage medium stores an executable program; when the executable program is executed, the DDR write data eye diagram training method based on the standard delay unit as described in any one of claims 6 to 12 is implemented.

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