DDR write data mask training system and method based on standard delay unit

Abstract

The invention provides a DDR write data mask training system and method based on a standard delay unit, and a computer storage medium, the DDR write data mask training system comprises a DDR training control module, a delay module and an IO module, and the DDR training control module comprises a command generation unit which sends a read-write command through the IO module and generates a training related signal; the delay control unit adjusts the delay module so as to adjust the delay time of the training related signal; and the detection judgment unit judges whether read data returned by the IO interface is correct or not and records related delay information. The DDR training control module generates commands and training related signals in an instruction control mode and controls adjustment of delay time in the mask training process, so that the system is simple in structure and low in hardware resource consumption, the delay amount can be flexibly adjusted according to the actual situation, training precision and stability are improved, and meanwhile, the training efficiency is improved. The training complexity is reduced, the training time is saved, and the problems of large hardware consumption and poor training effect of the existing DDR write data mask training are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a DDR write data mask training system and method based on a standard delay unit, and a computer storage medium. Background Art

[0002] Double Data Rate (DDR) system is the customary abbreviation of double data rate synchronous dynamic random access memory system. Its advantages are large storage capacity, low cost, mature interface, and high access rate during parallel burst access. The external signal interface of DDR mainly includes: clock signal (CK), data signal (DQ), data mask signal (WDM), data bus inversion signal (DBI), selection signal (DQS) and command / address signal (CA).

[0003] When DDR performs a write operation, each set of DQ signals will have an accompanying WDM signal to indicate whether the data needs to be written into the memory chip. After the DDR system completes write equalization, write delay, and write data eye diagram training, its write selection signal (WDQS) and write data signal (WDQ) are in the appropriate position to ensure that DQ can be sampled normally. In order to ensure that the WDM signal can also be correctly sampled by WDQS, the DDR system usually also needs to train WDM, that is, write data mask training.

[0004] The WDM training process requires that the control logic of DDR must have the ability to adjust the WDM delay. The delay scale mainly includes delays of integer multiples of tCK and delays of non-integer multiples. For non-integer multiples of delay, the common practice is to divide a tCK into fixed equal parts, such as dividing tCK into 32 or 64 parts, that is, for each additional equal-division delay unit, the delay time will increase by 1 / 32 tCK or 1 / 64 tCK. Since the applicable frequency range of DDR3 / 4 is relatively wide (800MTS~3200MTS), using this delay method, each equal-division delay unit needs to use different numbers of hardware delay resources at different frequencies, and the hardware delay module needs to perform complex calculations and processing. In addition, for different frequencies, the training error will also be different. Taking DDR3-800 as an example, each DDR clock cycle is 2.5ns. In the case of 64 equal divisions, the delay time of each equal-division delay unit is 39ps, and the training error will also reach 39ps.

[0005] In addition, the DDR address signal line adopts a fly-by structure, which causes different particles to receive commands at different times. Therefore, during write balance and write delay training, the training results of different particle WDQS are quite different. In the DDR system, the wiring lengths of WDM and WDQS are generally close, so during the WDM training process, the training results of different particle WDM will also be quite different. Moreover, in the traditional WDM training method, the initial delay of all particle WDM starts from the same position, which will cause the overall training time to be longer.

[0006] At the same time, since the training of WDM needs to indirectly determine whether its position is correct through the result of WDQ, two write operations and one read operation are required for each delay position during the WDM training process: first, a background value is written through a write operation, and the WDM accompanying the write operation is all 1; then a target value is written through a write operation, and the corresponding WDM contains part of 0 and part of 1; finally, the read operation is used to compare whether the read data is a combination of the two write operations to determine whether the WDM position is correct. In the existing DDR3 / 4 system, WDM is not directly stored in the memory particles. Using this training method, the data and WDM required for the two write operations need to be stored in advance, and the status of the training process needs to be recorded to determine which data needs to be written and when to perform the read operation. The logical process and state jump are relatively complex, and the logical overhead and hardware need to record more data. Summary of the invention

[0007] The object of the present invention is to provide a DDR write data mask training system and method based on a standard delay unit, and a computer storage medium, so as to solve the problem that the existing DDR write data mask training hardware consumes a lot and has a poor training effect.

[0008] In order to solve the above technical problems, the present invention provides a DDR write data mask training system based on a standard delay unit, comprising a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module comprises: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal, a WDQ signal and a WDM signal; A delay control unit, used to adjust the delay module during the mask training process so that the delay module adjusts the delay time of the WDQS signal, the WDQ signal and the WDM signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the mask training process and the final delay information after the mask training is completed.

[0009] Optionally, in the DDR write data mask training system based on the standard delay unit, the DDR training control module also includes a whole UI delay unit; the whole UI delay unit is used to delay the WDQS signal, WDQ signal and WDM signal by UI units through digital logic.

[0010] Optionally, in the DDR write data mask training system based on the standard delay unit, the delay module includes a first delay unit and a second delay unit; the first delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the second delay unit is used to adjust the delay time of the WDQ signal and the WDM signal under the control of the delay control unit.

[0011] Optionally, in the DDR write data mask training system based on the standard delay unit, the first delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series; the second delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series.

[0012] Optionally, in the DDR write data mask training system based on the standard delay unit, whenever the delay time of the first delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the first delay unit is cleared; whenever the delay time of the second delay unit increases to 1 UI, the generation time of the WDQ signal and the WDM signal is delayed by 1 UI, and the setting of the second delay unit is cleared.

[0013] In order to solve the above technical problems, the present invention further provides a DDR write data mask training method based on a standard delay unit, which is applied to the DDR write data mask training system based on a standard delay unit as described in any one of the above items, and the DDR write data mask training method based on a standard delay unit comprises: Setting the initial position of the WDM signal according to the WDQS signal; Updated delay settings for WDM signals; Perform two write operations and one read operation in sequence; Determine whether the current WDM signal position meets the reading and writing requirements; If the current WDM signal position meets the read and write requirements, the current WDM signal position is divided into the success interval, otherwise, the current WDM signal position is divided into the failure interval; The delay setting of the WDM signal is updated until a complete success interval is found between two failure intervals.

[0014] Optionally, in the DDR write data mask training method based on the standard delay unit, the method of setting the initial position of the WDM signal according to the WDQS signal includes: In a command configuration manner, the delay configuration of the WDQS signal of each DDR particle is reduced by a preset value to serve as the initial delay configuration of the WDM signal of the DDR particle.

[0015] Optionally, in the DDR write data mask training method based on the standard delay unit, the method for updating the delay setting of the WDM signal includes: Starting from the initial position of the WDM signal, each time it is updated, the WDM signal is delayed by one step according to the step size set in the instruction.

[0016] Optionally, in the DDR write data mask training method based on the standard delay unit, the method of sequentially performing two write operations and one read operation includes: In the manner of command configuration, the code patterns of the WDQ signal and the WDM signal of the first write operation are set, and the first write operation is performed; In a command configuration manner, the code patterns of the WDQ signal and the WDM signal of the second write operation are set, and the second write operation is performed, wherein the address of the second write operation is the same as the address of the first write operation; The code pattern of the expected data of the read operation is set in the form of instruction configuration, and the read operation is performed.

[0017] Optionally, in the DDR write data mask training method based on the standard delay unit, the method for determining whether the current WDM signal position meets the read and write requirements includes: If the read-back data is consistent with the expected data at the current WDM signal position, it is determined that the current WDM signal position meets the reading and writing requirements.

[0018] Optionally, in the DDR write data mask training method based on the standard delay unit, the DDR write data mask training method based on the standard delay unit further includes: If a complete success interval is not found between two failure intervals from the initial position of the WDM signal until the position of the WDM signal reaches the maximum position set in the instruction, the training is marked as failed.

[0019] Optionally, in the DDR write data mask training method based on the standard delay unit, the DDR write data mask training method based on the standard delay unit further includes: The middle value of the success interval is used as the final delay configuration of the WDM signal so that the rising edge of the WDQS signal is aligned with the center of the WDM signal.

[0020] Optionally, in the DDR write data mask training method based on the standard delay unit, before the delay setting of the WDM signal is updated, the DDR write data mask training method based on the standard delay unit includes: Determine whether the signal skew between the WDQS signal and the WDM signal of each DDR particle is within a preset range; If so, a fixed delay time is added based on the delay configuration of the WDQS signal of each DDR particle in the form of instruction configuration to serve as the final delay configuration of the WDM signal of the DDR particle, and the subsequent mask training process is omitted.

[0021] In order to solve the above technical problems, the present invention also provides a computer storage medium, wherein the computer storage medium stores an executable program; when the executable program is executed, the DDR write data mask training method based on the standard delay unit as described in any one of the above items is implemented.

[0022] The present invention provides a DDR write data mask training system and method based on a standard delay unit, and a computer storage medium, comprising a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module comprises: a command generation unit, used to send read and write commands to the DDR particle through the IO module, and generate a WDQS signal, a WDQ signal and a WDM signal; a delay control unit, used to adjust the delay module during the mask training process so that the delay module adjusts the delay time of the WDQS signal, the WDQ signal and the WDM signal; a detection and judgment unit, used to judge whether the read data returned by the IO interface is correct, and used to record boundary information during the mask training process and final delay information after the mask training is completed. The DDR training control module generates commands and signals in an instruction-controlled manner and controls the adjustment of the delay time during mask training. Not only does the system structure have a simple structure and consumes less hardware resources, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. This improves the training accuracy and stability while reducing the training complexity. It also ensures that each DDR particle completes the training in the same time, saving training time and solving the problem of high hardware consumption and poor training effect in existing DDR write data mask training. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A structural block diagram of a DDR write data mask training system based on a standard delay unit provided in this embodiment; Figure 2 A schematic diagram of the specific structure of the DDR write data mask training system based on the standard delay unit provided in this embodiment; Figure 3A schematic diagram of the initial correspondence between the WDM signal and the WQDS signal provided in this embodiment; Figure 4 A flowchart of a DDR write data mask training method based on a standard delay unit provided in this embodiment; Figure 5 Schematic diagram of signal delay between particle 0 and particle 1 during existing mask training; Figure 6 A schematic diagram of signal delay between particle 0 and particle 1 during mask training provided in this embodiment; Figure 7 A schematic diagram of the signal timing of two write operations provided in this embodiment; Figure 8 A signal timing diagram of a read operation provided in this embodiment; Fig. 9 A timing diagram showing that the WDM signal and the WQDS signal provided in this embodiment have the same delay. DETAILED DESCRIPTION

[0024] The DDR write data mask training system and method based on the standard delay unit and the computer storage medium proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0025] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] In order to better explain the DDR write data mask training system and method based on the standard delay unit provided by the present application, the relevant terms are first explained as follows: FPGA: Field Programmable Gate Array, a field programmable gate array is an integrated circuit with programmable features pre-designed and implemented on a silicon chip; DDR: Double Data Rate, double data transmission rate; DDR particles: DDR SDRAM, synchronous dynamic random access memory with double data transfer rate; DQ: data, bidirectional data signal line of DDR particles; DQS: data strobe, equivalent to the reference clock of the data signal, used to sample the data signal line; WDQ: write data, data signal line in the write direction, referred to as write data signal in this application; WDQS: write data strobe, used to sample the data signal line in the write direction, referred to as write strobe signal in this application, including a pair of differential signals WDQS_t and WDQS_c; RDQ: read data, data signal line in the read direction, referred to as read data signal in this application; WDM: write data mask, used to mask out data that does not need to be written into DDR particles; CK: clock, the clock of DDR particles, including a pair of differential clocks CK_t and CK_c; SDL: Standard Cell Delay Line, a standard delay cell with fixed delay function composed of combinational logic cascade, with a simple structure and a fixed delay time of about 20ps; CDL: Customer delay line, a user-defined standard delay unit composed of analog circuits, with a fixed delay time of about 5ps; Skew: Different signals have transmission delay deviations due to wiring problems, so that the signals at the receiving end cannot be completely aligned. tCK: DDR clock cycle; UI: Half of the DDR particle clock cycle, that is, 1 / 2CK.

[0027] WRITE LEVELING: Write leveling is a DDR particle training process used to align the rising edge of WDQS_t and the rising edge of CK_t received by the DDR particle; WRITE LATENCY: write delay. After receiving a write command, the DDR particle needs to go through a fixed number of tCK delays before it can accept WDQS. This delay is the write delay. CS: Chip select, chip select signal, one of the standard interface signals of DDR particles and one of the command signals.

[0028] This embodiment provides a DDR write data mask training system based on a standard delay unit, such as Figure 1 As shown, it includes a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal, a WDQ signal and a WDM signal; A delay control unit, used to adjust the delay module during the mask training process so that the delay module adjusts the delay time of the WDQS signal, the WDQ signal and the WDM signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the mask training process and the final delay information after the mask training is completed.

[0029] The DDR write data mask training system based on the standard delay unit provided in this embodiment generates commands and signals in an instruction-controlled manner through the DDR training control module, and controls the adjustment of the delay time during the mask training process. Not only is the system structure simple and the hardware resource consumption low, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. Therefore, while improving the training accuracy and stability, it not only reduces the training complexity, but also ensures that the time to complete the training of each DDR particle is the same, saving training time, and solving the problem of high hardware consumption and poor training effect of existing DDR write data mask training.

[0030] Specifically, in this embodiment, the delay module includes a first delay unit and a second delay unit; the first delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the second delay unit is used to adjust the delay time of the WDQ signal and the WDM signal under the control of the delay control unit.

[0031] In practical applications, such as Figure 2 As shown, the first delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series; the second delay unit includes 96 levels of SDL and 4 levels of CDL arranged in series. Among them, the series connection of the 96 levels of SDL units can be configured by setting configuration information thereof by means of instruction configuration, thereby adjusting the number of SDL units passed during the transmission of the WDQS signal and the WDM signal, and further adjusting the length of the delay time of the WDQS signal and the WDM signal; the series connection of the 4 levels of CDL units can also be configured by setting configuration information thereof by means of instruction configuration, thereby adjusting the number of CDL units passed during the transmission of the WDQS signal and the WDM signal, and further adjusting the length of the delay time of the WDQS signal and the WDM signal.

[0032] Since the delay time of each CDL level is about 5ps and the delay time of SDL is about 20ps, the delay time of 4 levels of CDL in series is approximately equal to the delay time of 1 level of SDL. When the delay time of the used CDL reaches 4 levels, one level of SDL will be added and the value of CDL will be cleared. During the training process, if the delay accuracy requirement is relatively low, CDL can be omitted.

[0033] The DDR write data mask training system based on the standard delay unit provided in this embodiment can meet the WDM training requirements of all frequencies of DDR3 / 4 by adopting SDL and CDL connected in series, and the accuracy of the training results can be as high as 5ps at all frequencies; at the same time, since the total delay of SDL and CDL does not exceed 1UI, the delay of the WDM signal is less affected by PVT (process, voltage, temperature).

[0034] Better, such as Figure 2 As shown, in order to reduce the resource consumption of the delay module and further improve the training efficiency and accuracy, in this embodiment, the DDR training control module also includes a whole UI delay unit; the whole UI delay unit is used to delay the WDQS signal, WDQ signal and WDM signal by UI units through digital logic.

[0035] Specifically, the first delay unit and the second delay unit correspond to an integer UI delay unit respectively, so that the first integer UI delay unit is used to delay the WDQS signal by UI units, and the second integer UI delay unit is used to delay the WDQ signal and the WDM signal by UI units. After that, the WDQS signal is transmitted to the first delay unit, and the WDQ signal and the WDM signal are transmitted to the second delay unit.

[0036] Since 2 UIs are equal to 1 CK, the minimum unit of the whole UI delay unit is 1UI. Whenever the delay time of the first delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the first delay unit is cleared; and whenever the delay time of the second delay unit increases to 1 UI, the generation time of the WDM signal (together with the WDQ signal) is delayed by 1 UI, and the setting of the second delay unit is cleared. It should be noted that the delay time here mainly refers to the delay time of SDL, that is, when the delay time of SDL increases to 1 UI, 1UI will be added to the whole UI delay unit, so that the generation time of the signal is delayed by 1 UI, and the delay configuration of SDL is cleared at the same time. It should be noted that the signal generation time here refers to the time when the WDQS signal and the WDQ signal are sent from the DDR training control module.

[0037] like Figure 2As shown, the DDR write data mask training system based on the standard delay unit provided in this embodiment is implemented based on FPGA, and uses its internal resources to build an instruction set-based DDR training platform. By combining and calling FPGA resources, the training of DDR write data mask can be realized.

[0038] Of course, in practical applications, in addition to being used on an FPGA platform, the DDR write data mask training system based on a standard delay unit provided in this embodiment can also be applied to various integrated circuit systems and SOCs using DDR particles.

[0039] And, in this embodiment, DDR particles select DDR3 / 4 particles. Of course, in practical applications, DDR particles are not limited to DDR3 / 4, and can also be applied to various memory particles such as DDR5 or LPDDR, and this application does not limit this.

[0040] And, in this embodiment, when implemented based on FPGA, the IO module can be specifically IOB (input / output buffer), which is the external interface resource of FPGA. Of course, in actual applications, the IO module can select other interface resources according to actual needs, and this application does not limit this.

[0041] Although the delay settings of the WDQS signal and the WDQ signal have met the requirements of the write operation after completing the write equalization, write delay, and write data eye diagram training, the correspondence between the WDM signal and the WDQS signal still needs further training. Figure 3 For example, there may be a certain deviation in the initial correspondence between the WDM signal and the WQDS signal, so it is necessary to adjust the relative position of the WDM signal and the WDQS signal by continuously delaying the WDM signal.

[0042] Specifically, two write commands and one read command can be sent at each WDM signal position to determine whether the position meets the read and write requirements. That is, in the process of moving the WDM signal, the read and write operations will fail (fail) → succeed (pass) → fail (fail). The training process of the write data mask is the process of determining the center position of the successful interval. After the delay information of the WDM signal at this position is determined, the WDQS signal will be aligned with the center position of the WDM signal, thereby achieving the best sampling requirements.

[0043] Based on this, this embodiment also provides a DDR write data mask training method based on a standard delay unit, which is applied to the DDR write data mask training system based on a standard delay unit as described above. Figure 4 As shown, the DDR write data mask training method based on the standard delay unit includes: S1, setting the initial position of the WDM signal according to the WDQS signal; S2, updating the delay setting of the WDM signal; S3, two write operations and one read operation are performed in sequence; S4, judging whether the current WDM signal position meets the reading and writing requirements; S5, if the current WDM signal position meets the reading and writing requirements, the current WDM signal position is divided into a success interval, otherwise, the current WDM signal position is divided into a failure interval; S6, updating the delay setting of the WDM signal until a complete success interval is found between the two failure intervals.

[0044] The DDR write data mask training method based on the standard delay unit provided in this embodiment is implemented based on the DDR write data mask training system based on the standard delay unit, so that commands and signals are generated in an instruction-controlled manner through the DDR training control module, and the delay setting of the WDM signal in the mask training process is updated. Not only is the training process simple and the hardware resources consumed less, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference, thereby improving the training accuracy and stability while ensuring that each DDR particle completes the training in the same time, saving training time, and solving the problem of high hardware consumption and poor training effect of existing DDR write data mask training.

[0045] Specifically, in this embodiment, step S1, the method of setting the initial position of the WDM signal according to the WDQS signal includes: reducing the delay configuration of the WDQS signal of each DDR particle by a preset value in an instruction configuration manner to serve as the initial delay configuration of the WDM signal of the DDR particle.

[0046] Since the current DDR system usually adopts a fly-by structure, different DDR particles will receive different CS times. Figure 5 For example, the CS time received by particle 0 and particle 1 differs by 2UI, so the delay time of the WDQS signal of particles 0 and 1 obtained by write leveling and write delay training differs by 2UI. When performing WDM mask training, if the initial delay of the WDM signal of particles 0 and 1 is set to the same value, the range that the WDM signal of particle 1 needs to scan will be 2UI more than that of particle 0, resulting in an excessively long overall training time.

[0047] To solve this problem, this embodiment reduces the delay configuration of the WDQS signal of each particle by a fixed delay unit through instruction configuration, which serves as the initial delay setting of the WDM signal of the corresponding particle. Figure 6For example, at this time, the starting position of each particle WDM signal is about 2UI ahead of the WDQS signal of the particle. Then the time required for each particle WDM signal to complete the training is roughly the same, thereby shortening the overall training time.

[0048] In actual applications, the preset value of the delay configuration reduction of the WDQS signal of each DDR particle can be adjusted according to the frequency, so that the offset of the starting position of the WDM signal can be flexibly adjusted. Usually, it is necessary to ensure that the initial position of the WDM signal is before the left boundary of the mask success (pass) interval, so that the WDM signal can sweep the entire failure (fail) → success (pass) → failure (fail) interval during the movement. For example, at low frequency, the initial position of the WDM signal can be advanced by only about 1.5UI relative to the WDQS signal.

[0049] In addition, the logic of the instruction configuration method adopted in this embodiment is the logic shared by the entire system, so it does not require too much additional logic overhead, thereby saving hardware resource consumption.

[0050] Further, in this embodiment, step S2, the method for updating the delay setting of the WDM signal includes: starting from the initial position of the WDM signal, each time it is updated, the WDM signal is delayed by one step according to the step set in the instruction, wherein the step set in this embodiment is the delay time of 1 CDL, i.e., 5ps, so as to ensure that the overall training results have high accuracy. Of course, in actual applications, the step can be reasonably set in the instruction according to actual needs.

[0051] And, in this embodiment, step S3, the method of sequentially performing two write operations and one read operation includes: S31, setting the code types of the WDQ signal and the WDM signal of the first write operation in a command configuration manner, and performing the first write operation.

[0052] Specifically, in this embodiment, the first write operation is used to write a background value, and the code type of the corresponding WDM signal is all 1, thereby ensuring that all data of the WDQ signal can be written normally.

[0053] In practical applications, the data pattern of the WDQ signal in the first write operation can be set according to actual needs. For example, the bit width of the WDQ signal is 8 bits. Figure 6 As shown, WDQ0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 are 8 bits wide, the corresponding WDM is 1 bit wide, and the WDQ code type is 8'haa (8 "aa").

[0054] S32, setting the code types of the WDQ signal and the WDM signal of the second write operation in a command configuration manner, and performing the second write operation, wherein the address of the second write operation is the same as the address of the first write operation.

[0055] Specifically, in this embodiment, the second write operation is used to write the target value, and the corresponding WDM signal pattern includes a portion of 0s and a portion of 1s, so that the portion of the WDM signal that is 1 is written into the DDR particle.

[0056] In actual applications, the code patterns of the WDM signal and the WDQ signal are changed through instructions, and the second write operation is performed on the same address. The code pattern can be set according to the requirements. Taking the above example, all WDQ0 to WDQ7 are set to 8'h55 (8 "55"), and the corresponding WDM signal is set to 0101_0101. Under this code pattern, if the WDM signal is at the correct delay position, then this write operation will mask the data corresponding to WDQ0 / 2 / 4 / 6 and will not be written, while the data corresponding to WDQ1 / 3 / 5 / 7 will be written to the DDR particles, that is, the expected code pattern of the data WDQ0-WDQ7 stored at this address is aa_55_aa_55_aa_55_aa_55.

[0057] The schematic diagram of the two write operations is as follows: Figure 7 shown.

[0058] S33, setting the code pattern of the expected data of the read operation in the form of instruction configuration, and performing the read operation.

[0059] Specifically, in this embodiment, the data RDQ is read through a read operation, so that it can be compared with two write operations to determine whether the position of the WDM signal is correct.

[0060] Still taking the above example, the expected data pattern of the read operation is set to aa_55_aa_55_aa_55_aa_55 through instructions, and a read operation is performed. By comparing whether the read-back data is consistent with the expected data, it is indirectly determined whether the position of the WDM signal is correct.

[0061] The read operation process is shown as follows Figure 8 shown.

[0062] In practical applications, the WDQ signal, WDM signal and WDQS signal required for the two write operations are generated according to the write command, and the RDQ signal returned by the DDR particle is generated according to the read command. Multiple writes and reads can be performed at each delay position as required. The methods of generating read and write commands, WDQ signals, WDM signals and WDQS signals, and sending read and write commands are well known to those skilled in the art, and this application will not go into details.

[0063] Further, in this embodiment, step S4, the method for determining whether the current WDM signal position meets the read and write requirements includes: if at the current WDM signal position, the data read back each time is consistent with the expected data, then determining that the current WDM signal position meets the read and write requirements.

[0064] Specifically, two write operations and one read operation can be performed multiple times under the delay setting of each WDM signal, and the result of each read and write data can be determined. If the read data is consistent with the expected data, then the read and write are correct, and it is determined that the current WDM signal position meets the read and write requirements.

[0065] And, in this embodiment, in step S5, if the current WDM signal position meets the reading and writing requirements, the current WDM signal position is divided into the success interval, otherwise, the current WDM signal position is divided into the failure interval.

[0066] Furthermore, in this embodiment, step S6 updates the delay setting of the WDM signal until a complete success interval is found between the two failure intervals. That is, before a complete success (pass) interval is found and the delay setting of the WDM signal has not reached the maximum setting, the delay of the WDM signal is continuously increased according to the step size set in the instruction, and the reading and writing process is repeated, that is, steps S2 to S5 are repeated.

[0067] When a complete success (pass) interval is found, that is, a complete failure (fail) → success (pass) → failure (fail) process occurs, the training is completed, and the start and end positions of the success (pass) interval are recorded.

[0068] If a complete success interval is not found between two failure intervals from the initial position of the WDM signal until the position of the WDM signal reaches the maximum position set in the instruction, the training is considered to have failed and the training failure is marked as fail.

[0069] The judgment logic and read / write control logic of the above-mentioned process of finding the successful interval are highly consistent with the logic of the write data eye diagram training process. Therefore, in practical applications, time-sharing multiplexing of logic can be achieved through instruction control, thereby effectively reducing hardware overhead.

[0070] Furthermore, in this embodiment, the DDR write data mask training method based on the standard delay unit further includes: S7, taking the middle value of the success interval as the final delay configuration of the WDM signal, so that the rising edge of the WDQS signal is aligned with the center of the WDM signal, thereby achieving optimal sampling.

[0071] Preferably, in order to further reduce the complexity of training and save training time, in this embodiment, before updating the delay setting of the WDM signal in step S2, it can be determined based on the actual wiring whether the signal skew between the WDQS signal and the WDM signal of each DDR particle is within a preset range; if so, a fixed delay time is added on the basis of the delay configuration of the WDQS signal of each DDR particle in an instruction configuration manner as the final delay configuration of the WDM signal of the DDR particle, and the subsequent mask training process is omitted.

[0072] Specifically, Fig. 9 As shown in the figure, if the routing delay of the WDM signal is the same as that of the WDQS signal, the right edge of the mask of the WDM signal is aligned with the rising edge of the WDQS signal. Through the instruction, 0.5UI is added to the training result of the WDQS signal as the delay setting of the WDM signal. At this time, the center position of the mask of the WDM signal is aligned with the upper edge of the WDQS signal, and correct sampling can be achieved. In this way, the delay configuration of the WDM signal can be quickly realized without complete mask training, thereby greatly simplifying the training complexity of the DDR system.

[0073] The DDR write data mask training method based on the standard delay unit provided in this embodiment can flexibly adjust the delay amount according to the frequency and the routing delay gap through instruction control, and does not require an additional register to store the value to be reduced in advance, thereby increasing flexibility while minimizing the hardware logic overhead as much as possible. In addition, if the DDR system can ensure that the routing delay gap between the WDM signal and the WDQS signal is within a certain range, the training result of the WDQS signal can be directly increased or decreased by a fixed time as the training result of the WDM signal through instructions, thereby omitting the write data mask training process, greatly simplifying the complexity of DDR system training, and saving training time.

[0074] The DDR write data mask training method based on the standard delay unit provided in this embodiment uses an instruction control method, does not require complex state machine control, and does not require recording of the WDM training process, which can greatly simplify the logic of the data generation module. During the data generation process, the training logic control module only needs to complete the parsing of the instructions, and the read and write command generation logic of different modules can be shared, which greatly reduces the complexity of the overall training and reduces the hardware logic overhead.

[0075] Furthermore, this embodiment further provides a computer storage medium, wherein the computer storage medium stores an executable program; when the executable program is executed, the DDR write data mask training method based on the standard delay unit as described above is implemented.

[0076] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0077] The DDR write data mask training system and method based on the standard delay unit and the computer storage medium provided in this embodiment include a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: a command generation unit, used to send read and write commands to the DDR particle through the IO module, and generate a WDQS signal and a WDM signal; a delay control unit, used to adjust the delay module during the mask training process so that the delay module adjusts the delay time of the WDQS signal and the WDM signal; a detection and judgment unit, used to judge whether the read data returned by the IO interface is correct, and used to record the boundary information during the mask training process and the final delay information after the mask training is completed. The DDR training control module generates commands and signals in an instruction-controlled manner and controls the adjustment of the delay time during mask training. Not only does the system structure have a simple structure and consumes less hardware resources, but the delay amount can also be flexibly adjusted according to the frequency and the routing delay difference. This improves the training accuracy and stability while reducing the training complexity. It also ensures that each DDR particle completes the training in the same time, saving training time and solving the problem of high hardware consumption and poor training effect in existing DDR write data mask training.

[0078] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DDR write data mask training system based on a standard delay unit, characterized in that: It includes a DDR training control module, a delay module and an IO module, wherein the IO module is connected to an external DDR particle, wherein the DDR training control module includes: A command generating unit, used for sending read and write commands to the DDR particles through the IO module, and generating a WDQS signal, a WDQ signal and a WDM signal; A delay control unit, used to adjust the delay module during the mask training process so that the delay module adjusts the delay time of the WDQS signal, the WDQ signal and the WDM signal; The detection and judgment unit is used to judge whether the read data returned by the IO interface is correct, and to record the boundary information during the mask training process and the final delay information after the mask training is completed.

2. The DDR write data mask training system based on the standard delay unit according to claim 1, characterized in that: The DDR training control module further includes an integral UI delay unit; the integral UI delay unit is used to delay the WDQS signal, the WDQ signal and the WDM signal by UI units through digital logic.

3. The DDR write data mask training system based on the standard delay unit according to claim 1, characterized in that: The delay module includes a first delay unit and a second delay unit; the first delay unit is used to adjust the delay time of the WDQS signal under the control of the delay control unit; the second delay unit is used to adjust the delay time of the WDQ signal and the WDM signal under the control of the delay control unit.

4. The DDR write data mask training system based on the standard delay unit according to claim 3, characterized in that: The first delay unit includes 96 stages of SDL and 4 stages of CDL arranged in series; the second delay unit includes 96 stages of SDL and 4 stages of CDL arranged in series.

5. The DDR write data mask training system based on the standard delay unit according to claim 4, characterized in that: Whenever the delay time of the first delay unit increases to 1 UI, the generation time of the WDQS signal is delayed by 1 UI, and the setting of the first delay unit is cleared; whenever the delay time of the second delay unit increases to 1 UI, the generation time of the WDQ signal and the WDM signal is delayed by 1 UI, and the setting of the second delay unit is cleared.

6. A DDR write data mask training method based on a standard delay unit, applied to a DDR write data mask training system based on a standard delay unit as claimed in any one of claims 1 to 5, characterized in that: The DDR write data mask training method based on the standard delay unit includes: Setting the initial position of the WDM signal according to the WDQS signal; Updated delay settings for WDM signals; Perform two write operations and one read operation in sequence; Determine whether the current WDM signal position meets the reading and writing requirements; If the current WDM signal position meets the read and write requirements, the current WDM signal position is divided into the success interval, otherwise, the current WDM signal position is divided into the failure interval; The delay setting of the WDM signal is updated until a complete success interval is found between two failure intervals.

7. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: The method for setting the initial position of the WDM signal according to the WDQS signal comprises: In a command configuration manner, the delay configuration of the WDQS signal of each DDR particle is reduced by a preset value to serve as the initial delay configuration of the WDM signal of the DDR particle.

8. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: The method for updating the delay setting of the WDM signal comprises: Starting from the initial position of the WDM signal, each time it is updated, the WDM signal is delayed by one step according to the step size set in the instruction.

9. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: The method of sequentially performing two write operations and one read operation comprises: In the manner of command configuration, the code patterns of the WDQ signal and the WDM signal of the first write operation are set, and the first write operation is performed; In a command configuration manner, the code patterns of the WDQ signal and the WDM signal of the second write operation are set, and the second write operation is performed, wherein the address of the second write operation is the same as the address of the first write operation; The code pattern of the expected data of the read operation is set in the form of instruction configuration, and the read operation is performed.

10. The DDR write data mask training method based on the standard delay unit according to claim 9, characterized in that: The method for determining whether the current WDM signal position meets the reading and writing requirements includes: If the read-back data is consistent with the expected data at the current WDM signal position, it is determined that the current WDM signal position meets the reading and writing requirements.

11. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: The DDR write data mask training method based on the standard delay unit also includes: If a complete success interval is not found between two failure intervals from the initial position of the WDM signal until the position of the WDM signal reaches the maximum position set in the instruction, the training is marked as failed.

12. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: The DDR write data mask training method based on the standard delay unit also includes: The middle value of the success interval is used as the final delay configuration of the WDM signal so that the rising edge of the WDQS signal is aligned with the center of the WDM signal.

13. The DDR write data mask training method based on the standard delay unit according to claim 6, characterized in that: Before the delay setting of the WDM signal is updated, the DDR write data mask training method based on the standard delay unit includes: Determine whether the signal skew between the WDQS signal and the WDM signal of each DDR particle is within a preset range; If so, a fixed delay time is added based on the delay configuration of the WDQS signal of each DDR particle in the form of instruction configuration to serve as the final delay configuration of the WDM signal of the DDR particle, and the subsequent mask training process is omitted.

14. A computer storage medium, characterized in that: The computer storage medium stores an executable program; when the executable program is executed, the DDR write data mask training method based on the standard delay unit as described in any one of claims 6 to 13 is implemented.

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