A PCIe Retimer Path Switching Method and System

Abstract

The present invention relates to the field of integrated circuit design, and provides a PCIe retimer path switching method and system. The retimer includes a general path and a low-latency path, and is disposed between the root complex and the endpoint of the PCIe system. The method includes: pre-caching the status lock code stream transmitted between the root complex and the endpoint, where the status lock code stream is used to maintain the current status of the root complex and the endpoint; detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; in the data stream received first by the retimer, starting from the position of the electrical idle exit ordered set code stream, replacing the subsequent ordered set code streams with the status lock code stream; and completing the path switching before the position of the electrical idle exit ordered set code stream corresponding to the code stream replacement. The present invention enables the PCIe retimer to not cause the PCIe system to re-enter the link recovery state due to path switching when switching from the general path to the low-latency path.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to a method and system for switching PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) retimer paths. Background Art

[0002] In a system where a PCIe RC (Root Complex) is interconnected with a PCIe EP (Endpoint), when the PCIe rate is greater than a certain rate, the signal is severely attenuated after passing through the PCB traces, and a PCIe retimer needs to be added between the RC and EP chips to solve the signal attenuation problem.

[0003] Adding a PCIe retimer in the PCIe system, although solving the signal attenuation problem, will increase the system delay due to the addition of the PCIe retimer. Therefore, a low-delay path needs to be constructed in the PCIe retimer, so there are two paths in the PCIe retimer: a general path and a low-delay path. The schematic diagram is shown in Figure 1 Among them, the general path will perform encoding / decoding, scrambling / descrambling, SKP ordered set addition / subtraction, etc., with a relatively large delay; the low-delay path does not need to perform encoding / decoding, scrambling / descrambling, SKP ordered set addition / subtraction, etc., and the data of this path passes through directly, with a delay close to 0.

[0004] When the PCIe retimer switches from the general path to the low-delay path, since the low-delay path does not perform descrambling, when the RC and EP descramble the received bitstream, there will be a period of descrambling errors, and the bitstream cannot be correctly received. Then, after receiving the EIEOS (Electrical Idle Exit Ordered Set) bitstream, the descrambling is restored. Since the time when the RC and EP devices receive the EIEOS is uncertain, the recovery time of the RC and EP devices is also uncertain. The device that recovers first will correctly receive the bitstream first. After receiving the correct bitstream, the PCIe state machine may jump to the next state and send a new type of bitstream in the new state. When the device that recovers later receives the bitstream, it can no longer receive the bitstream in the previous state of the other party, resulting in the PCIe state machine being unable to jump correctly, causing a state machine timeout, and the PCIe state machines of the RC and EP devices return to the link recovery state (recovery) and cannot jump to the next state normally.

[0005] Switch from the general path to the low-latency path, and assume that the RC receives the EIEOS data stream first. The PCIe protocol stipulates that an EIEOS data stream needs to be sent every 32 data streams to reset the descrambler on the peer chip. In the general path, both the RC and the EP are in the first state A, and they send the first-state ordered set data stream OSA to each other, as shown in Figure 2(a). After receiving the OSA, the RC and the EP normally jump to the second state B, as shown in Figure 2(b). When the system enables the low-latency function, the PCIe retimer will switch from the general path to the low-latency path when the RC and the EP are in the first state A, and send the data stream OSA to each other through the low-latency path, as shown in Figure 3(a). The normal state transition should be as shown in Figure 3(b). Since there is no scrambling / descrambling function in the low-latency path, after the path is switched for a period of time, the RC and the EP will have descrambling errors and cannot correctly receive the data stream. After receiving the EIEOS data stream, the descrambler is reset, and then the data stream is normally received. Here, it is assumed that the RC receives the EIEOS data stream first. As Figure 4 shown, assuming that the RC receives the EIEOS data stream first, the RC resets the descrambler first. The RC normally receives the first-state ordered set data stream OSA first, and then the RC jumps to the second state B. In the second state B, the RC sends the second-state ordered set data stream OSB. Since the EP is still in the first state A and has been waiting to receive the first-state ordered set data stream OSA, but the RC has started to send the second-state ordered set data stream OSB, the EP can never receive the OSA, resulting in the EP timing out in the second state B and the state jumping to the link recovery state, unable to jump to the second state B as normal. Summary of the Invention

[0006] Aiming at the problems existing in the prior art, a PCIe retimer path switching method and system are provided, which can effectively solve the problem that the system enters the link recovery state when switching to the low-latency path.

[0007] In the first aspect of the present invention, a PCIe retimer path switching method is proposed. The retimer includes a general path and a low-latency path, and is set between the root complex (RC) and the endpoint (EP) of the PCIe system. The path switching method includes:

[0008] Pre-cache the state-locking data stream transmitted between the root complex and the endpoint, and the state-locking data stream is used to maintain the current states of the root complex and the endpoint;

[0009] Detect the interval of the electrical idle exit ordered set data stream in the data stream sent by the root complex and the endpoint;

[0010] In the data stream received by the retimer first, starting from the position of the ordered set code stream where the electrical idle exit occurs, the subsequent ordered set code stream is replaced with the status lock code stream, and the ordered set code stream is used for the status jump of the root complex and the endpoint; wherein, the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream.

[0011] The path switching is completed before the position of the electrical idle exit ordered set code stream corresponding to the code stream replacement occurs.

[0012] In an embodiment of the present invention, the detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint includes:

[0013] Detecting the time when the retimer receives the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint;

[0014] Determining the shortest interval of the electrical idle exit ordered set code stream received from both ends according to the reception time.

[0015] In an embodiment of the present invention, the pre-caching the status lock code stream transmitted between the root complex and the endpoint includes:

[0016] Starting from the position of the electrical idle exit ordered set code stream, caching the subsequent 16 consecutive status lock code streams.

[0017] In an embodiment of the present invention, when caching the status lock code stream, if the skipped ordered set code stream is included in the 16 consecutive status lock code streams, the cache is reset, and the subsequent status lock code stream is cached starting from the next electrical idle exit ordered set code stream.

[0018] In an embodiment of the present invention, the completing the path switching before the position of the electrical idle exit ordered set code stream corresponding to the code stream replacement specifically includes:

[0019] Completing the switching from the general path to the low-latency path at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

[0020] In an embodiment of the present invention, it further includes detecting the synchronization header position of each code stream in the data stream, and completing the replacement of the corresponding code stream according to the synchronization header position.

[0021] A second aspect of the present invention proposes a PCIe retimer path switching system. The retimer is arranged between the PCIe root complex and the endpoint. The retimer includes a general path and a low-latency path. The path switching system includes a low-latency switching control module and a switching switch. The low-latency switching control module:

[0022] A ranging unit for detecting the interval between the root complex and the electrical idle exit ordered set code stream in the data stream sent by the endpoint;

[0023] A code stream caching unit for caching the status lock code stream transmitted between the root complex and the endpoint, where the status lock code stream is used to maintain the current status of the root complex and the endpoint;

[0024] A synchronization header position detection unit for detecting the synchronization header positions of each code stream in the data stream;

[0025] A code stream replacement unit for replacing the subsequent ordered set code streams with the status lock code stream starting from the electrical idle exit ordered set code stream according to the synchronization header position in the data stream received first by the retimer. The ordered set code stream is used for the state transition of the root complex and the endpoint; wherein, the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream;

[0026] A switching switch for controlling the path switching according to the position of the electrical idle exit ordered set code stream where the code stream replacement occurs.

[0027] In an embodiment of the present invention, in the code stream caching unit, starting from the position of the electrical idle exit ordered set code stream, the subsequent 16 consecutive status lock code streams are cached. If the skipped ordered set code stream is included in the consecutive 16 status lock code streams, the cache is reset, and the subsequent status lock code streams are cached starting from the next electrical idle exit ordered set code stream.

[0028] In an embodiment of the present invention, it further includes a path switching state machine unit for controlling the units to work in sequence and finally controlling the switching switch to complete the switching from the general path to the low-latency path.

[0029] In an embodiment of the present invention, the switching switch is controlled by the path switching state machine unit to complete the switching from the general path to the low-latency path at the previous code stream corresponding to the electrical idle exit ordered set code stream where the code stream replacement occurs.

[0030] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: The present invention can prevent the PCIe retimer from re-entering the recovery state due to path switching when switching from the general path to the low-latency path. Description of the Drawings

[0031] Figure 1 It is a schematic diagram of the general path and the low-latency path of the PCIe retimer.

[0032] Figure 2(a) is a schematic diagram of the code stream transmission and reception when the RC and EP are in the first state A under the general path, and Figure 2(b) is a schematic diagram of the code stream transmission and reception when the RC and EP are in the second state B under the general path.

[0033] Figure 3(a) is a schematic diagram of the code stream transceiver when RC and EP are in the first state A under the low-latency path, and Figure 3(b) is a schematic diagram of the code stream transceiver when RC and EP normally jump to the second state B under the low-latency path.

[0034] Figure 4 It is a schematic diagram of the code stream transceiver with abnormal status under the low-latency path.

[0035] Figure 5 It is a schematic diagram of the traditional PCIe retimer path switching.

[0036] Figure 6 It is a flowchart of the PCIe retimer path switching method proposed in the embodiment of the present application.

[0037] Figure 7 It is a schematic diagram of the positions of the code stream synchronization headers received on the RC side and the EP side.

[0038] Figure 8 It is a schematic diagram of code stream replacement.

[0039] Figure 9 It is a schematic diagram of the PCIe retimer path switching system proposed in the embodiment of the present application. Detailed implementation manners

[0040] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application. Without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0041] The terms "first" and "second" in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0042] Figure 5FIG. 0 is a schematic diagram of the traditional PCIe retimer path switching. In this solution, when the link negotiation reaches a certain stage, the switching control circuit switches the data stream from the general path to the low-latency path without performing bitstream control according to the bitstream state, resulting in descrambling errors in the RC (Root Complex) and EP (Endpoint). Since the descrambling recovery time is uncertain, state transition timeouts occur in the subsequent recovery, causing the system to re-enter the link recovery state (recovery). Based on this, in view of the problem that the current PCIe retimer switching to the low-latency path causes the system to enter the recovery state, an embodiment of the present invention proposes a PCIe retimer path switching method. The retimer includes a general path and a low-latency path, which is disposed between the PCIe root complex and the endpoint and is used to control path switching to ensure that the PCIe root complex and the endpoint can still perform correct state transitions after switching to the low-latency path. The specific solution is as follows:

[0043] S100. Cache the state-locked bitstream transmitted between the root complex and the endpoint in advance.

[0044] In this embodiment, the subsequent description will be made by taking the example that both the RC and the EP can successfully jump from the first state A to the second state B. Specifically, whether it is the RC or the EP, when the descrambler is working properly and receives the ordered set bitstream (Ordered Sets, hereinafter abbreviated as OS) OSA sent by the peer in the first state A, it will jump to the second state B and then send the ordered set OSB at a subsequent time. Before the RC or the EP enters the first state A, the state-locked bitstream is sent by both the RC and the EP. After receiving the state-locked bitstream of a certain length, the RC and the EP will jump to the first state A. Since the RC and the EP in the first state A will send OSA, in some scenarios, it is necessary to make the RC and the EP hover in the first state A. The retimer between the RC and the EP can replace the OSA sent by both sides with the state-locked bitstream. Therefore, the RC and the EP still receive the state-locked bitstream and will always remain in the first state A. This operation usually occurs in the general path. The specific replacement and control are not the focus of this application and will not be elaborated here.

[0045] It should be noted that in this embodiment, only the example of maintaining the first state is described. In fact, other states can also be maintained, which essentially means maintaining the state of the RC and the EP before the jump. In this embodiment, the state-locked bitstream transmitted between the root complex and the endpoint can be cached in advance, and this state-locked bitstream is used to maintain the current state of the root complex and the endpoint so that no state transition occurs.

[0046] In the subsequent process, the present application mainly uses the interval of the Electrical Idle Exit Ordered Set (abbreviated as EIEOS hereinafter) in the data stream sent by EP and RC to replace the OS code stream to be sent with the state lock code stream to delay the state transition time at one end. According to the PCIe rule, the EIEOS code stream appears once every 32 code streams in the code stream, and the interval of the EIEOS received by RC and EP should be between 0 and 16. Therefore, when caching the state lock code stream, starting from the position of the EIEOS code stream, cache the subsequent 16 consecutive state lock code streams. It should be noted that if the skipped ordered set (SKP) code stream is included in the 16 consecutive state lock code streams, the cache needs to be reset and the subsequent state lock code streams need to be cached again starting from the next EIEOS code stream.

[0047] S200. Detect the interval of the EIEOS code stream in the data stream sent by the root complex and the endpoint.

[0048] As the code stream for restoring the PCIe root complex and endpoint descrambling functions, since the receiving times of the EIEOS code stream at both ends are different, it will cause the descrambling functions at both ends to be restored at different times, which will cause the section that restores descrambling later to be unable to complete the normal state transition. In order to achieve the correct state transition at both ends, it is necessary to first determine the interval between the descrambling functions restored at both ends, and then use the obtained interval to adjust the code stream. In this embodiment, first, by detecting the time when the retimer receives the EISOS code stream in the data stream sent by the root complex and the endpoint, the shortest interval of the EIEOS code stream received at both ends is determined according to the receiving time, and this interval determines the length of the code stream to be replaced later.

[0049] S300. In the data stream received by the retimer first, starting from the position of the EIEOS code stream, replace the subsequent OS code stream with the state lock code stream.

[0050] After the path is switched, once an end receives the EIEOS bitstream, the normal descrambling function will be restored. At this time, when the end that restores the normal descrambling receives the OS bitstream, it will perform a status jump and send the bitstream after the status jump (for example, an end in the first state A will jump to the second state B after receiving the OSA bitstream and start sending the OSB bitstream). Then, the end that receives the EIEOS bitstream cannot perform a normal jump because it does not receive the OSA bitstream in the first state. Therefore, to ensure that both ends can perform normal status jumps, the embodiment of the present application delays the status jump of the end that first receives the EIEOS bitstream by means of bitstream replacement, so that both ends complete the status jump together. Specifically, according to the EIEOS bitstream interval determined by S200, the number of bitstreams to be replaced is determined, that is, if the EIEOS bitstream interval is n, the retimer replaces the last n OS bitstreams with the first n status-locked bitstreams cached in S100 starting from the EIEOS bitstream position in the first received data stream. Through bitstream replacement, after the end that first receives the EIEOS bitstream restores the descrambling function, it will continue to receive n status-locked bitstreams. At this time, the status will not jump, and the (n + 1)th bitstream is a normal OS bitstream, and a normal status jump occurs when it is received. Correspondingly, when this end receives (n + 1) bitstreams, the other end receives the EIEOS bitstream and restores the descrambling function at the same time, and performs a status jump together. That is, by delaying the status jump time of the end that first receives the EIEOS bitstream, the status jumps of both ends are performed simultaneously.

[0051] When performing path switching, as Figure 7 shown, since the positions of the synchronization headers in the bitstreams received by the RC side and the EP side are uncertain, it is necessary to first detect the positions of the synchronization headers of each bitstream in the data stream according to the PCIe synchronization header rule before replacing the bitstream, and complete the corresponding bitstream replacement according to the synchronization header positions. As Figure 8 shown, only the bitstream is replaced during replacement, and the synchronization header is not replaced.

[0052] S400. Complete the path switching before the EIEOS bitstream position corresponding to the bitstream replacement occurs.

[0053] Furthermore, in the embodiments of the present application, the timing of path switching is related to the position of the bitstream replacement, that is, it is necessary to ensure that after the path switching, the OS bitstream after the first received EIEOS bitstream is replaced, so that the end that first receives the EIEOS bitstream will not have a state jump in advance. Specifically, in this embodiment, it is necessary to complete the switching from the general path to the low-latency path at the previous bitstream corresponding to the electrical idle exit ordered set bitstream where the bitstream replacement occurs. For example, the data stream is: 2-bit synchronization header + EIEOS1 +... + 2-bit synchronization header + 128-bit bitstream 1 + 2-bit synchronization header + 128-bit bitstream 2 + 2-bit synchronization header + EIEOS2 + synchronization header + 128-bit bitstream 3 +..., and both the SKP bitstream, the EIEOS bitstream, and the OSA bitstream are 128-bit in length. In the foregoing data stream, the 128-bit bitstream is directly used for replacement. Assuming that the bitstream replacement occurs after EIEOS2, the path switching needs to be performed at 128-bit bitstream 2 at this time. This can effectively ensure that after the path switching occurs, both ends can quickly restore the descrambling function and perform the correct state jump.

[0054] It should be added that the data stream transmission in the two directions of RC to EP and EP to RC. In practical applications, it is only necessary to replace the data stream on the side that first receives the EIEOS bitstream, and the other side is not replaced. Further, in terms of the path switching timing, the data stream direction that first receives the EIEOS bitstream performs the path switching, and the other data stream direction can perform the path switching simultaneously, or can perform the path switching after the shortest interval time of the EIEOS bitstream in the data stream sent by the root complex and the endpoint.

[0055] For the RC and EP in the first state A, through the path switching method of the present application, at the end that first receives the EIEOS bitstream (assuming it is the EP end), after the EP end restores the descrambling function, it will continue to receive the state lock bitstream and remain in the first state A. After an interval of n, it will continue to receive the OSA for a normal state jump. At this time, the RC end also receives the EIEOS bitstream and completes the state jump according to the subsequent OSA, realizing the simultaneous state jump of the RC and EP ends.

[0056] In the path switching method proposed by the present invention, the bitstream replacement is performed by pre-caching the state lock bitstreams sent by both ends, rather than using a bitstream generation unit to generate bitstreams, which can effectively avoid the compatibility problem that the bitstreams generated by the bitstream generation are inconsistent with the bitstreams sent by the RC and EP. Through the bitstream replacement, the time for both ends to receive the OS bitstream is reduced, ensuring that the RC and EP can simultaneously jump to the next state.

[0057] Please refer to Figure 9, embodiments of the present invention also propose a PCIe retimer path switching system. The retimer is set between the PCIe root complex and the endpoint. The retimer includes a general path and a low-latency path. The path switching system includes a low-latency switching control module and a switching switch. The low-latency switching control module mainly includes a ranging unit, a code stream caching unit, a sync header position detection unit, and a code stream replacement unit.

[0058] Specifically, the ranging unit is mainly used to detect the interval of the EIEOS code stream in the data stream sent by the root complex and the endpoint. The EIEOS code stream in the data stream appears once every 32 code streams. Then, the interval between the RC and EP receiving the EIEOS code stream is between 0 and 16. This interval is used for the number of code stream replacements in the follow-up.

[0059] The code stream caching unit is used to cache the status lock code stream transmitted between the root complex and the endpoint. The status lock code stream is used to maintain the current status of the root complex and the endpoint. Since the maximum interval between the EIEOS code streams at both ends is 16 code streams, therefore, in the embodiments of the present application, by caching 16 consecutive status lock code streams after the EIEOS code stream through the code stream caching unit, it can be ensured that the EIEOS interval can be completely covered. It should be noted that if there is a SKP code stream in the cached status lock code stream, the cache is reset, and the status lock code stream after the next EIEOS code stream is cached.

[0060] The sync header position detection unit is mainly used to determine the sync header position of each code stream in the data stream according to the PCIe sync header rule. This sync header position can be used to determine the position of code stream replacement.

[0061] The code stream replacement unit is mainly used to replace the subsequent ordered set code streams with the status lock code stream in the data stream received first by the retimer, starting from the ordered set code stream exiting electrical idle according to the sync header position. The ordered set code stream is used for the status jump of the root complex and the endpoint; among them, the length of the replaced code stream is the interval length of the detected ordered set code stream exiting electrical idle.

[0062] The switching switch is mainly used to control path switching according to the position of the EIEOS code stream where code stream replacement occurs.

[0063] In one embodiment, the PCIe retimer path switching system further includes a path switching state machine unit, which is used to control the units to work in sequence and finally control the switching switch to complete the switching from the general path to the low-latency path. Correspondingly, the switching switch is controlled by the path switching state machine unit to complete the switching from the general path to the low-latency path at the previous code stream of the ordered set code stream exiting electrical idle corresponding to the code stream replacement.

[0064] Next, take Figure 8Take this as an example to further illustrate the working process of the path switching system in this embodiment. RC sends data to EP, and at the same time, EP also sends data to RC. Assume that the retimer first receives the EIEOS in the data stream sent from RC to EP. If the path is directly switched, it means that the descrambling function at the EP side will be restored first and then a jump will occur. At this time, in order to avoid the jump at the EP side first, it is necessary to perform bitstream replacement through the retimer, that is, replace the n OS bitstreams after the EIEOS bitstream in this data stream with the status lock bitstream, where n is the interval between the EIEOS bitstreams detected at both ends. The data stream on the other side is not replaced.

[0065] For the switching timing of the switching switch for the two data flows, due to the bitstream replacement of the data stream sent from RC to EP, the switching needs to be performed at the previous bitstream of the EIEOS bitstream where the replacement occurs.

[0066] For the switching switch in the EP-to-RC direction, in order to avoid compatibility problems caused by receiving the OS bitstream first, it is necessary to delay the control of the switching switch on this side for switching, and the delay time is the shortest interval time between the EIEOS bitstreams in the data streams sent by the root complex and the endpoint. That is, after completing the switching of the switching switch in the RC-to-EP direction, wait for this shortest interval time and then complete the switching of the switching switch in the EP-to-RC direction, so that RC can directly restore the descrambling function after the path is switched, which is more suitable for the actual application scenario.

[0067] Through the PCIe retimer path switching system proposed by the present invention, when the PCIe retimer switches from a general path to a low-latency path, the PCIe system will not re-enter the recovery state due to the path switching.

[0068] For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations; the accompanying drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0069] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A PCIe retimer path switching method, characterized in that, The retimer includes a general path and a low-latency path, which are set between the root complex and the endpoint of the PCIe system. The path switching method includes: Pre-cache the status lock code stream transmitted between the root complex and the endpoint, where the status lock code stream is used to maintain the current status of the root complex and the endpoint; Detect the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; In the data stream received first by the retimer, starting from the position of the electrical idle exit ordered set code stream, replace the subsequent ordered set code streams with the status lock code stream. The ordered set code stream is used for the status jump of the root complex and the endpoint; among them, the length of the replaced code stream is the detected interval length of the electrical idle exit ordered set code stream; Complete the path switching before the position of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

2. The PCIe retimer path switching method according to claim 1, wherein The detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint includes: Detect the time of the electrical idle exit ordered set code stream in the data stream received by the retimer from the root complex and the endpoint; Determine the shortest interval of the electrical idle exit ordered set code stream received from both ends according to the receiving time.

3. The PCIe retimer path switching method according to claim 1 or 2, characterized in that The pre-caching the status lock code stream transmitted between the root complex and the endpoint includes: Starting from the position of the electrical idle exit ordered set code stream, cache the subsequent 16 consecutive status lock code streams.

4. The PCIe retimer path switching method according to claim 3, wherein When caching the status lock code stream, if the skipped ordered set code stream is included in the consecutive 16 status lock code streams, reset the cache and start caching the subsequent status lock code stream from the next electrical idle exit ordered set code stream.

5. The PCIe retimer path switching method according to claim 1, wherein The completing the path switching before the position of the electrical idle exit ordered set code stream corresponding to the code stream replacement specifically includes: Complete the switching from the general path to the low-latency path at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

6. The PCIe retimer path switching method according to claim 1, wherein It also includes detecting the sync header position of each code stream in the data stream and completing the corresponding code stream replacement according to the sync header position.

7. A PCIe retimer path switching system, characterized in that The retimer is set between the PCIe root complex and the endpoint. The retimer includes a general path and a low-latency path. The path switching system includes a low-latency switching control module and a switching switch. The low-latency switching control module includes: A ranging unit for detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; A code stream caching unit for caching the status lock code stream transmitted between the root complex and the endpoint, where the status lock code stream is used to maintain the current status of the root complex and the endpoint; A sync header position detection unit for detecting the sync header position of each code stream in the data stream according to; A code stream replacement unit for, in the data stream received first by the retimer, according to the sync header position, starting from the electrical idle exit ordered set code stream, replacing the subsequent ordered set code streams with the status lock code stream. The ordered set code stream is used for the status jump of the root complex and the endpoint; among them, the length of the replaced code stream is the detected interval length of the electrical idle exit ordered set code stream; A switching switch for controlling the path switching according to the position of the electrical idle exit ordered set code stream where the code stream replacement occurs.

8. The PCIe retimer path switching system according to claim 7, wherein In the bitstream buffer unit, starting from the bitstream position of the ordered set that exits from the electrical idle state, the subsequent 16 consecutive state lock bitstreams are buffered. If the consecutive 16 state lock bitstreams contain a skip ordered set bitstream, the buffer is reset, and the subsequent state lock bitstreams are buffered starting from the next bitstream of the ordered set that exits from the electrical idle state.

9. The PCIe retimer path switching system according to claim 7, wherein It further includes a path switching state machine unit, which is used to control the sequential operation of each unit and finally control the switching switch to complete the switching from the general path to the low-latency path.

10. The PCIe retimer path switching system according to claim 7, wherein The switching switch is controlled by the path switching state machine unit to complete the switching from the general path to the low-latency path at the previous bitstream corresponding to the bitstream replacement of the ordered set that exits from the electrical idle state.

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