High-level synthesis method and system

Abstract

The invention relates to a high-level synthesis method and system, and the method comprises the following steps: obtaining a high-level language source code, compiling the source code into an assembly code, and converting the assembly code into a binary instruction code through an assembler; an instruction template library is established, and binary instruction codes are converted into an integral logic circuit composed of different basic logic circuits; performing optimization iteration on the instruction template library in the conversion process; and evaluating the performance and resource occupation condition of the overall logic circuit, and performing iterative optimization on the combination mode of the basic logic circuit in the overall logic circuit based on an evaluation result. According to the method, the optimization iteration process is carried out on the logic abstraction layer, the parallelism and the resource utilization rate of the generated logic circuit structure can be ensured to be optimal, the resource consumption is reduced, meanwhile, compared with a traditional method, the process of manually adding a specific language field is reduced, the manual workload is reduced, and the efficiency is improved. And the applicability of the method is improved.

Description

Technical Field

[0001] The present invention belongs to the field of computer science and technology, and in particular relates to a high-level synthesis method and system. Background Art

[0002] High-level synthesis (HLS) is a process that automatically converts the logic structure described in a high-level language into a circuit model described in a low-level language. Its core is to convert the behavioral description of the algorithm layer into the structural description of the register transfer layer / RTL layer, thereby combining the advantages of easy software design with the advantages of higher hardware implementation efficiency.

[0003] In the existing technology, the high-level synthesis process includes compilation and conversion, operator scheduling, resource allocation, register allocation, wiring network generation and controller and control code generation. For the six stages in the existing process, domestic and foreign universities, research institutions and enterprises have developed high-level synthesis tools such as GAUT, ROCCC, CHiMPS, LegUP, Coder, etc. that use C / C++ language as the input language for high-level synthesis, high-level synthesis tools such as AccelDSP, MATLABSimulinkHDLCoder, etc. that mainly use MATLAB language, and high-level synthesis tools such as MaxelerMaxCompiler, etc. that mainly use JAVA language.

[0004] However, existing tools usually have many defects in high-level languages ​​and system architecture. For example, in terms of high-level languages, since high-level languages ​​such as C / C++ / JAVA lack a lot of hardware physical information, high-level synthesis often requires adding features and expansions. Adding specific fields requires the compiler to perform specific code optimizations, such as adding fields for variable width descriptions and feature indications. However, features such as system calls, dynamic memory allocation, dynamic pointer allocation, and recursive functions are limited by the fixed nature of hardware resources. Even after the language features are expanded, high-level synthesis still cannot support them. In terms of system architecture, due to the specific differences between hardware system architecture and software system development, all code must be recompiled each time a code block is used, and it cannot be saved. At the same time, a lot of parameter adjustments and source code modifications are required to achieve the ideal results after synthesis, and it is difficult to debug. Summary of the invention

[0005] The purpose of the present invention is to solve one of the above technical problems and provide a high-level synthesis method and system.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A high-level synthesis method includes the following steps:

[0008] Obtain high-level language source code, compile the source code into assembly code, and convert the assembly code into binary instruction code through an assembler;

[0009] Establishing an instruction template library based on a mapping relationship between binary instruction codes and corresponding basic logic circuits;

[0010] Based on the instruction template library, the binary instruction code is converted into an overall logic circuit composed of different basic logic circuits; during the conversion process, the instruction template library is optimized and iterated, and the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit is updated in the instruction template library;

[0011] Evaluate the performance and resource usage of the overall logic circuit, and iteratively optimize the combination of basic logic circuits in the overall logic circuit based on the evaluation results.

[0012] In some embodiments of the present invention, the method for establishing an instruction template library specifically includes the following steps:

[0013] Determine the mapping relationship between the binary instruction code and the corresponding basic logic circuit; store the mapping relationship in the instruction template library as the instruction template corresponding to the binary instruction code.

[0014] In some embodiments of the present invention, the instruction templates include control flow instruction templates, data flow operation instruction templates, function and IO access instruction templates, and emulation instruction templates.

[0015] In some embodiments of the present invention, the method for optimizing and iterating the instruction template library specifically includes the following steps:

[0016] Converting an instruction sequence composed of different binary instruction codes into a control flow graph representing a control relationship between the different binary instruction codes;

[0017] Constructing instruction modules composed of different binary instruction codes based on control flow graph;

[0018] Based on the instruction template library, analyze the parallel relationship and resource usage within each instruction module and between different instruction modules;

[0019] Based on the analysis results, the control flow graph is iteratively optimized to generate an optimized instruction module, and the mapping relationship between the optimized instruction module and the overall logic circuit is updated in the instruction template library.

[0020] In some embodiments of the present invention, the method for optimizing and iterating the instruction template library further comprises the following steps:

[0021] Construct an evaluation function. When the parallel relationship and resource usage within each instruction module and between different instruction modules meet the requirements of the evaluation function, stop the iteration, or,

[0022] A predetermined number of iterations is set, and when the number of optimization iterations for the instruction template library reaches the predetermined number of iterations, the iteration is stopped.

[0023] In some embodiments of the present invention, the method for iteratively optimizing the combination of basic logic circuits in the overall logic circuit specifically includes:

[0024] Evaluate overall logic circuit resources, register cycles, data associations, and dependencies;

[0025] Based on the evaluation results, the minimum number of required registers and computing resources is determined, and then the resources are optimally restructured.

[0026] In some embodiments of the present invention, the method for iteratively optimizing the combination of basic logic circuits in the overall logic circuit further includes:

[0027] Based on the data flow graph, the parallel and serial structures of the overall logic circuit are extracted, and parallel and serial logic resource units are constructed. The serial resources are controlled by constructing multiplexers, and the parallel resources are processed by pipeline balance.

[0028] Some embodiments of the present invention further provide a high-level integrated system, including:

[0029] A compilation module is used to obtain high-level language source code, compile the source code into assembly code, and convert the assembly code into binary instruction code through an assembler;

[0030] Instruction template library, used to store the mapping relationship between binary instruction codes and logical circuits;

[0031] A logic analysis module is used to convert binary instruction codes into an overall logic circuit composed of different basic logic circuits based on an instruction template library; during the conversion process, the instruction template library is optimized and iterated to obtain the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit, and the mapping relationship is updated to the instruction template library;

[0032] The optimization analysis module is used to evaluate the performance and resource usage of the overall logic circuit, iteratively optimize the combination of basic logic circuits in the overall logic circuit based on the evaluation results, and output the optimized overall logic circuit.

[0033] Some embodiments of the present invention further provide an electronic device, including:

[0034] at least one processor;

[0035] at least one memory for storing at least one program;

[0036] When at least one program is executed by at least one processor, the at least one processor implements the above high-level synthesis method.

[0037] Some embodiments of the present invention further provide a storage medium storing a program executable by a processor. The program executable by the processor is used to implement the above-mentioned high-level synthesis method when executed by the processor.

[0038] The beneficial effects of the present invention are:

[0039] 1. The high-level synthesis method provided by the present invention first reduces the dimension of the high-level language code into binary instruction code, and converts the binary instruction into an overall logic circuit structure in combination with the instruction template library and the IP core library, and then optimizes and iterates the overall logic circuit structure, and reduces the optimization iterative process to the logic abstraction layer, which can ensure that the parallelism and resource utilization of the generated logic circuit structure are optimal and reduce resource consumption.

[0040] 2. Compared with traditional high-level synthesis solutions, the high-level synthesis method provided by the present invention implements compilation, scheduling, allocation and binding by adding specific language fields in the absence of a large amount of hardware information, reduces the process of manually adding specific language fields, optimizes the generated logic circuit structure through optimization algorithms, reduces manual workload, and improves the applicability of the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A flowchart of a high-level synthesis method;

[0043] Figure 2 Flowchart of the high-level language compilation process;

[0044] Figure 3 It is a flowchart of the logic analysis process;

[0045] Figure 4 Flowchart of the iterative process for optimizing the instruction template library;

[0046] Figure 5 Flowchart of the optimization analysis process. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0048] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] In order to better explain the solution of the present invention, the existing high-level synthesis method is first described.

[0050] High-level synthesis can convert software described in high-level languages ​​such as C into the synthesizable Verilog hardware description language, that is, convert the behavioral description of the algorithm layer into the structural description of the register transfer layer / RTL layer, thereby combining the advantages of easy software design and more efficient hardware implementation.

[0051] In the prior art, the high-level synthesis process mainly consists of six parts: compilation and conversion, operator scheduling, resource allocation, register allocation, connection network generation, and controller and control code generation. Among them, compilation and conversion converts the description language of the algorithm behavior level into an intermediate language format that is conducive to high-level synthesis, and then generates a data control flow graph that represents the relationship between system data, operations and controls; operator scheduling schedules the operators that represent the system's control of input data to each control step under the condition of satisfying constraints, and balances the required resources and the number of control steps through the optimal scheduling scheme / algorithm; resource allocation specifies the operation unit for each operator, that is, the operation unit is assigned to some non-conflicting operators of the same type, using the least resource cost; register allocation specifies the register that stores each data that needs to be saved; connection network generation is based on resource allocation and register allocation schemes, and connects input signals, output signals, registers and operation units through multiplexers; controller and control code generation realizes the control of the execution sequence of system operations based on external input and data channel feedback signals.

[0052] At present, universities, research institutes and enterprises at home and abroad have developed high-level synthesis tools using C / C++ language. For example, GAUT, which is specially used for DSP application design, can synthesize C programs into structures including computing units, storage units and transmission units, and meet special constraints such as parallel initial interval; ROCCC can convert C programs into hardware accelerators, and can accelerate key cores that repeatedly calculate a string of data, but it cannot support common functions such as floating point, shift, and loop in C language; CHiMPS can synthesize C programs into multi-cache structures to make full use of small RAM blocks on FPGA; LegUP can convert commonly used complex C programs into hardware circuits, supporting common C language functions such as function calls, structures, loops, logical operations and arithmetic operations, but does not support dynamic storage and recursion. In addition to high-level synthesis tools using C / C++ language as input language, there are also high-level synthesis tools such as AccelDSP, MATLABSimulinkHDLCoder based on MATLAB language, and MaxelerMaxCompiler based on JAVA language.

[0053] The above-mentioned high-level synthesis tools can implement high-level synthesis functions for different languages, but they still have many defects in the high-level language and system architecture levels. For example, in terms of high-level languages, since high-level languages ​​such as C / C++ / JAVA lack a lot of hardware physical information, high-level synthesis often requires adding features and expansions to them. Adding specific fields requires the compiler to perform specific code optimizations, such as adding fields for variable bit width descriptions and feature indications. However, features such as system calls, dynamic memory allocation, dynamic pointer allocation, and recursive functions are limited by the fixed nature of hardware resources. Even after the language features are expanded, high-level synthesis still cannot support them. In terms of system architecture, due to the specific differences between hardware system architecture and software system development, all code must be recompiled each time a code block is used, and it cannot be saved. At the same time, a lot of parameter adjustments and source code modifications are required to achieve the ideal results after synthesis, and it is difficult to debug.

[0054] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0055] The technical solution of the present invention is described in detail below in conjunction with specific embodiments and the accompanying drawings.

[0056] As attached Figure 1 -Attached Figure 5 As shown, in an illustrative embodiment of a high-level synthesis method and system of the present invention, the high-level synthesis method includes the following steps.

[0057] S1: High-level language compilation: Obtain source code of high-level languages ​​such as C, C++, and JAVA, and compile the high-level language source code into low-level assembly code ASM through a compiler of the high-level language and its related embedded hardware architecture, and then convert the assembly code into binary instruction code I representing functions and logical relationships through a related assembler. In this embodiment, a binary instruction code data set is constructed. The high-level language compilation process in step S1 is as follows: Figure 2 shown.

[0058] S2: Logical analysis: Based on the mapping relationship between the binary instruction code I and its corresponding basic logic circuit u in the IP core library, an instruction template library is established to characterize the relationship between binary instructions and hardware information.

[0059] Based on the mapping relationship in the instruction template library, the binary instruction code I in the data set is converted into an overall logic circuit U composed of different basic logic circuits u. It should be noted that some of the converted binary instruction codes can be associated / converted using only a single basic logic circuit u in the IP core library, while other binary instructions require a combination of multiple basic logic circuits u in the IP core library to achieve complete functional association / conversion.

[0060] During the conversion process, the instruction template library is optimized and iterated, and the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit is updated in the instruction template library to improve the excellence of the conversion result and the speed of subsequent processing.

[0061] Among them, Figure 3 As shown, the IP core library contains resource modules of basic logic circuits u such as adders, subtractors, and multipliers.

[0062] In some embodiments of the present invention, the method for establishing an instruction template library specifically includes the following steps.

[0063] Determine the mapping relationship between the binary instruction code I in the data set and its corresponding basic logic circuit u in the IP core library. Store the mapping relationship in the instruction template library as the instruction template of the function corresponding to the binary instruction code.

[0064] In some embodiments of the present invention, the instruction template is determined based on the function of the basic logic circuit corresponding to the binary instruction code, and the type of the instruction template can be continuously iterated and updated during the iteration of the instruction template library. In this embodiment, the initial version of the instruction template library constructed in step S2 includes at least four types of instruction templates: control flow instruction templates, data flow operation instruction templates, function and IO access instruction templates, and emulation instruction templates.

[0065] Among them, the control flow instruction template is an instruction that directly affects the controller's finite state machine in the constructed circuit. For example, relative jump instruction RJMP, subroutine call instruction CALL, conditional jump instruction BREQ, etc.

[0066] The data flow operation instruction template is a data operation instruction between registers. For example, addition instruction ADD, subtraction instruction SUB, increment instruction INC, AND instruction AND, OR instruction OR, arithmetic right shift ASR, data transfer MOV, etc.

[0067] The function and IO access instruction template is an instruction that needs to call IO resources. For example, input instruction IN, output instruction OUT, etc.

[0068] The memory emulation instruction template is an instruction related to memory read and write. For example, load instruction LD, store instruction ST, etc.

[0069] In some embodiments of the present invention, the method for optimizing and iterating the instruction template library in step S2 specifically includes the following steps.

[0070] Convert the instruction sequence Ip composed of different binary instruction codes I into a control flow graph CFG representing the control relationship between different instruction operations.

[0071] Construct an instruction module Ib composed of different binary instruction codes I based on the control flow graph.

[0072] Based on the instruction template library, analyze the parallel relationship and resource occupancy situation inside each instruction module Ib and between different instruction modules Ib.

[0073] Based on the analysis results, iteratively optimize the control flow graph, generate the optimized instruction module, and update the mapping relationship between the optimized instruction module and the overall logic circuit U to the instruction template library.

[0074] In some embodiments of the present invention, the method for optimizing and iterating the instruction template library further includes the following steps:

[0075] Build an evaluation function in Matlab software. When the parallel relationship and resource occupancy situation inside each instruction module and between different instruction modules meet the requirements of the evaluation function, stop the iteration, or

[0076] Set a predetermined number of iterations. When the number of times of optimizing and iterating the instruction template library reaches the predetermined number of iterations, stop the iteration.

[0077] The following combines Figure 4 Specifically illustrate the iteration process of the instruction template library in this embodiment:

[0078] In this embodiment, since the binary instruction codes converted from the high-level language source code are I1 to In, and I1 to In constitute an instruction sequence Ip, it is impossible to iterate the instruction sequence Ip composed of all binary instruction codes. Therefore, it is necessary to first convert the instruction sequence Ip into a control flow graph CFG that represents the control relationship between different instruction operations.

[0079] After the control flow graph is generated, the instructions in Ip are grouped based on the control flow graph. For example, instructions I1, I2, and I3 form a group of instruction modules Ib1, and instructions I4, I5, and I6 form a group of instruction modules Ib2. The original instruction sequence Ip is converted into an instruction module Ib composed of Ib1, Ib2, ..., Ibn.

[0080] After obtaining the instruction module Ib, the logic circuits ub1, ub2, ..., ubn corresponding to the instruction modules Ib1, Ib2, ..., Ibn are generated based on the instruction template library. At this time, the generated logic circuit ub can be analyzed / evaluated for the resources and parallel relationships within and between ubs. For example, the resource evaluation is the number of basic logic circuits such as adders and registers used in the ub of the panel library. The parallel relationship evaluation is to evaluate whether a pipeline structure is formed and whether there is data dependency or association. Finally, the optimal solution with less resource occupancy and more parallel structures / less time consumption when running at the same time is determined.

[0081] Then the mapping relationship between Ib1, Ib2, ..., Ibn and ub1, ub2, ..., ubn is added to the instruction template library. At this time, the mapping relationship in the instruction template library includes not only the one / multiple basic logic circuits u corresponding to the original binary instruction I, but also the mapping relationship between the instruction module Ibn composed of multiple instructions and the multiple logic circuit sets ubn. Then, according to the updated and iterative instruction template library, the division and conversion process from Ip to Ib can be changed, and the Ib with better parallel relationship and resource occupancy can be retained, and different combinations of other binary instruction codes I are made to generate new Ib, and a new round of optimization iteration is carried out.

[0082] S3: Optimization analysis: Use Vivado software to evaluate the performance and resource usage of the overall logic circuit, and iteratively optimize the combination of basic logic circuits u in the overall logic circuit U based on the evaluation results to obtain the optimal logic circuit structure. The optimization analysis process in step S3 is as follows: Figure 5 shown.

[0083] In some embodiments of the present invention, the method for iteratively optimizing the combination of basic logic circuits u in the overall logic circuit U specifically includes resource optimization.

[0084] Evaluate the resources, register cycles, data associations, and dependencies of the overall logic circuit U.

[0085] Based on the evaluation results, the minimum number of registers and computing resources required for the overall logic circuit U is determined, and then the resources are optimally reconstructed.

[0086] In some embodiments of the present invention, the method of iteratively optimizing the combination of basic logic circuits in the overall logic circuit further includes performance optimization.

[0087] Based on the data flow graph, the parallel and serial structures of the overall logic circuit are extracted, and parallel and serial logic resource units are constructed. The serial resources are controlled by constructing multiplexers, and the parallel resources are processed by pipeline balance.

[0088] Some embodiments of the present invention further provide a high-level integrated system, including:

[0089] A compilation module is used to obtain high-level language source code, compile the source code into assembly code, and convert the assembly code into binary instruction code through an assembler;

[0090] Instruction template library, used to store the mapping relationship between binary instruction codes and logical circuits;

[0091] A logic analysis module is used to convert binary instruction codes into an overall logic circuit composed of different basic logic circuits based on an instruction template library; during the conversion process, the instruction template library is optimized and iterated to obtain the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit, and the mapping relationship is updated to the instruction template library;

[0092] The optimization analysis module is used to evaluate the performance and resource usage of the overall logic circuit, iteratively optimize the combination of basic logic circuits in the overall logic circuit based on the evaluation results, and output the optimized overall logic circuit.

[0093] Some embodiments of the present invention further provide an electronic device, including:

[0094] at least one processor;

[0095] at least one memory for storing at least one program;

[0096] When at least one program is executed by at least one processor, the at least one processor implements the above high-level synthesis method.

[0097] Some embodiments of the present invention further provide a storage medium storing a program executable by a processor. The program executable by the processor is used to implement the above-mentioned high-level synthesis method when executed by the processor.

[0098] Finally, it should be noted that: the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0099] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A high-level synthesis method, characterized in that: The following steps are involved: Obtaining high-level language source code, compiling the source code into assembly code, and converting the assembly code into binary instruction code through an assembler; Establishing an instruction template library based on the mapping relationship between the binary instruction code and the corresponding basic logic circuit; Based on the instruction template library, the binary instruction code is converted into an overall logic circuit composed of different basic logic circuits; during the conversion process, the instruction template library is optimized and iterated, and the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit is updated in the instruction template library; The performance and resource usage of the overall logic circuit are evaluated, and based on the evaluation result, the combination of basic logic circuits in the overall logic circuit is iteratively optimized.

2. The high-level synthesis method according to claim 1, characterized in that: The method for establishing an instruction template library specifically includes the following steps: Determine a mapping relationship between a binary instruction code and a corresponding basic logic circuit; and store the mapping relationship in an instruction template library as an instruction template corresponding to a function of the binary instruction code.

3. The high-level synthesis method according to claim 1, characterized in that: The instruction templates include control flow instruction templates, data flow operation instruction templates, function and IO access instruction templates, and emulation instruction templates.

4. The high-level synthesis method according to any one of claims 1 to 3, characterized in that: The method for optimizing and iterating the instruction template library specifically comprises the following steps: Converting an instruction sequence composed of different binary instruction codes into a control flow graph representing a control relationship between the different binary instruction codes; Constructing an instruction module composed of different binary instruction codes based on the control flow graph; Based on the instruction template library, analyzing the parallel relationship and resource occupancy within each instruction module and between different instruction modules; Based on the analysis results, the control flow graph is iteratively optimized to generate an optimized instruction module, and the mapping relationship between the optimized instruction module and the overall logic circuit is updated in the instruction template library.

5. The high-level synthesis method according to claim 4, characterized in that: The method for optimizing and iterating the instruction template library further comprises the following steps: Construct an evaluation function, and stop iterating when the parallel relationship and resource occupancy within each instruction module and between different instruction modules meet the requirements of the evaluation function, or, A predetermined number of iterations is set, and when the number of optimization iterations for the instruction template library reaches the predetermined number of iterations, the iteration is stopped.

6. The high-level synthesis method according to claim 1, characterized in that: The method for iteratively optimizing the combination of basic logic circuits in the overall logic circuit specifically includes: evaluating resources, register cycles, data associations, and dependencies of the overall logic circuit; Based on the evaluation results, the minimum number of required registers and computing resources is determined, and then the optimal reconstruction of resources is performed.

7. The high-level synthesis method according to claim 6, characterized in that: The method for iteratively optimizing the combination of basic logic circuits in the overall logic circuit further includes: Based on the data flow graph, the parallel and serial structures of the overall logic circuit are extracted, parallel and serial logic resource units are constructed, the serial resources are controlled by constructing a multiplexer, and the parallel resources are processed by pipeline balance.

8. A high-level integrated system, characterized in that include: A compiling module, used for obtaining a high-level language source code, compiling the source code into an assembly code, and converting the assembly code into a binary instruction code through an assembler; Instruction template library, used to store the mapping relationship between binary instruction codes and logical circuits; A logic analysis module is used to convert the binary instruction code into an overall logic circuit composed of different basic logic circuits based on the instruction template library; during the conversion process, the instruction template library is optimized and iterated to obtain the mapping relationship between the code modules composed of different binary instruction codes and the overall logic circuit, and update it to the instruction template library; The optimization analysis module is used to evaluate the performance and resource usage of the overall logic circuit, iteratively optimize the combination of basic logic circuits in the overall logic circuit based on the evaluation result, and output the optimized overall logic circuit.

9. An electronic device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the high-level synthesis method according to any one of claims 1 to 8.

10. A storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to implement the high-level synthesis method according to any one of claims 1 to 8 when executed by the processor.

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