Neural networks for generating objects in different images

Abstract

The invention discloses a neural network for generating objects in different images. An apparatus, processor, computing system, device, non-transitory computer medium and / or method of generating a plurality of related images using a neural network. In at least one embodiment, a processor includes circuitry to generate several images using one or more neural networks, where each image includes a same object (e.g., a same subject) and a different background. For example, a processor includes one or more circuitry to use one or more neural networks to generate two or more different images (e.g., different backgrounds, different images, or different images,) based at least in part on one or more indications (e.g., textual cues) of one or more users. One or more indications (e.g., one or more objects (e.g., animals, vehicles, humans) within two or more different images (e.g., weather, season, environment, etc.), one or more indications indicative of content other than the one or more objects of at least one of the two or more different images (e.g., objects and / or backgrounds of each image in the text, e.g., adjectives and nouns).

Description

Technical Field

[0001] At least one embodiment relates to a processor, computing system, device, non-transitory computer medium, and / or method for generating multiple related images (e.g., images including the same subject in different poses) using a neural network. In at least one embodiment, a processor includes circuitry for generating several images using one or more neural networks, where each image includes the same object (e.g., the same subject) in a different background. Background Art

[0002] Training and using neural networks to generate images based on text input can be challenging. For example, generating training data (e.g., labeled images) that can be used to train a neural network to recognize objects (e.g., animals) in images can be challenging. Training can also be challenging because it uses computing resources, such as processing power and memory. If the neural networks are not adequately trained and / or there is not enough processing power to train them, the neural networks may not produce accurate outputs. Using neural networks to generate images is also challenging because images can be complex (e.g., thousands of pixels, with objects in the image having specific orientations and positions relative to other objects). Therefore, there is a need for improved neural networks that generate images and methods for improving the training of these neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A computing environment including a neural network according to at least one embodiment is shown;

[0004] Figure 2 A block diagram is shown for training a neural network to generate different images including the same object in accordance with at least one embodiment;

[0005] Figure 3 Another block diagram for training a neural network to generate different images including the same object is shown in accordance with at least one embodiment;

[0006] Figure 4 Another block diagram for training a neural network to generate images of the same object is shown in accordance with at least one embodiment;

[0007] Figure 5 Another block diagram for training a neural network to generate images of the same object is shown in accordance with at least one embodiment;

[0008] Figure 6 An example neural network generating an image including the same subject in different backgrounds in accordance with at least one embodiment is shown;

[0009] Figure 7is a flow chart of a process for training a neural network to generate objects in different images according to at least one embodiment;

[0010] Figure 8 is another process flow diagram for training a neural network to generate objects in different images according to at least one embodiment;

[0011] Figure 9 is a flow chart illustrating an example of an inference process for generating one or more objects in two or more different images using one or more neural networks;

[0012] Figure 10 An example including a processor and modules according to at least one embodiment is shown;

[0013] Figure 11 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0014] Figure 12A illustrates logic according to at least one embodiment;

[0015] Figure 12B illustrates logic according to at least one embodiment;

[0016] Figure 13 illustrates the training and deployment of a neural network according to at least one embodiment;

[0017] Figure 14 An example data center system is shown in accordance with at least one embodiment;

[0018] Figure 15A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 15B According to at least one embodiment, Figure 15A Examples of camera positions and fields of view for autonomous vehicles;

[0020] Figure 15C According to at least one embodiment Figure 15A A block diagram of an example system architecture for an autonomous vehicle;

[0021] Figure 15D is a diagram illustrating a method for one or more cloud-based servers and Figure 15A A diagram of a system for communicating between autonomous vehicles;

[0022] Figure 16 is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 17 is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 18 A computer system according to at least one embodiment is shown;

[0025] Figure 19 A computer system according to at least one embodiment is shown;

[0026] Figure 20A A computer system according to at least one embodiment is shown;

[0027] Figure 20B A computer system according to at least one embodiment is shown;

[0028] Figure 20C A computer system according to at least one embodiment is shown;

[0029] Figure 20D A computer system according to at least one embodiment is shown;

[0030] Figure 20E and Figure 20F illustrates a shared programming model in accordance with at least one embodiment;

[0031] Figure 21 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0032] Figure 22A and Figure 22B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0033] Figure 23A and Figure 23B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0034] Figure 24 A computer system according to at least one embodiment is shown;

[0035] Figure 25A A parallel processor according to at least one embodiment is shown;

[0036] Figure 25B shows a partition unit according to at least one embodiment;

[0037] Figure 25C illustrates a processing cluster according to at least one embodiment;

[0038] Figure 25D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0039] Figure 26 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0040] Figure 27 A graphics processor according to at least one embodiment is shown;

[0041] Figure 28 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 29 A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 30 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0044] Figure 31 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 32 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 33 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0047] Figure 34 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 35 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 36A and Figure 36B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0050] Figure 37 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0051] Figure 38 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0052] Figure 39 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0053] Figure 40 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0054] Figure 41 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0055] Figure 42 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0056] Figure 43 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0057] Figure 44A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0058] Figure 44B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0059] Figure 45A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment;

[0060] Figure 45B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment; and

[0061] Figure 46 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0062] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the concepts of the present invention may be practiced without one or more of these specific details.

[0063] In at least one embodiment, a processor uses a neural network to receive different text prompts and generate images of the same subject (e.g., the same dog) in different backgrounds corresponding to the different text prompts. For example, the neural network can generate a first image of a fox in the snow and a second image of the same fox in the forest in response to receiving a text prompt that states to generate images of a "fox in the snow" and a "fox in the forest." In at least one embodiment, these images are generated simultaneously, for example, in response to a user inputting different text prompts into a user interface. In at least one embodiment, the neural network includes a diffusion neural network, a diffusion model, and / or other software that uses a diffusion neural network to generate images.

[0064] In at least one embodiment, software executed by one or more processors trains a neural network using pairs of images (including the same object in different settings) with corresponding textual cues (e.g., an image of a dog in a forest and an image of the same dog in snow, with corresponding textual cues for different settings and / or backgrounds). In at least one embodiment, the encoding portion of the neural network identifies features corresponding to an object (e.g., the same subject) in both images and is trained to identify the same features corresponding to the object in both images. In at least one embodiment, the software executed by one or more processors causes the decoding portion to be trained to associate features with corresponding keywords from the textual cues (e.g., by associating features of a dog with the word "dog" and features of snow with "snow") by causing the decoding portion to decode the features identified by the decoder portion. In at least one embodiment, the training causes the neural network to associate specific features with one or more words indicating an object, such that when the one or more words are used in different textual cues, the neural network generates different images depicting the same object (e.g., the same subject).

[0065] In at least one embodiment, a processor includes circuitry for generating, using one or more neural networks, two or more images depicting the same subject (e.g., the same dog, the same cat) in different settings based, at least in part, on two or more different input text prompts. In at least one embodiment, the processor includes circuitry for generating, using one or more neural networks, one or more objects in two or more different images based, at least in part, on one or more instructions from one or more users, the instructions indicating content other than the one or more objects in at least one of the two or more different images. In at least one embodiment, the neural network generates images of the same object (e.g., a cat, dog, bird, helicopter) against different backgrounds, wherein the same object is in a different pose, state, or position in each of the images. For example, in response to receiving a text prompt to generate an image of a dog running in the snow, walking in the rain, and swimming underwater, the neural network generates images of the same dog running in the snow, walking in the rain, and swimming underwater.

[0066] In at least one embodiment, specific layers of the neural network are trained to recognize which features of a subject are common across different images and how different textual cues correspond to image features. In at least one embodiment, the neural network includes a layer that receives training images of the same subject (e.g., images of the same dog against different backgrounds) and learns to recognize which features of the subject should be assigned more weight because they are present in the (same) subject in all images. In at least one embodiment, a self-attention layer receives a feature map (e.g., a data structure comprising image features identified in a convolution of an input image) and generates a new feature map comprising weights assigned to features common to the (same) subject in the image (e.g., assigning more weight to common features and no weight or less weight to other features). For example, in an image of a cat, the self-attention layer generates a feature map with identified features including higher weights for features that identify it as a cat, such as eyes, ears, or fur texture.

[0067] In at least one embodiment, the generated feature map (which includes the identified features and weight values) is then input into another layer that identifies image features corresponding to the text prompt. In at least one embodiment, the layer receives a feature map (for each input image) and a text prompt corresponding to each feature map (e.g., a feature map corresponding to a fox in the snow and a corresponding text prompt "fox in the snow", a feature map corresponding to a fox in the forest and a corresponding text prompt "fox in the forest"), and the layer then outputs a data structure including representations of features of the feature map corresponding to features of the text prompt. In at least one embodiment, the layer includes a cross-attention layer that receives as input the feature map and the text prompt from the self-attention layer, and then outputs a data structure including representations of the image features and corresponding features representing the text (e.g., image features of green, leaves, and trees are associated with a representation of a forest in the data structure). In at least one embodiment, after the data structure is generated, a decoder can be used to decode the features in the data structure to generate an image (in response to receiving the text prompt).

[0068] Figure 1 A computing environment 100 including a neural network according to at least one embodiment is shown. In at least one embodiment, the computing environment 100 includes one or more processors, one or more circuits, one or more data centers, or other computing hardware (e.g., graphics processing units) for executing software, neural networks, and other modules (e.g., Figure 1In at least one embodiment, computing environment 100 includes a neural network 102, which may be implemented by one or more processors (e.g., a graphics processing unit (GPU), a data processing unit (DPU), a central processing unit (CPU), e.g., Figures 20A-40 In at least one embodiment, the neural network 102 receives one or more inputs 101. In at least one embodiment, the input 101 can be text, an image, a video, or a combination thereof. In at least one embodiment, the input 101 can be provided by a user (e.g., via a user interface), a server, a different neural network, or other text input source (e.g., received from a large language model, a user interface). In at least one embodiment, the input 101 indicates the content of at least two or more different images (e.g., background, setting). In at least one embodiment, the input 101 includes one or more instructions from one or more users indicating the content of at least one of the two or more different images other than one or more objects. For example, the input 101 can include words other than the subject, such as forest, background, snow, weather, and season. In at least one embodiment, the neural network 102 uses the words in the sentence as the content to generate features of the background.

[0069] In at least one embodiment, the neural network 102 includes convolutional layers 103, self-attention layers 104, and cross-attention layers 105. In at least one embodiment, the neural network 102 includes a diffusion model that is a pre-trained model and is learned to reverse the diffusion process. In at least one embodiment, the diffusion model receives random noise samples (e.g., drawn from a Gaussian distribution) and applies a reverse diffusion step to progressively denoise them (e.g., in each layer of the diffusion neural network). In at least one embodiment, the diffusion model is conditional and utilizes additional conditional information such as text descriptions or class labels to guide generation toward a desired outcome. In at least one embodiment, the diffusion model includes learned parameters for predicting and subtracting noise at each step. In at least one embodiment, the diffusion model includes a sampling algorithm (e.g., ancestral sampling) that guides, influences, or otherwise modifies the denoising process. In at least one embodiment, the neural network 102 can provide output to a post-processing step that improves, modifies, or otherwise adjusts the output. In at least one embodiment, the processor uses the neural network 102 to determine, recognize, or otherwise infer relationships described in the input 101, which are imparted to one or more outputs 106a-106n. For example, the input 101 may include sentences describing subjects (e.g., a fox in the snow, a fox in the rain, a fox running in the grass), where the sentences include words with relationships, and the output images may depict these relationships (e.g., the same fox in various contexts, and the same fox performing related actions based on the text input).

[0070] In at least one embodiment, input 101 may include text prompts, such as "generate an image of a fox in the snow" and "generate an image of a fox in the forest," and neural network 102 receives these inputs 101 and generates outputs 106a-106n, where outputs 106a-106n include two or more images, each of which has an image of a fox, but each of the two or more output images has the same fox in a snowy background and in a forest background. In at least one embodiment, the number of outputs 106a-106n is not limited to four and includes a closed set of outputs corresponding to the number of inputs (e.g., 4, 8, 10, 1000).

[0071] In at least one embodiment, the self-attention layer 104 is, includes, or otherwise corresponds to a self-attention layer. In at least one embodiment, a layer of a neural network may be referred to as a portion of a neural network. In at least one embodiment, a layer of a neural network includes individual units referred to as neurons or weights. In at least one embodiment, the processor executes, trains, or uses a self-attention layer 104 that compares all input sequence members to each other and modifies the corresponding output sequences. For example, the self-attention layer may distinguishably perform a key-value search on the input sequence for each input and add the results to the output sequence, causing the neural network to focus on important features of the data modality (e.g., important related portions of text, important related portions of images, such as the same subject). In at least one embodiment, the self-attention layer 104 receives features or feature maps from a residual block.

[0072] In at least one embodiment, the cross-attention layer 105 includes identifying how those features in one data type or modality are related to features in another data type or modality. In at least one embodiment, the cross-attention layer enables the model to weight different parts of the input data relative to (in relation to) another sequence. In at least one embodiment, the cross-attention layer 105 includes a set of query vectors from one sequence and a set of key and value vectors from another sequence, which the processor uses to calculate an attention score using a compatibility function between each query and all keys. In at least one embodiment, the score determines the weighting of the values, which are then aggregated to form the output of the cross-attention layer.

[0073] Figure 2 A block diagram is shown for training a neural network to generate different images of the same object in accordance with at least one embodiment. Figure 2 The training process 200 includes input 201, neural network 202, text description 204, neural network 205, image set 206, and post-processing 208. In at least one embodiment, the training process 200 performed by one or more processors trains Figure 1 In at least one embodiment, Figure 2A training process 200 is included, which can be stored in software and executed by one or more processors to generate training data (e.g., text and image pairs with or without labels). For example, the training process executed by the one or more processors can be used to generate training images of blue helicopters, where each image is paired with a different text prompt (e.g., one image is paired with "blue helicopter flying near grass at sunset", another image is paired with "blue helicopter landing on grass", another image is paired with "blue helicopter landing on beach", and another image is paired with "blue helicopter flying over ocean", where each image includes a blue helicopter and a background corresponding to the action and adjective in each text prompt). In at least one embodiment, the input 201 can include text, images, or a combination of text and images (e.g., Figure 1 Input 101 in ).

[0074] In at least one embodiment, the subject of input 201 is the object of two or more outputs 209 (e.g., the text includes a fox, and each image includes the fox). In at least one embodiment, neural network 202 may include a diffusion neural network, a transformer neural network, a large language model, or other language processing model. In at least one embodiment, to generate a text prompt having the subject of input 201, the neural network is provided with a list of subjects. In at least one embodiment, the list of subjects forms the subject set {x n ,x n+1 ,x n+2 ,…N}, where x n 、x n+1 、x n+2 , N are different subjects in the subject list. In at least one embodiment, the input 201 text includes "dog, cat, fox, mouse", and the neural network generates sentences {dog running in the rain, cat sleeping on the coach, fox jumping in the forest, mouse hiding under the rock} for each subject in response to receiving these inputs. In at least one embodiment, the neural network 202 generates many (e.g., 10, 100) sentences for each subject. In at least one embodiment, the neural network 202 generates one or more text descriptions 204 (e.g., sentences) of the scene. In at least one embodiment, the neural network 202 generates one or more text descriptions 204 of one or more scenes, thereby creating a description set {y m ,y m+1 ,y m+2...M}. For example, a scene can include one or more backgrounds, scenery, settings, environments, surroundings, one or more contexts, or other descriptions of non-foreground portions of an image. In at least one embodiment, input 201 includes one or more indications from one or more users indicating content other than one or more objects in at least one of the two or more different images. For example, input 201 can include words other than subjects (e.g., nouns such as fox, helicopter), such as forest, background, snow, weather, and season.

[0075] In at least one embodiment, the neural network 205 generates images for the image set 206 and connects the subjects from each text description dataset to the images to form text-image pairs (e.g., to generate training data). In at least one embodiment, the neural network 205 receives outputs such as text descriptions 204 and generates the image set 206. In at least one embodiment, the neural network 205 includes a stable diffusion model (e.g., SDXL), a generative artificial intelligence model, a diffusion neural network, or a text-to-image generation neural network model. In at least one embodiment, the neural network 205 receives a subject text description dataset as input and generates a collage or image set 206 corresponding to one or more subjects of the subject description dataset (e.g., generating four images corresponding to the text input based on an input prompt). In at least one embodiment, for example, the second neural network 206 parses the subject set {x n ,x n+1 ,x n+2 ,…N} for each subject, and for the image set {z l ,z l+1 ,z l+2 ...L} generates a collage or image set 206. In at least one embodiment, each image constituting image set 206 is an image of the subject of input 201 in a different pose. In at least one embodiment, image set 206 includes one or more images of each subject in different poses, and may also include subjects in different poses on one or more different backgrounds. For example, for the subject "fox" in the subject text description dataset, neural network 205 generates foxes in different poses and different backgrounds, thereby constituting image set 203 of subject "fox" {z l ,z l+1 ,z l+2 In at least one embodiment, for the subject “dog” in the subject text description dataset, the neural network 205 generates dogs with different poses and different backgrounds, thereby forming an image set 206 of the subject “dog” {z l ,z l+1 ,z l+2In at least one embodiment, this operation is repeated for each subject in the subject set and each text description in the description set.

[0076] In at least one embodiment, the training process 200 includes one or more post-processing 208 of the output of the neural network 205 or the image-subject pairs. The post-processing 208 is performed by any of a neural network model, machine learning, artificial intelligence, software, or hardware. The post-processing 208 includes, for each image of the image-subject pair, processing the image by object detection and segmentation to separate the subject (e.g., fox) of each image in the image set (e.g., image set {z l ,z l+1 ,z l+2 ...L}) and extract a foreground mask. In at least one embodiment, the extracted foreground mask is a representation of the pose of each subject separated from any background imagery that may be present in the image set 206. In at least one embodiment, post-processing 208 of the collage of image-subject pairs or the set of extracted foreground masks includes separating the collage of images 206 into individual outputs 209.

[0077] In at least one embodiment, post-processing 208 of the image-subject pairs includes filtering using a neural network trained to recognize text-image pairs. Filtering the image-subject pairs can identify whether the image-subject pair is correct. For example, in at least one embodiment, if the subject is a fox and the description is a forest, but the image-subject pair is a fox on the moon, filtering the image-subject pairs will reject the fox-moon pair. In at least one embodiment, for example, filtering is performed by a contrastive language-image pre-training (CLIP) model (e.g., a neural network) that scores the image-subject pairs. Any image-subject pair with a score below a threshold (e.g., below 0.95) is filtered out.

[0078] In at least one embodiment, post-processing 208 includes generating output 209, which is an intermediate image. In at least one embodiment, output 209 is an image of the one or more input 201 subjects without the background. Output 209 is generated by one or more post-processing 208 neural networks that combine a foreground mask representation of each subject's pose with the white space image to generate output 209 of one or more subjects, each subject having a different pose and a white background. Generation of output 209 may include using one or more neural networks, machine learning models, artificial intelligence models, software, hardware, or other post-processing processes.

[0079] Figure 3 A training process 300 is shown, which may include processing by one or more processors (e.g., 20A to 40In at least one embodiment, the training process 300 includes: Figure 1-Figure 2 In at least one embodiment, the training process 200 and the training process 300 can be combined and performed by one or more processors executing training software to train the neural network or generate training data (e.g., image and text pairs). In at least one embodiment, the training process 300 includes a neural network 302 that is configured to: receive one or more inputs 301 including one or more subjects, generate one or more background cues 303a-303n, connect one or more intermediate images corresponding to the output 209 with the one or more background cues 303a-303n, and generate one or more output images 305, thereby generating text and image pairs that can be used for training. In at least one embodiment, the one or more output images 305 include one or more subjects of the subject set located on one or more different backgrounds described by the one or more background cues 303a-303n.

[0080] In at least one embodiment, the training process 300 includes generating one or more contextual cues 303a-303n from one or more input texts 301 using a trained neural network 302. The neural network 302 can be one or more of a transformer neural network, a large language model, or other language processing model. In at least one embodiment, the neural network 302 receives a subject set {x n ,x n+1 ,x n+2 ,…N} as input 301, where x n 、x n+1 、x n+2 Each of N is a different subject from the list of subjects in input 201. For each subject, neural network 302 generates one or more contextual cues 303a-303n. Neural network 302 provides one or more contextual cues 303a-303n, which form a contextual cues set {b n ,b n+1 ,b n+2,…B}. For example, given an input text including the subject "fox", the neural network 302 generates one or more contextual cues 303a-303n. In at least one embodiment, the generated contextual cues 303a-303n are texts including words, phrases, or sentences describing the context. In at least one embodiment, for example, the neural network 301 generates the contextual cues 303a-303n "in the snow, in the forest, ... in the fall". The neural network 301 combines the subject of the input 301 and the one or more contextual cues 303a-303n into an output vector space (e.g., a subject-contextual cues vector space). When combining the subject with the contextual cues, the neural network 302 learns the connection between the text describing the subject of the subject set 203 and one or more textual descriptions of the one or more contextual cues 303a-303n.

[0081] In at least one embodiment, the training process 300 includes a neural network 304 that receives as input the subject-background cue vector space of the neural network 302 and the output 209 of the neural network 205, and outputs one or more images 305a-305n of the subject of the subject set 203 on one or more backgrounds described by one or more background cues 303a-303n. In at least one embodiment, the neural network 304 is one or more of a text-to-image diffusion model, a latent text-to-image diffusion model, a stable diffusion inpainting model, or other neural network models trained to associate text with an image described by the text.

[0082] In at least one embodiment, the training processes 200 and 300 (see Figure 2 and Figure 3 ) is used by one or more processors to train neural network 102. For example, images paired with sentences that include the same subject in each sentence and each image are used to train neural network 102. In at least one embodiment, during training, neural network 102 learns to denoise noisy images. In at least one embodiment, neural network 102 may be referred to as a joint diffusion model or a multi-diffusion model because it is a diffusion model with two distributions, e.g., one distribution for text and another distribution for images. In at least one embodiment, the joint distribution may include a combined distribution of text features and image features, such that the distribution may be sampled and the samples may be used to generate and denoise images of the same subject (e.g., the same dog) in different contexts based on a text prompt input. In at least one embodiment, during training, neural network 102 learns the joint distribution, and after training, neural network 102 may be used to sample the joint distribution to generate images of the same subject in different contexts based on different prompts.

[0083] Training is done via ∈ prediction and a simplified training objective, introduced by:

[0084]

[0085] where ∈ θ represents the network parameterized by θ, T is the number of diffusion steps, and x t There are N images x=[x 1 ,x 2 ,...,x N ] is a t-step noisy version of the ground-truth image collage.

[0086] Figure 4 Another block diagram for training a neural network to generate images of the same object according to at least one embodiment is shown. In at least one embodiment, Figure 4 You can use Figures 1 to 3 In at least one embodiment, neural network 401 (e.g., Figure 1 The neural network 102 in FIG. 1 receives one or more inputs 402 and generates one or more output images 408, wherein each of the output images 408 includes a shared image object (e.g., from the subject set 203 {x n ,x n+1 ,x n+2 ,…N}, where x n 、x n+1 、x n+2 , N are each a different subject in the subject list. In at least one embodiment, input 402 is text, an image, or a combination of text and images (e.g., inputs 101, 201). For example, the input may include prompts for generating a fox in the snow, the same fox in the forest, and the same fox jumping over a river.

[0087] In at least one embodiment, input 402 is received by one or more convolutional layers 403 of a neural network 401. The one or more convolutional layers 403 generate a feature image map for each input 402. The feature image maps generated by the convolutional layers 403 are received by one or more concatenation layers 404, which concatenate each feature image map into a single feature map, wherein the single feature map is provided to one or more self-attention layers 405. In at least one embodiment, the self-attention layer 405, executed by one or more processors, compares each element of the single feature map to determine which elements are more similar to each other element (e.g., fox fur is the same or very similar, fox eyes are the same or very similar). In at least one embodiment, the one or more self-attention layers 405 generate another feature map that includes weights indicating the importance of the feature (e.g., how common it is) or a representation of the feature (e.g., a matrix, a feature map) so that it can be converted from one domain to another. In at least one embodiment, software executed by one or more processors receives a self-attentioned feature map and divides it into a corresponding number of individual self-attentioned feature maps, such as each self-attentioned feature map. In at least one embodiment, each self-attentioned feature map is received by a cross-attention layer 406, which can associate the self-attentioned feature map with text 407 (e.g., text prompts 303a-303n) to generate one or more output images 408. The output image 408 is a shared image object (e.g., from the subject set 203{x n ,x n+1 ,x n+2 ,…N}, where x n 、x n+1 、x n+2 , …N, each of which is an image of a different subject in the subject list).

[0088] In at least one embodiment, for example, input 402 is the text "fox in the snow." Neural network 401, executed by one or more processors, receives input 402 and generates one or more images 408 of a fox in the snow. In at least one embodiment, input 402 is the text "fox in the snow" and "fox in the forest." Neural network 401 receives input 402 and generates one or more images 408 of a fox in the snow and a fox in the forest.

[0089] In at least one embodiment, input 402 is text and an image. For example, input 402 is an image of a fox and the text "fox in the snow." Neural network 401 can capture the image of a fox from input 402 and generate one or more images 408 of a fox in a snowy background.

[0090] Figure 5 Another block diagram for training a neural network to generate images of the same object is shown in accordance with at least one embodiment. In at least one embodiment, neural network 501 includes one or more neural networks or one or more neural network portions, such as neural network portion 504. In at least one embodiment, neural network 501 receives one or more inputs (e.g., input 502, input 503). Although Figure 5 Only two inputs are depicted in FIG. 4 , but the neural network 501 can have more than two inputs (e.g., 20 images). In at least one embodiment, the inputs 502 and 503 can be text, images, or a combination of text and images. For each input 502 and 503, the neural network portion 504 (e.g., the convolutional layer 403) generates one or more feature image maps 505 and 506. The one or more feature image maps 505 and 506 are stitched together by one or more stitching layers 404.

[0091] In at least one embodiment, the concatenation of one or more feature image maps generates a single feature image map 507. In at least one embodiment, the feature map 507 is processed by one or more self-attention layers 405 (e.g., scaled dot product attention). The self-attention layer 405 weights the importance of different elements of the spliced ​​image map 507 so that the self-attention layer 405 can capture the relationships and dependencies between the elements of the spliced ​​image map 507. Each element of the spliced ​​image map 507 is associated with a feature vector. For each element in the spliced ​​image map 507, the self-attention layer 405 generates a query vector 508, a key vector 509, and a value vector 510. The query vector 508 captures the relationship between the elements of the spliced ​​image map 507. The key vector 509 compares the current element to all other elements in the sequence. The value vector 510 contains information about the current element.

[0092] In at least one embodiment, the self-attention layer 405 generates an attention score for each element of the concatenated image map 507 by performing a dot product of the query vector 508 with the key vectors 509 of all other elements. The attention score indicates how much attention the current element should pay to each other element in the sequence.

[0093] In at least one embodiment, each attention score is passed through a softmax function to generate an attention weight. The attention weight reflects the importance of each element relative to the current element. Elements with higher attention weights are considered more relevant.

[0094] In at least one embodiment, the spliced ​​image map 507 is input to one or more self-attention layers 405 of the neural network 501. The self-attention layer 405 enhances the information content of the spliced ​​image map 507 by including information about the context of the inputs (e.g., 502, 503). The self-attention layer 405 derives dependencies between foreground images of one or more input images (e.g., 502, 503) through self-attention of the spliced ​​image map 507. In addition, the self-attention layer 405 derives dependencies between backgrounds of one or more inputs (e.g., 502, 503). In effect, the self-attention layer 405 separates the foreground image from the background image through self-attention.

[0095] In at least one embodiment, the output of the self-attention layer 511 is processed to generate one or more processed feature maps (e.g., 512, 513). In at least one embodiment, the processing includes dividing the output of the self-attention layer 508 into a number of processed feature maps (512, 513) corresponding to the number of input images (502, 503). In at least one embodiment, for example, if two input images (e.g., 502, 503) are input to the self-attention layer 405, the output of the self-attention layer 405 is divided into two processed feature maps (e.g., 512, 513).

[0096] In at least one embodiment, the processed feature maps 512, 513 are input to the cross-attention layer 406. In addition, the input of the cross-attention layer 406 includes one or more text prompts 514, 515 (e.g., text prompt 407). Although only two text prompts 514, 515 are depicted, the cross-attention layer 406 can be input to any finite number of text prompts.

[0097] In at least one embodiment, for each element of the processed feature maps 512, 513 that is input to the crisscross attention layer 406, the layer 406 generates a query vector 516, a key vector 517, and a value vector 518. The query vector 516 captures the relationship between the elements. The key vector 517 compares the current element to all other elements in the sequence. The value vector 518 contains information about the current element.

[0098] In at least one embodiment, the crisscross attention layer 406 references one or more of the query vector 516, key vector 517, and value vector 518 for each element of the processed feature maps 512, 514, concatenating one or more of the vectors 516-518 with the input text prompt 514, 515.

[0099] In at least one embodiment, text prompts 514, 515 (e.g., prompts 303a-303n) include words, phrases, or sentences describing the background. In at least one embodiment, for example, text prompts 514, 515 include "in the snow, in the forest" describing a snowy background and a forest background.

[0100] In at least one embodiment, the crisscross attention layer 406 outputs images 519, 520. Images 519, 520 are images having inputs 502, 503 as foreground images and background images described by prompts 514, 515. In effect, the neural network 501 combines the inputs 502, 503 with the background described in the prompts 514, 515 to generate personalized images 519, 520.

[0101] In at least one embodiment, the neural network 501 generates personalized images 519, 520. Given n input images The n input images are part of a generated multi-image set x such that When sampling a set of images, for each diffusion step, keep the unknown image The backward diffusion output of the corresponding step is used at the same time (for example, the real image with noise ) to replace the known image.

[0102] In at least one embodiment, by adding additional masks and input image channels to the diffusion model training, the input images 502 , 503 can be better adapted for personalized image generation.

[0103] In at least one embodiment, during training, each image can be randomly assigned a known probability value. In at least one embodiment, for example, the randomly assigned known probability value can be 0.5. The mask for the known image is set to 1 for all pixels and to 0 for the unknown image. In at least one embodiment, any additional input channels are copied from the original image for the known image and set to an all-zero map for the unknown image.

[0104] In at least one embodiment, the training loss is:

[0105]

[0106] Where M is the spatial tiling of the binomial vector m; Represents a partially known image set where unknown elements are set to zero.

[0107] In at least one embodiment, personalized image generation adapts image generation to the custom concepts given in user-provided sample images. These custom concepts can be diverse and deviate significantly from the training data. This problem can be addressed by using sample images as guidance during inference. During image guidance, sampling is performed using a modified score estimate as follows:

[0108]

[0109] Where λ represents the guidance intensity; is the unconditional score when all sample images are set to all zeros; is the fraction of the i-th example image that is set to all zeros.

[0110] Image guidance improves the fidelity of the custom concepts presented in the input image. Image guidance in the above equation modifies the sampling distribution so that sample images are assigned with high probability and adapt to the sample images. The accumulation term in the above equation encourages the model to fully utilize information from each image when multiple sample images are present, allowing the model to benefit from a large number of sample images.

[0111] Figure 6 An example neural network is shown for generating images including the same subject in different backgrounds in accordance with at least one embodiment. In at least one embodiment, neural network 600 includes the following: Figure 1-Figure 5 The components and / or processes shown, for example, a processor executing software may be based on Figure 2-Figure 4 In at least one embodiment, the neural network 600 receives one or more inputs 601 (e.g., input 402) and one or more prompts 602. In at least one embodiment, the input 601 can be text, an image, or a combination of text and images. In at least one embodiment, the input 601 includes a subject 610 (e.g., a fox), such as Figure 6 In at least one embodiment, neural network 600 receives only text as input. In at least one embodiment, input 601 includes an image of a fox.

[0112] In at least one embodiment, prompt 602 may be one or more words, phrases, or sentences describing a background scene. In at least one embodiment, prompt 602 includes one or more instructions from one or more users indicating content other than one or more objects in at least one of two or more different images (e.g., words describing the background or image features other than the subject in the image). For example, input 101 may include words other than the subject, such as forest, background, snow, weather, and season. In at least one embodiment, neural network 102 uses the words in the sentence as content to generate features of the background. In at least one embodiment, prompt 602 includes a phrase such as "Generate images of foxes in a forest during different seasons," where the fox refers to input 601. In at least one embodiment, neural network 600 uses the first portion of the neural network (e.g., neural network 504, convolutional layer 403) to generate feature maps (e.g., 505, 506) from input 601. In at least one embodiment, the feature maps (e.g., 505, 506) of input 601 are input to stitching layer 404, which generates a stitched image map 507. In at least one embodiment, the neural network 600 includes a second neural network portion (e.g., the self-attention layer 405) that generates, for each element, a concatenated image map 507, a query vector 508, a key vector 509, and a value vector 510. In at least one embodiment, the query vector 508 represents the relationship between the elements of the concatenated image map 507. In at least one embodiment, the key vector 509 compares the current element to all other elements in the sequence, and the value vector 510 contains information about the current element.

[0113] In at least one embodiment, the self-attention layer 405 generates an attention score for each element of the concatenated image map 507 by performing a dot product of the query vector 508 with the key vectors 509 of all other elements. The attention score indicates how much attention the current element should pay to each other element in the sequence.

[0114] In at least one embodiment, each attention score is passed through a softmax function to generate an attention weight. The attention weight reflects the importance of each element relative to the current element. Elements with higher attention weights are considered more relevant.

[0115] In at least one embodiment, the spliced ​​image map 507 is input to one or more self-attention layers 405 of the neural network 501. The self-attention layer 405 enhances the information content of the spliced ​​image map 507 by including information about the context of the inputs (e.g., 502, 503). The self-attention layer 405 derives dependencies between foreground images of one or more input images (e.g., 502, 503) through self-attention of the spliced ​​image map 507. In addition, the self-attention layer 405 derives dependencies between backgrounds of one or more inputs (e.g., 502, 503). In effect, the self-attention layer 405 separates the foreground image from the background image through self-attention.

[0116] In at least one embodiment, the self-attention layer 511 generates one or more feature maps (e.g., 512, 513), wherein the features are self-attentional, e.g., focused on common features of the subject. In at least one embodiment, processing includes dividing the output of the self-attention layer 508 into a number of processed feature maps (512, 513) corresponding to the number of input images (502, 503). In at least one embodiment, for example, if two input images (e.g., 502, 503) are input to the self-attention layer 405, the output of the self-attention layer 405 is divided into two processed feature maps (e.g., 512, 513).

[0117] In at least one embodiment, the processed feature maps 512, 513 are input to the crisscross attention layer 406. In addition, the input to the crisscross attention layer 406 includes textual cues 603 (e.g., cues 514, 515, and 407).

[0118] In at least one embodiment, for each element of the processed feature maps 512, 513 input to the crisscross attention layer 406, the layer 406 generates a query vector 516, a key vector 517, and a value vector 518. The query vector 516 captures the relationship between the elements. The key vector 517 compares the current element to all other elements in the sequence. The value vector 518 contains information about the current element.

[0119] In at least one embodiment, the cross-attention layer 406 references one or more of the query vector 516 , key vector 517 , and value vector 518 for each element of the processed feature maps 512 , 514 , thereby connecting the one or more vectors 516 - 518 with the input text prompt 603 .

[0120] In at least one embodiment, the text prompt 602 is "Generate images of foxes (e.g., input 601) in a forest in different seasons." In at least one embodiment, the cross-attention layer 406 outputs images 603, 604, 605, and 606. Images 603, 604, 605, and 606 are generated by the neural network 600. The generated images have input 601 as a foreground image, in which the subject "fox" 611 is in different poses. The background of images 603, 604, 605, and 606 is the scene described by the prompt 602. In at least one embodiment, image 603 is input 601, and its background scene is a forest in spring. In at least one embodiment, image 604 is input 601, and its background scene is a forest in winter. In at least one embodiment, image 605 is input 601, and its background scene is a forest in summer. In at least one embodiment, image 606 is input 601, and its background scene is a forest in autumn. In this manner, neural network 600 generates personalized images of foxes with different poses and background scenes, as requested by text prompt 602. In at least one embodiment, fox 611 appears in different poses, states, or other postures, as shown in images 603, 604, 605, and 606. As shown in output images 603, 604, 605, and 606, each background 607, 608, 609, and 610 has a different background (e.g., 607 is a forest background during the day, 608 is a forest background during the day, 609 is a forest background but different from the forest in 607 and 608, and 610 is a different forest background with leaves on the ground). In at least one embodiment, backgrounds 607, 608, 609, and 610 are inferred from prompt 602 (e.g., forest, daytime, snow, green forest, forest with leaves on the ground in autumn). In at least one embodiment, neural network 600 generates foxes 611 in different poses that are learned from its training data and / or when denoising images of foxes in different poses using a diffusion layer.

[0121] In at least one embodiment, based at least in part on the one or more indications, the step of performing a weighting operation, a softmax operation, or other pooling operation to generate a value for the image feature is performed using one or more neural networks (e.g., neural network 102) and / or one or more layers of a neural network.

[0122] Figure 7 is a flow chart illustrating an example of a process 700 for training one or more neural networks to generate one or more objects in two or more different images in accordance with at least one embodiment. In at least one embodiment, one or more systems, processors, or communication devices may be used to perform Figure 7In at least one embodiment, one or more operations performed as part of process 700 may be performed in a manner different from that of process 700 (or any other process described, or variations and / or combinations thereof) to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating the content of at least one of the two or more different images other than the one or more objects. Figure 7 The various orders and combinations described in the are executed, including in parallel. In at least one embodiment, in combination with Figure 7 The components, methods and / or systems described in Figures 1-6 Any one of which is further non-exclusively shown.

[0123] In at least one embodiment, the neural network learns to recognize 702 features corresponding to the subject of one or more inputs. The input can be text, an image, or a combination of text and images (e.g., input 101). In at least one embodiment, the neural network learns to recognize features corresponding to the subject of input 201. The list of subjects forms a subject set 203 {x n ,x n+1 ,x n+2 ,…N}, where x n 、x n+1 、x n+2 , each of N is a different subject in the subject list.

[0124] In at least one embodiment, the neural network model generates 704 a subject set {x n ,x n+1 ,x n+2 ,…N}. In at least one embodiment, a non-limiting example is that, given the input 201 text “dog, cat, fox, mouse”, the first neural network model generates the subject set 203 {dog, cat, fox, mouse}.

[0125] In at least one embodiment, the first neural network model generates 706 one or more text descriptions 204 of the scene. The neural network 202 generates one or more text descriptions 204 of the one or more scenes, thereby creating a description set {y m ,y m+1 ,y m+2 ...M}. For example, a scene may include one or more backgrounds, scenery, settings, environments, surroundings, or other descriptions of portions of an image that are not the foreground. Neural network 202 assigns the subject set {x n ,x n+1 ,x n+2 ,…N} and each subject in the description set {y m ,ym+1 ,y m+2 ...M} are combined with each text description of one or more scenes in the subject set 203 to generate 706 a subject text description dataset. When combining the subjects with the text descriptions, the first neural network model learns a connection between each subject in the subject set 203 and one or more text descriptions of the scenes in the description set 204.

[0126] In at least one embodiment, the neural network 205 generates 708 one or more images in the image set 206 and connects the subjects of the subject text description dataset with one or more images forming subject-image pairs. In at least one embodiment, the neural network 205 is a stable diffusion model (e.g., SDXL), a generative artificial intelligence model, a diffusion neural network, or a text and image generation neural network model. In at least one embodiment, the neural network 205 receives the subject text description dataset as input and generates 708 a collage or image set 206 corresponding to one or more subjects of the subject description dataset. In at least one embodiment, the neural network 205 parses the subject set 203 {x n ,x n+1 ,x n+2 ,…N}, and generate an image set {z l ,z l+1 ,z l+2 ...L}. Each image constituting image set 206 is an image of the input 201 subject in a different pose. In at least one embodiment, image set 206 includes one or more images of each subject in different poses, and may also include the subject in different poses on one or more different backgrounds. For example, for the subject "fox" in the subject text description dataset, neural network 205 generates foxes in different poses and different backgrounds, constituting image set 203{z l ,z l+1 ,z l+2 In at least one embodiment, for the subject “dog” in the subject text description dataset, the second neural network 206 generates dogs with different postures and different backgrounds, constituting an image set 206 of the subject “dog” {z l ,z l+1 ,z l+2 ...L}. Repeat this for each subject in the subject set and each text description in the description set.

[0127] In at least one embodiment, when generating an image set 203 for each subject, l ,z l+1 ,z l+2...L}, neural network 205 then associates 710 the subject with each image in image set 206. In at least one embodiment, for example, neural network 205 associates the subject "fox" with each different image in image set 206, where each image in image set 206 includes an image of a fox in a different pose or with a different pose or appearance. By generating these image-subject pairs, the stable diffusion model provides an association between the subject and the pose or aspect of each image in image set 206.

[0128] In at least one embodiment, the training process 200 includes one or more post-processing 208 of the output of the second neural network model or the image-subject pairs. The post-processing 208 is performed by any of a neural network model, machine learning, artificial intelligence, software, or hardware. The post-processing 208 includes, for each image of the image-subject pair, processing the image through object detection and segmentation to separate the subject (e.g., fox) of each image in the image set (e.g., image set {z l ,z l+1 ,z l+2 ...L}) and extract a foreground mask. The extracted foreground mask is a representation of the pose of each subject separated from any background image that may be present in the image set 206.

[0129] In at least one embodiment, post-processing 712 (eg, post-processing 208 ) of the collage of image-subject pairs or the extracted set of foreground masks includes separating the collage of images 206 into individual output images 209 .

[0130] In at least one embodiment, post-processing 712 of the image-subject pairs includes filtering using a neural network trained to recognize text-image pairs. Filtering the image-subject pairs can identify whether the image-subject pair is correct. For example, in at least one embodiment, if the subject is a fox and the description is a forest, but the image-subject pair is a fox on the moon, filtering the image-subject pairs will reject the fox-moon pair. In at least one embodiment, for example, filtering is performed by a contrastive language-image pre-training (CLIP) model (e.g., a neural network) that scores the image-subject pairs. Any image-subject pair with a score below a threshold (e.g., below 0.95) is filtered out.

[0131] In at least one embodiment, post-processing includes generating outputs 713 (e.g., generating outputs 209), which are intermediate images. The intermediate images 209 are images of the one or more input 201 subjects without the background. The intermediate images 209 are generated by one or more post-processing 208 neural networks that combine a foreground mask representation of the pose of each subject with the white space image to generate one or more images 209 of the one or more subjects and a white background, each subject having a different pose. The generation of the intermediate images 209 can include the use of one or more neural networks, machine learning models, artificial intelligence models, software, hardware, or other post-processing processes.

[0132] Figure 8 is a flow chart illustrating an example of a process 800 for training one or more neural networks to generate one or more objects in two or more different images, according to at least one embodiment. Figure 8 Part or all of process 800 of the image generation system shown in (or any other process described, or variations and / or combinations of such processes) may be performed using one or more systems, processors, or communication devices to generate one or more objects in two or more different images based at least in part on one or more indications from one or more users indicating content other than the one or more objects in at least one of the two or more different images. In at least one embodiment, one or more operations performed as part of process 800 may be performed in a manner different from Figure 8 In at least one embodiment, the various orders and combinations shown in Figure 8 The components, methods and / or systems described in Figure 1-Figure 7 Any one of which is further non-exclusively shown.

[0133] In at least one embodiment, Figure 8 A neural network (e.g., neural network 302) training is shown, which includes generating 802 one or more contextual cues 303a-303n from one or more input texts 301. The neural network can be one or more of a transformer neural network, a large language model, or other language processing model. In at least one embodiment, the neural network receives a subject set 203 {x n ,x n+1 ,x n+2 ,…N} as input 301, where x n ,x n+1 ,x n+2, ... N is a different subject from the subject list of input 201. For each subject, the neural network 302 generates one or more contextual cues 303a-303n. The neural network 302 provides a set of contextual cues {b n ,b n+1 ,b n+2 ,…B} one or more contextual cues 303a-303n. For example, but not limited to, given an input text including the subject "fox", the neural network 302 generates one or more contextual cues 303a-303n. In at least one embodiment, the generated contextual cues 303a-303n are texts including words, phrases, or sentences describing the context. In at least one embodiment, for example, the neural network 301 generates the contextual cues 303a-303n "in the snow, in the forest, ... in the fall". The neural network 301 combines the subject of the input 301 and the one or more contextual cues 303a-303n into an output vector space (e.g., a subject-contextual cues vector space). When combining the subject with the contextual cues, the neural network 302 learns the connection between the text describing the subject in the subject set 203 and one or more textual descriptions in the one or more contextual cues 303a-303n.

[0134] In at least one embodiment, neural network training includes receiving 804 a subject-background cue vector space from neural network 302 and receiving 806 an intermediate image 209 from neural network 205 .

[0135] In at least one embodiment, neural network training includes generating 808 one or more images (e.g., images 305a-305n) of subjects in subject set 203 on one or more backgrounds described by one or more background cues 303a-303n. In at least one embodiment, neural network 304 is one or more of a text-to-image diffusion model, a latent text-to-image diffusion model, a stable diffusion inpainting model, or other neural network models trained to associate text with images described by the text.

[0136] Figure 9 is a flow chart illustrating an example of a process 900 for performing inference using one or more neural networks to generate one or more objects in two or more different images. In at least one embodiment, diffusion of an image (eg, a diffusion neural network) includes denoising an input image.

[0137] In at least one embodiment, performing inference using one or more neural networks includes generating a feature map 902. A neural network (e.g., a diffusion neural network) receives one or more inputs (e.g., input 502, input 503). Although Figure 5Only two inputs are depicted in FIG, but the inputs to the neural network can be any finite number of inputs. Inputs 502, 503 can be text, images, or a combination of text and images. For each input 502, 503, a neural network portion 504 (e.g., convolutional layer 403) generates one or more feature image maps 505, 506.

[0138] In at least one embodiment, performing inference using one or more neural networks includes concatenating one or more feature maps 904. The one or more feature image maps 505, 506 are concatenated together by one or more concatenation layers 404. In at least one embodiment, the concatenation of the one or more feature image maps generates a single feature image map 507.

[0139] In at least one embodiment, performing inference using one or more neural networks includes processing the concatenated feature map using one or more self-attention neural networks or layers 906. In at least one embodiment, the feature map 507 is processed by one or more self-attention layers 405. The self-attention (e.g., scaled dot product attention) layer 405 weights the importance of different elements of the concatenated image map 507, enabling the self-attention layer 405 to capture relationships and dependencies between elements of the concatenated image map 507. Each element of the concatenated image map 507 is associated with a feature vector. For each element in the concatenated image map 507, the self-attention layer 405 generates a query vector 508, a key vector 509, and a value vector 510. The query vector 508 captures the relationship between elements of the concatenated image map 507. The key vector 509 compares the current element to all other elements in the sequence. The value vector 510 contains information about the current element.

[0140] In at least one embodiment, the self-attention layer 405 generates an attention score for each element of the concatenated image map 507 by performing a dot product of the query vector 508 with the key vectors 509 of all other elements. The attention score indicates how much attention the current element should pay to each other element in the sequence.

[0141] In at least one embodiment, each attention score is passed through a softmax function to generate an attention weight. The attention weight reflects the importance of each element relative to the current element. Elements with higher attention weights are considered more relevant.

[0142] In at least one embodiment, performing inference using one or more neural networks includes partitioning the self-attention processed feature maps 908. In at least one embodiment, the output of the self-attention layer 511 is processed to generate one or more processed feature maps (e.g., 512, 513). In at least one embodiment, the processing includes partitioning the output of the self-attention layer 508 into a number of processed feature maps (512, 513) corresponding to the number of input images (502, 503). In at least one embodiment, for example, if two input images (e.g., 502, 503) are input to the self-attention layer 405, the output of the self-attention layer 405 is partitioned into two processed feature maps (e.g., 512, 513).

[0143] In at least one embodiment, reasoning using one or more neural networks includes processing the partitioned feature maps by one or more cross-attention layers 910. In at least one embodiment, the processed feature maps 512, 513 are input to the cross-attention layer 406. In addition, the input to the cross-attention layer 406 includes one or more text prompts 514, 515 (e.g., text prompt 407). Although only two text prompts 514, 515 are depicted, the cross-attention layer 406 can be input to any finite number of text prompts.

[0144] In at least one embodiment, for each element of the processed feature maps 512, 513 input to the crisscross attention layer 406, the layer 406 generates a query vector 516, a key vector 517, and a value vector 518. The query vector 516 captures the relationship between the elements. The key vector 517 compares the current element to all other elements in the sequence. The value vector 518 contains information about the current element.

[0145] In at least one embodiment, the cross-attention layer 406 references one or more of the query vector 516, key vector 517, and value vector 518 for each element of the processed feature maps 512, 514, thereby associating the one or more vectors 516-518 with the input text prompt 514, 515.

[0146] In at least one embodiment, text prompts 514, 515 (e.g., prompts 303a-303n) include words, phrases, or sentences describing the background. In at least one embodiment, for example, text prompts 514, 515 include "in the snow, in the forest" describing a snowy background and a forest background.

[0147] In at least one embodiment, performing inference using one or more neural networks includes generating one or more output images 912. In at least one embodiment, the cross-attention layer 406 outputs images 519, 520. Images 519, 520 are images having inputs 502, 503 as foreground images and background images described by prompts 514, 515. In practice, the neural network 501 combines the inputs 502, 503 with the background described in the prompts 514, 515 to generate personalized images 519, 520.

[0148] Figure 10 An example including a processor and modules according to at least one embodiment is shown. Figure 10 An example 1000 including a processor 1002 and modules is shown in accordance with at least one embodiment. In at least one embodiment, the processor 1002 includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications from one or more users indicating content other than the one or more objects in at least one of the two or more different images. In at least one embodiment, the processor 1002 includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications from one or more users indicating content other than the one or more objects in at least one of the two or more different images.

[0149] In at least one embodiment, processor 1002 includes one or more processors, such as a processor in conjunction with Figures 1-9 In at least one embodiment, processor 1002 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, processor 1002 includes or has access to convolutional model 1003, stitching module 1004, self-attention module 1005, and cross-attention module 1006, which are distributed among multiple processors that communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication process (such as the communication process described herein).

[0150] In at least one embodiment, a module used in any implementation described herein, unless the context clearly dictates otherwise or clearly dictates otherwise, refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" (as used by, for example, a processor in any implementation described herein) may include (e.g., individually or in any combination) hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may be collectively or individually embodied as circuitry that constitutes part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units (e.g., one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof).

[0151] Figure 10 1002 uses a convolutional model 1003, a stitching module 1004, a self-attention module 1005, and a cross-attention module 1006 to generate one or more output images. In at least one embodiment, the processor uses any one or all of the convolutional model 1003, the stitching module 1004, the self-attention module 1005, and the cross-attention module 1006 to generate one or more output images, such as in combination. Figures 1-9 In at least one embodiment, the processor 1002 uses the convolutional model 1003, the concatenation module 1004, the self-attention module 1005, and the cross-attention module 1006 to make the use of computing resources based on the software program (based on the received combined Figures 1-9 The text prompts generate images) to execute the software program.

[0152] In at least one embodiment, the processor 1002 uses a convolutional model 1003 to generate one or more feature maps of one or more inputs (e.g., input 402). The convolution module 1003 includes one or more convolutional layers, neural networks, or other machine learning elements. The convolution module 1003 receives one or more inputs (e.g., input 502, input 503). The inputs of the convolution module 1003 can be any finite number of inputs. The inputs of the convolution module 1003 can be text, images, or a combination of text and images. For each input, one or more convolutional neural networks (e.g., convolutional neural network 504, convolutional layer 403) of the convolution module 1003 generate one or more feature image maps (e.g., feature image maps 505, 506).

[0153] In at least one embodiment, processor 1002 stitches together one or more feature image maps using stitching module 1004. Stitching module 1004 includes one or more processing layers, neural networks, convolutional layers, or other machine learning elements. Stitching module 1004 stitches together one or more feature image maps using one or more stitching layers (e.g., stitching layer 404). In at least one embodiment, the stitching of one or more feature image maps generates a single feature image map (e.g., feature image map 507).

[0154] In at least one embodiment, processor 1002 generates one or more feature vectors using self-attention module 1005. Self-attention module 1005 includes one or more self-attention layers or self-attention neural networks. In at least one embodiment, feature map 507 is processed by one or more self-attention layers (e.g., self-attention layer 405). Self-attention layer 405 (e.g., scaled dot product attention) weights the importance of different elements of spliced ​​image map 507, enabling self-attention layer 405 to capture relationships and dependencies between elements of spliced ​​image map 507. Each element of spliced ​​image map 507 is associated with a feature vector. For each element in spliced ​​image map 507, self-attention layer 405 generates a query vector 508, a key vector 509, and a value vector 510. Query vector 508 captures the relationship between elements of spliced ​​image map 507. Key vector 509 compares the current element to all other elements in the sequence. Value vector 510 contains information about the current element.

[0155] In at least one embodiment, the self-attention module 1005 generates an attention score for each element of the spliced ​​image map 507 by taking a dot product of the query vector 508 with the key vectors 509 of all other elements. The attention score indicates how much attention the current element should pay to each other element in the sequence. In at least one embodiment, each attention score is passed through a softmax function to generate an attention weight. The attention weight reflects the importance of each element relative to the current element. Elements with higher attention weights are considered more relevant. In at least one embodiment, the self-attention module outputs one or more feature maps.

[0156] In at least one embodiment, the processor 1002 generates one or more images containing image objects (e.g., one or more subjects of the subject set 203) with one or more different backgrounds using a crisscross attention module 1006. The crisscross attention module 1006 includes one or more crisscross attention layers or crisscross attention neural networks.

[0157] In at least one embodiment, the output of the self-attention module 1005 is processed by the cross-attention module 1006 to generate one or more processed feature maps (e.g., 512, 513). In at least one embodiment, the processing includes dividing the output of the self-attention layer 508 into a number of processed feature maps (512, 513) corresponding to the number of input images (502, 503). In at least one embodiment, for example, if two input images (e.g., 502, 503) are input to the self-attention layer 405, the output of the self-attention layer 405 is divided into two processed feature maps (e.g., 512, 513).

[0158] In at least one embodiment, the processed feature maps (e.g., processed feature maps 512, 513) are input to the cross-attention module 1006. Additionally, the input to the cross-attention module 1006 includes one or more text cues (e.g., text cues 407, 514, 515).

[0159] In at least one embodiment, for each element of the processed feature maps 512, 513 input to the crisscross attention module 1006, one or more crisscross attention layers (e.g., crisscross attention layer 406) generate a query vector 516, a key vector 517, and a value vector 518. The query vector 516 captures the relationship between elements. The key vector 517 compares the current element with all other elements in the sequence. The value vector 518 contains information about the current element.

[0160] In at least one embodiment, the cross-attention layer 406 references one or more of the query vector 516, key vector 517, and value vector 518 for each element of the processed feature maps 512, 514, thereby associating the one or more vectors 516-518 with the input text prompt 514, 515.

[0161] In at least one embodiment, text prompts 514, 515 (e.g., prompts 303a-303n) include words, phrases, or sentences describing the background. In at least one embodiment, for example, text prompts 514, 515 include "in the snow, in the forest" describing a snowy background and a forest background.

[0162] In at least one embodiment, the cross-attention layer (e.g., cross-attention layer 406) of the cross-attention module 1006 outputs one or more images (e.g., images 408, 519, 520, 603-606). The output image has a subject of the input (e.g., input 502, 503) as a foreground image and a background image described by a prompt (e.g., prompt 514, 515). In practice, the processor 1002 combines the input subject with the background described in the prompt (e.g., prompt 514, 515) to generate a personalized image (e.g., images 408, 519, 520, 603-606).

[0163] In at least one embodiment, combined Figure 10 The components, methods and / or systems described in Figures 1-9 any one of which is further described non-exclusively.

[0164] Figure 11 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 1102 is a software module. In at least one embodiment, software program 1102 includes Figure 1-10 In at least one embodiment, the software program 1102 includes one or more software modules. In at least one embodiment, one or more software modules such as Figure 10 In at least one embodiment, one or more APIs 1110 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 1110 are distributed or otherwise provided as part of one or more libraries 1106, runtimes 1104, drivers 1104, and / or any other grouping of software and / or executable code as further described herein. In at least one embodiment, one or more APIs 1110 perform one or more computing operations in response to a call from a software program 1102. In at least one embodiment, a software program 1102 is a collection of software code, commands, instructions, or other text sequences that directs a computing device to perform one or more computing operations and / or call one or more other instruction sets, such as APIs 1110 or API functions 1112, to be executed. In at least one embodiment, the functionality provided by one or more APIs 1110 includes software functions 1112, such as software functions that can be used to accelerate one or more portions of a software program 1102 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, the software program is a compiler that, in conjunction with Figure 1-10 Non-exclusively further shown.

[0165] In at least one embodiment, the API 1110 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 1110 described herein are implemented as one or more circuits for performing the following operations in conjunction with Figure 1-9 In at least one embodiment, one or more software programs 1102 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform operations in conjunction with Figure 1-10 One or more techniques further described.

[0166] In at least one embodiment, a software program 1102 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 1110 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, the one or more APIs 1110 provide a set of callable functions 1112, referred to herein as APIs, API functions, and / or functions, that each perform one or more computational operations, such as computational operations related to parallel computing. For example, in an embodiment, the one or more APIs 1110 provide functions 1112 to enable the image generator 1116 to use Figure 1-10 The systems, methods, and other components disclosed in the disclosure generate multiple images that include the same object in different backgrounds.

[0167] In at least one embodiment, one or more software programs 1102 interact with or otherwise communicate with one or more APIs 1110 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 1102 interact with the one or more APIs 1110 to facilitate parallel computing using remote or local interfaces.

[0168] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 1112 provided by one or more APIs 1110. In at least one embodiment, the software programs 1102 use native interfaces when a software developer compiles one or more software programs 1102 in conjunction with one or more libraries 1106 that include or otherwise provide access to the one or more APIs 1110. In at least one embodiment, the one or more software programs 1102 are statically compiled in conjunction with precompiled libraries 1106 or uncompiled source code that include instructions to implement the one or more APIs 1110. In at least one embodiment, the one or more software programs 1102 are dynamically compiled and linked to the one or more precompiled libraries 1106 that include the one or more APIs 1110 using a linker.

[0169] In at least one embodiment, a software program 1102 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 1106 including one or more APIs 1110 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 1106 including one or more APIs 1110 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 1106 including one or more APIs 1110 are executed by any other computing host that provides the one or more APIs 1110 to the one or more software programs 1102.

[0170] In at least one embodiment, a processor executing or using one or more software programs 1102 calls, uses, executes, or otherwise implements one or more APIs 1110 to allocate and otherwise manage memory to be used by the software programs 1102. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 to allocate and otherwise manage memory to be used by one or more portions of the software programs 1102 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors described further herein). Those software programs 1102 can be executed by one or more processors using functions 1112 provided by one or more APIs 1110, in embodiments, based at least in part on the latency of an interconnect coupling the one or more processors.

[0171] In at least one embodiment, API 1110 is an API for facilitating parallel computing. In at least one embodiment, API 1110 is any other API described further herein. In at least one embodiment, API 1110 is provided by a driver and / or runtime 1104. In at least one embodiment, API 1110 is provided by a CUDA user-mode driver. In at least one embodiment, API 1110 is provided by a CUDA runtime. In at least one embodiment, driver 1104 is data values ​​and software instructions that, if executed, execute or otherwise facilitate the execution of one or more functions 1112 of API 1110 during the loading and execution of one or more portions of software program 1102. In at least one embodiment, runtime 1104 is data values ​​and software instructions that, if executed, execute or otherwise facilitate the execution of one or more functions 1112 of API 1110 during the execution of software program 1102. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 implemented or otherwise provided by a driver and / or runtime 1104 to perform combined arithmetic operations by the one or more software programs 1102 during execution of the one or more software programs 1102 by one or more PPUs (e.g., GPUs).

[0172] In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by a driver and / or runtime 1104 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 1110 provide combined arithmetic operations through the driver and / or runtime 1104, as described above. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by the driver and / or runtime 1104 to allocate or otherwise reserve one or more blocks of memory 1114 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by the driver and / or runtime 1104 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 1110 are used to perform combined arithmetic operations, as described below in conjunction with Figures 1-10 Any one of the above.

[0173] To improve the usability of the software program 1102 and / or optimize one or more portions of the software program 1102 for acceleration by one or more PPUs (e.g., GPUs), in one embodiment, the one or more APIs 1110 provide one or more API functions 1112 to implement a scheduling system that can be used by or by one or more computing devices, as described above and in conjunction with Figure 1-6 Further described. In at least one embodiment, exemplary block diagram 1100 depicts a processor comprising one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 1100 depicts a system comprising one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the API to cause a scheduler to select a thread selection mechanism and / or otherwise perform the operations described herein. In at least one embodiment, exemplary block diagram 1100 shows a system for calling one or more modules (modules 1003-1006) to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images.

[0174] In at least one embodiment, a processor uses the exemplary API to schedule one or more instructions to be executed by one or more processors based at least in part on the latency of one or more interconnects coupled to the one or more processors. Figure 5 The components, methods and / or systems described in Figure 1-10 Further non-exclusively shown in.

[0175] Those skilled in the art will appreciate from this disclosure that certain embodiments may be able to achieve certain advantages, including some or all of the following: Improvements in the field of computing and job scheduler systems to distribute jobs across a cluster of nodes. Thus, according to the embodiments disclosed above, one or more processors use one or more neural networks to identify the subject of one or more inputs, where the input can be text, an image, or a combination of text and an image, and generate one or more output images that include the subject of the input as a foreground image and one or more background elements described by one or more cues.

[0176] logic

[0177] Figure 12A12 shows logic 1215 according to at least one embodiment, as described elsewhere herein, which can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 1215 is reasoning and / or training logic. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic used to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0178] In at least one embodiment, logic 1215 may include, but is not limited to, code and / or data storage 1201 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 1215 may include or be coupled to code and / or data storage 1201 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1201 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1201 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0179] In at least one embodiment, any portion of code and / or data storage 1201 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1201 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1201 is internal or external to a processor, e.g., or including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of a neural network, or some combination of these factors.

[0180] In at least one embodiment, logic 1215 may include, but is not limited to, code and / or data storage 1205 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1205 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 1215 may include or be coupled to code and / or data storage 1205 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0181] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 1205 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1205 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1205 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1205 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0182] In at least one embodiment, code and / or data store 1201 and code and / or data store 1205 may be separate storage structures. In at least one embodiment, code and / or data store 1201 and code and / or data store 1205 may be the same storage structure. In at least one embodiment, code and / or data store 1201 and code and / or data store 1205 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 1201 and code and / or data store 1205 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0183] In at least one embodiment, logic 1215 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1210 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 1220, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1201 and / or code and / or data storage 1205. In at least one embodiment, activations stored in activation storage 1220 are generated based on linear algebra and / or matrix-based math performed by ALU 1210 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 1205 and / or code and / or data storage 1201 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1205 or code and / or data storage 1201 or other on-chip or off-chip storage.

[0184] In at least one embodiment, one or more ALUs 1210 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1210 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 1210 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1201, code and / or data storage 1205, and activation storage 1220 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1220 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0185] In at least one embodiment, activation storage 1220 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1220 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1220 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0186] In at least one embodiment, Figure 12A The logic 1215 shown in FIG. 1 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 12A The illustrated logic 1215 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0187] Figure 12B Logic 1215 is shown in accordance with at least one embodiment. In at least one embodiment, logic 1215 is inference and / or training logic. In at least one embodiment, logic 1215 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 12B The logic 1215 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 12BThe logic 1215 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 1215 includes, but is not limited to, code and / or data storage 1201 and code and / or data storage 1205, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 12B In at least one embodiment shown in FIG, code and / or data storage 1201 and code and / or data storage 1205 are each associated with dedicated computing resources, such as computing hardware 1202 and computing hardware 1206, respectively. In at least one embodiment, computing hardware 1202 and computing hardware 1206 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 1201 and code and / or data storage 1205, respectively, with the results being stored in activation storage 1220.

[0188] In at least one embodiment, each of the code and / or data stores 1201 and 1205 and the corresponding computing hardware 1202 and 1206 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 1201 / 1202 of the code and / or data store 1201 and computing hardware 1202 are provided as inputs to the next storage / computation pair 1205 / 1206 of the code and / or data store 1205 and computing hardware 1206, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 1201 / 1202 and 1205 / 1206 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 1215 after or in parallel with the storage / computation pairs 1201 / 1202 and 1205 / 1206.

[0189] In at least one embodiment, Figures 12A-12B The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figures 12A-12B The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figures 12A-12BThe assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0190] Neural network training and deployment

[0191] Figure 13 The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1306 is trained using a training dataset 1302. In at least one embodiment, the training framework 1304 is the PyTorch framework, while in other embodiments, the training framework 1304 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1304 trains the untrained neural network 1306 and enables it to be trained using the processing resources described herein to generate a trained neural network 1308. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0192] In at least one embodiment, untrained neural network 1306 is trained using supervised learning, where training dataset 1302 includes inputs paired with expected outputs for the inputs, or where training dataset 1302 includes inputs with known outputs and the outputs of neural network 1306 are manually graded. In at least one embodiment, untrained neural network 1306 is trained in a supervised manner, processing inputs from training dataset 1302 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 1306. In at least one embodiment, training framework 1304 adjusts the weights that control untrained neural network 1306. In at least one embodiment, training framework 1304 includes tools for monitoring the degree to which untrained neural network 1306 converges toward a model (such as trained neural network 1308) suitable for generating correct answers (such as results 1314) based on input data (such as new dataset 1312). In at least one embodiment, the training framework 1304 iteratively trains the untrained neural network 1306 while adjusting the weights to refine the output of the untrained neural network 1306 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1304 trains the untrained neural network 1306 until the untrained neural network 1306 reaches a desired accuracy. In at least one embodiment, the trained neural network 1308 can then be deployed to implement any number of machine learning operations.

[0193] In at least one embodiment, untrained neural network 1306 is trained using unsupervised learning, wherein untrained neural network 1306 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1302 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1306 can learn groupings within training dataset 1302 and can determine how individual inputs relate to untrained dataset 1302. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1308, which can perform operations useful for reducing the dimensionality of new dataset 1312. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1312 that deviate from the normal pattern of new dataset 1312.

[0194] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1302. In at least one embodiment, the training framework 1304 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1308 to adapt to new datasets 1312 without forgetting the knowledge that was infused into the trained neural network 1308 during initial training.

[0195] In at least one embodiment, the training framework 1304 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 1215 or uses logic 1215 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0196] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0197] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or their variants.

[0198] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0199] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0200] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0201] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0202] Data Center

[0203] Figure 14 An example data center 1400 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1400 includes a data center infrastructure layer 1410, a framework layer 1420, a software layer 1430, and an application layer 1440.

[0204] In at least one embodiment, Figure 14As shown, the data center infrastructure layer 1410 may include a resource coordinator 1412, grouped computing resources 1414, and node computing resources ("node CRs") 1416(1)-1416(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1416(1)-1416(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1418(1)-1418(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1416(1)-1416(N) may be a server having one or more of the above-mentioned computing resources.

[0205] In at least one embodiment, the grouped computing resources 1414 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks housed in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1414 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0206] In at least one embodiment, resource coordinator 1412 may configure or otherwise control one or more nodes CR 1416(1)-1416(N) and / or grouped computing resources 1414. In at least one embodiment, resource coordinator 1412 may comprise a software design infrastructure ("SDI") management entity for data center 1400. In at least one embodiment, resource coordinator 1412 may comprise hardware, software, or some combination thereof.

[0207] In at least one embodiment, Figure 14As shown, the framework layer 1420 includes a job scheduler 1422, a configuration manager 1424, a resource manager 1426, and a distributed file system 1428. In at least one embodiment, the framework layer 1420 may include a framework that supports software 1432 of the software layer 1430 and / or one or more applications 1442 of the application layer 1440. In at least one embodiment, the software 1432 or the application 1442 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1420 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1428 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1422 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1400. In at least one embodiment, the configuration manager 1424 may be capable of configuring different layers, such as the software layer 1430 and the framework layer 1420 including Spark and a distributed file system 1428 for supporting large-scale data processing. In at least one embodiment, the resource manager 1426 may be capable of managing the mapping or allocation of clustered or grouped computing resources to support the distributed file system 1428 and the job scheduler 1422. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 1414 at the data center infrastructure layer 1410. In at least one embodiment, the resource manager 1426 may coordinate with the resource coordinator 1412 to manage these mapped or allocated computing resources.

[0208] In at least one embodiment, the software 1432 included in the software layer 1430 may include software used by at least portions of the node CRs 1416(1)-1416(N), the grouped computing resources 1414, and / or the distributed file system 1428 of the framework layer 1420. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0209] In at least one embodiment, the one or more applications 1442 included in the application layer 1440 may include one or more types of applications used by at least portions of the node CRs 1416(1)-1416(N), the grouped computing resources 1414, and / or the distributed file system 1428 of the framework layer 1420. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0210] In at least one embodiment, any of configuration manager 1424, resource manager 1426, and resource coordinator 1412 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1400 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0211] In at least one embodiment, data center 1400 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1400. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1400.

[0212] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0213] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12BDetails are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in data center 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0214] In at least one embodiment, Figure 14 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 14 The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 14 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0215] autonomous vehicles

[0216] Figure 15A An example of an autonomous vehicle 1500 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1500 (alternatively referred to herein as "vehicle 1500") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1500 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1500 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0217] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of the standards). In at least one embodiment, the vehicle 1500 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1500 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0218] In at least one embodiment, vehicle 1500 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1500 may include, but is not limited to, a propulsion system 1550, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1550 may be connected to a drive train of vehicle 1500, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1500. In at least one embodiment, propulsion system 1550 may be controlled in response to receiving a signal from throttle / accelerator 1552.

[0219] In at least one embodiment, when propulsion system 1550 is operating (e.g., when vehicle 1500 is in motion), a steering system 1554 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1500 (e.g., along a desired path or route). In at least one embodiment, steering system 1554 may receive signals from steering actuator 1556. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1546 may be used to operate vehicle brakes in response to signals received from brake actuator 1548 and / or brake sensors.

[0220] In at least one embodiment, one or more controllers 1536, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 15A) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1500. For example, in at least one embodiment, one or more controllers 1536 can send signals to operate vehicle brakes via brake actuator 1548, operate steering system 1554 via one or more steering actuators 1556, and operate propulsion system 1550 via one or more throttle / accelerator 1552. In at least one embodiment, one or more controllers 1536 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1500. In at least one embodiment, one or more controllers 1536 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0221] In at least one embodiment, the one or more controllers 1536 provide signals for controlling one or more components and / or systems of the vehicle 1500 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1558 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1560, one or more ultrasonic sensors 1562, one or more LIDAR sensors 1564, one or more inertial measurement unit (IMU) sensors 1566 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1596, one or more stereo cameras 1568, one or more wide angle cameras 1570 (e.g., fisheye cameras), one or more infrared cameras 1572, one or more surround cameras 1574 (e.g., 360 degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 15A Not shown), mid-range camera ( Figure 15A), one or more speed sensors 1544 (e.g., for measuring the speed of the vehicle 1500), one or more vibration sensors 1542, one or more steering sensors 1540, one or more brake sensors (e.g., as part of a brake sensor system 1546), and / or other sensor types.

[0222] In at least one embodiment, one or more controllers 1536 may receive input (e.g., represented by input data) from a dashboard 1532 of the vehicle 1500 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1534, an audible annunciator, a speaker, and / or via other components of the vehicle 1500. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 15A ), location data (e.g., the location of the vehicle 1500, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1536, etc. For example, in at least one embodiment, the HMI display 1534 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0223] In at least one embodiment, the vehicle 1500 further includes a network interface 1524 that can communicate over one or more networks using one or more wireless antennas 1526 and / or one or more modems. For example, in at least one embodiment, the network interface 1524 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1526 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, and the like protocols).

[0224] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12BDetails are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in vehicle 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0225] In at least one embodiment, Figure 15A The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 15A The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 15A The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0226] Figure 15B According to at least one embodiment, Figure 15A 1500. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1500.

[0227] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1500. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0228] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0229] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1500 (e.g., reflected light from the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0230] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1500 can be used for surround vision to help identify the path ahead and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1536 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0231] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1570 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 15B Only one wide-angle camera 1570 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1500. In at least one embodiment, any number of remote cameras 1598 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1598 can also be used for object detection and classification and basic object tracking.

[0232] In at least one embodiment, any number of stereo cameras 1568 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1568 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1500's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1568 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1500 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1568 may be used in addition to or in place of those described herein.

[0233] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1500 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1574 (e.g., Figure 15B Four surround cameras (shown) can be positioned on the vehicle 1500. In at least one embodiment, the one or more surround cameras 1574 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1500. In at least one embodiment, the vehicle 1500 can use three surround cameras 1574 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0234] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1500 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1598 and / or one or more mid-range cameras 1576, one or more stereo cameras 1568, one or more infrared cameras 1572, etc.), as described herein.

[0235] In at least one embodiment, Figure 15B The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 15B The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 15B The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0236] Figure 15C is a diagram illustrating a method according to at least one embodiment Figure 15A A block diagram of an example system architecture for an autonomous vehicle 1500 is provided. In at least one embodiment, Figure 15CEach of the components, features, and systems of vehicle 1500 is shown as being connected via bus 1502. In at least one embodiment, bus 1502 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1500 that assists in controlling various features and functions of vehicle 1500, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1502 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1502 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1502 can be an ASIL B compliant CAN bus.

[0237] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1502, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1502 may communicate with any component of vehicle 1500, and two or more buses in bus 1502 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1504 (e.g., SoC 1504(A) and SoC 1504(B)), each of one or more controllers 1536, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1500) and can be connected to a common bus, such as a CAN bus.

[0238] In at least one embodiment, the vehicle 1500 may include one or more controllers 1536, such as those described herein with respect to Figure 15A In at least one embodiment, the controller 1536 can be used for a variety of functions. In at least one embodiment, the controller 1536 can be coupled to any of the various other components and systems of the vehicle 1500 and can be used to control the vehicle 1500, the artificial intelligence of the vehicle 1500, the infotainment and / or other functions of the vehicle 1500.

[0239] In at least one embodiment, the vehicle 1500 may include any number of SoCs 1504. In at least one embodiment, each of the SoCs 1504 may include, but is not limited to, a central processing unit ("CPU(s)") 1506, a graphics processing unit ("GPU(s")) 1508, one or more processors 1510, one or more caches 1512, one or more accelerators 1514, one or more data stores 1516, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1504 may be used to control the vehicle 1500 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1504 may be combined in a system (e.g., a system of the vehicle 1500) along with a high-definition ("HD") map 1522 that may be downloaded from one or more servers (e.g., a system of the vehicle 1500) via a network interface 1524. Figure 15C ) to obtain map refreshes and / or updates.

[0240] In at least one embodiment, one or more CPUs 1506 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1506 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1506 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1506 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1506 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1506 may be active at any given time.

[0241] In at least one embodiment, one or more CPUs 1506 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1506 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0242] In at least one embodiment, one or more GPUs 1508 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1508 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1508 may utilize an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1508 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1508 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1508 may utilize one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1508 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0243] In at least one embodiment, one or more GPUs 1508 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1508 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0244] In at least one embodiment, one or more GPUs 1508 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0245] In at least one embodiment, one or more GPUs 1508 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1508 to directly access one or more CPU 1506 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1508 experiences a miss, an address translation request may be sent to one or more CPUs 1506. In response, in at least one embodiment, two of the one or more CPUs 1506 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1508. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1506 and the one or more GPUs 1508, thereby simplifying programming the one or more GPUs 1508 and porting applications to the one or more GPUs 1508.

[0246] In at least one embodiment, one or more GPUs 1508 may include any number of access counters that can track the frequency with which one or more GPUs 1508 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0247] In at least one embodiment, one or more SoCs 1504 may include any number of caches 1512, including those described herein. For example, in at least one embodiment, one or more caches 1512 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1506 and one or more GPUs 1508. In at least one embodiment, one or more caches 1512 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0248] In at least one embodiment, one or more SoCs 1504 may include one or more accelerators 1514 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1504 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1508 and offload some tasks of one or more GPUs 1508 (e.g., to free up more cycles of one or more GPUs 1508 to perform other tasks). In at least one embodiment, one or more accelerators 1514 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network (“RCNN”) and a fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0249] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0250] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1508, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1508. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1508 and / or one or more accelerators 1514.

[0251] In at least one embodiment, one or more accelerators 1514 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1538, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0252] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0253] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1506. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0254] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0255] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0256] In at least one embodiment, one or more accelerators 1514 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1514. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0257] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0258] In at least one embodiment, one or more SoCs 1504 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0259] In at least one embodiment, one or more accelerators 1514 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the domain of algorithms that require predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1500, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0260] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0261] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0262] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1566 associated with vehicle 1500 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1564 or one or more RADAR sensors 1560).

[0263] In at least one embodiment, one or more SoCs 1504 may include one or more data stores 1516 (e.g., memory). In at least one embodiment, one or more data stores 1516 may be on-chip memory of one or more SoCs 1504 that may store neural networks to be executed on one or more GPUs 1508 and / or DLAs. In at least one embodiment, one or more data stores 1516 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 1516 may include one or more L2 or L3 caches.

[0264] In at least one embodiment, one or more SoCs 1504 may include any number of processors 1510 (e.g., embedded processors). In at least one embodiment, one or more processors 1510 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1504 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1504 thermal and temperature sensors, and / or manage one or more SoCs 1504 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1504 may use the ring oscillator to detect the temperature of one or more CPUs 1506, one or more GPUs 1508, and / or one or more accelerators 1514. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1504 into a lower power state and / or place the vehicle 1500 into a driver's safe parking mode (e.g., bringing the vehicle 1500 to a safe stop).

[0265] In at least one embodiment, one or more processors 1510 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0266] In at least one embodiment, one or more processors 1510 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0267] In at least one embodiment, one or more processors 1510 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1510 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1510 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0268] In at least one embodiment, one or more processors 1510 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1570, one or more surround cameras 1574, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1504, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0269] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0270] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1508 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1508 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1508 to improve performance and responsiveness.

[0271] In at least one embodiment, one or more of the SoCs 1504 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1504 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0272] In at least one embodiment, one or more of the SoCs 1504 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1504 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1564, one or more RADAR sensors 1560, etc., which may be connected via an Ethernet channel), data from the bus 1502 (e.g., vehicle 1500 speed, steering wheel position, etc.), data from one or more GNSS sensors 1558 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1504 may further include dedicated high-performance large-scale storage controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1506 from routine data management tasks.

[0273] In at least one embodiment, one or more SoCs 1504 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1504 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1514, when combined with one or more CPUs 1506, one or more GPUs 1508, and one or more data stores 1516, can provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0274] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0275] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1520) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0276] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1508.

[0277] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1500. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1504 provide protection against theft and / or carjacking.

[0278] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1596 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1504 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1558. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1562 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0279] In at least one embodiment, the vehicle 1500 may include one or more CPUs 1518 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1504 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1518 may include, for example, an X86 processor. The one or more CPUs 1518 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1504, and / or monitoring the status and health of one or more controllers 1536 and / or an infotainment system on a chip ("infotainment SoC") 1530. In at least one embodiment, the SoC 1504 includes one or more interconnects, and the interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0280] In at least one embodiment, the vehicle 1500 may include one or more GPUs 1520 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1504 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1520 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1500 (e.g., sensor data).

[0281] In at least one embodiment, vehicle 1500 may further include a network interface 1524, which may include, but is not limited to, one or more wireless antennas 1526 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1524 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1500 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1500 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1500). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1500.

[0282] In at least one embodiment, the network interface 1524 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1536 to communicate over a wireless network. In at least one embodiment, the network interface 1524 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0283] In at least one embodiment, the vehicle 1500 may further include one or more data stores 1528, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1504) storage. In at least one embodiment, the one or more data stores 1528 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0284] In at least one embodiment, the vehicle 1500 may further include one or more GNSS sensors 1558 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1558 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0285] In at least one embodiment, the vehicle 1500 may further include one or more RADAR sensors 1560. In at least one embodiment, the one or more RADAR sensors 1560 may be used by the vehicle 1500 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1560 may use a CAN bus and / or bus 1502 (e.g., for transmitting data generated by the one or more RADAR sensors 1560) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1560 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1560 are pulse Doppler RADAR sensors.

[0286] In at least one embodiment, one or more RADAR sensors 1560 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1560 can help distinguish between static objects and moving objects and can be used by the ADAS system 1538 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1560 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1500 at a higher speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1500 .

[0287] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1560 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1538 for blind spot detection and / or lane change assistance.

[0288] In at least one embodiment, the vehicle 1500 may further include one or more ultrasonic sensors 1562. In at least one embodiment, one or more ultrasonic sensors 1562, which may be positioned at the front, rear, and / or side of the vehicle 1500, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1562 may be used, and different ultrasonic sensors 1562 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1562 may operate at an ASIL B functional safety level.

[0289] In at least one embodiment, the vehicle 1500 can include one or more LIDAR sensors 1564. In at least one embodiment, the one or more LIDAR sensors 1564 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1564 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1500 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1564 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0290] In at least one embodiment, one or more LIDAR sensors 1564 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1564 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1564 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of vehicle 1500. In at least one embodiment, one or more LIDAR sensors 1564 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1564 may be configured for a horizontal field of view between 45 and 135 degrees.

[0291] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1500. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1500 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1500. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0292] In at least one embodiment, the vehicle 1500 may also include one or more IMU sensors 1566. In at least one embodiment, the one or more IMU sensors 1566 may be located at the center of the rear axle of the vehicle 1500. In at least one embodiment, the one or more IMU sensors 1566 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1566 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1566 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0293] In at least one embodiment, the one or more IMU sensors 1566 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1566 can enable the vehicle 1500 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1566, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1566 and the one or more GNSS sensors 1558 can be combined in a single integrated unit.

[0294] In at least one embodiment, vehicle 1500 can include one or more microphones 1596 positioned within and / or around vehicle 1500. In at least one embodiment, one or more microphones 1596 can be used for emergency vehicle detection and identification.

[0295] In at least one embodiment, the vehicle 1500 may further include any number of camera types, including one or more stereo cameras 1568, one or more wide angle cameras 1570, one or more infrared cameras 1572, one or more surround cameras 1574, one or more long range cameras 1598, one or more mid range cameras 1576, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1500. In at least one embodiment, the type of camera used depends on the vehicle 1500. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1500. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1500 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the various embodiments of the present invention. Figure 15A and Figure 15B Each camera is described in more detail.

[0296] In at least one embodiment, vehicle 1500 may further include one or more vibration sensors 1542. In at least one embodiment, one or more vibration sensors 1542 may measure vibration of a component (e.g., an axle) of vehicle 1500. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1542 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0297] In at least one embodiment, the vehicle 1500 may include an ADAS system 1538. In at least one embodiment, the ADAS system 1538 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1538 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0298] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1560, one or more LIDAR sensors 1564, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1500 and automatically adjusts the speed of the vehicle 1500 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1500 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0299] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1524 and / or one or more wireless antennas 1526. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1500 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1500, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0300] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1560, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0301] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0302] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1500 crosses a lane marking. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1500 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1500.

[0303] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0304] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1500 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0305] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1500 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1536). For example, in at least one embodiment, the ADAS system 1538 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1538 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0306] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0307] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1504.

[0308] In at least one embodiment, the ADAS system 1538 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0309] In at least one embodiment, the output of the ADAS system 1538 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1538 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0310] In at least one embodiment, the vehicle 1500 may further include an infotainment SoC 1530 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1530 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1530 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1500. For example, the infotainment SoC 1530 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1534, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1530 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1500, such as information from an ADAS system 1538, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0311] In at least one embodiment, the infotainment SoC 1530 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1530 can communicate with other devices, systems, and / or components of the vehicle 1500 via the bus 1502. In at least one embodiment, the infotainment SoC 1530 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1536 (e.g., the vehicle's 1500 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1530 can place the vehicle 1500 in a driver-to-safety parking mode, as described herein.

[0312] In at least one embodiment, the vehicle 1500 may further include an instrument panel 1532 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1532 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1532 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1530 and the instrument panel 1532. In at least one embodiment, the instrument panel 1532 may be included as part of the infotainment SoC 1530, or vice versa.

[0313] In at least one embodiment, Figure 15C The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 15C The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 15C The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0314] Figure 15D In accordance with at least one embodiment, one or more cloud-based servers and Figure 15AFIG1 is a diagram of a system for communicating between autonomous vehicles 1500. In at least one embodiment, the system may include, but is not limited to, one or more servers 1578, one or more networks 1590, and any number and type of vehicles, including vehicle 1500. In at least one embodiment, one or more servers 1578 may include, but is not limited to, multiple GPUs 1584(A)-1584(H) (collectively referred to herein as GPUs 1584), PCIe switches 1582(A)-1582(D) (collectively referred to herein as PCIe switches 1582), and / or CPUs 1580(A)-1580(B) (collectively referred to herein as CPUs 1580). In at least one embodiment, GPUs 1584, CPUs 1580, and PCIe switches 1582 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1588 and / or PCIe connection 1586 developed by NVIDIA. In at least one embodiment, the GPUs 1584 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1584 and PCIe switches 1582 are connected via PCIe interconnects. Although eight GPUs 1584, two CPUs 1580, and four PCIe switches 1582 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1578 may include, but is not limited to, any number of GPUs 1584, CPUs 1580, and / or PCIe switches 1582 in any combination. For example, in at least one embodiment, one or more servers 1578 may each include eight, sixteen, thirty-two, and / or more GPUs 1584.

[0315] In at least one embodiment, one or more servers 1578 may receive image data representing an image from a vehicle via one or more networks 1590 that depicts an unexpected or altered road condition, such as a recently begun road project. In at least one embodiment, one or more servers 1578 may transmit an updated neural network 1592 and / or map information 1594 to the vehicle via one or more networks 1590, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1594 may include, but not limited to, updates to the HD map 1522, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1592 and / or map information 1594 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1578 and / or other servers).

[0316] In at least one embodiment, one or more servers 1578 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1590, and / or the machine learning model can be used by one or more servers 1578 to remotely monitor the vehicle.

[0317] In at least one embodiment, one or more servers 1578 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1578 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1584, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1578 can include the deep learning infrastructure of a data center using CPU power.

[0318] In at least one embodiment, the deep learning infrastructure of one or more servers 1578 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1500. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1500, such as an image sequence and / or objects that the vehicle 1500 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1500, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1500 is malfunctioning, the one or more servers 1578 may send a signal to the vehicle 1500 instructing the vehicle's 1500 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0319] In at least one embodiment, one or more servers 1578 may include one or more GPUs 1584 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-powered servers and inference acceleration can enable real-time responses. In at least one embodiment, servers powered by CPUs, FPGAs, and other processors can be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 1215 are used to execute one or more embodiments. Figure 12A and / or Figure 12B Provides details about the hardware structure 1215.

[0320] Computer system

[0321] Figure 16 16 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1600 may include, but is not limited to, components such as processor 1602 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1600 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1600 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0322] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0323] In at least one embodiment, computer system 1600 may include, but is not limited to, a processor 1602, which may include, but is not limited to, one or more execution units 1608 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, computer system 1600 is a single-processor desktop or server system, but in another embodiment, computer system 1600 may be a multi-processor system. In at least one embodiment, processor 1602 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1602 may be coupled to a processor bus 1610, which may transmit data signals between processor 1602 and other components in computer system 1600.

[0324] In at least one embodiment, processor 1602 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1604. In at least one embodiment, processor 1602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1602. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1606 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0325] In at least one embodiment, an execution unit 1608, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1602. In at least one embodiment, the processor 1602 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1608 may include logic for processing a packed instruction set 1609. In at least one embodiment, by including the packed instruction set 1609 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1602. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0326] In at least one embodiment, execution unit 1608 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1600 may include, but is not limited to, memory 1620. In at least one embodiment, memory 1620 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1620 may store one or more instructions 1619 and / or data 1621 represented by data signals that may be executed by processor 1602.

[0327] In at least one embodiment, the system logic chip can be coupled to the processor bus 1610 and the memory 1620. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1616, and the processor 1602 can communicate with the MCH 1616 via the processor bus 1610. In at least one embodiment, the MCH 1616 can provide a high-bandwidth memory path 1618 to the memory 1620 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1616 can direct data signals between the processor 1602, the memory 1620, and other components in the computer system 1600, and bridge data signals between the processor bus 1610, the memory 1620, and the system I / O interface 1622. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1616 may be coupled to the memory 1620 via a high-bandwidth memory path 1618 , and the graphics / video card 1612 may be coupled to the MCH 1616 via an accelerated graphics port (“AGP”) interconnect 1614 .

[0328] In at least one embodiment, computer system 1600 may use system I / O interface 1622 as a proprietary hub interface bus to couple MCH 1616 to I / O controller hub ("ICH") 1630. In at least one embodiment, ICH 1630 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1620, chipset, and processor 1602. Examples may include, but are not limited to, an audio controller 1229, a firmware hub ("flash BIOS") 1628, a wireless transceiver 1626, a data store 1624, a legacy I / O controller 1623 including a user input and keyboard interface 1625, a serial expansion port 1627 (such as a universal serial bus ("USB") port), and a network controller 1634. In at least one embodiment, data store 1624 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0329] In at least one embodiment, Figure 16 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 16 An exemplary SoC may be shown. In at least one embodiment, Figure 16The devices shown in FIG16 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1600 are interconnected using a Compute Express Link (CXL) interconnect.

[0330] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in a computer system to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0331] In at least one embodiment, Figure 16 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 16 The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 16 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0332] Figure 17 1 is a block diagram illustrating an electronic device 1700 for utilizing a processor 1710 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1700 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0333] In at least one embodiment, the electronic device 1700 may include, but is not limited to, a processor 1710 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1710 is coupled using a bus or interface, such as an I 2C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 17 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 17 An exemplary SoC may be shown. In at least one embodiment, Figure 17 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 17 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0334] In at least one embodiment, Figure 17 It may include a display 1724, a touch screen 1725, a touchpad 1730, a near field communication unit (“NFC”) 1745, a sensor hub 1740, a thermal sensor 1746, a fast chipset (“EC”) 1735, a trusted platform module (“TPM”) 1738, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1722, a DSP 1760, a drive 1720 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1750, a Bluetooth unit 1752, a wireless wide area network unit (“WWAN”) 1756, a global positioning system (GPS) unit 1755, a camera (“USB 3.0 camera”) 1754 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1715 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0335] In at least one embodiment, other components may be communicatively coupled to processor 1710 via the components described herein. In at least one embodiment, accelerometer 1741, ambient light sensor (“ALS”) 1742, compass 1743, and gyroscope 1744 may be communicatively coupled to sensor hub 1740. In at least one embodiment, thermal sensor 1739, fan 1737, keyboard 1736, and touchpad 1730 may be communicatively coupled to EC 1735. In at least one embodiment, speaker 1763, earphone 1764, and microphone (“mic”) 1765 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1762, which in turn may be communicatively coupled to DSP 1760. In at least one embodiment, audio unit 1762 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1757 may be communicatively coupled to WWAN unit 1756. In at least one embodiment, components such as the WLAN unit 1750 and the Bluetooth unit 1752 and the WWAN unit 1756 may be implemented as a next generation form factor ("NGFF").

[0336] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 may be used in electronic device 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0337] In at least one embodiment, Figure 17 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 17 The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 17 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0338] Figure 18A computer system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1800 is configured to implement the various processes and methods described throughout this disclosure.

[0339] In at least one embodiment, computer system 1800 includes, but is not limited to, at least one central processing unit ("CPU") 1802 connected to a communication bus 1810 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1800 includes, but is not limited to, main memory 1804 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1804, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1822 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1800.

[0340] In at least one embodiment, computer system 1800 includes, but is not limited to, input device 1808, parallel processing system 1812, and display device 1806, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1808 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0341] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in computer system 1800 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0342] In at least one embodiment, Figure 18 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 18The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 18 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0343] Figure 19 A computer system 1900 is shown according to at least one embodiment. In at least one embodiment, computer system 1900 includes, but is not limited to, a computer 1910 and a USB drive 1920. In at least one embodiment, computer 1910 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1910 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0344] In at least one embodiment, the USB disk 1920 includes, but is not limited to, a processing unit 1930, a USB interface 1940, and USB interface logic 1950. In at least one embodiment, the processing unit 1930 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1930 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1930 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1930 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1930 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0345] In at least one embodiment, USB interface 1940 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1940 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1940 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1950 can include any number and type of logic that enables processing unit 1930 to interface with a device (e.g., computer 1910) via USB connector 1940.

[0346] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in computer system 1900 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0347] In at least one embodiment, Figure 19 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 19 The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 19 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0348] Figure 20A An exemplary architecture is shown in which a plurality of GPUs 2010(1)-2010(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed links 2040(1)-2040(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 2040(1)-2040(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 2010(1)-2010(N) include: Figure 23A and Figure 23B2300. In at least one embodiment, one or more graphics cores 2300 may be referred to as streaming multiprocessors ("SMs"), streaming processors ("SPs"), streaming processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where, in this context, a slice may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0349] Furthermore, in at least one embodiment, two or more GPUs 2010 are interconnected via high-speed links 2029(1)-2029(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 2040(1)-2040(N). Similarly, two or more multi-core processors 2005 may be connected via high-speed link 2028, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 20A All communications between the various system components shown in .

[0350] In at least one embodiment, each multi-core processor 2005 is communicatively coupled to processor memory 2001(1)-2001(M) via memory interconnects 2026(1)-2026(M), respectively, and each GPU 2010(1)-2010(N) is communicatively coupled to GPU memory 2020(1)-2020(N) via GPU memory interconnects 2050(1)-2050(N), respectively. In at least one embodiment, memory interconnects 2026 and 2050 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 2001(1)-2001(M) and GPU memory 2020 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 2001 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0351] As described herein, although each multi-core processor 2005 and GPU 2010 can be physically coupled to a specific memory 2001, 2020, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 2001(1)-2001(M) can each include 64GB of system memory address space, and GPU memories 2020(1)-2020(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0352] Figure 20B Additional details are shown for the interconnection between the multi-core processor 2007 and the graphics acceleration module 2046 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 2046 may include one or more GPU chips integrated on a line card that is coupled to the processor 2007 via a high-speed link 2040 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 2046 may alternatively be integrated on a package or chip with the processor 2007.

[0353] In at least one embodiment, the processor 2007 includes a plurality of cores 2060A-2060D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 2061A-2061D and one or more caches 2062A-2062D. In at least one embodiment, the cores 2060A-2060D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 2062A-2062D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 2056 may be included in the caches 2062A-2062D and shared by each group of cores 2060A-2060D. For example, one embodiment of the processor 2007 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 2007 and the graphics acceleration module 2046 are connected to the system memory 2014, which may include Figure 20A Processor memory 2001(1)-2001(M) in.

[0354] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 2062A-2062D, 2056 and system memory 2014 via inter-core communication over a coherence bus 2064. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 2064 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 2064 to snoop cache accesses.

[0355] In at least one embodiment, proxy circuitry 2025 communicatively couples graphics acceleration module 2046 to coherence bus 2064, thereby allowing graphics acceleration module 2046 to participate in a cache coherence protocol as a peer of cores 2060A-2060D. In particular, in at least one embodiment, interface 2035 provides connectivity to proxy circuitry 2025 via high-speed link 2040, and interface 2037 connects graphics acceleration module 2046 to high-speed link 2040.

[0356] In at least one embodiment, the accelerator integrated circuit 2036 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 2031(1)-2031(N) of the graphics acceleration module 2046. In at least one embodiment, the graphics processing engines 2031(1)-2031(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 2031(1)-2031(N) of the graphics acceleration module 2046 include, for example, a combination of Figure 23A and Figure 23B The one or more graphics cores 2300 discussed. In at least one embodiment, the graphics processing engines 2031(1)-2031(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 2046 may be a GPU having multiple graphics processing engines 2031(1)-2031(N), or the graphics processing engines 2031(1)-2031(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0357] In at least one embodiment, the accelerator integrated circuit 2036 includes a memory management unit (MMU) 2039 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 2014. In at least one embodiment, the MMU 2039 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, the cache 2038 may store commands and data for efficient access by the graphics processing engines 2031(1)-2031(N). In at least one embodiment, a fetch unit 2044 may be used to keep data stored in the cache 2038 and graphics memory 2033(1)-2033(M) consistent with the core caches 2062A-2062D, 2056, and system memory 2014. As previously described, this can be implemented on behalf of cache 2038 and memory 2033(1)-2033(M) via proxy circuit 2025 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 2062A-2062D, 2056 to cache 2038 and receiving updates from cache 2038).

[0358] In at least one embodiment, a set of registers 2045 stores context data for threads executed by graphics processing engines 2031(1)-2031(N), and context management circuitry 2048 manages thread contexts. For example, context management circuitry 2048 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 2048 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 2047 receives and processes interrupts received from system devices.

[0359] In at least one embodiment, the MMU 2039 converts virtual / effective addresses from the graphics processing engine 2031 into real / physical addresses in the system memory 2014. In at least one embodiment, the accelerator integrated circuit 2036 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 2046 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 2046 can be dedicated to a single application executing on the processor 2007, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 2031 (1)-2031 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0360] In at least one embodiment, the accelerator integrated circuit 2036 acts as a bridge to the system for the graphics acceleration module 2046 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 2036 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 2031(1)-2031(N).

[0361] In at least one embodiment, because the hardware resources of graphics processing engines 2031(1)-2031(N) are explicitly mapped into the real address space seen by host processor 2007, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 2036 is the physical separation of graphics processing engines 2031(1)-2031(N) so that they appear to the system as independent units.

[0362] In at least one embodiment, one or more graphics memories 2033(1)-2033(M) are coupled to each graphics processing engine 2031(1)-2031(N), respectively, with N=M. In at least one embodiment, graphics memories 2033(1)-2033(M) store instructions and data being processed by each graphics processing engine 2031(1)-2031(N). In at least one embodiment, graphics memories 2033(1)-2033(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0363] In at least one embodiment, to reduce data traffic on high-speed link 2040, a biasing technique may be used to ensure that the data stored in graphics memory 2033(1)-2033(M) is the data most frequently used by graphics processing engines 2031(1)-2031(N), and preferably is not used (at least not frequently) by cores 2060A-2060D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 2031(1)-2031(N)) in caches 2062A-2062D, 2056, and system memory 2014.

[0364] Figure 20C Another exemplary embodiment is shown in which an accelerator integrated circuit 2036 is integrated within the processor 2007. In this embodiment, the graphics processing engines 2031(1)-2031(N) communicate directly with the accelerator integrated circuit 2036 via interface 2037 and interface 2035 (again, which can be any form of bus or interface protocol) over a high-speed link 2040. In at least one embodiment, the accelerator integrated circuit 2036 can perform operations related to Figure 20B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 2064 and caches 2062A-2062D, 2056. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 2036 and a programming model controlled by the graphics acceleration module 2046.

[0365] In at least one embodiment, graphics processing engines 2031(1)-2031(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 2031(1)-2031(N), thereby providing virtualization within a VM / partition.

[0366] In at least one embodiment, graphics processing engines 2031(1)-2031(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 2031(1)-2031(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 2031(1)-2031(N). In at least one embodiment, the operating system can virtualize graphics processing engines 2031(1)-2031(N) to provide access to each process or application.

[0367] In at least one embodiment, the graphics acceleration module 2046 or the individual graphics processing engines 2031(1)-2031(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 2014 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 2031(1)-2031(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0368] Figure 20D An exemplary accelerator integrated slice 2090 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 2036. In at least one embodiment, the application is an effective address space 2082 in system memory 2014, which stores a process element 2083. In at least one embodiment, the process element 2083 is stored in response to a GPU call 2081 from the application 2080 executing on the processor 2007. In at least one embodiment, the process element 2083 contains the process state of the corresponding application 2080. In at least one embodiment, the work descriptor (WD) 2084 contained in the process element 2083 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 2084 is a pointer to a job request queue in the effective address space 2082 of the application.

[0369] In at least one embodiment, the graphics acceleration module 2046 and / or the individual graphics processing engines 2031(1)-2031(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 2084 to the graphics acceleration module 2046 to start a job in a virtualized environment.

[0370] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either a graphics acceleration module 2046 or an individual graphics processing engine 2031. In at least one embodiment, when a graphics acceleration module 2046 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 2046 is assigned, the operating system initializes the accelerator integrated circuit 2036 for the owned process.

[0371] In at least one embodiment, in operation, a WD fetch unit 2091 in the accelerator integrated slice 2090 fetches a next WD 2084, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 2046. In at least one embodiment, data from the WD 2084 can be stored in registers 2045 and used by the MMU 2039, interrupt management circuitry 2047, and / or context management circuitry 2048, as shown. For example, one embodiment of the MMU 2039 includes segment / page walk circuitry for accessing segment / page tables 2086 within the OS virtual address space 2085. In at least one embodiment, the interrupt management circuitry 2047 can process interrupt events 2092 received from the graphics acceleration module 2046. In at least one embodiment, when performing graphics operations, effective addresses 2093 generated by the graphics processing engines 2031(1)-2031(N) are converted to real addresses by the MMU 2039.

[0372] In at least one embodiment, registers 2045 are replicated for each graphics processing engine 2031(1)-2031(N) and / or graphics acceleration module 2046, and these registers 2045 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 2090. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0373] Table 1 - Registers initialized by the hypervisor

[0374]

[0375]

[0376] Example registers that may be initialized by the operating system are shown in Table 2.

[0377] Table 2 – Registers initialized by the operating system

[0378]

[0379] In at least one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or graphics processing engine 2031(1)-2031(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 2031(1)-2031(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0380] Figure 20E 2096 virtualizes the graphics acceleration module engine for the operating system 2095.

[0381] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 2046. In at least one embodiment, there are two programming models in which the graphics acceleration module 2046 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0382] In at least one embodiment, in this model, the hypervisor 2096 owns the graphics acceleration module 2046 and makes its functionality available to all operating systems 2095. In at least one embodiment, for the graphics acceleration module 2046 to support virtualization through the hypervisor 2096, the graphics acceleration module 2046 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 2046 must provide a context save and restore mechanism, (2) the graphics acceleration module 2046 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 2046 provides the ability to preempt job processing, and (3) the graphics acceleration module 2046 must ensure fairness between processes when operating in a directed shared programming model.

[0383] In at least one embodiment, the application 2080 is required to make an operating system 2095 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 2046 and can take the form of a graphics acceleration module 2046 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 2046.

[0384] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 2036 (not shown) and the graphics acceleration module 2046 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 2096 may selectively apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 2083. In at least one embodiment, the CSRP is one of the registers 2045 that contains the effective address of an area in the application's effective address space 2082 for the graphics acceleration module 2046 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0385] Upon receiving the system call, the operating system 2095 can verify that the application 2080 has been registered and granted permission to use the graphics acceleration module 2046. Then, in at least one embodiment, the operating system 2095 calls the hypervisor 2096 using the information shown in Table 3.

[0386] Table 3 - OS to hypervisor call parameters

[0387]

[0388]

[0389] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1596 verifies that operating system 1595 has registered and been granted permission to use graphics acceleration module 1546. Then, in at least one embodiment, hypervisor 1596 places process element 1583 into a linked list of process elements of the corresponding type of graphics acceleration module 1546. In at least one embodiment, the process element may include the information shown in Table 4.

[0390] Table 4 - Process element information

[0391]

[0392] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 2090 registers 2045 .

[0393] like Figure 20F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 2001(1)-2001(N) and GPU memories 2020(1)-2020(N). In this implementation, operations executed on GPUs 2010(1)-2010(N) utilize the same virtual / effective memory address space to access processor memories 2001(1)-2001(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 2001(1), a second portion is allocated to second processor memory 2001(N), a third portion is allocated to GPU memory 2020(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 2001 and GPU memory 2020, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0394] In at least one embodiment, bias / coherency management circuitry 2094A-2094E within one or more MMUs 2039A-2039E ensures cache coherency between the caches of one or more host processors (e.g., 2005) and GPU 2010 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 20F Multiple instances of bias / coherence management circuits 2094A- 2094E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 2005 and / or within an accelerator integrated circuit 2036 .

[0395] One embodiment allows GPU memory 2020 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 2020 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 2005 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 2020 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 2010. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0396] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory per GPU additional page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 2020, with or without a bias cache in the GPU 2010 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0397] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 2020 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 2010 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 2020. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 2005 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 2005 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 2010. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0398] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from the host processor 2005 bias to the GPU bias, but not for the reverse migration.

[0399] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by the host processor 2005. In at least one embodiment, to access these pages, the processor 2005 may request access from the GPU 2010, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 2005 and the GPU 2010, it is beneficial to ensure that the GPU-biased pages are the pages required by the GPU and not the host processor 2005, and vice versa.

[0400] One or more hardware structures 1215 are used to implement one or more embodiments. Figure 12A and / or Figure 12B Details regarding one or more hardware structures 1215 are provided.

[0401] Figure 21An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated ones, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0402] Figure 21 21 is a block diagram illustrating an exemplary system on a chip integrated circuit 2100 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 2100 includes one or more application processors 2105 (e.g., CPUs), at least one graphics processor 2110, and may additionally include an image processor 2115 and / or a video processor 2120, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 2100 includes peripheral or bus logic including a USB controller 2125, a UART controller 2130, an SPI / SDIO controller 2135, and an I / O controller. 2 S / I 2 C controller 2140. In at least one embodiment, the integrated circuit 2100 may include a display device 2145 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2150 and a Mobile Industry Processor Interface (MIPI) display interface 2155. In at least one embodiment, storage may be provided by a flash memory subsystem 2160, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2170.

[0403] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 may be used in integrated circuit 2100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0404] In at least one embodiment, Figure 21 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 21The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 21 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0405] Figures 22A-22B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0406] Figures 22A-22B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 22A An exemplary graphics processor 2210 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 22B An additional exemplary graphics processor 2240 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 22A The graphics processor 2210 is a low-power graphics processor core. In at least one embodiment, Figure 22B The graphics processor 2240 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2210, 2240 can be Figure 21 A variant of the graphics processor 2110.

[0407] In at least one embodiment, the graphics processor 2210 includes a vertex processor 2205 and one or more fragment processors 2215A-2215N (e.g., 2215A, 2215B, 2215C, 2215D through 2215N-1 and 2215N). In at least one embodiment, the graphics processor 2210 can execute different shader programs via separate logic, such that the vertex processor 2205 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2215A-2215N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2205 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2215A-2215N use the primitives and vertex data generated by the vertex processor 2205 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2215A-2215N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0408] In at least one embodiment, the graphics processor 2210 additionally includes one or more memory management units (MMUs) 2220A-2220B, one or more caches 2225A-2225B, and one or more circuit interconnects 2230A-2230B. In at least one embodiment, the one or more MMUs 2220A-2220B provide virtual to physical address mapping for the graphics processor 2210 (including for the vertex processor 2205 and / or the fragment processors 2215A-2215N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2225A-2225B. In at least one embodiment, the one or more MMUs 2220A-2220B can synchronize with other MMUs within the system, including with Figure 21 One or more MMUs associated with one or more application processors 2105, graphics processor 2115, and / or video processor 2120 enable each processor 2105-2120 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2230A-2230B enable the graphics processor 2210 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0409] In at least one embodiment, graphics processor 2240 includes the following: Figure 22B One or more shader cores 2255A-2255N (e.g., 2255A, 2255B, 2255C, 2255D, 2255E, 2255F through 2255N-1 and 2255N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2240 includes an inter-core task manager 2245 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2255A-2255N and a tiling unit 2258 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0410] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 may be used in graphics processors 2210 and / or 2240 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0411] In at least one embodiment, Figures 22A-22B The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figures 22A-22B The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figures 22A-22B The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0412] Figures 23A-23B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 23A-23B Chinese diagram and combination Figures 23A-23BThe components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. In at least one embodiment, Figure 23A Shows that can be included in Figure 21 Graphics core 2300 within graphics processor 2110 of FIG. 1 and, in at least one embodiment, may be such as Figure 22B Unified shader cores 2255A-2255N are shown. Figure 23B A highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 2330 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics processing unit 2330 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 2100 includes graphics core 2300, for example, to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0413] In at least one embodiment, graphics core 2300 includes a shared instruction cache 2302, texture units 2318, and cache / shared memory 2320 (e.g., including L1, L2, L3, last level cache, or other caches), which are common to execution resources within graphics core 2300. In at least one embodiment, graphics core 2300 may include multiple slices 2301A-2301N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2300. In at least one embodiment, each slice 2301A-2301N refers to graphics core 2300. In at least one embodiment, slices 2301A-2301N have subslices that are part of slices 2301A-2301N. In at least one embodiment, slices 2301A-2301N may be independent of other slices or dependent on other slices. In at least one embodiment, the slices 2301A-2301N may include support logic including a local instruction cache 2304A-2304N, a thread scheduler (sequencer) 2306A-2306N, a thread dispatcher 2308A-2308N, and a set of registers 2310A-2310N. In at least one embodiment, the slices 2301A-2301N may include a set of additional function units (AFUs 2312A-2312N), floating point units (FPUs 2314A-2314N), integer arithmetic logic units (ALUs 2316A-2316N), address calculation units (ACUs 2313A-2313N), double precision floating point units (DPFPUs 2315A-2315N), and matrix processing units (MPUs 2317A-2317N). In at least one embodiment, the MPUs 2317A-2317N are referred to as a matrix engine.

[0414] In at least one embodiment, each slice 2301A-2301N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data set workloads. In at least one embodiment, one or more slices 2301A-2301N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 2301A-2301N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, wherein the vector engines and math units are exposed through matrix expansion. In at least one embodiment, a designated portion of the processing resources of a processing unit (e.g., 16 cores and ray tracing units or 8 cores), a thread scheduler, a thread distributor, and additional functional units of the processor are sliced. In at least one embodiment, graphics core 2300 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0415] In at least one embodiment, one or more slices 2301A-2301N include one or more ray tracing units for computing ray tracing operations (e.g., slices 2301A-2301N, 16 ray tracing units per slice). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0416] In at least one embodiment, one or more slices 2301A-2301N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0417] In at least one embodiment, one or more slices 2301A-2301N are linked to L2 cache and memory structures, link connectors, high bandwidth memory (HBM) (e.g., HBM2e, HDMI3) stacks, and media engines. In at least one embodiment, one or more slices 2301A-2301N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2301A-2301N have one or more L1 caches. In at least one embodiment, one or more slices 2301A-2301N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 2301A-2301N include memory structures, such as an L2 cache.

[0418] In at least one embodiment, the FPUs 2314A-2314N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2315A-2315N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2316A-2316N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2317A-2317N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2317A-2317N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2312A-2312N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0419] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 may be used in graphics core 2300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0420] In at least one embodiment, graphics core 2300 includes an interconnect and link fabric sublayer attached to a switch and GPU-GPU bridge that enables multiple graphics processors 2300 (e.g., 8) to be interconnected without glue to each other via load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 2300. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0421] In at least one embodiment, the graphics core 2300 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where a single die can be connected to an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 2300 includes compute tiles, memory tiles (e.g., where a memory tile can be exclusively accessed by different tiles or different chipsets (such as a Rambo tile)), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, where all tiles are packaged together in the graphics core 2300 as part of the GPU. In at least one embodiment, the graphics core 2300 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have eight graphics cores 2300, an L1 cache, and a base tile can have host interfaces with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the tiles are connected with face-to-face (F2F) chip-on-chip bonding via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 2300 includes a memory structure that includes memory and is accessible to multiple tiles. In at least one embodiment, the graphics core 2300 stores, accesses, or loads its own hardware context into memory, where the hardware context is a set of data loaded from registers before a process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0422] In at least one embodiment, graphics core 2300 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or converts a parallel data stream into a serial data stream.

[0423] In at least one embodiment, graphics core 2300 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0424] In at least one embodiment, the graphics core 2300 executes an API that abstracts the graphics core 2300 hardware and uses instructions to access libraries to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0425] In at least one embodiment, Figure 23A The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 23A The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 23A The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0426] Figure 23BA GPGPU 2330 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 2330 can be directly linked to other instances of GPGPU 2330 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2330 includes a host interface 2332 for connecting to a host processor. In at least one embodiment, host interface 2332 is a PCI Express interface. In at least one embodiment, host interface 2332 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2330 receives commands from the host processor and uses a global scheduler 2334 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 2336A-2336H. In at least one embodiment, compute clusters 2336A-2336H share a cache memory 2338. In at least one embodiment, cache memory 2338 may be used as a higher level cache for cache memory within compute clusters 2336A-2336H. In at least one embodiment, compute clusters 2336A-2336H include slices or are referred to as "slices." In at least one embodiment, GPGPU 2330 is part of a SoC, such as part of integrated circuit 2100 ( Figure 21 ).

[0427] In at least one embodiment, GPGPU 2330 includes memory 2344A-2344B coupled to compute clusters 2336A-2336H via a set of memory controllers 2342A-2342B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2344A-2344B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0428] In at least one embodiment, the computing clusters 2336A-2336H each include a set of graphics cores, such as Figure 23AThe graphics core 2300 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2336A-2336H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0429] In at least one embodiment, multiple instances of GPGPU 2330 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2336A-2336H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 2330 communicate via host interface 2332. In at least one embodiment, GPGPU 2330 includes an I / O hub 2339 that couples GPGPU 2330 to a GPU link 2340, which enables direct connections to other instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2330 are located in separate data processing systems and communicate via a network device accessible via host interface 2332. In at least one embodiment, GPU link 2340 may be configured to enable connection to a host processor in addition to or in lieu of host interface 2332 .

[0430] In at least one embodiment, the GPGPU 2330 can be configured to train a neural network. In at least one embodiment, the GPGPU 2330 can be used within an inference platform. In at least one embodiment, when using the GPGPU 2330 for inference, the GPGPU 2330 can include fewer compute clusters 2336A-2336H than when using the GPGPU 2330 for training a neural network. In at least one embodiment, the memory technology associated with the memories 2344A-2344B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2330 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0431] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 may be used in GPGPU 2330 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0432] In at least one embodiment, Figure 23B The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 23B The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 23B The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0433] Figure 24 24 is a block diagram illustrating a computing system 2400 according to at least one embodiment. In at least one embodiment, computing system 2400 includes a processing subsystem 2401 having one or more processors 2402 and system memory 2404 communicating via an interconnect path that may include a memory hub 2405. In at least one embodiment, memory hub 2405 may be a separate component within a chipset assembly or may be integrated within one or more processors 2402. In at least one embodiment, memory hub 2405 is coupled to an I / O subsystem 2411 via a communication link 2406. In at least one embodiment, I / O subsystem 2411 includes an I / O hub 2407, which enables computing system 2400 to receive input from one or more input devices 2408. In at least one embodiment, I / O hub 2407 may enable a display controller, which may be included in one or more processors 2402, to provide output to one or more display devices 2410A. In at least one embodiment, the one or more display devices 2410A coupled to the I / O hub 2407 may include local, internal, or embedded display devices.

[0434] In at least one embodiment, the processing subsystem 2401 includes one or more parallel processors 2412 coupled to a memory hub 2405 via a bus or other communication link 2413. In at least one embodiment, the communication link 2413 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2412 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2412 form a graphics processing subsystem that can output pixels to one of one or more display devices 2410A coupled via an I / O hub 2407. In at least one embodiment, the one or more parallel processors 2412 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 2410B. In at least one embodiment, the one or more parallel processors 2412 include one or more cores, such as the graphics core 2300 discussed herein.

[0435] In at least one embodiment, a system storage unit 2414 can be connected to the I / O hub 2407 to provide a storage mechanism for the computing system 2400. In at least one embodiment, an I / O switch 2416 can be used to provide an interface mechanism for enabling connections between the I / O hub 2407 and other components, such as a network adapter 2418 and / or a wireless network adapter 2419 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2420. In at least one embodiment, the network adapter 2418 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2419 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0436] In at least one embodiment, the computing system 2400 may include other components not explicitly shown that may also be connected to the I / O hub 2407, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Figure 24The communication paths between the various components in the system.

[0437] In at least one embodiment, one or more parallel processors 2412 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 2412 include graphics core 2300. In at least one embodiment, one or more parallel processors 2412 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computing system 2400 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2412, memory hub 2405, one or more processors 2402, and I / O hub 2407 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2400 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2400 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0438] Logic 1215 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 12A and / or Figure 12B Details are provided regarding logic 1215. In at least one embodiment, logic 1215 can be used in computing system 2400 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0439] In at least one embodiment, Figure 24 The components can be used with Figure 1-11 In at least one embodiment, the components, processes and / or combinations thereof are used together or in combination to generate an output image. Figure 24 The component includes one or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users indicating content other than one or more objects in at least one of the two or more different images. In at least one embodiment, Figure 24 The assembly includes one or more circuits for using one or more neural networks to generate two or more images depicting the same object in different settings based at least in part on two or more different input text prompts.

[0440] processor

[0441] Figure 25A 25. The parallel processor 2500 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2500 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (A...

Claims

1. A processor, comprising: One or more circuits for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications from one or more users, the one or more indications indicating content other than the one or more objects of at least one of the two or more different images. 2 . The processor of claim 1 , wherein the one or more objects in the two or more different images comprise the same object.

3. The processor of claim 1 , wherein the one or more neural networks comprise one or more layers that denoise an image to generate the two or more different images.

4. The processor of claim 1, wherein the one or more neural networks comprise a diffusion neural network. 5 . The processor of claim 1 , wherein the one or more indications include one or more input text prompts, wherein the text prompts are generated by one or more users.

6. The processor of claim 1 , wherein the one or more neural networks receive only text prompts as input. 7 . The processor of claim 1 , wherein the one or more objects are the same object in the two or more different images and are in different poses.

8. A system comprising: One or more processors for using one or more neural networks to generate one or more objects in two or more different images based at least in part on one or more indications from one or more users, the one or more indications indicating content other than the one or more objects of at least one of the two or more different images.

9. The system of claim 8, wherein the one or more objects in the two or more different images comprise a same subject.

10. The system of claim 8, wherein the one or more neural networks include one or more layers that denoise the two or more different images.

11. The system of claim 8, wherein the one or more neural networks comprise a diffusion neural network.

12. The system of claim 8, wherein the one or more instructions include one or more input text prompts.

13. The system of claim 8, wherein the one or more neural networks receive only text prompts as input.

14. The system of claim 8, wherein the one or more objects are in different poses in the two or more different images.

15. A method comprising: One or more neural networks are used to generate one or more objects in two or more different images based at least in part on one or more indications of one or more users, the one or more indications indicating content other than the one or more objects of at least one of the two or more different images.

16. The method of claim 15, wherein the one or more objects in the two or more different images comprise the same subject.

17. The method of claim 15, wherein the one or more neural networks include one or more layers that denoise the two or more different images.

18. The method of claim 15, wherein the one or more neural networks comprise a diffusion neural network.

19. The method of claim 15, wherein the one or more indications include one or more input text prompts.

20. The method of claim 15, wherein the one or more neural networks receive only text prompts as input.

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