Scheduling method and device, semiconductor process equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a scheduling method, which comprises the following steps of: when a process path of a plurality of wafers to be discharged is determined, firstly obtaining a wafer state, then determining a plurality of earliest completion times respectively corresponding to a plurality of theoretical wafer discharging sequences according to the wafer state and the process path of the plurality of wafers to be discharged, and finally determining a plurality of theoretical wafer discharging sequences according to the earliest completion times. The method comprises the steps that a plurality of wafers to be discharged are obtained, the shortest earliest completion time in the plurality of earliest completion time is used as the target earliest completion time, and the wafers to be discharged are controlled to be discharged according to the theoretical wafer discharging sequence corresponding to the target earliest completion time, so that the theoretical wafer discharging sequence with the shortest time is selected as the wafer discharging basis of the wafers to be discharged, and the wafer discharging efficiency is improved. Therefore, the time for completing processing of the plurality of wafers to be discharged is shortest, and the total time of the plurality of wafers to be discharged in the semiconductor process equipment after the wafers are discharged is reduced, so that the idle time of each process chamber in the semiconductor process equipment is reduced, and the utilization rate of the process chambers is improved.

Description

Technical Field

[0001] The present specification relates to the field of semiconductor technology, specifically, to equipment scheduling technology in the field of semiconductor technology, and more specifically, to a scheduling method, device, semiconductor process equipment, and computer-readable storage medium. Background Art

[0002] Cluster Tool is a kind of equipment widely used in semiconductor wafer manufacturing. Cluster Tool can include modules such as alignment module (Aligner), robot, vacuum lock (LoadLock), wafer loading and unloading position (LoadPort) and multiple process chambers (Process Chamber). Cluster Tool can realize automatic processing and circulation of wafers.

[0003] In order to improve the working efficiency of cluster equipment, cluster equipment can be used to process multiple types of wafers. However, in the current scheduling technology for multiple types of wafers in cluster equipment, the utilization rate of the process chamber of the cluster equipment is low. Summary of the invention

[0004] The embodiments of this specification provide a scheduling method, an apparatus, semiconductor process equipment, and a computer-readable storage medium to achieve the purpose of providing a scheduling method for improving the utilization rate of a process chamber.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present specification provides a scheduling method applied to a semiconductor process equipment, for determining a processing order of multiple types of wafers in the semiconductor process equipment, wherein the semiconductor process equipment includes a wafer loading and unloading position and a plurality of process chambers, and the scheduling method includes:

[0007] Obtaining a wafer status, where the wafer status is used to characterize a position and a process status of a wafer that has been produced in the semiconductor process equipment;

[0008] According to the wafer status and the process paths of the plurality of wafers to be shipped, a plurality of earliest completion times corresponding to a plurality of theoretical wafer shipment sequences are determined; the plurality of wafers to be shipped include a plurality of different types of wafers located in the wafer loading and unloading positions; the plurality of theoretical wafer shipment sequences include permutations and combinations of the wafer shipment sequences of the plurality of wafers to be shipped; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the plurality of wafers to be shipped according to the theoretical wafer shipment sequence corresponding to the earliest completion time;

[0009] According to the theoretical wafer discharge order corresponding to the target earliest completion time, the plurality of wafers to be discharged are controlled to discharge; the target earliest completion time is the earliest completion time with the shortest time among the plurality of earliest completion times.

[0010] In a second aspect, an embodiment of this specification provides a computing device, including: a processor and a memory;

[0011] Wherein, the memory is connected to the processor, and the memory is used to store a computer program;

[0012] The processor is used to implement the above-mentioned scheduling method by running the computer program stored in the memory.

[0013] On the third aspect, an embodiment of the present specification provides a semiconductor process scheduling device, characterized in that it is used to schedule the processing sequence of multiple types of wafers in a wafer loading and unloading position, and the semiconductor process scheduling device includes: a processor and a memory; a computer program is stored in the memory, and when the processor executes the computer program, it executes any of the scheduling methods described above to control the wafer loading and unloading position to discharge the multiple wafers to be discharged.

[0014] In a fourth aspect, an embodiment of the present specification provides a semiconductor process equipment, including: a wafer loading and unloading position and any of the semiconductor process scheduling equipment described above;

[0015] The wafer loading and unloading position is configured to set a plurality of different types of wafers to be shipped;

[0016] The semiconductor process scheduling device is configured to control the wafer loading and unloading position to discharge the plurality of wafers to be discharged according to any of the scheduling methods described above.

[0017] In a fifth aspect, an embodiment of the present specification provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the scheduling method as described above is implemented.

[0018] In a sixth aspect, an embodiment of the present specification provides a computer program product or a computer program, wherein the computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor implements the steps of the above-mentioned scheduling method when executing the computer program.

[0019] It can be seen from the above technical scheme that the scheduling method provided in the embodiment of this specification first obtains the wafer status when determining the process path of multiple wafers to be discharged, and then determines multiple earliest completion times corresponding to multiple theoretical discharge sequences according to the wafer status and the process path of the multiple wafers to be discharged, and uses the shortest earliest completion time among the multiple earliest completion times as the target earliest completion time, and controls the discharge of the multiple wafers to be discharged according to the theoretical discharge sequence corresponding to the target earliest completion time. In this way, by selecting the shortest theoretical discharge sequence as the discharge basis of the multiple wafers to be discharged, the time taken to complete the processing of the multiple wafers to be discharged is the shortest, which is beneficial to reducing the total time spent by the multiple wafers to be discharged in the semiconductor process equipment after the discharge, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

[0020] When determining multiple earliest completion times corresponding to multiple theoretical wafer delivery orders, they can be obtained based on the wafer status and the process paths of multiple wafers to be delivered, without the need to establish a complex algorithm model. This is beneficial to reducing the complexity of the scheduling algorithm and improving the execution efficiency of the scheduling algorithm.

[0021] In addition, the earliest completion time includes the cleaning time of the process chamber. Thus, the cleaning time of the process chamber is taken into consideration, so that the scheduling method can be applicable to a non-steady-state scheduling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of a semiconductor process equipment provided for one embodiment of the present specification;

[0024] Figure 2 A flowchart of a scheduling method provided for one embodiment of this specification;

[0025] Figure 3 A flowchart of another scheduling method provided for one embodiment of this specification;

[0026] Figure 4 A schematic diagram of the structure of a scheduling device provided for one embodiment of this specification;

[0027] Figure 5A schematic diagram of the structure of another semiconductor process equipment provided for one embodiment of the present specification;

[0028] Figure 6 A schematic diagram of the structure of a computing device provided for one embodiment of the present specification. DETAILED DESCRIPTION

[0029] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the common meanings understood by persons with ordinary skills in the field to which this specification belongs. The words "first", "second" and similar words used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of constituent elements.

[0030] Unless the context requires otherwise, throughout the specification, "plurality" means "at least two", and "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0031] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0032] Overview

[0033] refer to Figure 1 , still taking cluster equipment as an example, Figure 1 The structure diagram of a semiconductor process equipment is shown, and the semiconductor process equipment may include a first robot 10, a wafer loading and unloading position 21, a calibration module 22, a cooling plate 23 and a plurality of processing modules 11; wherein,

[0034] Each wafer loading and unloading position 21 can hold a wafer box, and each wafer box can hold multiple wafers.

[0035] The calibration module 22 may include a slot, and the calibration module 22 may calibrate the wafer placed in the slot.

[0036] Processing module 11 (Processing Module), each processing module 11 has a slot, which can place a wafer for processing.

[0037] The cooling plate 23 (Cooler) is used to cool the wafer after processing.

[0038] The first robot 10 can be a double-arm robot. The two arms of the double-arm robot can be 180° and fixed. Each arm has a slot, and each slot can hold a wafer. Generally, the two arms cannot perform wafer picking and placing operations at the same time; the first robot 10 is responsible for transporting wafers between the vacuum lock 30 and multiple process chambers 11.

[0039] In addition, in some embodiments, the semiconductor process equipment may further include: a vacuum lock and a second manipulator; wherein the vacuum lock (LoadLock) may have two slots, each slot may hold a wafer, and the vacuum lock may switch between an atmospheric state and a vacuum state, wherein the vacuum lock state is converted to an atmospheric state, and the wafer located on the second manipulator side may be sent into the vacuum lock; when the vacuum lock is converted to a vacuum state, the wafer located on the first manipulator side may be sent into the vacuum lock. The second manipulator may be a single-arm manipulator, and the second manipulator may have a slot, and a wafer may be placed thereon, and the second manipulator may be responsible for transporting wafers between the wafer loading and unloading position 11, the calibration module 22, and the vacuum lock.

[0040] The process path of a wafer may include multiple process nodes that the wafer passes through in the semiconductor process equipment and the process time required for each process node. The process path can be specifically formulated by process personnel according to the wafer process requirements and can be flexibly changed. For example, the wafer process path may include: wafer loading and unloading position -> second robot (3 seconds) -> calibration module (1 second) -> second robot (3 seconds) -> vacuum lock (3 seconds) -> first robot (3 seconds) -> first process chamber (60 seconds) -> first robot (3 seconds) -> second process chamber (120 seconds) -> first robot (3 seconds) -> third process chamber (60 seconds) -> first robot (3 seconds) -> fourth process chamber (60 seconds) -> first robot (3 seconds) -> vacuum lock (3 seconds) -> second robot (3 seconds) -> cooling plate (1 seconds)—>wafer loading and unloading position, where each step can be called a process node, and each process node consumes time. The time marked in brackets can be the time required for the process node (i.e., process time). The wafer can be processed in parallel or serially in multiple process chambers 11. In the above process path example, if the first process chamber to the fourth process chamber are all different process chambers, then the above process path can be called a serial process path; if there are at least two identical process chambers 11 in the first process chamber to the fourth process chamber, then the above process path can be called a re-entrant process path. In addition to serial process paths and re-entrant process paths, if there are multiple process chambers 11 that can be selected for a certain process node, then the process path can be called a parallel process path.

[0041] The serial process path, parallel process path, and re-entrant process path are illustrated below, where an example of the serial process path is as follows: wafer loading and unloading position -> calibration module -> first robot -> first process chamber PM1 -> first robot –> second process chamber PM2 -> first robot -> third process chamber PM3 -> first robot -> fourth process chamber PM4 -> cooling plate -> wafer loading and unloading position; wherein the wafer is processed in four different process chambers (first process chamber PM1 to fourth process chamber PM4) in sequence, so this path is called a serial process path.

[0042] An example of a parallel process path is as follows: wafer loading and unloading position -> calibration module -> first robot -> first process chamber PM1 / second process chamber PM2 / third process chamber PM3 -> first robot -> cooling plate -> wafer loading and unloading position; wherein, the wafer can choose to be processed in one of the process chambers: the first process chamber PM1 / second process chamber PM2 / third process chamber PM3, so this path is called a parallel process path.

[0043] An example of a re-entrant process path is as follows: wafer loading and unloading position->calibration module->first robot->first process chamber PM1->first robot->second process chamber PM2->first robot->first process chamber PM1->first robot->second process chamber PM2->first robot->cooling plate->wafer loading and unloading position; wherein the wafer is processed twice in the first process chamber PM1 and twice in the first process chamber PM2, so this path is called a re-entrant process path.

[0044] When semiconductor process equipment processes wafers, the process paths of different types (or different varieties) of wafers may be different. The process paths of different types of wafers may occupy the same process chamber (this situation belongs to mixed processing of multiple types of wafers with a shared chamber), or may not occupy the same process chamber (this situation belongs to mixed processing of multiple types of wafers without a shared chamber).

[0045] In the processing scenario for multiple types of wafers, the order in which multiple types of wafers are discharged is an important factor affecting the utilization rate of process chambers in semiconductor process equipment. In order to improve the utilization rate of each process chamber in semiconductor process equipment, the inventors have discovered through research that when determining the process paths of multiple wafers to be discharged, the wafer status characterizing the position and process status of the discharged wafers in the semiconductor process equipment can be first obtained, and then, based on the wafer status and the process paths of the multiple wafers to be discharged, multiple earliest completion times corresponding to multiple theoretical discharge orders are determined, and the shortest earliest completion time among the multiple earliest completion times is used as the target earliest completion time, and the discharge of the multiple wafers to be discharged is controlled according to the theoretical discharge order corresponding to the target earliest completion time. In this way, by optimizing the discharge order of multiple wafers to be discharged, the processing order of multiple wafers to be discharged in the process chamber is optimized, so that the time for multiple wafers to be discharged to complete processing and return to the wafer loading and unloading position is the shortest, that is, the completion time is minimized (the completion time may refer to the time from the wafer being discharged from the wafer loading and unloading position for processing to the wafer returning to the wafer loading and unloading position after the processing is completed). Because the process path of the wafer has already given which process chambers need to be processed and the processing time in each process chamber, if the scheduling method makes the idle time of the process chambers in the process path relatively long and the utilization rate is not high, then the total time required to complete the wafer processing will definitely increase, and the completion time will not be the minimum at this time. On the contrary, if the idle time of the process chamber is very short and the utilization rate is very high, then the wafers can be continuously circulated and processed in the process chamber, and the overall completion time will also be shorter. Therefore, by selecting the shortest theoretical wafer discharge sequence as the basis for the discharge of the multiple wafers to be discharged, the time taken to complete the processing of the multiple wafers to be discharged is the shortest, which is beneficial to reducing the total time spent by the multiple wafers to be discharged in the semiconductor process equipment after discharge, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

[0046] When determining multiple earliest completion times corresponding to multiple theoretical wafer delivery orders, they can be obtained based on the wafer status and the process paths of multiple wafers to be delivered, without the need to establish a complex algorithm model. This is beneficial to reducing the complexity of the scheduling algorithm and improving the execution efficiency of the scheduling algorithm.

[0047] In addition, the earliest completion time includes the cleaning time of the process chamber. Thus, the cleaning time of the process chamber is taken into consideration, so that the scheduling method can be applicable to a non-steady-state scheduling process.

[0048] Based on the above-mentioned inventive concept, an embodiment of the present specification provides a scheduling method, and the scheduling method provided in the embodiment of the present specification will be exemplarily described below in conjunction with the accompanying drawings.

[0049] Exemplary Methods

[0050] One embodiment of the present specification provides a scheduling method, which is applied to a semiconductor process equipment, and is used to determine the processing order of multiple types of wafers in the semiconductor process equipment, wherein the semiconductor process equipment includes a wafer loading and unloading position and multiple process chambers, such as Figure 2 As shown, the scheduling method includes:

[0051] S201: Acquire wafer status, where the wafer status is used to characterize the position and process status of the wafer that has been produced in the semiconductor process equipment;

[0052] S202: Determine a plurality of earliest completion times corresponding to a plurality of theoretical wafer discharge sequences respectively according to the wafer status and the process paths of a plurality of wafers to be discharged; the plurality of wafers to be discharged include a plurality of different types of wafers located in the wafer loading and unloading positions; the plurality of theoretical wafer discharge sequences include permutations and combinations of discharge sequences of the plurality of wafers to be discharged; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the plurality of wafers to be discharged according to the theoretical wafer discharge sequence corresponding to the earliest completion time;

[0053] S203: Controlling the plurality of wafers to be shipped to be shipped according to the theoretical wafer shipment order corresponding to the target earliest completion time; the target earliest completion time is the earliest completion time with the shortest time among the plurality of earliest completion times.

[0054] Figure 2 A feasible application scenario of the scheduling method is also shown. During the operation of the semiconductor process equipment, the semiconductor process scheduling device of the semiconductor process equipment can execute steps S201 to S203 to control the wafer loading and unloading position. The semiconductor process scheduling device can be a lower computer of the semiconductor process equipment, and specifically can be a device with computing and communication capabilities, such as a computer or other devices.

[0055] In this embodiment, wafer outflow may refer to the action of entering other modules of the semiconductor process equipment from the wafer loading and unloading position; wafers that have been outflow may refer to wafers in modules other than the wafer loading and unloading position in the semiconductor process equipment, for example, wafers in modules such as the calibration module 22 or the process chamber 11; and wafers to be outflow may refer to wafers located in the wafer loading and unloading position.

[0056] The position of the wafer that has been discharged in the semiconductor process equipment may refer to which module the wafer is in the semiconductor process equipment, and the process status of the wafer that has been discharged in the semiconductor process equipment may refer to the processing status of the wafer that has been discharged in the process chamber 11, and the processing status may include at least one of the process time, the processed time, and the remaining processing time (the remaining processing time may be equal to the process time minus the processed time) of the wafer that has been discharged in the process chamber 11. In some embodiments, if there is no wafer that has been discharged in the semiconductor process equipment, the wafer status may be empty, and in step S202, multiple earliest completion times corresponding to multiple theoretical discharge orders may be determined directly according to the process paths of multiple wafers to be discharged.

[0057] In the process of determining multiple earliest completion times corresponding to the multiple theoretical output sequences according to the wafer status and the process paths of the multiple wafers to be output, the time (hereinafter referred to as the completion time) for each wafer to be output in the theoretical output sequence to complete processing and return to the wafer loading and unloading position can be calculated according to the process paths of the wafers to be output and the wafer status. It is not difficult to understand that when calculating the completion time required for a wafer to be output that is not the first wafer to be output in the theoretical output sequence in the semiconductor process equipment, it is necessary to consider the impact of other wafers to be output that are relatively earlier in the output sequence on the wafer to be output.

[0058] The theoretical wafer output sequence refers to a combination of the wafer output sequence of multiple types of wafers, or in other words, the theoretical wafer output sequence refers to a theoretically feasible wafer output sequence of multiple types of wafers. For example, assuming that there are three types of wafers to be output, and the three types of wafers to be output are A, B and C, then the multiple theoretical wafer output sequences may include: ABC, ACB, BAC, BCA, CAB and CBA, a total of six possibilities, and each theoretical wafer output sequence is a combination of the wafer output sequence of wafers A, B, and C. Taking the theoretical wafer output sequence ABC as an example, when calculating the completion time required after the wafer B to be output is output, the influence of the wafer A to be output, which is at the front of the output sequence, needs to be considered. Assume that the process path of the wafer A to be output includes: wafer loading and unloading position->calibration module (1 second)->first process chamber PM1 (60 seconds)->first robot (3 seconds)->second process chamber PM2 (120 seconds)->first robot (3 seconds)->cooling plate (2 seconds)->wafer loading and unloading position;

[0059] The process path of the wafer B to be shipped includes: wafer loading and unloading position->calibration module (1 second)->first process chamber PM1 (60 seconds)->first robot (3 seconds)->cooling plate (2 seconds)->wafer loading and unloading position.

[0060] Since the process paths of A and B both pass through process chamber PM1, when considering the completion time required for wafer B to be produced, it is necessary to consider whether A occupies process chamber PM1 when B needs to enter process chamber PM1 for processing, and the waiting time for B to use process chamber PM1.

[0061] The impact of the wafer status on the earliest completion time is similar to the above example. Taking the process path of the above-mentioned wafer A to be shipped as an example, it is assumed that when calculating the completion time of the wafer A to be shipped after it is shipped, there are wafers that have been shipped in the semiconductor process equipment. For example, the first process chamber PM1 has already had a wafer C that has just been processed, and the process time is 100 seconds. When the wafer A to be shipped passes through the calibration module and waits to enter PM1, it is necessary to wait for the wafer C to be processed in PM1 before entering, that is, it is necessary to wait for (100-1=)99 seconds. Then the completion time of the wafer A to be shipped is equal to 1+(100-1)+60+3+120+3+2=288 seconds.

[0062] Assuming that there is no wafer already shipped in the semiconductor process equipment when calculating the completion time of wafer A to be shipped, the completion time of wafer A to be shipped is equal to 1+60+3+120+3+2=189 seconds.

[0063] In this embodiment, when determining the process paths of multiple wafers to be discharged, the wafer status is first obtained, and then according to the wafer status and the process paths of the multiple wafers to be discharged, multiple earliest completion times corresponding to multiple theoretical discharge sequences are determined, and the shortest earliest completion time among the multiple earliest completion times is used as the target earliest completion time. According to the theoretical discharge sequence corresponding to the target earliest completion time, the discharge of the multiple wafers to be discharged is controlled. In this way, by selecting the shortest theoretical discharge sequence as the discharge basis for the multiple wafers to be discharged, the time taken to complete the processing of the multiple wafers to be discharged is the shortest, which is beneficial to reducing the total time spent by the multiple wafers to be discharged in the semiconductor process equipment after the discharge, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

[0064] When determining multiple earliest completion times corresponding to multiple theoretical wafer delivery orders, they can be obtained based on the wafer status and the process paths of multiple wafers to be delivered, without the need to establish a complex algorithm model. This is beneficial to reducing the complexity of the scheduling algorithm and improving the execution efficiency of the scheduling algorithm.

[0065] In addition, in some embodiments, the earliest completion time includes the cleaning time of the process chamber. In this way, the cleaning time of the process chamber is taken into consideration, so that the scheduling method can be applicable to a non-steady-state scheduling process.

[0066] In order to achieve more precise control so that the completion time of each wafer to be shipped can be as short as possible, in one embodiment of the present specification, controlling the wafers to be shipped according to the theoretical wafer shipment sequence corresponding to the earliest target completion time includes:

[0067] According to the theoretical wafer discharge sequence corresponding to the target earliest completion time, the first wafer among the plurality of wafers to be discharged is controlled to be discharged, and the process returns to the step of obtaining the wafer status.

[0068] Generally speaking, in the wafer loading and unloading position, the number of each type of wafers to be discharged can be multiple. In the theoretical discharge order corresponding to the target earliest completion time, after controlling the discharge of the first wafer among the multiple wafers to be discharged, the step of obtaining the wafer status can be returned to re-schedule and plan the subsequent multiple types of wafers to be discharged, so as to reduce the completion time of each wafer to be discharged as much as possible and improve the utilization rate of the process chamber.

[0069] For example, assuming that there are three types of wafers to be discharged in the wafer loading and unloading position, and these three types of wafers to be discharged are A, B, and C respectively. As mentioned above, the multiple theoretical discharge sequences of these three types of wafers may include: ABC, ACB, BAC, BCA, CAB and CBA, a total of six possibilities. Assuming that after calculation, the theoretical discharge sequence ABC corresponds to the target earliest completion time, then the wafer loading and unloading position is controlled to determine a wafer to be discharged among multiple wafers of type A. Afterwards, the discharged wafer is regarded as a discharged wafer, and the process returns to step S201, and the three types of wafers to be discharged are re-planned and scheduled so that the completion time of each wafer is as minimum as possible under the current state, thereby improving the utilization rate of the process chamber.

[0070] In one embodiment of the present specification, a feasible method for calculating the earliest completion time is provided. For example, the method of determining multiple earliest completion times corresponding to multiple theoretical wafer delivery orders respectively according to the wafer status and the process paths of multiple wafers to be delivered includes:

[0071] In combination with the wafer status, multiple theoretical wafer discharge sequences are traversed to obtain the first completion time corresponding to each target process chamber in the theoretical wafer discharge sequence; the target process chamber is a process chamber in the process path of the wafer to be discharged in the theoretical wafer discharge sequence; the first completion time is the time required for multiple wafers to be discharged to be processed in the target process chamber and return to the wafer loading and unloading position;

[0072] The maximum value of the first completion times corresponding to the target process chambers in the theoretical wafer-out sequence is used as the earliest completion time corresponding to the theoretical wafer-out sequence.

[0073] It is not difficult to know from the above description that in the process path of the wafer to be discharged, the processing time of the wafer to be discharged in the process chamber usually occupies a large part of the completion time. Therefore, in this embodiment, the target process chamber in the process path is used as a node, and the first completion time corresponding to the target process chamber is calculated, and the situation that the wafer waits outside the chamber due to the occupancy of the process chamber is considered, and the maximum value of the first completion time corresponding to each target process chamber in the theoretical discharge sequence is used as the earliest completion time corresponding to the theoretical discharge sequence. The earliest completion time is calculated by this algorithm without the need to construct a complex mathematical model, and it is simple and easy to use.

[0074] Optionally, in one embodiment, the first completion time specifically includes: the sum of the first minimum time, the second minimum time, the first chamber cleaning time and the first process time;

[0075] The first minimum time includes the minimum time for a plurality of wafers to be discharged in the theoretical discharge sequence to enter the target process chamber according to their respective corresponding process paths;

[0076] The second minimum time includes the minimum time for the plurality of wafers to be discharged in the theoretical discharge sequence to be processed in the target process chamber and returned to the wafer loading and unloading position according to their respective corresponding process paths;

[0077] The first chamber cleaning time includes the chamber cleaning time of the target process chamber during processing of the plurality of wafers to be produced;

[0078] The first process processing time includes the sum of the time taken by the target process chamber to process the plurality of wafers to be discharged in the theoretical discharge sequence according to their respective corresponding process paths.

[0079] With reference to the following formula 1, the first completion time can be calculated according to the formula 1.

[0080] T=max k {min i,j (S i,j,k )+∑ i,j D i,j,k +∑ h C h,k +min i,j (E i,j,k )} Formula 1

[0081] In Formula 1, T represents the earliest completion time, subscript k represents the number of the process chamber, i represents the number of the wafer to be produced, j represents the number of the process node in the process path of the wafer i to be produced, and h represents the number of cleaning times of the process chamber k.

[0082] S i,j,k represents the fastest time for wafer i to arrive at process chamber k at process node j, then min i,j (S i,j,k ) represents the minimum time for a plurality of the wafers to be discharged in the theoretical discharge sequence to enter the target process chamber according to their respective corresponding process paths, that is, the first minimum time;

[0083] D i,j,k represents the time that process node j of wafer i to be produced occupies process chamber k, then ∑ i,j D i,j,k Indicates the processing time of the first process;

[0084] C h,k represents the time required for process chamber k to perform the hth chamber cleaning, then ∑ h C h,k It represents the sum of the time required for one or more chamber cleanings of the process chamber k during the process of processing a plurality of the wafers to be discharged in the theoretical discharge sequence.

[0085] E i,j,k represents the time required for the wafer i to be shipped to return from the process chamber k to the wafer loading and unloading position from the process node j as soon as possible, then min i,j (E i,j,k ) represents the second minimum time.

[0086] Suppose there are two types of wafers to be processed in a mixed process, namely type A and type B, and there are 10 wafers waiting to be processed respectively. The process path of type A is wafer loading and unloading position -> calibration module (1 second) -> first robot (3 seconds) -> process chamber PM1 (60 seconds) -> first robot (3 seconds) -> process chamber PM2 (120 seconds) -> first robot (3 seconds) -> cooling plate (1 second) -> wafer loading and unloading position; the process path of type B is wafer loading and unloading position -> calibration module (1 second) -> first robot (3 seconds) -> process chamber PM1 (30 seconds) -> first robot (3 seconds) -> process chamber PM3 (60 seconds) -> first robot (3 seconds) -> cooling plate (1 second) -> wafer loading and unloading position; the time in brackets after each module is the time consumption of this step (process node);

[0087] 1) For different chamber numbers k, the k corresponding to process chamber PM1 is 1, the k corresponding to process chamber PM2 is 2, and the k corresponding to process chamber PM3 is 3; for wafer number i, the wafer numbers i of type A are 1 to 10, and the wafer numbers i of type B are 11 to 20; for wafer process path number j, the process step numbers j of type A are wafer loading and unloading position -> calibration module (j=1) -> first robot (j=2) -> process chamber PM1 (j=3) -> First robot (j=4)->Process chamber PM2 (j=5)->First robot (j=6)->Cooling plate (j=7)->Wafer loading and unloading position; Process step number j of type B is Wafer loading and unloading position->Calibration module (j=1)->First robot (j=2)->Process chamber PM1 (j=3)->First robot (j=4)->Process chamber PM3 (j=5)->First robot (j=6)->Cooling plate (j=7)->Wafer loading and unloading position;

[0088] 2) Assume that all process chamber cleaning settings are set to clean one piece at a time, and the cleaning time is 10 seconds; (In actual production, this parameter is specified in advance by the process personnel)

[0089] 3) When all wafers have not left the wafer loading and unloading position, the calculation process of the first completion time of a wafer from the wafer loading and unloading position of type A is as follows:

[0090] a) For k = 1, S i,j,1 = The shortest time it takes for a wafer to be unloaded from the wafer loading and unloading position, pass through the calibration module, and reach the process chamber PM1 is 1 second (calibration module) + 3 seconds (first robot) = 4 seconds; D i,j,1 = The process time of the wafer in the process chamber PM1 is 60 seconds; E i,j,1 = The total time from the completion of the process in process chamber PM1 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 120 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling plate) = 127 seconds; the cumulative number of process wafers before the process in process chamber PM1 starts is 0, and cleaning will not be triggered, so h = 0, C h,1 is equal to 0;

[0091] b) For k = 2, S i,j,2 = The shortest time from the wafer loading and unloading position to the process chamber PM2 through the calibration module, the first robot, the process chamber PM1, and the first robot is 1 second (Agliner) + 3 seconds (first robot) + 60 seconds (process chamber PM1) + 3 seconds (first robot) = 67 seconds; D i,j,2 = The process time of the wafer in the process chamber PM2 is 120 seconds; E i,j,2= The total time from the completion of the process in process chamber PM2 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 1 second (cooling plate) = 4 seconds; the cumulative number of process wafers before the process in process chamber PM2 starts is 0, and cleaning will not be triggered, so h = 0, C h,2 is equal to 0;

[0092] c) The earliest completion time T of this wafer A is equal to max{4+60+127+0,67+120+4+0}=191 seconds.

[0093] When all wafers have not left the wafer loading and unloading position, the calculation process of the first completion time of a wafer from the wafer loading and unloading position of type B is as follows:

[0094] a) For k = 1, S i,j,1 = The shortest time it takes for a wafer to be unloaded from the wafer loading and unloading position, pass through the calibration module, and reach the process chamber PM1 is 1 second (calibration module) + 2 seconds (first robot) = 3 seconds; D i,j,1 = The process time of wafer B in process chamber PM1 is 30 seconds; E i,j,1 = The total time from the completion of the process in process chamber PM1 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 60 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling plate) = 67 seconds; the cumulative number of process wafers before the process in process chamber PM1 starts is 0, and cleaning will not be triggered, so h = 0, C h,1 is equal to 0;

[0095] b) For k=3, S i,j,2 The shortest time from the wafer loading and unloading position to the process chamber PM3 through the calibration module, the first robot, the process chamber PM1, and the first robot is 1 second (Agliner) + 3 seconds (first robot) + 30 seconds (process chamber PM1) + 3 seconds (first robot) = 37 seconds; D i,j,2 = The process time of the wafer in the process chamber PM3 is 60 seconds; E i,j,2 = The total time from the completion of the process in process chamber PM3 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 1 second (cooling plate) = 4 seconds; the cumulative number of process wafers before the process in process chamber PM3 starts is 0, and cleaning will not be triggered, so h = 0, C h,2 is equal to 0;

[0096] c) The earliest completion time T of this wafer B is equal to max{3+30+67+0,37+60+4+0}=101 seconds.

[0097] Through similar calculation methods as above, the earliest completion time of wafer output sequence 1: wafer A-wafer B when all wafers have not left the wafer loading and unloading position can be calculated; and the earliest completion time of wafer output sequence 2: wafer B-wafer A can be calculated. If the earliest completion time of wafer output sequence 1 is less than the earliest completion time of wafer output sequence 2, wafer A is controlled to be output according to wafer output sequence 1. If the earliest completion time of wafer output sequence 2 is less than the earliest completion time of wafer output sequence 1, wafer B is controlled to be output according to wafer output sequence 2.

[0098] When a wafer of type A has just entered the process chamber PM1 for processing and the remaining processing time is 60 seconds, the first completion time calculation process of a wafer of type A coming out of the wafer loading and unloading position is as follows:

[0099] a) For k = 1, S i,j,1 = The shortest time from the wafer loading and unloading position to the process chamber PM1 through the calibration module and the first robot is 1 second (calibration module) + 3 seconds (first robot) + (60-4 =) 56 seconds (waiting for the first type A wafer to be processed) = 60 seconds; D i,j,1 = The process time of the wafer in the process chamber PM1 is 60 seconds; E i,j,1 = The total time from the completion of the process in process chamber PM1 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 120 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling plate) = 127 seconds; the cumulative number of process wafers before the process in process chamber PM1 starts is 1, triggering 1 cleaning, so h = 1, C h,1 Equal to 10 seconds;

[0100] b) For k = 2, S i,j,2 = The shortest time from the wafer loading and unloading position, through the calibration module, the first robot, the process chamber PM1, and the first robot to the process chamber PM2 is 1 second (Agliner) + 3 seconds (first robot) + (60-4 =) 56 seconds (waiting for the first type A wafer to be processed) + 60 seconds (process chamber PM1) + 3 seconds (first robot) = 123 seconds; D i,j,2 = The process time of the wafer in the process chamber PM2 is 120 seconds; E i,j,2 = The total time from the completion of the process in process chamber PM2 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 1 second (cooling plate) = 4 seconds; the cumulative number of process wafers before the process in process chamber PM2 starts is 1, which will trigger cleaning, so h = 10, C h,2 Equal to 10 seconds;

[0101] c) The earliest completion time T of wafer A is equal to max{60+60+127+10,123+120+4+10}=257 seconds.

[0102] When a wafer of type A has just entered process chamber PM1 for processing and the remaining processing time is 60 seconds, the first completion time calculation process of a wafer of type B coming out of the wafer loading and unloading position is as follows:

[0103] a) For k = 1, S i,j,1 = The shortest time it takes for a wafer to be unloaded from the wafer loading and unloading position, pass through the calibration module and the first robot and arrive at the process chamber PM1 is 1 second (calibration module) + 2 seconds (first robot) + 57 seconds (waiting time for wafer A to be processed) = 60 seconds; D i,j,1 = The process time of wafer B in process chamber PM1 is 30 seconds; E i,j,1 = The total time from the completion of the process in process chamber PM1 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 60 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling plate) = 67 seconds; the cumulative number of process wafers before the process in process chamber PM1 starts is 1, which will trigger cleaning, so h = 1, C h,1 Equal to 10 seconds;

[0104] b) For k=3, S i,j,2 The shortest time from the wafer loading and unloading position to the process chamber PM3 after passing through the calibration module, the first robot, the process chamber PM1, and the first robot is 1 second (Agliner) + 3 seconds (first robot) + 57 seconds (waiting time for wafer A to be processed) + 30 seconds (process chamber PM1) + 3 seconds (first robot) = 93 seconds; D i,j,2 = The process time of the wafer in the process chamber PM3 is 60 seconds; E i,j,2 = The total time from the completion of the process in process chamber PM3 to the return to the wafer loading and unloading position is 3 seconds (first robot) + 1 second (cooling plate) = 4 seconds; the cumulative number of process wafers before the process in process chamber PM3 starts is 0, and cleaning will not be triggered, so h = 0, C h,2 is equal to 0;

[0105] c) The earliest completion time T of wafer B is equal to max{60+30+67+10,93+60+4+0}=157 seconds.

[0106] Through similar calculation methods as above, the earliest completion time of wafer A in the order 1: wafer A-wafer B and the earliest completion time of wafer B-wafer A can be calculated when the existing wafer A just enters the process chamber PM1. If the earliest completion time of wafer A in the order 1 is less than the earliest completion time of wafer B-wafer A, wafer A is controlled to be discharged according to the order 1. If the earliest completion time of wafer B in the order 2 is less than the earliest completion time of wafer B in the order 1, wafer B is controlled to be discharged according to the order 2.

[0107] Through this method, taking the process chamber as a node and considering the waiting time of the wafer outside the process chamber during the processing, the first completion time corresponding to each target process chamber and the earliest completion time of the theoretical wafer output sequence can be quickly calculated without establishing a complex algorithm model, which is beneficial to reducing the complexity of the scheduling algorithm and improving the efficiency of the scheduling method.

[0108] For the process path of the wafer to be produced being a parallel process path, in order to select the most time-saving process chamber from a plurality of alternative process chambers so that the process path of the wafer to be produced is relatively time-saving, in one embodiment of the present specification, Figure 3 As shown, the determining of multiple earliest completion times corresponding to multiple theoretical wafer delivery orders respectively according to the wafer status and the process paths of multiple wafers to be delivered includes:

[0109] S301: If the process path of the wafer to be produced includes multiple parallel chambers, then determine a processing chamber among the multiple parallel chambers; the multiple parallel chambers are alternative process chambers for the target process node in the process path of the wafer to be produced; and the processing chamber is the process chamber determined to execute the target process node.

[0110] When executing step S301, the process nodes in the process path of each wafer to be produced can be traversed. If a process node in the process path includes multiple candidate process chambers, the multiple candidate process chambers can be called multiple parallel chambers, and the process node can be called a target process node. For example, assuming that the process path of wafer A includes: wafer loading and unloading position->calibration module->first robot->process chamber PM1 / process chamber PM2 / process chamber PM3->first robot->cooling plate->wafer loading and unloading position, the fourth process node in the process path includes three parallel chambers (process chamber PM1 / process chamber PM2 / process chamber PM3), that is, the process node can be selected in process chamber PM1 / process chamber PM2 / process chamber PM3. In order to determine the process path of wafer A and facilitate the calculation of the completion time of other subsequent wafers, it is necessary to determine the processing chamber of the target process node (that is, determine the process chamber that executes the target process node).

[0111] Therefore, in this embodiment, in order to facilitate the calculation of multiple earliest completion times corresponding to multiple theoretical wafer delivery orders of multiple wafers to be shipped, before calculating the earliest completion time, it is also necessary to determine the processing chamber when the process path of each of the wafers to be shipped includes multiple parallel chambers.

[0112] It is understandable that, for parallel process paths, after the processing chamber is determined according to step S301, the earliest completion time can be calculated; and for other types of process paths, the earliest completion time can be calculated directly.

[0113] Specifically, in one embodiment of the present specification, determining a processing chamber among the plurality of parallel chambers includes:

[0114] In combination with the wafer status, a second completion time corresponding to the parallel chamber is calculated, where the second completion time is the time required for the wafer to be processed in the parallel chamber and returned to the wafer loading and unloading position;

[0115] The parallel chamber corresponding to the minimum value of the plurality of second completion times is determined as the processing chamber of the target process node in the process path of the wafer to be produced.

[0116] Similar to the calculation of the first completion time, the second completion time corresponding to the parallel chambers can be calculated in combination with the wafer status, and the second completion time with the shortest time can be found from the second completion times corresponding to each of the parallel chambers, and the parallel chamber corresponding to the second completion time with the shortest time can be determined as the processing chamber of the target process node. In this way, the target process node of the process path of each of the wafers to be produced can select the process chamber with the least time as the chamber to execute the node, thereby reducing the time required for the process path of the wafers to be produced.

[0117] Optionally, in one embodiment of the present specification, the second completion time specifically includes: the sum of the third minimum time, the fourth minimum time, the second chamber cleaning time, and the second process time;

[0118] The third minimum time includes the minimum time for the wafer to be ejected to enter the parallel chamber according to the process path corresponding to it;

[0119] The fourth minimum time includes the minimum time for the wafer to be shipped to return to the wafer loading and unloading position after the parallel chamber is processed according to the process path corresponding to the wafer;

[0120] The second chamber cleaning time includes the chamber cleaning time required for the parallel chamber before processing the wafer to be produced;

[0121] The second process processing time includes the time for processing multiple wafers to be shipped according to the process paths corresponding to the wafers to be shipped.

[0122] Similarly, the third minimum time, the fourth minimum time, the second chamber cleaning time and the second process processing time mentioned above can be calculated with reference to Formula 1. Through this method, taking the parallel chamber as the node and considering the waiting time of the wafer outside the process chamber during the processing, the second completion time corresponding to each parallel chamber can be quickly calculated, which is beneficial to improving the efficiency of the scheduling method.

[0123] In an optional embodiment, before step S301, it can also include selecting a wafer with the highest priority for each type of wafer according to the wafer priority as the wafer to be shipped of that type of wafer, so that a plurality of wafers to be shipped can be determined. Among them, the wafer priority of each type of wafer is negatively correlated with the ID of the slot where the wafer is located, such as the larger the ID of the slot where the wafer is located, the lower its wafer priority. Of course, in some embodiments, the wafer priority of wafers of the same type can also be determined in other ways, and this specification does not limit this.

[0124] The specific feasible execution method of step S203 may include: controlling the first wafer to be shipped in the theoretical wafer shipment sequence corresponding to the target earliest completion time to ship, and returning to step S301, and scheduling the remaining multiple wafers to be shipped according to the scheduling method. For example, assuming that the theoretical wafer shipment sequence corresponding to the target earliest completion time includes wafer B, wafer C, and wafer A, then after controlling wafer B to ship, return to the step of obtaining the wafer status, and schedule the remaining wafers to be shipped according to the current wafer status. In this way, it can be ensured that the theoretical wafer shipment sequence corresponding to each wafer at the time of shipment corresponds to the target earliest completion time.

[0125] Exemplary devices and apparatus

[0126] In an exemplary embodiment of the present specification, a scheduling device is also provided, which is applied to a semiconductor process equipment and is used to determine the processing order of multiple types of wafers in the semiconductor process equipment. The semiconductor process equipment includes a wafer loading and unloading position and multiple process chambers, such as Figure 4 As shown, the scheduling device includes:

[0127] A status acquisition module 401 is used to acquire a wafer status, where the wafer status is used to characterize the position and process status of the wafer that has been produced in the semiconductor process equipment;

[0128] The time calculation module 402 is used to determine a plurality of earliest completion times corresponding to a plurality of theoretical wafer discharge sequences according to the wafer state and the process paths of the plurality of wafers to be discharged; the plurality of wafers to be discharged include a plurality of different types of wafers located in the wafer loading and unloading positions; the plurality of theoretical wafer discharge sequences include permutations and combinations of the discharge sequences of the plurality of wafers to be discharged; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the plurality of wafers to be discharged according to the theoretical wafer discharge sequence corresponding to the earliest completion time, and the earliest completion time includes the cleaning time of the process chamber;

[0129] The wafer output control module 403 is used to control the output of the multiple wafers to be output according to the theoretical output sequence corresponding to the target earliest completion time; the target earliest completion time is the earliest completion time with the shortest time among the multiple earliest completion times.

[0130] For the specific definition of the scheduling device, please refer to the definition of the scheduling method above, which will not be repeated here. Each module in the above scheduling device can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0131] In another exemplary embodiment of the present specification, a semiconductor process scheduling device is provided, which is characterized in that it is used to schedule the processing sequence of multiple types of wafers in a wafer loading and unloading position, and the semiconductor process scheduling device includes: a processor and a memory; a computer program is stored in the memory, and when the processor executes the computer program, it executes any of the scheduling methods described above to control the wafer loading and unloading position to discharge the multiple wafers to be discharged.

[0132] like Figure 5 As shown, in an exemplary embodiment of the present specification, a semiconductor process equipment 100 is also provided, comprising: a semiconductor process scheduling device 30 and a wafer loading and unloading position 21;

[0133] The wafer loading and unloading position 21 is configured to set a plurality of wafers to be discharged;

[0134] The semiconductor process scheduling device 30 is configured to control the wafer loading and unloading position to unload the plurality of wafers to be unloaded according to the scheduling method described in any of the above embodiments.

[0135] In some embodiments, the semiconductor process scheduling device 30 can collect information of the controlled module 40 and control the controlled module 40 to work in coordination. In addition to the wafer loading and unloading position 21, the controlled module 40 can also include part or all of the first robot 10 and multiple processing modules 11. In some embodiments, the controlled module 40 can also include a second robot, a calibration module 22, a cooling plate 23, etc.

[0136] In some implementations, the semiconductor process scheduling device 30 is, for example, a lower computer of the semiconductor process equipment 100 , and this specification does not limit this, and the specific situation depends on the actual situation.

[0137] Exemplary Computing Devices

[0138] Another embodiment of the present application further provides a computing device, see Figure 6 As shown, an exemplary embodiment of the present specification also provides a computing device, including: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification are executed.

[0139] The internal structure of the computing device can be as follows Figure 6 As shown, the computing device includes a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification are performed.

[0140] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0141] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0142] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0143] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor.

[0144] Output devices may include means that allow information to be output to a user, such as display screens, printers, speakers, etc.

[0145] The communication interface may include using any transceiver or the like to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0146] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any scheduling method provided in the above embodiments of the present application.

[0147] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display or an electronic ink display. The input device of the computing device may be a touch layer covered on the display component, or a button, trackball or touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse.

[0148] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of this specification, and does not constitute a limitation on the computing device to which the scheme of this specification is applied. The specific computing device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0149] Exemplary computer program products and storage media

[0150] In addition to the above-mentioned methods and devices, the scheduling method provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the scheduling method according to various embodiments of this specification described in the above "Exemplary Method" section of this specification.

[0151] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present specification, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0152] In addition, an embodiment of the present specification also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the scheduling method according to various embodiments of the present specification described in the above "Exemplary Method" section of the present specification.

[0153] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0154] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-mentioned embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the solutions provided by the embodiments of this specification. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A scheduling method, It is characterized in that The method is applied to semiconductor process equipment to determine the processing sequence of multiple types of wafers in the semiconductor process equipment, wherein the semiconductor process equipment includes a wafer loading and unloading position and multiple process chambers. The scheduling method includes: Obtaining a wafer status, where the wafer status is used to characterize a position and a process status of a wafer that has been produced in the semiconductor process equipment; According to the wafer status and the process paths of the plurality of wafers to be shipped, a plurality of earliest completion times corresponding to a plurality of theoretical wafer shipment sequences are determined; the plurality of wafers to be shipped include a plurality of different types of wafers located in the wafer loading and unloading positions; the plurality of theoretical wafer shipment sequences include permutations and combinations of the wafer shipment sequences of the plurality of wafers to be shipped; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the plurality of wafers to be shipped according to the theoretical wafer shipment sequence corresponding to the earliest completion time; According to the theoretical wafer discharge order corresponding to the target earliest completion time, the plurality of wafers to be discharged are controlled to discharge; the target earliest completion time is the earliest completion time with the shortest time among the plurality of earliest completion times.

2. The method according to claim 1, It is characterized in that The controlling the plurality of wafers to be shipped to be shipped according to the theoretical wafer shipment sequence corresponding to the target earliest completion time comprises: According to the theoretical wafer discharge sequence corresponding to the target earliest completion time, the first wafer among the plurality of wafers to be discharged is controlled to be discharged, and the process returns to the step of obtaining the wafer status.

3. The method according to claim 1, It is characterized in that The earliest completion time includes a cleaning time of the process chamber.

4. The method according to claim 1, It is characterized in that The determining, according to the wafer status and the process paths of the plurality of wafers to be shipped, a plurality of earliest completion times corresponding to a plurality of theoretical wafer shipping sequences respectively comprises: In combination with the wafer status, multiple theoretical wafer discharge sequences are traversed to obtain the first completion time corresponding to each target process chamber in the theoretical wafer discharge sequence; the target process chamber is a process chamber in the process path of the wafer to be discharged in the theoretical wafer discharge sequence; the first completion time is the time required for multiple wafers to be discharged to be processed in the target process chamber and return to the wafer loading and unloading position; The maximum value of the first completion times corresponding to the target process chambers in the theoretical wafer-out sequence is used as the earliest completion time corresponding to the theoretical wafer-out sequence.

5. The method according to claim 4, It is characterized in that The first completion time specifically includes: the sum of the first minimum time, the second minimum time, the first chamber cleaning time, and the first process time; The first minimum time includes the minimum time for a plurality of wafers to be discharged in the theoretical discharge sequence to enter the target process chamber according to their respective corresponding process paths; The second minimum time includes the minimum time for the plurality of wafers to be discharged in the theoretical discharge sequence to be processed in the target process chamber and returned to the wafer loading and unloading position according to their respective corresponding process paths; The first chamber cleaning time includes the chamber cleaning time of the target process chamber during processing of the plurality of wafers to be produced; The first process processing time includes the sum of the time taken by the target process chamber to process the plurality of wafers to be discharged in the theoretical discharge sequence according to their respective corresponding process paths.

6. The method according to claim 1, It is characterized in that The determining, according to the wafer status and the process paths of the plurality of wafers to be shipped, a plurality of earliest completion times corresponding to a plurality of theoretical wafer shipping sequences respectively comprises: If the process path of the wafer to be produced includes multiple parallel chambers, a processing chamber is determined among the multiple parallel chambers; the multiple parallel chambers are alternative process chambers for the target process node in the process path of the wafer to be produced; and the processing chamber is the process chamber determined to execute the target process node.

7. The method according to claim 6, It is characterized in that Determining a processing chamber among the plurality of parallel chambers comprises: In combination with the wafer status, a second completion time corresponding to the parallel chamber is calculated, where the second completion time is the time required for the wafer to be processed in the parallel chamber and returned to the wafer loading and unloading position; The parallel chamber corresponding to the minimum value of the plurality of second completion times is determined as the processing chamber of the target process node in the process path of the wafer to be produced.

8. The method according to claim 7, It is characterized in that The second completion time specifically includes: the sum of the third minimum time, the fourth minimum time, the second chamber cleaning time, and the second process time; The third minimum time includes the minimum time for the wafer to be ejected to enter the parallel chamber according to the process path corresponding to it; The fourth minimum time includes the minimum time for the wafer to be shipped to return to the wafer loading and unloading position after the parallel chamber is processed according to the process path corresponding to the wafer; The second chamber cleaning time includes the chamber cleaning time required for the parallel chamber before processing the wafer to be produced; The second process processing time includes the time for processing multiple wafers to be shipped according to the process paths corresponding to the wafers to be shipped.

9. A semiconductor process scheduling device, It is characterized in that The semiconductor process scheduling device is used to schedule the processing sequence of multiple types of wafers in a wafer loading and unloading position, and includes: a processor and a memory; a computer program is stored in the memory, and when the processor executes the computer program, it executes the scheduling method described in any one of claims 1 to 8 to control the wafer loading and unloading position to discharge the multiple wafers to be discharged.

10. A semiconductor process equipment, It is characterized in that include: A wafer loading and unloading station and a semiconductor process scheduling device as claimed in claim 9; The wafer loading and unloading position is configured to set a plurality of different types of wafers to be shipped; The semiconductor process scheduling device is configured to control the wafer loading and unloading position to unload the plurality of wafers to be unloaded according to the scheduling method according to any one of claims 1 to 8.

11. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the scheduling method according to any one of claims 1 to 8 is implemented.

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