Adaptive baud rate module and method based on FPGA
By splitting the FPGA adaptive baud rate module into multiple submodules and adopting a modular design and setting the baud rate using clear commands, the problems of complex design and long development cycle of traditional modules are solved, and more efficient and flexible baud rate management is achieved.
Patent Information
- Application Number
- CN202411987855.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-23
AI Technical Summary
Traditional FPGA-based adaptive baud rate modules have problems such as high design complexity, long development cycle, high scalability and upgrade difficulty, and low resource utilization.
By splitting the adaptive baud rate module into multiple submodules, each submodule focuses on a specific function, such as serial port data filtering, baud rate conversion, etc., adopts a modular design, and uses clear commands.BAUD (digital) to set the baud rate.
It realizes a modular system with clearer and easier to understand design, simplifies the baud rate setting process, reduces hardware resource consumption and implementation complexity, and improves the scalability and flexibility of the system.
Smart Images
Figure CN120034411A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to an adaptive baud rate module and method based on FPGA, belonging to the field of communication technology. Background Art
[0002] Adaptive baud rate technology based on Field-Programmable Gate Array (FPGA) refers to the technology of using FPGA hardware to realize automatic detection and adjustment of baud rate in communication system. It can automatically adjust baud rate under different communication environments and conditions to improve communication efficiency and stability. Among them, baud rate refers to the number of code symbols transmitted per second, which is a unit of measurement for symbol transmission rate. The higher the baud rate, the faster the communication speed.
[0003] In traditional serial communication, the sender and receiver need to negotiate and set the same baud rate in advance, otherwise the data will not be transmitted correctly. Generally, FPGA-based adaptive baud rate communication technology requires at least one communication end to send several data frames for handshake before each data transmission to obtain baud rate information and adjust its own baud rate settings accordingly.
[0004] There are several ways to obtain baud rate information:
[0005] 1. Minimum number method: In this method, the minimum number of pulse width (the width of continuous 0 or 1) is continuously detected, and then the baud rate is obtained by comparing the minimum number with the unit pulse width.
[0006] 2. Differential sorting method: This method is an improvement on the minimum number method. It continuously calculates each pulse width, sorts, subtracts, and repeats until the smallest number is obtained. The baud rate is obtained by comparing the number with the unit pulse width.
[0007] 3. Fixed data transmission method. This method needs to transmit a fixed number before transmitting data, such as 0X00. Then the receiver receives a low level. By calculating the width of this low level and dividing it by the data, the unit pulse width is obtained, thereby obtaining the baud rate used for transmission.
[0008] The above-mentioned adaptive baud rate methods are usually implemented based on software or rely on specific hardware devices. These solutions have the following disadvantages:
[0009] 1) Design complexity: FPGA design and programming usually require professional knowledge of hardware description language (HDL), such as VHDL or Verilog. This makes the design process of the adaptive baud rate method complex and requires high professional skills from developers.
[0010] 2) Long development cycle: The development cycle of FPGA is usually longer than software development, and it takes a long time from design to verification.
[0011] 3) Scalability and upgrade difficulty: Once the hardware design of FPGA is completed and deployed, it is usually more difficult to upgrade and modify than software. For applications that require frequent updates or expanded functions, scalability and upgrade difficulties are high.
[0012] 4) Resource utilization: In order to adapt, the incoming data frames need to be continuously detected, and the internal resources may not be fully utilized, resulting in resource waste, especially on FPGA devices with limited resources.
[0013] 5) Real-time and convenience: After receiving the baud rate adjustment frame, comparison or additional calculation and sorting are required to obtain the desired baud rate result. Summary of the invention
[0014] The present application provides an FPGA-based adaptive baud rate module and method, which can solve the problems of high design complexity, long development cycle, high scalability and upgrade difficulty, and low resource utilization of traditional FPGA-based adaptive baud rate modules. The present application provides the following technical solutions:
[0015] In a first aspect, an FPGA-based adaptive baud rate module is provided, the module comprising:
[0016] Data transmission submodule, used to receive data sent by external devices through the serial port;
[0017] A string comparison submodule connected to the data transmission submodule compares the data with a predetermined string based on combinational logic to obtain a comparison result; the predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes the specific command, and the specific command is used to indicate switching the baud rate;
[0018] A parameter extraction submodule connected to the data transmission submodule, used to extract baud rate parameters from the data;
[0019] a baud rate setting submodule connected to the string comparison submodule and the parameter extraction submodule respectively, for outputting a modification signal when the comparison result indicates that the data includes the specific command and the parameter extraction submodule outputs the baud rate parameter;
[0020] A delay modification submodule connected to the baud rate setting submodule, used to start timing when receiving the modification signal, and output a timing completion signal after reaching a preset delay time;
[0021] A parameter conversion submodule connected to the parameter extraction submodule, used for converting the baud rate parameter into BCD code;
[0022] A BCD code storage submodule connected to the modification delay submodule and the parameter conversion submodule respectively, for updating the data stored in the BCD code storage submodule using the BCD code output by the parameter conversion submodule based on the received timing completion signal, and outputting the updated BCD code;
[0023] A BCD code conversion submodule connected to the BCD code storage submodule, used to convert the updated BCD code into a hexadecimal code;
[0024] The data transmission submodule is also connected to the BCD code conversion submodule, and is used to store the hexadecimal code output by the BCD code conversion submodule and transmit data according to the hexadecimal code.
[0025] Optionally, the parameter extraction submodule and the data transmission submodule both include a state machine, and the state machine is used to:
[0026] In the case where the comparison result indicates that the character string includes the specific command, controlling the module to enter a baud rate setting state, performing baud rate modification in the baud rate setting state and waiting for the delay of the modification delay submodule to end;
[0027] During normal data transmission, a data transmission state is entered, in which data is sent and received according to the current baud rate.
[0028] Optionally, the data transmission submodule instantiates a first submodule and a second submodule;
[0029] The first submodule includes a counter for adjusting the baud rate according to the baud rate limit value indicated by the input hexadecimal code to receive data;
[0030] The second submodule includes a data shift register and a counter, which are used to control the transmission rate according to the baud rate limit value indicated by the input hexadecimal code to perform data transmission.
[0031] Optionally, the parameter extraction submodule includes a counter, which can identify the start signal and the end signal, and save the baud rate parameter between the start signal and the end signal into a buffer.
[0032] Optionally, the string comparison submodule includes three output terminals, namely an equal output terminal, a greater than output terminal and a less than output terminal, and the equal output terminal is connected to the baud rate setting submodule so that the baud rate setting submodule outputs the modification signal when the data includes the specific command.
[0033] Optionally, the string comparison submodule includes a buffer and a comparison unit, the buffer is used to store the data, and the comparison unit is used to read the string from the buffer and compare the read string with the predetermined string to obtain the comparison result.
[0034] Optionally, the data transmission submodule is initialized to transmit the data with the external device based on a reference baud rate until the data transmission submodule receives the specific command sent by the external device and delays modifying the baud rate, and then transmits data using the modified baud rate.
[0035] Optionally, the specific command includes a command identifier and a baud rate parameter, the command identifier is used to distinguish the specific command from other commands received by the module, and the baud rate parameter is used to indicate a modified baud rate.
[0036] Optionally, the specific command is expressed as follows:
[0037] .BAUD(a)
[0038] Wherein, “.BAUD” is the command identifier, and a is the baud rate parameter.
[0039] In a second aspect, an FPGA-based adaptive baud rate method is provided, which is used for the FPGA-based adaptive baud rate module described in the first aspect, and the method comprises:
[0040] Receive data sent by external devices through the serial port;
[0041] Compare the data with a predetermined string to obtain a comparison result; the predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes the specific command, and the specific command is used to indicate switching the baud rate;
[0042] extracting a baud rate parameter from the data;
[0043] When the comparison result indicates that the data includes the specific command and the baud rate parameter in the specific command is extracted, start timing, and output a timing completion signal after reaching a preset delay time;
[0044] Convert the baud rate parameter into BCD code;
[0045] converting the updated BCD code into a hexadecimal code based on the received timing completion signal;
[0046] The data is transmitted according to the hexadecimal code.
[0047] The beneficial effects of the present application include: by splitting the adaptive baud rate module into multiple submodules, each submodule focuses on a specific function, such as serial port data filtering, baud rate conversion, etc., making the overall design clearer and easier to understand. The input and output interfaces of each module are also relatively simple and clear, which facilitates connection and debugging between modules.
[0048] In addition, modular design makes the system easier to maintain and modify. When a function needs to be modified, you only need to focus on the design and code of the corresponding module, which will not have a big impact on the overall system. This separation design allows team members to independently develop, test and maintain each module.
[0049] In addition, modular design encourages code reuse. Some common modules, such as string processing modules and baud rate conversion modules, can be reused in different projects, reducing the workload of rewriting code and improving the reliability and stability of the code.
[0050] In addition, modular design makes the system more flexible and scalable. The addition of new functions or the modification of old functions can be achieved by adding, replacing or adjusting modules without making large-scale modifications to the entire system. This design style also helps the system to be gradually iterated and upgraded.
[0051] In addition, modular design facilitates unit testing and inter-module interface testing. Each module can be tested independently to ensure the functional correctness of each module. At the same time, the interfaces between modules are clear and concise, which helps to quickly locate and solve problems.
[0052] In addition, traditional methods, such as the minimum number method, differential sorting method, and fixed data transmission method, all rely on pulse width measurement of the received data. These methods are susceptible to noise, jitter, and other transmission interference, resulting in reduced accuracy and stability of baud rate detection. Setting the baud rate through the explicit command .BAUD (digital) completely avoids these measurement errors because the baud rate is directly specified by explicit digital instructions and is accurate.
[0053] In addition, the traditional detection method needs a period of time to analyze the received data stream and extract the baud rate information from it, which may be time-consuming. Using the .BAUD (number) command, the baud rate switching can be completed in a very short time, because only a simple instruction needs to be parsed without long data analysis.
[0054] In addition, traditional methods, especially differential sorting, involve complex calculations and sorting operations, which consume a certain amount of hardware resources and processing time. Using explicit commands to set the baud rate greatly simplifies the calculation process, requiring only simple string parsing and digital conversion, greatly reducing hardware resource consumption and implementation complexity.
[0055] In addition, the traditional method relies on automatic detection, and the user cannot directly control and intervene in the baud rate detection and setting process. When the detection error occurs, the user cannot manually correct it. Using the .BAUD (digital) command, the user can fully control the baud rate setting and adjust it at any time according to needs, which has better adaptability and flexibility.
[0056] In addition, the traditional method of automatic baud rate detection is relatively complicated, and when problems occur, it is difficult to quickly locate and solve them. Using clear commands to set the baud rate makes debugging and maintenance more convenient. Users can directly view and modify the baud rate settings, making it easy to identify and solve problems.
[0057] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0058] Figure 1a and Figure 1b This is a schematic diagram of the circuit structure of an FPGA-based adaptive baud rate module provided by an embodiment of the present application;
[0059] Figure 2 is a schematic diagram of a data transmission submodule uart_var provided in one embodiment of the present application;
[0060] Figure 3 is a schematic diagram of a first submodule uart_var_limit_rx provided by an embodiment of the present application;
[0061] Figure 4 is a schematic diagram of a second submodule uart_var_limit_tx provided in one embodiment of the present application;
[0062] Figure 5 is a schematic diagram of a buffer string_save provided by an embodiment of the present application;
[0063] Figure 6 is a schematic diagram of a comparison unit string_compare provided in one embodiment of the present application;
[0064] Figure 7is a schematic diagram of a string comparison submodule string_save_cmp provided by an embodiment of the present application;
[0065] Figure 8 is a schematic diagram of a parameter extraction submodule string_param provided in one embodiment of the present application;
[0066] Fig. 9 It is a schematic diagram of a parameter conversion submodule numstr_to_bcd provided in one embodiment of the present application;
[0067] Fig.10 is a schematic diagram of modifying the delay submodule delay provided by an embodiment of the present application;
[0068] Fig.11 is a schematic diagram of a counter cnt provided by an embodiment of the present application;
[0069] Fig.12 Schematic diagram of a BCD code conversion submodule BCD_TO_HEX provided in one embodiment of the present application;
[0070] Fig.13 This is a flow chart of an FPGA-based adaptive baud rate method provided by an embodiment of the present application. DETAILED DESCRIPTION
[0071] The specific implementation methods of the present application are further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present application but are not intended to limit the scope of the present application.
[0072] As can be seen from the above, the traditional FPGA-based adaptive baud rate technology has the problems of high design complexity, long development cycle, high scalability and upgrade difficulty, and low resource utilization. The inventor creatively discovered that the above problems are caused by the non-modular design and the shortcomings of the adaptive termination method design. Specifically,
[0073] 1) Lack of flexibility: Non-modular designs are usually customized for specific applications, which means that once the requirements change, the entire design may need to be readjusted, resulting in the problem that the original resources cannot be effectively utilized.
[0074] 2) Redundant design: In non-modular design, due to the lack of reusability, the designs of different parts may have repeated functions or structures, which will lead to the problem of redundant use of resources.
[0075] 3) Difficult to optimize: In non-modular designs, since the various parts are tightly coupled, the optimization of one part may affect other parts, which makes resource optimization difficult.
[0076] 4) Design complexity: Non-modular design usually requires all details and possibilities to be considered at once, which makes the design process complicated and prone to design errors, leading to problems such as extended development cycles.
[0077] 5) Difficulty in verification and testing: Since the entire system is an integrated whole, any small change may require re-verification and testing of the entire system, which increases the time for verification and testing.
[0078] 6) High iteration cost: In non-modular design, each iteration may require a comprehensive redesign, which is much more expensive than the iteration cost of a modular design where only specific modules need to be modified or replaced.
[0079] Based on the above problems, the present application proposes an adaptive baud rate module based on FPGA, which completes all target requirements step by step in a form similar to building blocks by creating various sub-modules, increasing iterability and availability, and these different sub-modules can be coupled to different design modules, thereby improving reusability. At the same time, a reference baud rate is selected, and each time the baud rate is switched, there is no need to know the current baud rate. It only needs to switch to the reference baud rate, and then send the set switching command, ".BAUD (switched baud rate)", the module will automatically detect the command, and extract the baud rate data therein, and then perform transcoding storage, delay modification of the baud rate, and ensure that the previous data transmission is normal. Finally, the subsequent data transmission is continued at the modified baud rate, and the baud rate can be adapted. At this point, using clear commands to set the baud rate, only simple string parsing and digital conversion are required, which can greatly simplify the calculation process of the baud rate, reduce hardware resource consumption and implementation complexity.
[0080] The following is a detailed introduction to the FPGA-based adaptive baud rate module provided by the present application.
[0081] Figure 1a and Figure 1b FIG. 1 is a schematic diagram of a circuit structure of an FPGA-based adaptive baud rate module provided in an embodiment of the present application. Since the circuit structure is relatively large, the circuit structure is divided into two parts in this embodiment (i.e. Figure 1a and Figure 1b ) indicates. Figure 1a and Figure 1bIt can be seen that the module includes data transmission submodule uart_var, string comparison submodule string_save_cmp, parameter extraction submodule string_param, baud rate setting submodule RTL_AND, delay modification submodule delay, parameter conversion submodule numstr_to_bcd, BCD code storage submodule RTL_REG_ASYNC and BCD code conversion submodule BCD_TO_HEX.
[0082] The data transmission submodule uart_var is used for data transmission between the module and external devices. Figure 2 In this embodiment, the data transmission submodule uart_var can realize the data receiving and sending functions at different baud rates, and instantiate two submodules: the first submodule uart_var_limit_rx and the second submodule uart_var_limit_tx, which respectively handle data receiving and sending. The data transmission submodule uart_var obtains the baud rate parameter through the baud_var pin, so that different baud rates can be flexibly set, so that the module can adapt to different communication requirements.
[0083] refer to Figure 3 The first submodule in the data transmission submodule uart_var shown
[0084] uart_var_limit_rx, the first submodule implements the Universal Asynchronous Receiver / Transmitter (UART) data reception function through a state machine and a counter. The first submodule can flexibly adjust the baud rate according to the input baud rate limit value (baud_limit) to adapt to different clock frequencies and baud rate requirements. The first submodule processes the logic of data reception, state machine conversion, data output, reception completion flag setting, and counter reset through multiple always blocks to ensure that data is correctly received at different baud rates.
[0085] refer to Figure 4 The second submodule in the data transmission submodule uart_var shown
[0086] uart_var_limit_tx, the second submodule implements the UART data transmission function through the state machine, data shift register and counter, and can flexibly control the transmission rate according to the baud rate parameter limit value obtained by the baud_var pin.
[0087] The external device sends data to the FPGA through the serial port. Correspondingly, the data transmission submodule uart_var in the FPGA is used to receive the data sent by the external device through the serial port. After that, the received data is stored in uart_rx_data.
[0088] The string comparison submodule string_save_cmp is connected to the data transmission submodule uart_var. The string comparison submodule string_save_cmp is used to compare the data with a predetermined string based on combinational logic to obtain a comparison result. The predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes the specific command, and the specific command is used to indicate switching the baud rate.
[0089] Exemplarily, the specific command includes a command identifier and the baud rate parameter, the command identifier is used to distinguish the specific command from other commands received by the module, and the baud rate parameter is used to indicate the modified baud rate.
[0090] For example, the specific command is expressed as follows:
[0091] .BAUD(a)
[0092] Wherein, “.BAUD” is the command identifier, and a is the baud rate parameter.
[0093] The string comparison submodule string_save_cmp includes a buffer and a comparison unit, wherein the buffer is used to store the data, and the comparison unit is used to read a string from the buffer and compare the read string with the predetermined string to obtain the comparison result.
[0094] refer to Figure 5 The buffer string_save shown in the figure is used to receive and save the string. Through the combination of the state machine and the counter, after receiving the start signal, data processing is enabled and the subsequent received characters are saved in the buffer string_save until reset or the start signal is received again. The module is designed with parameters, and the maximum number of bytes and other parameters can be flexibly configured.
[0095] refer to Figure 6The comparison unit string_compare shown in the figure uses combinational logic to compare two strings immediately when the input changes, and sets the output signals of three output terminals according to the results. The three output terminals are equal output terminal, greater output terminal, and less output terminal. These output signals indicate the relationship between the strings: equal, greater than, or less than. The comparison unit string_compare can be used in situations where strings need to be compared, and the comparison results can drive subsequent logical operations.
[0096] In this embodiment, the buffer string_save and the comparison unit string_compare are combined to obtain the string comparison submodule string_save_cmp. Figure 7 , the string comparison submodule string_save_cmp stores the received string in str_buf through the buffer string_save, and then uses the comparison unit string_compare to compare the stored string with the predetermined string str_cmp, and finally outputs equal, greater and less signals to indicate the comparison result. That is, the string comparison submodule string_save_cmp includes three output terminals, equal output terminal equal, greater output terminal greater and less output terminal less.
[0097] At this time, if the module receives data containing a specific command, the string comparison submodule string_save_cmp sets the equal_flag of the equal output terminal equal to 1 to indicate that the specific command is successfully recognized.
[0098] The parameter extraction submodule string_param is connected to the data transmission submodule uart_var and is used to extract the baud rate parameter from the data. For example, the parameter "9600" is extracted from ".BAUD(9600)" to obtain the baud rate parameter.
[0099] refer to Figure 8 The parameter extraction submodule string_param shown in the figure realizes a function of receiving and saving a string through the combination of a state machine and a counter. It can identify the start signal and the end signal, and save the received characters to the buffer string_save. Through parameterized design, the maximum number of bytes and other parameters can be flexibly configured. In the present embodiment, the parameter extraction submodule string_param is used to save the baud rate parameter between the start signal and the end signal to the buffer string_save.
[0100] The baud rate setting submodule RTL_AND is connected to the string comparison submodule string_save_cmp and the parameter extraction submodule string_param respectively. The baud rate setting submodule RTL_AND is used to output a modification signal when the comparison result indicates that the data includes the specific command and the parameter extraction submodule string_param outputs the baud rate parameter.
[0101] Specifically, the baud rate setting submodule RTL_AND is connected to the equal output terminal equal of the string comparison submodule string_save_cmp, so that the baud rate setting submodule RTL_AND outputs a modification signal when the data includes a specific command. The baud rate setting submodule RTL_AND is connected to the parameter extraction end pin param_rec_done of the parameter extraction submodule string_param, so that the parameter extraction submodule string_param extracts the baud rate parameter, and outputs a modification signal.
[0102] The parameter conversion submodule numstr_to_bcd connected to the parameter extraction submodule string_param is used to convert the baud rate parameter into a binary-coded decimal (BCD) code.
[0103] refer to Fig. 9 The parameter conversion submodule numstr_to_bcd converts the input ASCII-encoded digital string into BCD code through the numstr pin. In this embodiment, the ASCII-encoded digital string is a baud rate parameter.
[0104] The delay modification submodule delay is connected to the baud rate setting submodule RTL_AND. The delay modification submodule delay is used to generate a delay signal to perform delay control for baud rate modification. In this embodiment, the delay duration of the delay modification submodule delay is used to ensure that data transmitted at an unmodified baud rate can continue to be transmitted normally. Specifically, the delay modification submodule delay is used to start timing when receiving a modification signal (i.e., change_baud_flag is 1) output by the baud rate setting submodule RTL_ANDchange_baud_flag pin, and output a timing completion signal after reaching a preset delay duration, thereby applying the new baud rate to the system.
[0105] refer to Fig.10The modified delay submodule delay shown in the figure, after a certain clock cycle (i.e., delay duration), the output delay_done is set high, indicating that the delay is completed. This delay period can be fixed or variable. This module uses a parameterizable counter to implement the delay function. The main logic is as follows: enable the counter according to the signals of the delay_start pin and the delay_en pin; when the counter reaches the predetermined delay period (determined by delay_cycle), output the delay_done signal. The counter can be configured to different working modes according to the parameters, including whether it is enabled, whether the upper limit of the count is variable, etc.
[0106] In this application, reference Fig.11 , counter cnt is a comprehensive and highly configurable counter cnt. Through different parameter combinations, various counting requirements can be achieved, such as unidirectional / bidirectional counting, fixed / variable counting upper limit, etc. The output of counter cnt includes the current count value, completion flag, empty flag and full flag, and these output signals can be used to control other logic modules.
[0107] Generally speaking, the main design of counter cnt is as follows:
[0108] 1. Counting direction: Determine whether to count upward or downward based on the dir parameter.
[0109] 2. Bidirectional counting: If the dual parameter is 1, both increment and decrement operations are supported.
[0110] 3. Count upper limit: can be a fixed max_value or a variable var_value.
[0111] 4. Count enable: If the en parameter is 1, the counter cnt operation requires the cnt_en signal to enable.
[0112] 5. Limit mode: If the limit parameter is 1, the counter cnt stops counting when it reaches the upper or lower limit.
[0113] The BCD code storage submodule RTL_REG_ASYNC is connected to the modification delay submodule delay and the parameter conversion submodule numstr_to_bcd respectively, and is used to update the data stored in the BCD code storage submodule RTL_REG_ASYNC using the BCD code output by the parameter conversion submodule numstr_to_bcd based on the received timing completion signal, and output the updated BCD code.
[0114] The BCD code conversion submodule BCD_TO_HEX and the BCD code storage submodule RTL_REG_ASYNC are used to convert the updated BCD code into a hexadecimal code. Fig.12 ,The BCD code conversion submodule BCD_TO_HEX converts the BCD code into a hexadecimal number, and the conversion process involves the ,“binary to BCD double two-five conversion method”.
[0115] The data transmission submodule uart_var is also connected to the BCD code conversion submodule BCD_TO_HEX, and is used to store the hexadecimal code output by the BCD code conversion submodule BCD_TO_HEX, and transmit data according to the hexadecimal code.
[0116] The hexadecimal code is stored in baud_var of the data transmission submodule uart_var, so that the data transmission submodule uart_var can send and receive data according to the currently set baud rate baud_var. During the transmission process, the start of data transmission can be controlled by tx_start.
[0117] Specifically, the first submodule adjusts the baud rate according to the baud rate limit value indicated by the input hexadecimal code to receive data; the second submodule controls the sending rate according to the baud rate limit value indicated by the input hexadecimal code to send data.
[0118] In this embodiment, the data transmission submodule uart_var is initialized to transmit the data with the external device based on the reference baud rate until the data transmission submodule uart_var receives the specific command sent by the external device and delays to modify the baud rate, and then uses the modified baud rate to transmit data.
[0119] In this embodiment, the above sub-modules are integrated and superimposed to realize the baud rate setting and data transmission functions in serial communication, and the correct timing control and baud rate modification functions are realized through the state machine and timing delay module.
[0120] In summary, the FPGA-based adaptive baud rate module provided in this embodiment makes the overall design clearer and easier to understand by splitting the adaptive baud rate module into multiple sub-modules, each of which focuses on a specific function, such as serial port data screening, baud rate conversion, etc. The input and output interfaces of each module are also relatively simple and clear, which is convenient for connection and debugging between modules.
[0121] In addition, modular design makes the system easier to maintain and modify. When a function needs to be modified, you only need to focus on the design and code of the corresponding module, which will not have a big impact on the overall system. This separation design allows team members to independently develop, test and maintain each module.
[0122] In addition, modular design encourages code reuse. Some common modules, such as string processing modules and baud rate conversion modules, can be reused in different projects, reducing the workload of rewriting code and improving the reliability and stability of the code.
[0123] In addition, modular design makes the system more flexible and scalable. The addition of new functions or the modification of old functions can be achieved by adding, replacing or adjusting modules without making large-scale modifications to the entire system. This design style also helps the system to be gradually iterated and upgraded.
[0124] In addition, modular design facilitates unit testing and inter-module interface testing. Each module can be tested independently to ensure the functional correctness of each module. At the same time, the interfaces between modules are clear and concise, which helps to quickly locate and solve problems.
[0125] In addition, traditional methods, such as the minimum number method, differential sorting method, and fixed data transmission method, all rely on pulse width measurement of the received data. These methods are susceptible to noise, jitter, and other transmission interference, resulting in reduced accuracy and stability of baud rate detection. Setting the baud rate through the explicit command .BAUD (digital) completely avoids these measurement errors because the baud rate is directly specified by explicit digital instructions and is accurate.
[0126] In addition, the traditional detection method needs a period of time to analyze the received data stream and extract the baud rate information from it, which may be time-consuming. Using the .BAUD (number) command, the baud rate switching can be completed in a very short time, because only a simple instruction needs to be parsed without long data analysis.
[0127] In addition, traditional methods, especially differential sorting, involve complex calculations and sorting operations, which consume a certain amount of hardware resources and processing time. Using explicit commands to set the baud rate greatly simplifies the calculation process, requiring only simple string parsing and digital conversion, greatly reducing hardware resource consumption and implementation complexity.
[0128] In addition, the traditional method relies on automatic detection, and the user cannot directly control and intervene in the baud rate detection and setting process. When the detection error occurs, the user cannot manually correct it. Using the .BAUD (digital) command, the user can fully control the baud rate setting and adjust it at any time according to needs, which has better adaptability and flexibility.
[0129] In addition, the traditional method of automatic baud rate detection is relatively complicated, and when problems occur, it is difficult to quickly locate and solve them. Using clear commands to set the baud rate makes debugging and maintenance more convenient. Users can directly view and modify the baud rate settings, making it easy to identify and solve problems.
[0130] Fig.13 : is a flowchart of an FPGA-based adaptive baud rate method provided by an embodiment of the present application. Figure 1a and Figure 1b The adaptive baud rate module shown in the figure is used as an example for explanation. The method includes at least the following steps:
[0131] Step 1301, receiving data sent by an external device through a serial port;
[0132] Step 1302, comparing the data with a predetermined string to obtain a comparison result; the predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes a specific command, and the specific command is used to indicate switching the baud rate;
[0133] Step 1303, extracting baud rate parameters from the data;
[0134] Step 1304, when the comparison result indicates that the data includes a specific command and the baud rate parameter in the specific command is extracted, start timing, and output a timing completion signal after reaching a preset delay time;
[0135] Step 1305, converting the baud rate parameter into BCD code;
[0136] Step 1306, converting the updated BCD code into a hexadecimal code based on the received timing completion signal;
[0137] Optionally, steps 1305 and 1306 may be performed synchronously with step 1304 .
[0138] Step 1307, when the timing is completed, transmit data according to the hexadecimal code.
[0139] In summary, the FPGA-based adaptive baud rate method provided in this embodiment uses clear string commands to set the baud rate instead of relying on the traditional automatic detection method. It provides higher accuracy and stability, and is easy for users to control and debug. It also supports a wide range of baud rate settings, which can be flexibly adjusted from the lowest baud rate to the highest baud rate. The parameterized design allows users to adjust the supported baud rate range according to specific needs.
[0140] In addition, the state machine and counter cnt are used together to accurately control the data transmission and reception process. This ensures that data transmission and reception can be accurately synchronized at different baud rates, ensuring the reliability and stability of communication.
[0141] In addition, each functional module (such as string storage, string comparison, baud rate adjustment, etc.) is highly modularized, which is easy to understand, test and maintain. The modules communicate through clear interfaces, making the overall design more scalable and reusable.
[0142] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0143] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. An adaptive baud rate module based on FPGA, characterized in that: The modules include: Data transmission submodule, used to receive data sent by external devices through the serial port; A string comparison submodule connected to the data transmission submodule compares the data with a predetermined string based on combinational logic to obtain a comparison result; the predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes the specific command, and the specific command is used to indicate switching the baud rate; A parameter extraction submodule connected to the data transmission submodule, used to extract baud rate parameters from the data; a baud rate setting submodule connected to the string comparison submodule and the parameter extraction submodule respectively, for outputting a modification signal when the comparison result indicates that the data includes the specific command and the parameter extraction submodule outputs the baud rate parameter; A delay modification submodule connected to the baud rate setting submodule, used to start timing when receiving the modification signal, and output a timing completion signal after reaching a preset delay time; A parameter conversion submodule connected to the parameter extraction submodule, used for converting the baud rate parameter into BCD code; A BCD code storage submodule connected to the modification delay submodule and the parameter conversion submodule respectively, for updating the data stored in the BCD code storage submodule using the BCD code output by the parameter conversion submodule based on the received timing completion signal, and outputting the updated BCD code; A BCD code conversion submodule connected to the BCD code storage submodule, used to convert the updated BCD code into a hexadecimal code; The data transmission submodule is also connected to the BCD code conversion submodule, and is used to store the hexadecimal code output by the BCD code conversion submodule and transmit data according to the hexadecimal code.
2. The module according to claim 1, characterized in that The parameter extraction submodule and the data transmission submodule both include a state machine, and the state machine is used to: In the case where the comparison result indicates that the character string includes the specific command, controlling the module to enter a baud rate setting state, performing baud rate modification in the baud rate setting state and waiting for the delay of the modification delay submodule to end; During normal data transmission, a data transmission state is entered, in which data is sent and received according to the current baud rate.
3. The module according to claim 1, characterized in that The data transmission submodule instantiates a first submodule and a second submodule; The first submodule includes a counter for adjusting the baud rate according to the baud rate limit value indicated by the input hexadecimal code to receive data; The second submodule includes a data shift register and a counter, which are used to control the transmission rate according to the baud rate limit value indicated by the input hexadecimal code to perform data transmission.
4. The module according to claim 1, characterized in that The parameter extraction submodule includes a counter, which can identify the start signal and the end signal, and save the baud rate parameter between the start signal and the end signal into a buffer.
5. The module according to claim 1, characterized in that The string comparison submodule includes three output terminals, namely, an equal output terminal, a greater than output terminal and a less than output terminal. The equal output terminal is connected to the baud rate setting submodule so that the baud rate setting submodule outputs the modification signal when the data includes the specific command.
6. The module according to claim 1, characterized in that The string comparison submodule includes a buffer and a comparison unit. The buffer is used to store the data. The comparison unit is used to read a string from the buffer and compare the read string with the predetermined string to obtain the comparison result.
7. The module according to any one of claims 1 to 6, characterized in that: Initialize the data transmission submodule and the external device to transmit the data based on the reference baud rate until the data transmission submodule receives the specific command sent by the external device and delays the modification of the baud rate, and then uses the modified baud rate to transmit data.
8. The module according to any one of claims 1 to 6, characterized in that: The specific command includes a command identifier and a baud rate parameter, the command identifier is used to distinguish the specific command from other commands received by the module, and the baud rate parameter is used to indicate a modified baud rate.
9. The module according to claim 8, characterized in that The specific command is represented as follows: .BAUD(a) Wherein, ".BAUD" is the command identifier, and a is the baud rate parameter.
10. An adaptive baud rate method based on FPGA, characterized in that: The method is used in the FPGA-based adaptive baud rate module according to any one of claims 1 to 9, and the method comprises: Receive data sent by external devices through the serial port; Compare the data with a predetermined string to obtain a comparison result; the predetermined string is a string corresponding to a specific command, and accordingly, the comparison result is used to indicate whether the data includes the specific command, and the specific command is used to indicate switching the baud rate; extracting a baud rate parameter from the data; When the comparison result indicates that the data includes the specific command and the baud rate parameter in the specific command is extracted, start timing, and output a timing completion signal after reaching a preset delay time; Convert the baud rate parameter into BCD code; converting the updated BCD code into a hexadecimal code based on the received timing completion signal; The data is transmitted according to the hexadecimal code.