Latency-driven shared buffer algorithm

Abstract

The invention discloses a time-delay driven shared buffer algorithm. A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of portions, one or more ports read data from and write the data to the shared buffer, and controller circuitry associates egress ports with available portions of the plurality of portions that are as close as possible to the respective egress ports.

Description

Technical Field

[0001] The present disclosure is generally directed to networking, and more particularly to networking devices, switches, and methods of operating the same. Background Art

[0002] Switches and similar network devices represent core components of many communications, security, and computing networks. Switches are often used to connect multiple devices, device types, networks, and network types.

[0003] Devices (including but not limited to personal computers, servers or other types of computing devices) can be interconnected using network devices such as switches. These interconnected entities form a network that enables data communication and resource sharing between nodes. Summary of the invention

[0004] According to one or more embodiments described herein, a computing system (e.g., a switch) can enable various systems (e.g., switches, servers, personal computers, and other computing devices) to communicate across a network. Multiple blocks or memories of a computing system can be used as shared buffers, thereby allowing multiple ports of the computing system to share buffer space.

[0005] Each port of the computing system may be associated with an ingress queue for packets and / or other formats of data received through the port. Each port may store data in one or more memory blocks of a shared buffer, which are selected based on a general algorithm, local RAM occupancy, physical location (e.g., location relative to an associated egress port of the data), shared buffer configuration / mode, etc. A shared buffer control and rebalancing system may be used to control which port writes to and / or reads from which particular block of the shared buffer.

[0006] The shared buffer rebalancing functionality as described herein allows for dynamic binding of ingress ports to portions of a shared buffer to implement an abstraction of a shared buffer. In an embodiment, an ingress port is dynamically bound to an available portion (one or more) of a shared buffer that is closest to an egress port associated with data to be transmitted. The disclosed delay-driven shared buffer algorithm enhances the rebalancing algorithm by taking into account forwarding "locality" or distance (e.g., the physical location of an egress port or set-of-egress ports Tq / set-of-Tq relative to a corresponding ingress port) and performs rebalancing on the "closest available" portion of a shared buffer between an ingress port and a target egress port Tq / set-of-Tq.

[0007] As described herein, traffic may be selectively sent through one or more specific ports of a computing system based on a number of factors, such as fairness, minimum buffer requirements, quality of service (QoS) requirements, prioritizing important flows, congestion control, etc. By evaluating various factors and changing the weights of ports or queues, the switching hardware of the computing system may be enabled to route traffic through the computing system in an efficient manner.

[0008] The present disclosure describes a system and method for enabling a switch or other computing system to associate an egress port with the closest available portion of a shared buffer. Embodiments of the present disclosure are intended to improve forwarding latency and other issues by implementing an improved buffer allocation method. The buffering method shown and described herein may be applied to a switch, a router, or any other suitable type of network device known or yet to be developed.

[0009] In an illustrative example, a system is disclosed that includes a shared buffer, wherein the shared buffer includes a plurality of portions; and a plurality of ports, wherein each of the plurality of ports includes a forwarding database to associate an egress port with at least one of the plurality of portions of the shared buffer.

[0010] In another example, a network device is disclosed that includes a shared buffer, wherein the shared buffer includes a plurality of portions; and a plurality of ports, wherein each of the plurality of ports includes a forwarding database to associate an egress port with at least one of the plurality of portions of the shared buffer.

[0011] In yet another example, a method is disclosed that includes writing a data packet to a shared buffer, wherein the shared buffer includes a plurality of portions; and forwarding the data packet using a plurality of ports, wherein each of the plurality of ports has a forwarding database that associates an egress port with at least one of the plurality of portions of the shared buffer.

[0012] Any of the above example aspects include, wherein based on the shared buffer algorithm and the forwarding database, the data packet is routed to a portion of the shared buffer, the portion of the available buffer that is as close as possible to the egress port associated with the data packet, and wherein the closest available portion of the shared buffer is different from the portion of the shared buffer that is closest to the egress port associated with the data packet. In other words, buffer allocation fairness is maintained between the ports, and the data packet is routed to the portion of the available buffer that is closest to the associated egress port.

[0013] Any of the above example aspects include where the plurality of portions of the shared buffer are distributed between different physical locations within the device, and the data packet is routed to a portion of the plurality of portions that is available and as close as possible to an egress port associated with the data packet.

[0014] Any of the above example aspects include where each forwarding database is determined based at least in part on a minimum requirement to reduce latency and maintain a shared buffer.

[0015] Any of the above example aspects include where each ingress port or group of ingress ports includes a forwarding database, and each forwarding database maps each ingress port with an available portion of the shared buffer that is as close as possible to the corresponding egress port.

[0016] Any of the above example aspects includes where each port of the plurality of ports is a destination egress (Tq) and an ingress destination (Rq).

[0017] Any of the example aspects above include where the controller circuit selectively associates the egress port with at least one of the plurality of portions of the shared buffer.

[0018] Any of the above.

[0019] Any of the above example aspects include, wherein the shared buffer is one of a plurality of shared buffers. Example aspects include, wherein data received from a first port of the one or more ports is stored in the shared buffer prior to transmission by a second port of the one or more ports.

[0020] Other features and advantages are described herein, and will be apparent from the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure is described in conjunction with the accompanying drawings, which are not necessarily drawn to scale:

[0022] Figure 1 is a block diagram showing an illustrative configuration of a switch according to at least some embodiments of the present disclosure;

[0023] Figure 2 is a block diagram showing an illustrative configuration of a shared buffer according to at least some embodiments of the present disclosure;

[0024] Figure 3 is a block diagram showing an illustrative configuration of a shared buffer according to at least some embodiments of the present disclosure;

[0025] Figure 4 is a block diagram showing an illustrative configuration of a switch network in accordance with at least some embodiments of the present disclosure; and

[0026] Figure 5 is a flow chart showing an illustrative configuration of a method in accordance with at least some embodiments of the present disclosure.

[0027] Like reference numbers and designations in the various drawings represent like elements. DETAILED DESCRIPTION

[0028] The following description provides only embodiments and is not intended to limit the scope, applicability or configuration of the claims. Instead, the following description will provide a feasible description for those skilled in the art to implement the embodiments. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the spirit and scope of the appended claims.

[0029] It will be appreciated from the following description that, for reasons of computational efficiency, the components of the system may be arranged in any suitable locations in a distributed network of components without affecting the operation of the system.

[0030] In addition, it should be understood that the various links connecting the elements can be wired, trace or wireless links, or any suitable combination thereof, or any other suitable known or later developed elements capable of providing data to and / or transmitting data from the connected elements. For example, the transmission medium used as a link can be any suitable electrical signal carrier, including coaxial cable, copper wire and optical fiber, electrical traces on a printed circuit board (PCB), etc.

[0031] As used herein, the phrases "at least one," "one or more," "or," and "and / or" are open-ended expressions that are both conjunctions and disjunctions in operation. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," "A, B and / or C," and "A, B, or C" means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0032] As used herein, the term "automatic" and variations thereof refer to any suitable process or operation that can be accomplished without substantial human input when the process or operation is performed. However, if input is received prior to the performance of the process or operation, then the process or operation may be automatic, even if the performance of the process or operation uses substantial or immaterial human input. Human input is considered substantial if it affects the manner in which the process or operation is performed. Human input that consents to the performance of a process or operation shall not be considered "substantial."

[0033] As used herein, the terms "determine," "compute," and "calculate" and variations thereof may be used interchangeably and include any suitable type of method, process, operation, or technique.

[0034] Various aspects of the disclosure are described herein with reference to the accompanying drawings, which are schematic illustrations of idealized configurations.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and the present disclosure.

[0036] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when the terms "include", "comprise", and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof is not excluded. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Reference now Figure 1-5 , various systems and methods for managing shared buffers in computing systems will be described. The concepts of shared buffer management shown and described herein can be applied to any type of computing system capable of receiving and / or transmitting data, whether the computing system includes one port or multiple ports. Such a computing system can be a switch, but it should be understood that any type of computing system can be used. The term "data packet" used herein should be interpreted as any suitable discrete amount of digitized information. Without departing from the scope of the present disclosure, the data stored in the shared buffer can be in the form of a single data packet, multiple data packets, or non-packetized data. In addition, it should be understood that the features and functions of the centralized architecture can be applied to or used in a distributed architecture, and vice versa.

[0038] According to one or more embodiments described herein, Figure 1 The illustrated switch 103 enables various systems (e.g., switches, servers, personal computers, and other computing devices) to communicate across the network. Figure 1 The computing device is described herein as switch 103, but it should be understood that Figure 1 The computing device may be any computing device capable of receiving data through the ports 106a-106d. Such a switch 103 described herein may be, for example, a switch or any computing device including a plurality of ports 106a-106d for connecting nodes on a network.

[0039] The ports 106a-106d of the switch 103 can be used as communication endpoints, thereby allowing the switch 103 to manage multiple simultaneous network connections with one or more nodes. Each port 106a-106d can be used to receive data associated with one or more streams or communication sessions. After receiving the data, each port 106a-106d can write the data to the units 121a-121d in the shared buffer 112. The ports 106a-106d of the switch 103 can be physical connection points, allowing a network cable to connect the switch 103 to one or more network nodes. Any known or unknown communication protocol (e.g., Ethernet, InfiniBand (IB), NVLink, etc.) can be used to provide a connection.

[0040] Once a data packet (or other format of data) is received by a port 106a-106d of the switch 103, the data packet may be temporarily stored in a shared buffer 112. The shared buffer 112 may include temporary storage space within the switch 103. Physically, the storage space of the shared buffer 112 may include a plurality of cells 121a-121d or blocks, each of which may be, for example, a random access memory (RAM) device. The shared buffer 112 may be used as an intermediate storage area, allowing the switch 103 to manage and control the forward transmission of data packets from the buffer 112. Packet buffering allows the switch to address issues such as forwarding decision delays, egress congestion, scheduling considerations (e.g., QoS), etc.

[0041] The shared buffer may have a specific amount of storage space, such as 156MB, 256MB, etc., and may include multiple RAM devices. Each RAM device may be a computer memory that can be used to store data (e.g., data packets received through ports 106a-106d). The smallest unit of RAM may be a cell 121a-121d, and each cell stores a bit or byte of data. Each cell 121a-121d in the shared buffer 112 may include a transistor and a capacitor. The transistor may be used as a switch to allow the control circuit of the switch to read the capacitor or change its state. The capacitor may be used to store an information bit, which may be 0 or 1.

[0042] Shared buffer 112 may include cells anywhere within switch 103. For example, cells 121a-121d may be part of a memory array or block, such as 1MB per block. A memory block may contain cells 121a-121d arranged in rows and columns.

[0043] Shared buffer 112 may include RAM devices organized into one or more cell arrays.

[0044] Each unit 121a - 121d can be assigned a specific address that can be used by components of the switch 103 to access or direct other components to access each specific unit 121a - 121d. When the processor needs to read or write specific data bits, it sends the corresponding memory address to the RAM. In some embodiments, each block of the shared buffer 112 can be assigned an address, and components can generally refer to a specific block rather than a more specific unit reference. In some embodiments, the address of a unit (e.g., a RAM location) 121a - 121d can indicate which block the unit 121a - 121d is in and the row and column of the unit 121a - 121d within the block. In this way, the processor 115, the shared buffer control system 109, and / or another component of the switch 103 can be enabled to reference any specific unit 121a - 121d of the shared buffer 112 and / or all units of a specific block.

[0045] In some embodiments, the units 121a - 121d of the shared buffer 112 can form a single, fragmented logical unit. To the ports 106a - 106d, the shared buffer 112 may appear as a memory of a single unit. Each port 106a - 106d can write data to any one of the units 121a - 121d in the shared buffer memory 118. The shared buffer control system 109 can control which unit 121a - 121d a specific port 106a - 106d writes the received data packet to. For example, the shared buffer control system 109 can direct each port 106a - 106d to write to a specific unit 121a - 121d. In some embodiments, the shared buffer control system 109 can be enabled to associate a specific unit 121a - 121d and / or a specific block of the shared buffer 112 with an egress port. In an embodiment, the units 121a - 121d and the egress port are associated based on "locality" or their relative positions to each other.

[0046] To read data from the units 121a - 121d, the control circuit of the switch 103 can cause a transistor to allow the charge on a capacitor to flow out onto the bit line. In some embodiments, buffered data packets can be organized in a queue, for example, associated with a dedicated queue for each egress port, as the data packets wait for transmission.

[0047] The shared buffer control system 109 can communicate with or be controlled by the processor 115. For example, the switch 103 can include a processor 115, such as a central processing unit (CPU), a microprocessor, or any circuit or device capable of reading instructions from the memory 118 and performing actions. The processor 115 can execute software instructions to control the operation of the switch 103.

[0048] Processor 115 may function as a central processing unit for switch 103 and execute operational capabilities of switch 103. Processor 115 may communicate with other components of switch 103, including shared buffer control system 109, to manage and execute computing operations.

[0049] The processor 115 can be configured to perform various computing tasks. The functions of the processor 115 may include executing program instructions, managing data within the system, and controlling the operation of other hardware components (e.g., shared buffer control system 109). The processor 115 may be a single-core or multi-core processor and may include one or more processing units, depending on the specific design and requirements of the switch 103. The design of the processor 115 may allow instruction execution, data processing, and overall system management, thereby achieving the performance and practicality of the switch 103 in various applications. In addition, the processor 115 may be programmed or adjusted to perform specific tasks and operations according to application requirements, thereby potentially enhancing the versatility and adaptability of the switch 103.

[0050] The switch 103 may also include one or more memory 118 components that may store data such as the shared buffer control and rebalancing algorithm 124. The memory 118 may be configured to communicate with the processor 115 of the switch 103. The communication between the memory 118 and the processor 115 may enable various operations, including but not limited to data exchange, command execution, and memory management. According to the embodiments described herein, the memory 118 may be used to store data related to the use of the units 121a-121d of the shared buffer 112 of the switch 103, such as the shared buffer control and rebalancing algorithm 124.

[0051] The memory 118 may be composed of a variety of physical components, depending on the specific type and design. The memory 118 may include one or more memory cells capable of storing data in the form of binary information. Such memory cells may be composed of transistors, capacitors, or other suitable electronic components, depending on the memory type, such as dynamic random access memory (DRAM), static random access memory (SRAM), or flash memory. In order to facilitate data transmission and communication with other parts of the switch 103, the memory 118 may also include Figure 1 Such physical components may collectively constitute memory 118 and / or shared buffer 112, thereby facilitating their ability to store and manage data, such as shared buffer control and rebalancing algorithm 124.

[0052] The shared buffer control and rebalancing algorithm 124 may be stored in the memory 118 and may include information about various aspects of the usage of the shared buffer 112. Such information may include data about the current buffer usage and the location of the available portions, etc. The shared buffer control and rebalancing algorithm 124 may include, for example, the number of currently active cells 121a-121d, the total number of cells 121a-121d, the number of currently inactive cells 121a-121d, and / or other data, as described in more detail below.

[0053] The shared buffer control and rebalancing algorithm 124 can be accessed and utilized by the processor 115 and / or the shared buffer control system 109 to manage the operation of the shared buffers and ports 106a-106d. For example, the processor 115 can utilize the shared buffer control and rebalancing algorithm 124 to manage the network traffic received by the ports 106a-106d by determining which units are closest to the egress port for a particular portion of the traffic, as described in more detail below. Therefore, the memory 118, potentially in combination with the processor 115, can play a key role in optimizing the use and performance of the ports 106a-106d of the switch 103.

[0054] In one or more embodiments of the present disclosure, the processor 115 or the shared buffer control system 109 of the switch 103 may perform a polling operation to retrieve data related to the activity of the units 121a-121d, for example, by polling the units 121a-121d, the shared buffer 112, the shared buffer control and rebalancing algorithm 124, the shared buffer control system 109, and / or other components of the switch 103 described herein. As used herein, polling may involve the processor 115 periodically or continuously querying or requesting data from the shared buffer control system 109, or may involve the processor 115 or the shared buffer control system 109 periodically or continuously querying or requesting data from the units 121a-121d or from the memory 118. In some embodiments, the polling process may include the processor 115 sending a request to the shared buffer control system 109 to retrieve the desired data. Upon receiving the request, the shared buffer control system 109 may compile the requested data and send it back to the processor 115.

[0055] like Figure 2As shown, similar to ports 106a - 106d, the ingress port 203a and egress port 203b of switch 203 can write / read data to / from the shared buffer 212. Each port 203a or 203b can write / read to / from a specific cell 121 of the shared buffer 212 based on instructions received by the shared buffer control system 109. In other words, each ingress port 203a can be dynamically bound to the available portion 121 of the shared buffer 112 that is closest to the egress port 203b associated with the data to be transmitted. Not every ingress port 203a always writes data to a specific portion of the shared buffer 121. The correlation between the ingress port 203a and the portion 121 is dynamic and can be adjusted according to availability (the occupancy of each portion 121), the destination of the data, etc. For example, ingress port_1 may have data for egress port_1 and egress port_8, so ingress port_1 can be dynamically bound to the available portion 121 closest to egress port_1 and egress port_8. At another point in time, ingress port_1 may have data for egress port_3 and egress port_6, so ingress port_1 can be dynamically bound to the available portion 121 closest to egress port_3 and egress port_6. Ports 203a - b can also report buffer usage to the shared buffer control system 109. The buffer usage information can be used to rebalance the shared buffer 212 via the rebalancer 200.

[0056] As described herein, data (e.g., data packets) can be selectively sent to the cell 121 of the shared buffer 212 through a specific one or more ports 203a based on various factors. The shared buffer control system 109 of switch 203 can include one or more application - specific integrated circuits (ASICs) or microprocessors to perform tasks such as determining which cell 121 the received data packet should be sent to. The shared buffer control system 109 can include various components, including, for example, port controllers that manage the operations of each port, network interface cards that facilitate data transmission, and internal data paths that direct the data flow within the switch 203. The shared buffer control system 109 can also include memory elements for temporarily storing data and management software for controlling the operation of the switch 203. Such a configuration can enable the shared buffer control system 109 to accurately track the usage of the shared buffer and provide data to the processor 115 of the switch 103 upon request.

[0057] The shared buffer control system 109 can control the management and rebalancing of the shared buffer 212 by governing which port writes each block of the shared buffer. The decision of which port 203 writes to which cell 121 of the shared buffer 112 can be based on factors such as occupancy, location, quota, required pool size, μBurst conditions, etc. of the shared buffer 112.

[0058] like Figure 3 As shown, data entering inlet port 303a (diagonal line) may be destined for outlet port 303b (with matching diagonal line). Inlet port 303a includes forwarding database 303c (e.g., forwarding table), which indicates the available portion 121a-121c closest to outlet port 303b in shared buffer 312. As shown, portion 121d is closest to outlet port 303b, however, gray shaded portion 121 is an occupied / unavailable portion of shared buffer 312. In addition to forwarding database 303c, flows are typically routed based on a control plan that includes a shared buffer algorithm, a forwarding table, and dynamic / static or complex state rules. Each forwarding database 303c is implemented to map the corresponding best matching portion (e.g., the closest available portion) of the shared buffer 312 of each outlet port 303b.

[0059] like Figure 4 As shown, switch 103a can be connected to multiple nodes, such as other switches 103b, 103c and / or other computing devices 403a, 403b, to form a network. The systems and methods described herein can be performed by switches 103a-103c in an interconnected node network. Multiple switches 103a-103c and / or other computing devices 403a, 403b can be interconnected in various topologies, such as star, ring or mesh, depending on the specific requirements and resilience required for the network. For example, in a star topology, multiple switches can be connected to a central switch, while in a ring topology, each switch can be connected to two other switches in a closed loop. In a mesh topology, each switch can be interconnected with each other switch in the network. These robust structures provide a degree of redundancy because data has multiple paths to propagate, thereby ensuring that network functionality can be maintained even in the event of a switch failure.

[0060] Each switch 103a-103c may be Figure 1 The switch 103 shown may also be any type of computing device. Each port 106a-106l of each switch 103a-103c may be connected to the same or different nodes. Figure 4In the example shown, the first switch 103a is connected to two ports 106g-106h of the second switch 103b through two ports 106a-106b, and is connected to two ports 106i-106j of the third switch 103c through two ports 106c-106d. Each of the second and third switches 103b-103c is connected to other computing devices 403a-403b through two ports 106e, 106f, 106k, 106l. Each switch 103a-103c may include a respective shared buffer 112a-112c. When a data packet is received through the port 106a-106l of the switch 103a-103c, the data packet may be stored in the shared buffer 112a-112c of the respective switch 103a-103c.

[0061] like Figure 5 As shown, according to one or more embodiments described herein, the method 500 described herein can be performed by the switch 103 or other computing device. The method 500 involves identifying information related to the use of the shared buffer, determining the available portion of the shared buffer, and associating the available portion of the shared buffer with the egress port according to the location (e.g., associating the available portion closest to the specific egress port). Although the features of the method 500 are described as being performed by the shared buffer control system 109 of the switch 103, 203, and 303, it should be understood that one or more functions can be performed by the processor 115, the rebalancing system 300, or any other computing device included in the switch 103, 203, and 303 or in communication with the switch 103, 203, and 303.

[0062] In some embodiments, the method can be performed by a network device (e.g., a controller circuit of a NIC, a switch, a switch, or any computing device including a shared buffer). In some embodiments, data received from a first port in a plurality of ports can be stored in a shared buffer before being transmitted by a second port in one or more ports. In addition, although the description provided herein relates to the use of a shared buffer used by a port, it should be understood that any computing system element capable of writing data to a memory can use a shared buffer in the same or similar manner as described herein. Therefore, the system and method described herein can be used by any entity using a shared buffer. In addition, a shared buffer can be one of a plurality of shared buffers. A controller (e.g., a microprocessor, an ASIC, or any other type of computing element) can selectively enable and disable the memory cell of each shared buffer according to the method 500 described herein.

[0063] At step 503, the shared buffer control system 109 may determine the occupancy of the shared buffer 112 of the switch 103. For example, the shared buffer control system 109 may poll the switch 103 to obtain the occupancy of the shared buffer 112. This may include the occupancy / availability of each unit / section 121.

[0064] Determining the occupancy of the shared buffer 112 of the switch 103 may include polling the occupancy of the shared buffer 112. Polling the occupancy may involve the processor 115 or the shared buffer control system 109 within the switch 103 repeatedly querying or checking the current state of the shared buffer 112 to measure how much capacity is being utilized at a particular moment. The polling process may occur at regular intervals, or may be event driven, triggered by certain conditions or changes in the state of the switch. The polling operation may result in a quantitative measure of the buffer occupancy, such as the occupancy of each portion 121 of the shared buffer 112.

[0065] At step 506, a plurality of egress ports are associated with a plurality of portions of the shared buffer. For example, the shared buffer control system 109 associates the egress port 303b with the available portion 121 of the shared buffer 112 that is closest to each respective egress port 303b.

[0066] At step 509, a data packet is received at ingress port 303a for routing.

[0067] At step 512, the shared buffer control system 109 or processor 115 identifies the available portion 121 of the shared buffer 112 closest to the egress port 303b associated with the received packet. In an embodiment, the forwarding database 303c associated with the ingress port 303a is used to determine which portion 121 of the shared buffer 112 the packet should be written to.

[0068] At step 515, the shared buffer control system 109 or processor 115 sends the received data packet to the identified portion 121 of the shared buffer 112. For example, the data packet is written to one of the portions 121a-121c.

[0069] At step 518, the shared buffer control system 109 or processor 115 routes the received data packet through the associated egress port.

[0070] In one or more embodiments of the present disclosure, method 500 can return to 503 after execution and restart the process. In some embodiments, the repetition of method 500 can occur without delay. In this case, once method 500 ends, method 500 can start the next iteration immediately. This arrangement can allow the continuous execution of method 500. In some embodiments, a pause of a predetermined amount of time can occur between the continuous iterations of method 500. The duration of the pause can be specified according to the operation needs of the method (e.g., specified by the user).

[0071] The present disclosure covers Figure 5 (and the corresponding method description), and including all the steps identified in Figure 5 The present disclosure also encompasses methods comprising one or more steps from the methods described herein and one or more steps from any other method described herein.

[0072] Embodiments of the present disclosure include a system comprising: a shared buffer, wherein the shared buffer includes a plurality of portions; and a plurality of ports, wherein each of the plurality of ports includes a forwarding database to associate an egress port with at least one of the plurality of portions of the shared buffer.

[0073] Embodiments of the present disclosure also include a network device having a shared buffer function, comprising: a shared buffer, wherein the shared buffer includes multiple parts; and multiple ports, wherein each of the multiple ports includes a forwarding database to associate an egress port with at least one of the multiple parts of the shared buffer.

[0074] Embodiments of the present disclosure also include a method for shared buffer rebalancing, comprising: writing a data packet to a shared buffer, wherein the shared buffer includes multiple parts; and forwarding the data packet using multiple ports, wherein each of the multiple ports has a forwarding database that associates an egress port with at least one of the multiple parts of the shared buffer.

[0075] Aspects of the above systems, devices, switches and / or methods include where a data packet is routed to a portion of a shared buffer based at least in part on a forwarding database, routed to an available portion of a plurality of portions that is as close as possible to an egress port associated with the data packet, and where the closest available portion of the shared buffer is different from the portion of the shared buffer that is closest to the egress port associated with the data packet.

[0076] Aspects of the above systems, devices, switches and / or methods include where multiple portions of a shared buffer are distributed between different physical locations within the device, and where a data packet is routed to a portion of the multiple portions that is available and as close as possible to an egress port associated with the data packet.

[0077] Aspects of the above-described systems, devices, switches, and / or methods include where each forwarding database is determined based at least in part on a minimum requirement to reduce latency and maintain a shared buffer.

[0078] Aspects of the above systems, devices, switches and / or methods include where each forwarding database maps each egress port with an available portion of the shared buffer that is as close as possible to the corresponding egress port.

[0079] Aspects of the above systems, devices, switches and / or methods include where each port of the plurality of ports is an egress target (Tq) and an ingress target (Rq).

[0080] Aspects of the above-described systems, devices, switches, and / or methods include where the controller circuit selectively associates the egress port with at least one of the plurality of portions of the shared buffer.

[0081] Aspects of the above systems, devices, switches, and / or methods include where data received from a first port of the one or more ports is stored in a shared buffer prior to transmission by a second port of the one or more ports.

[0082] Aspects of the above systems, devices, switches and / or methods include where the shared buffer is one of a plurality of shared buffers.

[0083] It should be understood that any feature described herein may be claimed in combination with any other feature described herein, whether or not such features are from the same embodiment described.

[0084] Specific details are given in the description to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will appreciate that the embodiments can be practiced without these specific details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the embodiments.

[0085] Although illustrative embodiments of the present disclosure are described herein in detail, it should be understood that the concepts of the present invention may be embodied and used in other various ways, and that the appended claims are intended to be interpreted to include such variations unless limited by the prior art.

Claims

1. A system comprising: a shared buffer, wherein the shared buffer comprises a plurality of portions; as well as A plurality of ports, wherein each port of the plurality of ports comprises a forwarding database to associate an egress port with at least one of the plurality of portions of the shared buffer.

2. The system of claim 1 , wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database, to an available portion of the plurality of portions that is as close as possible to an egress port associated with the packet, and wherein the closest available portion of the shared buffer is different from a portion of the shared buffer that is closest to the egress port associated with the packet.

3. The system of claim 1 , wherein the plurality of portions of the shared buffer are distributed between different physical locations within a device, and a data packet is routed to a portion of the plurality of portions that is as close as possible to an egress port associated with the data packet and is available. The system of claim 3 , wherein the device comprises a network switch.

5. The system of claim 1, wherein each forwarding database is determined based at least in part on a minimum requirement to reduce latency and maintain the shared buffer.

6. The system of claim 1, wherein each forwarding database maps each egress port to an available portion of the shared buffer that is as close as possible to the corresponding egress port.

7. The system of claim 1, wherein each port of the plurality of ports is a destination egress Tq and an ingress destination Rq.

8. A network device having a shared buffer function, the network device comprising: a shared buffer, wherein the shared buffer comprises a plurality of portions; as well as A plurality of ports, wherein each port of the plurality of ports comprises a forwarding database to associate an egress port with at least one of the plurality of portions of the shared buffer.

9. The network device of claim 8, wherein a data packet is routed to a portion of the shared buffer based at least in part on the forwarding database, to an available portion of the shared buffer that is as close as possible to an egress port associated with the data packet, and wherein the closest available portion of the shared buffer is not a portion of the shared buffer that is closest to the egress port associated with the data packet.

10. The network device of claim 8, wherein the plurality of portions of the shared buffer are distributed between different physical locations within the device, and wherein a data packet is routed to a portion of the shared buffer that is as close as possible to an egress port associated with the data packet and that is available.

11. The network device of claim 8, wherein each forwarding database is determined based at least in part on a minimum requirement to reduce latency and maintain the shared buffer.

12. The network device of claim 8, wherein each forwarding database maps each egress port to an available portion of the shared buffer that is as close as possible to the corresponding egress port.

13. The network device of claim 8, wherein the network device comprises a network switch.

14. The network device of claim 8, wherein each port of the plurality of ports is an egress target Tq and an ingress target Rq.

15. A method for shared buffer rebalancing, the method comprising: writing a data packet into a shared buffer, wherein the shared buffer comprises a plurality of portions; as well as The data packet is forwarded using a plurality of ports, wherein each port of the plurality of ports has a forwarding database that associates an egress port with at least one of the plurality of portions of the shared buffer.

16. The method of claim 15, wherein the data packet is routed to a portion of the shared buffer based at least in part on the forwarding database, to an available portion of the shared buffer that is as close as possible to an egress port associated with the data packet, and wherein the closest available portion of the shared buffer is not a portion of the shared buffer that is closest to the egress port associated with the data packet.

17. The method of claim 15, wherein the plurality of portions of the shared buffer are distributed between different physical locations within a device, and wherein a data packet is routed to a portion of the shared buffer that is as close as possible to an egress port associated with the data packet and that is available.

18. The method of claim 17, wherein the device comprises a network switch.

19. The method of claim 15, wherein each forwarding database is determined based at least in part on a minimum requirement to reduce latency and maintain the shared buffer.

20. The method of claim 15, wherein each forwarding database maps each egress port to an available portion of the shared buffer that is as close as possible to the corresponding egress port.

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