Memory and method for manufacturing the same, electronic device

Abstract

The application provides a memory and a manufacturing method thereof, and an electronic device. The memory comprises a substrate and a storage unit, and the storage unit comprises a reading transistor and a writing transistor arranged in sequence in a direction away from the substrate; the reading transistor comprises a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain connected with the first channel respectively; the writing transistor comprises a ring-shaped second channel, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel; and the first gate of the reading transistor is electrically connected with the third source / drain of the writing transistor. The device architecture of the application can reduce the leakage current, reduce the power consumption, and reduce the area.

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, semiconductor technology, and in particular to a memory and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of a device is increasingly reduced, and the types and number of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the present application.

[0005] In an aspect, exemplary embodiments of the present application provide a memory, comprising a substrate and a memory cell, the memory cell comprising a read transistor and a write transistor arranged in sequence in a direction away from the substrate;

[0006] The read transistor comprises a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain connected to the first channel, respectively;

[0007] The write transistor comprises a second channel in the shape of a ring, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel;

[0008] The first gate of the read transistor is electrically connected to the third source / drain of the write transistor.

[0009] In exemplary embodiments, the first source / drain and the second source / drain at least partially surround the first gate, respectively, and the first source / drain, the first channel, and the second source / drain are arranged in sequence in a direction away from the substrate.

[0010] In exemplary embodiments, at least one of the third source / drain and the fourth source / drain is in the shape of a ring.

[0011] In exemplary embodiments, the first gate and the third source / drain are in an integral structure.

[0012] In an exemplary embodiment, the read transistor further comprises a first gate insulating layer in an annular shape, the first gate insulating layer being located between the first channel and the first gate, the first source / drain and the second source / drain being located on a side of the first gate insulating layer away from the first gate.

[0013] In an exemplary embodiment, the write transistor further comprises a second gate insulating layer in an annular shape, the second gate insulating layer being located between the second channel and the second gate, the third source / drain and the fourth source / drain being located on a side of the second gate insulating layer away from the second gate.

[0014] In an exemplary embodiment, the first channel comprises P-type or N-type doped single crystal silicon or polycrystalline silicon.

[0015] In an exemplary embodiment, the first source / drain and the second source / drain each comprise N-type doped single crystal silicon, and the first channel comprises P-type doped single crystal silicon.

[0016] In an exemplary embodiment, the second channel comprises P-type or N-type doped single crystal silicon or polycrystalline silicon.

[0017] In an exemplary embodiment, the third source / drain and the fourth source / drain each comprise N-type doped single crystal silicon, and the second channel comprises P-type doped single crystal silicon.

[0018] In an exemplary embodiment, a first via structure is further included, the first gate insulating layer and the first gate being located within the first via structure.

[0019] In an exemplary embodiment, a second via structure is further included, the second gate insulating layer and the second channel being located within the second via structure.

[0020] In an exemplary embodiment, the memory cell further comprises a capacitor, the capacitor being electrically connected to the read transistor.

[0021] In an exemplary embodiment, a first electrode of the capacitor is the first gate of the read transistor, a dielectric layer of the capacitor is a part of the first gate insulating layer, and a second electrode of the capacitor is disposed on a side of the first gate insulating layer away from the write transistor.

[0022] In an exemplary embodiment, a second electrode of the capacitor is a substrate, and a material of the substrate comprises silicon.

[0023] In another aspect, exemplary embodiments of the present application provide a method for manufacturing a memory, comprising the following steps:

[0024] A substrate is provided, a first source / drain material layer, a first channel material layer and a second source / drain material layer are sequentially formed in a direction away from the substrate;

[0025] A first via structure is formed through the first source / drain material layer, the first channel material layer and the second source / drain material layer to form a first source / drain, a first channel and a second source / drain;

[0026] A first gate is formed in the first via structure;

[0027] A second gate material layer is formed;

[0028] A second via structure is formed through the second gate material layer to form a second gate;

[0029] A third source / drain material layer, a second channel material layer and a fourth source / drain material layer are sequentially formed in the second via structure; and

[0030] A third via structure is formed through the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain, a second channel and a fourth source / drain;

[0031] The first gate is electrically connected with the third source / drain.

[0032] In an exemplary embodiment, forming the third source / drain, the second channel and the fourth source / drain further comprises:

[0033] The third source / drain material layer is formed in the second via structure, and the third source / drain material layer is N-doped;

[0034] The second channel material layer is formed, and the second channel material layer is P-doped;

[0035] The fourth source / drain material layer is formed, and the fourth source / drain material layer is N-doped.

[0036] In yet another aspect, an exemplary embodiment of the present application provides an electronic device comprising the memory device as described above.

[0037] In an exemplary embodiment, the electronic device comprises a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

[0038] The memory of the present application can have a 2T0C memory structure, and the read and write are separated, without damaging the data and without rewriting the data. The write transistor above has small leakage current, large current and fast speed, which can be comparable to SRAM. The read transistor below is made of silicon material, and has high silicon mobility and fast reading speed.

[0039] The read transistor and the write transistor of the present application are vertically stacked, which reduces the area and saves the area of SRAM.

[0040] The read transistor and the write transistor of the present application are made of silicon material, which is easy to integrate with logic chip to make embedded memory and can replace SRAM.

[0041] The write transistor of the present application adopts a ring-shaped hollow structure to ensure low leakage.

[0042] The memory of the present application can also be in the form of 2T1C memory structure. The present application sets a capacitor in the substrate of the read transistor, thereby preventing the problem of low gate capacitance and high leakage through the write transistor and increasing the data retention time, and also being able to inhibit the current sharing problem in 2T0C devices.

[0043] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings are included to provide an understanding of the present application, and constitute a part of the specification, together with the embodiments of the present application, to explain the technical scheme of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0045] Figure 1A A perspective view of a memory for an exemplary embodiment of the present application;

[0046] Figure 1B A cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in Figure 1A

[0047] Another cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in another memory for an exemplary embodiment of the present application; Figure 1C

[0048] Still another cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in still another memory for an exemplary embodiment of the present application; Figure 1D

[0049] Yet another cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in yet another memory for an exemplary embodiment of the present application; Figure 1E

[0050] Still yet another cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in still yet another memory for an exemplary embodiment of the present application; Figure 2An intermediate product obtained by an intermediate step of a manufacturing method of a memory for an exemplary embodiment of the present application is schematically shown in a vertical sectional view taken along a plane perpendicular to the substrate.

[0051] Figure 3 An intermediate product obtained by an intermediate step of a manufacturing method of a memory for an exemplary embodiment of the present application is schematically shown in a vertical sectional view taken along a plane perpendicular to the substrate.

[0052] Figure 4 An intermediate product obtained by an intermediate step of a manufacturing method of a memory for an exemplary embodiment of the present application is schematically shown in a vertical sectional view taken along a plane perpendicular to the substrate.

[0053] Figure 5 An intermediate product obtained by an intermediate step of a manufacturing method of a memory for an exemplary embodiment of the present application is schematically shown in a vertical sectional view taken along a plane perpendicular to the substrate; and

[0054] Figure 6 An intermediate product obtained by an intermediate step of a manufacturing method of a memory for an exemplary embodiment of the present application is schematically shown in a vertical sectional view taken along a plane perpendicular to the substrate. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the present application clearer, below the embodiments of the present application will be described in detail with reference to the drawings. It should be explained that the embodiments in the present application and the features in the embodiments can be combined with each other in any manner without conflict.

[0056] The embodiments herein can be implemented in a number of different ways. One skilled in the art will readily recognize that the embodiments and the features in the embodiments can be varied, and are meant as example embodiments only. The embodiments herein can be implemented in hardware, software, or a combination thereof. The various embodiments and / or features in the embodiments can be implemented alone, or in combination with each other.

[0057] The drawings in the present application can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the semiconductor layer, the thickness and the interval of each film layer can be adjusted according to the actual needs. The drawings described in the present application are only schematic structural diagrams, and one embodiment of the present application is not limited to the shapes or values shown in the drawings.

[0058] In this specification, terms indicating directions or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of components with reference to the drawings for the convenience of explanation and to simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present application. The positional relationship of components is changed as appropriate according to the direction in which each component is described. Therefore, the terms described in the specification are not limiting, and can be appropriately changed according to the situation.

[0059] In this specification, unless explicitly defined and limited otherwise, the terms "provided", "connected" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. The specific meaning of the above terms in the present application can be understood by the person skilled in the art according to the specific circumstances.

[0060] In the description of the present application, the ordinal numbers "first", "second", and the like are provided to avoid confusion of components, and are not intended to be limiting in terms of quantity.

[0061] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can be replaced by "metal film" sometimes.

[0062] In the description of the present application, a transistor refers to an element including at least three terminals of gate, drain, and source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In the present application, the channel layer refers to the region through which current mainly flows. In the present application, the terms "metal oxide semiconductor channel", "channel", and "channel layer" are interchangeable.

[0063] Static random access memory (SRAM) is widely used because it does not require a refresh circuit to save data stored therein and can operate at a speed of 20 ns or faster. However, SRAM has problems of large area and power leakage. Therefore, it is desirable to provide a DRAM memory that can match the response speed of SRAM and eliminate the problems of area and power leakage.

[0064] An exemplary embodiment of this application provides a memory including a substrate and a memory cell. The memory cell includes a read transistor and a write transistor sequentially disposed in a direction away from the substrate. The read transistor includes a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain respectively connected to the first channel. The write transistor includes an annular second channel, a third source / drain located on the side of the second channel near the substrate, a fourth source / drain located on the side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel. The first gate of the read transistor is electrically connected to the third source / drain of the write transistor.

[0065] As used in this application, the term "monolithic structure" can refer to a structure in which A and B have no obvious boundary interface such as discontinuities or gaps in their microstructure. Generally, a monolithic structure is a membrane layer patterned to form interconnected layers. For example, A and B are formed into a single membrane layer using the same material and simultaneously formed into a structure with interconnected relationships through the same patterning process.

[0066] Figure 1A A perspective view of a memory provided for an exemplary embodiment of this application; Figure 1B For along Figure 1A A schematic diagram of a cross-section perpendicular to the substrate, taken by section line AA'. (See diagram below.) Figure 1A and 1B As shown, the memory may include a substrate 1 and a memory cell. The memory cell includes a read transistor 100 and a write transistor 200 arranged sequentially in a direction away from the substrate. The read transistor 100 may include a first gate 150, a first channel 120 at least partially surrounding the first gate 150, and a first source / drain 110 and a second source / drain 130 respectively connected to the first channel 120. The write transistor 200 may include an annular second channel 230, a third source / drain 210 located on the side of the second channel 220 near the substrate, a fourth source / drain 230 located on the side of the second channel 220 away from the substrate, and a second gate 250 at least partially surrounding the second channel 220.

[0067] In an exemplary embodiment, the first source / drain 110 and the second source / drain 130 at least partially surround the first gate 150, and the first source / drain 110, the first channel 120, and the second source / drain 130 are arranged sequentially in a direction away from the substrate. This arrangement increases the contact area between the source and drain of the read transistor and the annular first channel, thereby reducing the contact resistance between them.

[0068] In an exemplary embodiment, at least one of the third source / drain electrode 210 and the fourth source / drain electrode 230 is ring-shaped. In an exemplary embodiment, both the third source / drain electrode 210 and the fourth source / drain electrode 230 are ring-shaped structures.

[0069] In the present application, surrounding can be understood as partially or entirely surrounding the first gate 150 or the second channel 220. In some embodiments, the surrounding can be entirely surrounding, and the cross section of the channel layer after surrounding can be a closed ring shape, and the ring shape can be adapted to the cross section outer contour shape of the first gate 150 or the second channel 220. For example, the cross section of the first gate 150 or the second channel 220 can be a circular shape, a rectangular shape, an elliptical shape, etc. The cross section is taken along a direction parallel to the substrate 1. In an exemplary embodiment, the surrounding can be partial surrounding, and the cross section after surrounding can not be closed, such as a ring shape with an opening.

[0070] With reference to Figure 1B , the read transistor 100 can further include a ring-shaped first gate insulating layer 140, the first gate insulating layer 140 being located between the first channel 120 and the first gate 150, and the first source / drain electrode 110 and the second source / drain electrode 130 being located on the side of the first gate insulating layer 140 away from the first gate 150. The write transistor 200 can further include a ring-shaped second gate insulating layer 240, the second gate insulating layer 240 being located between the second channel 220 and the second gate 250, and the third source / drain electrode 210 and the fourth source / drain electrode 230 being located on the side of the second gate insulating layer 240 away from the second gate 250.

[0071] In an exemplary embodiment, the first gate 150 of the read transistor 100 can be directly connected to the third source / drain electrode 210 of the write transistor 200, as shown in Figure 1E ; or the first gate 150 and the third source / drain electrode 210 can be an integral structure, as shown in Figure 1C , which can simplify the manufacturing process; or the first gate 150 can be connected to the third source / drain electrode 210 through a conductive connecting member 50, as shown in Figure 1B and Figure 1D . Thus, the present application can obtain a capacitor-free memory, such as a 2T0C DRAM memory, by interconnecting the gate of the read transistor and the third source / drain electrode of the write transistor.

[0072] With reference to Figure 1BThe diagram also shows that the memory may further include a first via structure K1 and a second via structure K2, wherein the first gate insulating layer 140 and the first gate 150 may be located within the first via structure K1; and the second gate insulating layer 240 and the second channel 220 may be located within the second via structure K2. This structural arrangement allows the second channel 220 to be formed within the via structure, facilitating the formation of an annular channel structure.

[0073] Figure 1E It is also shown that an insulating layer 40 may be included in the annular hollow second channel 220. The metal layer above the insulating layer 40 can be used to connect to the write bit line 260, while the metal layer below the insulating layer 40 can be used to connect to the first gate 150. Thus, the insulating layer 40 can be used to isolate the different metal layers deposited in the second channel.

[0074] Although this paper uses the references of first source / drain and second source / drain, as well as third source / drain and fourth source / drain, to identify two separate and distinct sources / drains, it is not intended that the source / drain referred to as "first" source / drain, or "second" source / drain, or "third" source / drain and "fourth" source / drain have a single meaning.

[0075] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is the source of a transistor, and the other is the drain of a transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain is the source of a transistor, and the other is the drain of a transistor.

[0076] like Figure 1A As shown, the first source / drain 110 of the read transistor can be connected to the read bit line 160, and the second source / drain 130 can be connected to the read word line 170, or the first source / drain 110 of the read transistor can be connected to the read word line 170, and the second source / drain 130 can be connected to the read bit line 160; the second gate 250 of the write transistor can be connected to the write word line 270, and the fourth source / drain 230 can be connected to the write bit line 260.

[0077] In an exemplary embodiment, the first channel 120 of the read transistor 100 may comprise P-type or N-type doped monocrystalline silicon or polycrystalline silicon. In an exemplary embodiment, the first source / drain 110 and the second source / drain 130 may comprise N-type doped monocrystalline silicon, while the first channel 120 may comprise P-type doped monocrystalline silicon.

[0078] In an exemplary embodiment, the second channel 220 of the write transistor 200 may comprise P-type or N-type doped monocrystalline silicon or polycrystalline silicon. In an exemplary embodiment, the third source / drain 210 and the fourth source / drain 230 may comprise N-type doped monocrystalline silicon, while the second channel 220 may comprise P-type doped monocrystalline silicon. Write transistors made of silicon can accelerate data writing speeds.

[0079] In addition, both the read transistor and the write transistor in this application are made of silicon material, which is compatible with the peripheral process. When making the silicon read transistor, the peripheral circuit can also be made at the same time, reducing the number of process steps.

[0080] The read transistor of this application has a ring channel structure, which is simpler than the ring gate process. Moreover, the ring channel is made of silicon, which has a fast response speed and can increase the turn-on current Ion, thereby improving the read speed.

[0081] The write transistor in this application also has a ring channel structure, and the middle of the ring channel has a hollow structure, thereby maximizing the protection against leakage current.

[0082] The device architecture of this application achieves operating response speeds comparable to SRAM while reducing leakage current, power consumption, and area. The device architecture of this application can achieve a lower shutdown current ISRAM than SRAM. off It's two orders of magnitude lower, and the turn-on current I... on The difference is not significant.

[0083] The write transistor 200 can primarily control leakage current. The device structure of this application allows the turn-off current I to be controlled. off It can be reduced to e -16 The order of magnitude, the turn-on current Ion can be reduced to e -4 Magnitude.

[0084] Furthermore, such as Figure 1D and 1E As shown, the memory of this application may further include a capacitor 300 electrically connected to the read transistor. The capacitor 300 may include a first electrode 310, a dielectric layer 320, and a second electrode 330. The first electrode 310 may be electrically connected to the memory node SN, and the first gate insulating layer 140 of the read transistor may also serve as the dielectric layer 320.

[0085] The first electrode 310 of the capacitor may be the first gate 150 of the read transistor, the dielectric layer 320 of the capacitor may be a part of the first gate insulating layer 140, and the second electrode 330 of the capacitor may be disposed on the side of the first gate insulating layer 140 away from the write transistor.

[0086] In the exemplary embodiment, the second electrode of the capacitor is a substrate, and the material of the substrate comprises silicon. Since the substrate comprises silicon material, it can be conductive and can serve as the second electrode of the capacitor, thus simplifying the manufacturing process of the capacitor.

[0087] The technical solution of the present application is further illustrated below by the manufacturing process of the memory of the exemplary embodiment of the present application. The "patterning process" in the present exemplary embodiment comprises deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which are mature manufacturing processes in the related art. The "photolithography process" in the present exemplary embodiment comprises coating of a film layer, mask exposure and development, which are mature manufacturing processes in the related art. Deposition can employ known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can employ known coating processes, and etching can employ known methods, which are not specifically limited herein. In the description of the present exemplary embodiment, it should be understood that "film" refers to a film of a certain material made on a substrate by deposition or coating process. If the "film" does not need to be subjected to patterning process or photolithography process during the entire manufacturing process, the "film" can also be referred to as "layer". If the "film" needs to be subjected to patterning process or photolithography process during the entire manufacturing process, it is referred to as "film" before the patterning process and referred to as "layer" after the patterning process. The "layer" after the patterning process or photolithography process comprises at least one "pattern".

[0088] In the exemplary embodiment, the manufacturing method of the memory can comprise the following steps:

[0089] S100: Forming a source / drain material layer and a first channel material layer of the read transistor.

[0090] The exemplary steps can comprise: depositing a layer of silicon substrate on the substrate and performing N-type doping to form an N+ type silicon substrate 1; depositing an insulating material film on the silicon substrate 1 to form a first insulating layer 10; forming a first source / drain material layer 110' of the read transistor 100 on the first insulating layer 10 by deposition; then depositing an insulating material film on the first source / drain material layer 110' to form a second insulating layer 20; forming a through hole penetrating through the second insulating layer 20 in the middle of the second insulating layer 20 by etching; filling Si into the through hole and performing P-type doping to form a first channel material layer 120'; depositing a layer of Si on the first channel material layer 120' and doping it into N+ type to form a second source / drain material layer 130' of the read transistor 100, as shown in FIG. 1. Figure 2 Figure 2 A vertical cross-sectional view of an intermediate product obtained by an intermediate step of the manufacturing method of the memory of the exemplary embodiment of the present application, taken along a plane perpendicular to the substrate.

[0091] ​In exemplary embodiments, the insulating layer thin films can be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0092] In exemplary embodiments, the first insulating layer 10 and the second insulating layer 20 can employ any one or more of non-conductive materials such as silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN). In exemplary embodiments, the first insulating layer 10 and the second insulating layer 20 can employ oxide insulating materials such as silicon dioxide (e.g., SiO2) for facilitating large-area deposition.

[0093] In exemplary embodiments, the first insulating layer 10 and the second insulating layer 20 can employ the same or different insulating materials.

[0094] In exemplary embodiments, the doping concentration of the first source / drain material layer 110’ and the second source / drain material layer 130’ is different from that of the first channel material layer 120’. In other exemplary embodiments, the first channel material layer 120’ can also be N-type doped, i.e., the doping type of the first source / drain material layer 110’, the first channel material layer 120’, and the second source / drain material layer 130’ is the same.

[0095] In exemplary embodiments, silicides can be prepared on the first source / drain material layer 110’ and the second source / drain material layer 130’ as connecting wires.

[0096] S200: Forming a first gate material layer of the read transistor.

[0097] Exemplary steps can include: forming a first via structure K1 in the structure formed in the foregoing steps by etching, the first via structure K1 passing through the second source / drain material layer 130’ and the first channel material layer 120’ and ending at the side of the first source / drain material layer 110’ away from the first channel material layer 120’; depositing a dielectric layer thin film and a conductive thin film in the first via structure K1 to form a first gate insulating material layer 140’ and a first gate material layer 150’ (i.e., the storage node SN of the read transistor); and then etching to remove the excess film layers, i.e., forming a read transistor 100 with a ring channel type structure, as shown in Figure 3 . Figure 3 A vertical cross-sectional view of an intermediate product obtained in an intermediate step of a manufacturing method of a memory according to an exemplary embodiment of the present application.

[0098] In an exemplary embodiment, the first gate insulating material layer 140' can be a high dielectric constant dielectric layer, i.e., a dielectric layer with K≥3.9. The high dielectric constant dielectric layer can serve as a gate oxide. The first gate insulating material layer 140' can employ any one or more of silicon dioxide (SiO2), aluminum trioxide (Al2O3), hafnium oxide (HfO2).

[0099] In an exemplary embodiment, the first gate material layer 150' can employ P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride, etc.

[0100] In an exemplary embodiment, the deposition of each thin film layer can employ an atomic layer deposition method.

[0101] In an exemplary embodiment, the orthographic projection of the first via structure K1 in a plane parallel to the substrate can be in the shape of a square, a rectangle, a circle, an ellipse, etc.

[0102] S300: Forming a second gate material layer of the write transistor.

[0103] An exemplary step can include: depositing an insulating material thin film to form a third insulating layer 30, etching to form a recess, and filling the recess with metal; depositing a metal material thin film on the third insulating layer 30 to form a second gate material layer 250'; forming a second via structure K2 in the second gate material layer 250' by etching; depositing a high dielectric constant material thin film around the inner sidewall of the second via structure K2 by an ALD process and etching away the high dielectric constant material at the bottom of the via, thereby forming a second gate insulating material layer 240', as shown in Figure 4 Figure 4 A vertical cross-sectional view of an intermediate product obtained in an intermediate step of a manufacturing method of a memory according to an exemplary embodiment of the present application.

[0104] S400: Forming a source-drain material layer and a second channel material layer of the write transistor.

[0105] ​The specific steps can include: depositing a third source / drain material layer 210' in the second via structure K2, and then performing N-type doping on the third source / drain material layer 210'; depositing a second channel material layer 220', and then performing P-type doping on the second channel material layer 220'; depositing a fourth source / drain material layer 230', and then performing N-type doping on the fourth source / drain material layer 230'; that is, sequentially forming an N-type doped silicon layer, a P-type doped silicon layer, and an N-type doped silicon layer in the second via structure K2, and finally forming an npn three-layer; forming a third via structure K3 penetrating the third source / drain material layer 210', the second channel material layer 220', and the fourth source / drain material layer 230' through etching, to form a third source / drain, a second channel, and a fourth source / drain, and the orthographic projection of the third via structure K3 on the substrate falls within the orthographic projection of the second via structure K2 and the second channel material layer 220' on the substrate, as shown in Figure 5 . Figure 5 An intermediate product obtained by an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application is shown in a vertical cross-sectional view taken along a plane perpendicular to the substrate.

[0106] S500: Through etching and interconnection process, depositing a metal thin film, an insulating layer thin film, and a metal thin film in the hollow structure K3, opening a source / drain / input / output terminal, leading out a Vout electrode, and the like, as shown in Figure 6 . Figure 6 An intermediate product obtained by an intermediate step of a manufacturing method of a memory provided by an exemplary embodiment of the present application is shown in a vertical cross-sectional view taken along a plane perpendicular to the substrate.

[0107] An exemplary embodiment of the present application further provides a manufacturing method of a memory, comprising the following steps:

[0108] Providing a substrate, sequentially forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer in a direction away from the substrate;

[0109] Forming a first via structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer to form a first source / drain, a first channel, and a second source / drain;

[0110] Forming a first gate in the first via structure;

[0111] Forming a second gate material layer;

[0112] Forming a second via structure penetrating the second gate material layer to form a second gate;

[0113] forming a third source / drain material layer, a second channel material layer and a fourth source / drain material layer in sequence in the second via structure; and

[0114] forming a third via structure penetrating through the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain, a second channel and a fourth source / drain;

[0115] electrically connecting the first gate and the third source / drain.

[0116] Exemplary embodiments of the present application also provide an electronic device comprising a memory as provided by exemplary embodiments of the present application.

[0117] In exemplary embodiments, the electronic device can comprise a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device or a mobile power supply.

[0118] Although the embodiments of the present application are disclosed as above, the content described is only the embodiments adopted for facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the form and details without departing from the spirit and scope of the present application. The protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A memory, comprising: The memory cell comprises a substrate and a memory cell, the memory cell comprises a read transistor and a write transistor arranged in sequence in a direction away from the substrate; The read transistor comprises a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain connected to the first channel respectively; The write transistor comprises a ring-shaped second channel, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel; The first gate of the read transistor is electrically connected to the third source / drain of the write transistor; The second channel comprises P-type or N-type doped single crystal silicon or polycrystalline silicon.

2. The memory of claim 1, wherein, The first source / drain and the second source / drain at least partially surround the first gate respectively, and the first source / drain, the first channel and the second source / drain are arranged in sequence in a direction away from the substrate.

3. The memory of claim 1, wherein, At least one of the third source / drain and the fourth source / drain is ring-shaped.

4. The memory of claim 1, wherein, The first gate and the third source / drain are an integral structure.

5. The memory of claim 1, wherein, The read transistor further comprises a ring-shaped first gate insulating layer located between the first channel and the first gate, and the first source / drain and the second source / drain are located on a side of the first gate insulating layer away from the first gate.

6. The memory of claim 1, wherein, The write transistor further comprises a ring-shaped second gate insulating layer located between the second channel and the second gate, and the third source / drain and the fourth source / drain are located on a side of the second gate insulating layer away from the second gate.

7. The memory of claim 1, wherein, The first channel comprises P-type or N-type doped single crystal silicon or polycrystalline silicon.

8. The memory of claim 7, wherein, The first source / drain and the second source / drain each comprise N-type doped single crystal silicon, and the first channel comprises P-type doped single crystal silicon.

9. The memory of claim 1, wherein, The third source / drain and the fourth source / drain each comprise N-type doped single crystal silicon.

10. The memory of claim 1, wherein, The second channel comprises P-type doped single crystal silicon.

11. The memory of claim 5, wherein, Further comprising a first via structure, the first gate insulating layer and the first gate are located in the first via structure.

12. The memory of claim 6, wherein, Further comprising a second via structure, the second gate insulating layer and the second channel are located in the second via structure.

13. The memory of claim 5, wherein, The memory cell further comprises a capacitor, and the capacitor is electrically connected to the read transistor.

14. The memory of claim 13, wherein, The first electrode of the capacitor is the first gate of the read transistor, the dielectric layer of the capacitor is part of the first gate insulating layer, and the second electrode of the capacitor is arranged on a side of the first gate insulating layer away from the write transistor.

15. The memory of claim 14, wherein, The second electrode of the capacitor is a substrate, and the material of the substrate comprises silicon.

16. A method of manufacturing a memory, characterized by: The method comprises the following steps: Providing a substrate, sequentially forming a first source / drain material layer, a first channel material layer and a second source / drain material layer in a direction away from the substrate; Forming a first via structure penetrating through the first source / drain material layer, the first channel material layer and the second source / drain material layer to form a first source / drain, a first channel and a second source / drain; forming a first gate electrode in the first via structure; forming a second gate material layer; forming a second via structure penetrating through the second gate material layer to form a second gate electrode; forming a third source / drain material layer, a second channel material layer and a fourth source / drain material layer in the second via structure in sequence; and forming a third via structure penetrating through the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain electrode, a second channel and a fourth source / drain electrode; electrically connecting the first gate electrode with the third source / drain electrode.

17. The manufacturing method according to claim 16, wherein forming a third source / drain electrode, a second channel and a fourth source / drain electrode further comprises: forming a third source / drain material layer in the second via structure, and performing N-type doping on the third source / drain material layer; forming a second channel material layer, and performing P-type doping on the second channel material layer; forming a fourth source / drain material layer, and performing N-type doping on the fourth source / drain material layer.

18. An electronic device, comprising: A memory comprising any one of claims 1-15.

Images