A gallium oxide solar-blind ultraviolet detector, its preparation method, and an imaging array

Abstract

The invention provides a gallium oxide solar-blind ultraviolet detector and a preparation method and an imaging array thereof, and belongs to the technical field of semiconductor devices. The gallium oxide solar-blind ultraviolet detector includes a substrate, a gate electrode, a first dielectric layer, an n-Ga2O3 layer, a second dielectric layer, a third dielectric layer, a first semiconductor layer from bottom to top, and also includes a source electrode, a drain electrode, an anode, a cathode and a second semiconductor layer. The gate electrode is covered by the first dielectric layer. The source electrode and the drain electrode are both located on the side of the n-Ga2O3 layer away from the first dielectric layer. The anode is located on the surface of the source electrode away from the n-Ga2O3 layer. The cathode and the n-Ga2O3 layer are respectively located at two ends of the surface of the first dielectric layer away from the substrate. The cathode is in direct contact with the first semiconductor layer. The anode is in direct contact with the second semiconductor layer. The first semiconductor layer and the second semiconductor layer form a pn junction. The gallium oxide solar-blind ultraviolet detector has the characteristics of high withstand voltage, small dark current and high detection efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide solar-blind ultraviolet detector and a preparation method thereof, and an imaging array composed of the gallium oxide solar-blind ultraviolet detector. Background Art

[0002] As an indispensable part of spectral detection, photodetectors play an important role in many scenarios such as biosensing, fire warning and deep space exploration. When used in unique scenarios, photodetectors will inevitably face extremely harsh environments (such as high temperature, high electric field and high radiation). However, traditional silicon-based photodetectors have high sensitivity to some light sources (such as ultraviolet light) and poor thermal stability, which makes it difficult to meet the needs of high sensitivity in harsh environments. Gallium oxide, as an emerging ultra-wide bandgap semiconductor material, has the advantages of good thermal stability, large bandgap width, large ultraviolet absorption coefficient, and easy material processing. Its corresponding light wavelength is 254~270nm, which corresponds to the day-blind ultraviolet band of 200~280nm. Therefore, gallium oxide material is an ideal candidate material for day-blind ultraviolet photodetectors. At the same time, since gallium oxide is an ultra-wide bandgap semiconductor material, its intrinsic carrier concentration is very low. Therefore, in the day-blind ultraviolet photodetector devices with the same structural design, the leakage current of gallium oxide day-blind ultraviolet photodetectors is smaller (that is, dark current is smaller), which further indicates that the noise of its detector is better.

[0003] In the prior art, when gallium oxide materials are used to design and prepare day-blind ultraviolet photodetectors, the most basic Schottky structure or metal-semiconductor-metal (MSM) structure is mainly used. Among them, the disadvantage of Schottky-type day-blind ultraviolet photodetectors is that the depletion region of the Schottky structure is thinner and the reverse barrier is lower, which leads to a larger leakage current (i.e., dark current) and a lower reverse bias voltage, making it more suitable for low-voltage occasions. Once the reverse bias voltage is higher, it cannot meet the use requirements. In addition, too many interface defects of the Schottky junction seriously affect the response speed of the device. The MSM structure is composed of two back-to-back Schottky barrier structures, which is essentially based on the Schottky junction and also has the disadvantages of the Schottky-type day-blind ultraviolet photodetector. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a gallium oxide solar-blind ultraviolet detector and a preparation method thereof. The gallium oxide solar-blind ultraviolet detector integrates a thin film transistor as a solar-blind ultraviolet detection unit and a light-emitting diode as a display unit, and the obtained integrated device has the characteristics of high withstand voltage and fast response speed.

[0005] Specifically, in order to achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A gallium oxide solar-blind ultraviolet detector comprises, from bottom to top, a substrate, a gate electrode, a first dielectric layer, an n-Ga2O3 layer, a second dielectric layer, a third dielectric layer, a first semiconductor layer, and also a source electrode, a drain electrode, an anode, a cathode and a second semiconductor layer; the gate electrode is covered by the first dielectric layer; the source electrode and the drain electrode are both located on the side of the n-Ga2O3 layer away from the first dielectric layer; the anode is located on the surface of the source electrode away from the n-Ga2O3 layer; the cathode and the n-Ga2O3 layer are respectively located at two ends of the surface of the first dielectric layer away from the substrate; the cathode is in direct contact with the first semiconductor layer; the anode is in direct contact with the second semiconductor layer; the first semiconductor layer and the second semiconductor layer form a pn junction.

[0007] In a preferred embodiment, the substrate is a transparent substrate.

[0008] In a preferred solution, the first medium layer is a transparent structure.

[0009] In a preferred embodiment, a p-type doped region is arranged in the surface layer or on the surface of the n-Ga2O3 layer on the side close to the second dielectric layer, and an n+ doped region is arranged in the surface layer or on the surface of the p-type doped region away from the first dielectric layer; the n+ doped region is in direct contact with the source electrode; and a base is arranged on the surface of the p-type doped region away from the first dielectric layer.

[0010] In a further preferred solution, the doping element of the p-type doping region is N.

[0011] In a further preferred embodiment, the doping element of the n+ doping region is Si.

[0012] In a preferred embodiment, the substrate is at least one of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate.

[0013] In a preferred embodiment, the material of the gate electrode is molybdenum.

[0014] In a preferred embodiment, the material of the first dielectric layer is at least one of SiN, SiO2, and Al2O3.

[0015] In a preferred embodiment, the material of the second dielectric layer is at least one of SiN, SiO2, and Al2O3.

[0016] In a preferred solution, the material of the third dielectric layer is at least one of SiN, SiO2, and Al2O3.

[0017] In a preferred embodiment, the material of the first semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

[0018] In a preferred embodiment, the material of the second semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

[0019] The method for preparing the gallium oxide solar-blind ultraviolet detector includes the following steps:

[0020] S1. Prepare a thin-film transistor and a light-emitting diode; wherein, the method for preparing the thin-film transistor includes the following steps:

[0021] S11-1. Fabricate a gate electrode on a substrate;

[0022] S11-2. Deposit a first dielectric layer on the substrate to cover the gate electrode;

[0023] S11-3. Deposit an n-Ga2O3 layer on the surface of the first dielectric layer facing away from the substrate, etch away a part of the n-Ga2O3 layer, and retain the n-Ga2O3 layer located above the gate electrode;

[0024] S11-4. Deposit a metal on the upper surface of the structure obtained in step S11-3, etch the metal layer to obtain a source electrode, a drain electrode, and a first cathode respectively; anneal;

[0025] S11-5. Deposit a second dielectric layer on the upper surface of the structure obtained in step S11-4, and etch the second dielectric layer to expose the upper surfaces of the source electrode and the first cathode;

[0026] The method for preparing the light-emitting diode includes the following steps:

[0027] S12-1. Fabricate a semiconductor layer, which includes a first semiconductor layer and a second semiconductor layer; the doping types of the first semiconductor layer and the second semiconductor layer are opposite; deposit a third dielectric layer on the surface of the semiconductor layer that needs to be combined with the second dielectric layer;

[0028] S12-2. Etch the third dielectric layer to obtain a first through hole and a second through hole that penetrate the third dielectric layer respectively;

[0029] S12-3. Deposit a metal on the surface of the third dielectric layer facing away from the semiconductor layer, etch, and retain the metal layer in the first through hole and the metal layer in the second through hole to obtain the anode and the second cathode of the light-emitting diode respectively;

[0030] S2. Combine the second dielectric layer with the third dielectric layer to make the anode in direct contact with the source electrode, and integrate the thin-film transistor and the light-emitting diode; the first cathode and the second cathode are in direct contact to form a whole as the cathode of the light-emitting diode.

[0031] In a preferred embodiment, in step S11-3, a p-type doped region is formed in the surface layer of the remaining n-Ga2O3 layer close to the second dielectric layer, and an n+-doped region is formed in the p-type doped region; in step S11-4, when etching the metal layer, a base is also obtained; the base forms an ohmic contact with the p-type doped region.

[0032] Arranging a plurality of gallium oxide solar-blind ultraviolet detectors provided by the present invention in an array can achieve array imaging display.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] (1) In the present invention, a gallium oxide thin-film transistor is used as a high-voltage-resistant solar-blind ultraviolet detection unit to convert an optical signal into an electrical signal; a light-emitting diode is used as a display unit to convert the electrical signal into an optical signal; by utilizing the characteristics of a large bandgap width of the gallium oxide material and being sensitive to ultraviolet light absorption, as well as the characteristic of the light-emitting diode to increase the carrier recombination rate, a gallium oxide solar-blind ultraviolet detector with characteristics such as high voltage resistance, small dark current, high detection efficiency, and fast response speed is obtained.

[0035] (2) Further, when there is one or more transparent structures in the device integrating the gallium oxide thin-film transistor and the light-emitting diode, light detection in multiple directions can be realized.

[0036] (3) Further, the integrated device also includes an APD. When the intensity of the ultraviolet light irradiation is small and the generated photo-generated carriers are small, the APD can increase the concentration of photo-generated carriers, thereby increasing the intensity of the current signal, so that even when the concentration of the original photo-generated carriers is very small, the light-emitting diode can emit light and display. Description of the Drawings

[0037] Figure 1 It is a schematic structural diagram of a gallium oxide solar-blind ultraviolet detector provided in Embodiment 1 of the present invention; it is also a schematic structural diagram of a gallium oxide solar-blind ultraviolet detector prepared in Embodiment 2 of the present invention.

[0038] Figure 2 It is another schematic structural diagram of a gallium oxide solar-blind ultraviolet detector provided in Embodiment 1 of the present invention.

[0039] Figure 3 It is another schematic structural diagram of a gallium oxide solar-blind ultraviolet detector provided in Embodiment 1 of the present invention.

[0040] Figure 4 Schematic structural diagram of another gallium oxide solar-blind ultraviolet detector provided in Embodiment 1 of the present invention;

[0041] Figures 5 to 12 Process schematic diagram of a method for preparing a gallium oxide solar-blind ultraviolet detector provided in Embodiment 2 of the present invention;

[0042] Figure 13 Schematic structural diagram obtained in step S11-3 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Embodiment 2 of the present invention;

[0043] Figure 14 Schematic structural diagram obtained in step S11-4 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Embodiment 2 of the present invention;

[0044] Figure 15 Schematic structural diagram obtained in step S12-1 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Embodiment 2 of the present invention;

[0045] Figure 16 Schematic structural diagram obtained in step S12-1 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Embodiment 2 of the present invention;

[0046] Figure 17 Schematic distribution diagram of gallium oxide solar-blind ultraviolet detectors in a gallium oxide solar-blind ultraviolet detector array provided by the present invention.

[0047] 1. Substrate; 2. Gate electrode; 3. First dielectric layer; 4. n-Ga2O3 layer; 5. Source electrode; 6. Drain electrode; 7. Cathode; 701. First cathode; 702. Second cathode; 8. Second dielectric layer; 9. First semiconductor layer; 10. Second semiconductor layer; 11. Third dielectric layer; 12. First via hole; 13. Second via hole; 14. Anode; 15. p-type doping region; 16. n+-doping region; 17. Base; 18. Groove; 100. Gallium oxide solar-blind ultraviolet detector. Detailed implementation manners

[0048] The following content describes the technical solutions of the present application clearly and completely in combination with embodiments, so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following embodiments by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0049] The directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the accompanying drawings of the specification, or the orientation or positional relationship in which the products of this application are usually placed during use. It is only for the convenience of describing and understanding the product structure of this application. Therefore, the directional terms should not be construed as a limitation to this application. In this application, unless otherwise clearly defined, expressions such as the first feature being "on", "above", "over", and "upper surface" of the second feature mean that the first feature and the second feature can be in direct contact or in indirect contact through an intermediate medium; the first feature can be directly above or obliquely above the second feature, or it only means that the first feature is at a higher horizontal level than the second feature. Expressions such as the first feature being "under", "beneath", "below", and "lower surface" of the second feature mean that the first feature and the second feature can be in direct contact or in indirect contact through an intermediate medium; the first feature can be directly below or obliquely below the second feature, or it only means that the first feature is at a lower horizontal level than the second feature. The ordinal numbers used in this application, such as "first", "second", etc., are only for descriptive purposes to distinguish similar objects, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0050] Embodiment 1

[0051] Referring to Figure 1 , a gallium oxide solar-blind ultraviolet detector includes a substrate 1, a gate electrode 2 and a first dielectric layer 3 located on the upper surface of the substrate 1, an n-Ga2O3 layer 4 located on the upper surface of the first dielectric layer 3, a second dielectric layer 8 located above the first dielectric layer 3, a third dielectric layer 11 located above the upper surface of the second dielectric layer 8, a first semiconductor layer 9 located on the upper surface of the third dielectric layer 11, and a source electrode 5, a drain electrode 6, a cathode 7, an anode 14, and a second semiconductor layer 10.

[0052] The gate electrode 2 is covered by the first dielectric layer 3. The direction from the substrate 1 to the first semiconductor layer 9 (or from the first semiconductor layer to the substrate 1) is defined as the first direction, the direction perpendicular to the paper surface is defined as the second direction, and the direction perpendicular to both the first direction and the second direction is defined as the third direction. In the third direction, one end of the n-Ga2O3 layer 4 is aligned with the side surface of the first dielectric layer 3, and the other end is located at a position near the middle on the upper surface of the first dielectric layer 3 (that is, in the third direction, there is a part of the upper surface of the first dielectric layer 3 without the n-Ga2O3 layer 4). The source electrode 5 and the drain electrode 6 are located on the upper surface of the n-Ga2O3 layer 4. The second dielectric layer 8 wraps around the outside of the n-Ga2O3 layer 4, the source electrode 5, and the drain electrode 6. The side surface of the n-Ga2O3 layer 4 aligned with the first dielectric layer 3 is exposed. The cathode 7 is located at the position on the upper surface of the first dielectric layer 3 without the n-Ga2O3 layer 4 and is in direct contact with the first semiconductor layer 9. The anode 14 is located on the upper surface of the source electrode 5. The upper surface of the anode 14 is in direct contact with the lower surface of the second semiconductor layer 10. The doping types of the second semiconductor layer 10 and the first semiconductor layer 9 are different, and a pn junction is formed between them. Specifically, the doping type of the first semiconductor layer 9 is n-type, and the doping type of the second semiconductor layer 10 is p-type.

[0053] The above-mentioned gallium oxide solar-blind ultraviolet detector is integrated with a bottom-gate thin-film transistor (TFT) and a light-emitting diode. The TFT serves as the detection unit, and the light-emitting diode serves as the display unit. In the detection unit, the depletion region of the n-Ga2O3 layer 4 (the n-Ga2O3 layer serves as the channel layer) is controlled by the gate electrode 2 to turn off the thin-film transistor. The anode 14 of the light-emitting diode is in direct contact with the source electrode 5 of the thin-film transistor, and the cathode 7 is located on one side of the entire integrated device. The working process of the entire integrated device is as follows: The drain electrode 6 of the thin-film transistor is connected to a high voltage. When a negative voltage is applied to the gate electrode 2 to deplete the carriers in the channel of the n-Ga2O3 layer 4, the TFT is turned off, and only a very small dark current passes through. When there is external light irradiation, such as solar-blind ultraviolet light irradiating on the depletion region, the gallium oxide material of the n-Ga2O3 layer 4 can just efficiently absorb the solar-blind ultraviolet light to generate photo-generated carriers. After a large number of electron-hole pairs are generated, under the action of the high-voltage strong electric field of the drain electrode 6, the electrons and holes quickly drift to both ends, forming a strong photocurrent (the current path is as shown by the red arrow in Figure 1 and Figure 2 ). When this photocurrent passes through the light-emitting diode, light of the corresponding color will be generated. Multiple above-mentioned gallium oxide solar-blind ultraviolet detectors 100 are packaged together and arranged in an array (such as Figure 17When the structure is as shown ( ), array imaging display can be achieved. When the materials of the light-emitting diodes in the structures of the gallium oxide solar-blind ultraviolet detectors 100 at different positions in the array are different, the colors of the light emitted by the gallium oxide solar-blind ultraviolet detectors 100 at different positions are different. According to different combinations of light colors, different information can be displayed. For example, when the light-emitting diode is a gallium arsenide (GaAs) diode, red light is emitted; when the light-emitting diode is a gallium phosphide (GaP) diode, green light is emitted; when the light-emitting diode is a silicon carbide (SiC) diode, yellow light is emitted; when the light-emitting diode is a gallium nitride (GaN) diode, blue light is emitted. By distributing the gallium oxide solar-blind ultraviolet detectors 100 integrated with these light-emitting diodes at different positions in the array as needed, different information can be displayed.

[0054] Further, with reference to Figure 4 , in some other specific structures of the gallium oxide solar-blind ultraviolet detector, a p-type doping region 15 is provided in or on the upper surface layer of the n-Ga2O3 layer 4, and an n+-doping region 16 is provided in or on the upper surface layer of the p-type doping region 15. The source electrode 5 is located on the upper surface of the n+-doping region 16. The area of the n+-doping region 16 is larger than the area of the projection of the source electrode 5 on the upper surface of the n-Ga2O3 layer 4. The n-Ga2O3 layer 4, the p-type doping region 15, and the n+-doping region 16 form an avalanche photodiode (APD). A base electrode 17 is provided on the surface of the p-type doping region 15 facing away from the first dielectric layer 3, and the base electrode 17 is located on the side of the source electrode 5 away from the drain electrode 6.

[0055] As an example, as Figure 4 shown, the upper surface of the p-type doping region 15 and the upper surface of the n+-doping region 16 are flush with the upper surface of the n-Ga2O3 layer 4. The n+-doping region 16 is located below the source electrode 5 (the source electrode 5 is located on the upper surface of the n+-doping region 16) and is in direct contact with the source electrode 5. The base electrode 17 is provided on the upper surface of the p-type doping region 15.

[0056] As an example, the upper surface of the p-type doping region 15 and the upper surface of the n+-doping region 16 are flush with the upper surface of the n-Ga2O3 layer 4. The bottom of the source electrode 5 extends deep into the n+-doping region 16 and is surrounded by the n+-doping region 16, and the top protrudes outside the upper surface of the n+-doping region 16. The bottom of the base electrode 17 extends deep into the p-type doping region 15 and is surrounded by the p-type doping region 15, and the top protrudes outside the upper surface of the p-type doping region 15.

[0057] As an example, the upper surface of the n+-doped region 16 protrudes beyond the upper surface of the p-type doped region 15. The source electrode 5 extends deep into the n+-doped region 16, and its bottom is surrounded by the n+-doped region 16 (i.e., the source electrode 5 does not contact the p-type doped region 15), and the top protrudes beyond the upper surface of the n+-doped region 16. Alternatively, the source electrode 5 is located on the upper surface of the n+-doped region 16.

[0058] As an example, the upper surface of the p-type doped region 15 protrudes beyond the upper surface of the n-Ga2O3 layer 4. The base electrode 17 extends deep into the p-type doped region 15, and its bottom is surrounded by the p-type doped region 15, and the top protrudes beyond the upper surface of the p-type doped region 15. Alternatively, the base electrode 17 is located on the upper surface of the p-type doped region 15.

[0059] When the intensity of the ultraviolet light irradiation received by the gallium oxide solar-blind ultraviolet detector is small, the concentration of photo-generated carriers is small, resulting in a small photo-generated current, which may cause the light-emitting diode not to conduct and display, thus unable to achieve the functions of ultraviolet detection and display. Therefore, an APD is further integrated in the above integrated device. When ultraviolet light irradiates the integrated device to form photo-generated carriers, the APD can increase the concentration of photo-generated carriers. Therefore, even when the concentration of photo-generated carriers is very small, the light-emitting diode can emit light and display.

[0060] Furthermore, the substrate 1 is a transparent substrate. When there is no transparent structure in the structure of the gallium oxide solar-blind ultraviolet detector, the solar-blind ultraviolet light can enter from the exposed side surface of the n-Ga2O3 layer 4. When the substrate 1 is a transparent substrate, in addition to entering from the exposed side surface of the n-Ga2O3 layer 4, the solar-blind ultraviolet light can also enter from the surface of the substrate 1 facing away from the first dielectric layer 3. Similarly, when there are other transparent structures in the structure of the gallium oxide solar-blind ultraviolet detector, the solar-blind ultraviolet light can also enter from the exposed surfaces of the other transparent structures.

[0061] Furthermore, the first dielectric layer 3 is a transparent structure.

[0062] As an example, the substrate 1 is any one or a combination of several of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate.

[0063] As an example, the material of the gate electrode 2 is metal molybdenum (Mo).

[0064] As an example, the material of the first dielectric layer 3 is any one or a combination of several of SiN, SiO2, and Al2O3.

[0065] As an example, the carrier concentration of the n-Ga2O3 layer 4 is 10 16 cm -3 order of magnitude.

[0066] As an example, the source electrode 5 is composed of a titanium layer and a gold (Ti / Au) layer.

[0067] As an example, the drain electrode 6 is composed of a titanium layer and a gold (Ti / Au) layer.

[0068] As an example, the cathode 7 is composed of a titanium layer and a gold (Ti / Au) layer.

[0069] As an example, the material of the second dielectric layer 8 is any one or a combination of several of SiN, SiO2, and Al2O3.

[0070] As an example, the material of the first semiconductor layer 9 is any one or a combination of several of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

[0071] As an example, the material of the second semiconductor layer 10 is any one or a combination of several of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

[0072] As an example, the upper surface of the second semiconductor layer 10 is flush with the upper surface of the third dielectric layer 11 (as Figure 1 shown); that is, the lower surface of the first semiconductor layer 9 is in direct contact with the upper surface of the second semiconductor layer 10 to form a pn junction, and the second semiconductor layer 10 is surrounded by the third dielectric layer 11. Or, the second semiconductor layer 10 is disposed inside the first semiconductor layer 9, and the lower surface of the second semiconductor layer 10 is flush with the lower surface of the first semiconductor layer 9 (as Figure 2 shown). Or, the second semiconductor layer 10 is disposed inside the first semiconductor layer 9 and is surrounded by the first semiconductor layer 9, and the anode 14 extends into the first semiconductor layer 9 to contact the lower surface of the second semiconductor layer 10, and the part of the anode 14 extending into the first semiconductor layer 9 is surrounded by the third dielectric layer 11 (as Figure 3 shown).

[0073] As an example, the material of the third dielectric layer 11 is any one or a combination of several of SiN, SiO2, and Al2O3.

[0074] As an example, the anode 14 is composed of a titanium layer and a gold (Ti / Au) layer.

[0075] As an example, the doping element of the p-type doping region 15 is N.

[0076] As an example, the doping concentration of the p-type doping region 15 is 1×10 18 cm -3 .

[0077] As an example, the doping element of the n+-doping region 16 is Si.

[0078] As an example, the doping concentration of the n+-doped region 16 is 1×10 19 cm -3 ~1×10 20 cm -3 ; for example, the doping concentration of the n+-doped region 16 is 1×10 19 cm -3 、1.1×10 19 cm -3 、1.2×10 19 cm -3 、1.5×10 19 cm -3 、2×10 19 cm -3 、2.5×10 19 cm -3 、3×10 19 cm -3 、3.5×10 19 cm -3 ……1×10 19 cm -3 。

[0079] Example 2

[0080] Referring to Figure 1 、 Figures 5 to 12 , a preparation method of a gallium oxide solar-blind ultraviolet detector includes the following steps:

[0081] S1. Prepare a thin film transistor and a light emitting diode. Among them, the preparation method of the thin film transistor includes the following steps:

[0082] S11-1. Fabricate a gate electrode 2 on a substrate 1 (as Figure 5 shown).

[0083] S11-2. Fabricate a first dielectric layer 3 on the upper surface of the structure obtained in step S11-1 (as Figure 6 shown). If the upper surface of the obtained first dielectric layer 3 has a large warpage, a chemical mechanical polishing (CMP) process can be used to flatten the sample surface.

[0084] S11-3. Deposit an n-Ga2O3 (n-type gallium oxide) layer on the upper surface of the first dielectric layer 3, etch away a part of the n-Ga2O3 layer, expose the upper surface of the first dielectric layer 3, and retain the n-Ga2O3 layer 4 located above the gate electrode 2 (as Figure 7 shown).

[0085] S11-4. Deposit a metal on the upper surface of the structure obtained in step S11-3, etch the metal layer, and respectively obtain a source electrode 5 and a drain electrode 6 of the thin film transistor and a first cathode 701 of the light emitting diode (asFigure 8 As shown); annealing is performed to form ohmic contacts between the source electrode 5 and the drain electrode 6 and the n-Ga2O3 layer 4 respectively.

[0086] S11-5. Deposit a second dielectric layer 8 on the upper surface of the structure obtained in step S11-4, and etch the second dielectric layer 8 to expose the upper surfaces of the source electrode 5 and the first cathode 701 (as Figure 9 shown).

[0087] The preparation of the light-emitting diode includes the following steps:

[0088] S12-1. Fabricate a semiconductor layer, which includes a first semiconductor layer 9 and a second semiconductor layer 10; the doping type of the first semiconductor layer 9 is n-type, and the doping type of the second semiconductor layer 10 is p-type. Deposit a third dielectric layer 11 on the upper surface of the semiconductor layer (as Figure 10 shown).

[0089] S12-2. Etch the third dielectric layer 11 to obtain a first through hole 12 and a second through hole 13 that penetrate the third dielectric layer respectively (as Figure 11 shown).

[0090] S12-3. Deposit metal on the upper surface of the structure obtained in step S12-2, and etch to retain the metal layers in the first through hole 12 and the second through hole 13 respectively to obtain the anode 14 and the second cathode 702 of the light-emitting diode (as Figure 12 shown).

[0091] S2. Integrate the thin-film transistor and the light-emitting diode, combine the third dielectric layer of the light-emitting diode with the second dielectric layer of the thin-film transistor, and make the anode 14 directly contact the source electrode 5, and the second cathode 702 directly contact the first cathode 701 to form a whole as the cathode 7 of the light-emitting diode (as Figure 1 shown).

[0092] Further, step S11-3 further includes the following steps: form a p-type doping region 15 in the remaining n-Ga2O3 layer 4, and form an n+ doping region 16 in the p-type doping region 15 (as Figure 13 shown). When etching the metal layer in step S11-4, the base 17 is also obtained (as Figure 14 shown). The source electrode 5 is located above the n+ doping region 16. The source electrode 5 forms an ohmic contact with the n-Ga2O3 layer 4, the drain electrode 6 forms an ohmic contact with the n+ doping region 16, and the base 17 forms an ohmic contact with the p-type doping region 15.

[0093] Further, after etching the anode 14 and the second cathode 702 in step S12-3, annealing is performed.

[0094] As an example, in step S11-1, the method of fabricating the gate electrode on the substrate is realized by a lift-off process (i.e., the Lift-Off process).

[0095] As an example, in step S11-3, the process of depositing the n-Ga2O3 layer is any one of molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and gallium oxide ceramic sputtering.

[0096] As an example, in step S11-3, the p-type doping region 15 is formed by nitrogen (N) ion implantation.

[0097] As an example, in step S11-3, the n+-doping region 16 is formed by silicon (Si) ion implantation.

[0098] As an example, in step S11-4, the method of depositing the metal is electron beam evaporation (EBE).

[0099] As an example, the annealing condition in step S11-4 is: maintaining at 470 °C for 1 min in a nitrogen atmosphere.

[0100] As an example, in step S12-1, the method of fabricating the semiconductor layer is: epitaxially growing a p-type second semiconductor layer 10 on the surface of the n-type first semiconductor layer 9, and the epitaxial method is homoepitaxy or heteroepitaxy. After the epitaxy is completed, the two ends of the second semiconductor layer 10 are etched away.

[0101] As an example, in step S12-1, the method of fabricating the semiconductor layer is: forming a p-type second semiconductor layer 10 inside the n-type first semiconductor layer 9 by ion implantation (as Figure 15 shown).

[0102] As an example, in step S12-1, the method of fabricating the semiconductor layer is: etching the n-type first semiconductor layer 9 to obtain a groove 18, and then obtaining a p-type second semiconductor layer 10 in the groove 18 by sputtering or epitaxy (as Figure 16 shown).

[0103] As an example, in step S12-3, the method of depositing the metal is electron beam evaporation.

[0104] As an example, the annealing condition in step S12-3 is: maintaining at 470 °C for 1 min in a nitrogen atmosphere.

[0105] As an example, in step S2, the thin-film transistor and the light-emitting diode are integrated by bonding.

[0106] The embodiments described above are only preferred embodiments of the present application and are not intended to limit the protection scope of the present application. For any person skilled in the art, various changes and modifications can be made to the present application. Any simple equivalent changes and modifications made based on the protection scope of the present application and the content of the specification shall be included within the protection scope of the present application.

Claims

1. A gallium oxide solar-blind ultraviolet detector, characterized in that, From bottom to top, it includes a substrate, a gate electrode, a first dielectric layer, an n-Ga2O3 layer, a second dielectric layer, a third dielectric layer, and a first semiconductor layer, and also includes a source electrode, a drain electrode, an anode, a cathode, and a second semiconductor layer; the gate electrode is covered by the first dielectric layer; both the source electrode and the drain electrode are located on the surface of the side of the n-Ga2O3 layer facing away from the first dielectric layer; the second dielectric layer wraps around the outside of the n-Ga2O3 layer, the source electrode, and the drain electrode; the anode is located on the surface of the source electrode facing away from the n-Ga2O3 layer; the cathode and the n-Ga2O3 layer are respectively located at both ends of the surface of the first dielectric layer on the side facing away from the substrate; the upper surface of the first dielectric layer between the cathode and the n-Ga2O3 layer is in direct contact with the second dielectric layer; the cathode is in direct contact with the first semiconductor layer; the upper surface of the anode is in direct contact with the lower surface of the second semiconductor layer; the first semiconductor layer and the second semiconductor layer form a pn junction.

2. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that, The substrate is a transparent substrate; and / or the first dielectric layer is a transparent structure.

3. The gallium oxide solar-blind ultraviolet detector according to claim 1, wherein, A p-type doping region is provided in or on the surface layer on the side of the n-Ga2O3 layer close to the second dielectric layer, and an n+-doping region is provided in or on the surface layer of the p-type doping region facing away from the first dielectric layer; the n+-doping region is in direct contact with the source electrode; a base electrode is provided on the surface of the p-type doping region facing away from the first dielectric layer.

4. The gallium oxide solar-blind ultraviolet detector according to claim 3, characterized in that The doping element of the p-type doping region is N; and / or the doping element of the n+-doping region is Si.

5. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that, The substrate is at least one of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate; and / or the material of the gate electrode is molybdenum.

6. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that, The material of the first dielectric layer is at least one of SiN, SiO2, and Al2O3; and / or the material of the second dielectric layer is at least one of SiN, SiO2, and Al2O3; and / or the material of the third dielectric layer is at least one of SiN, SiO2, and Al2O3.

7. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that, The material of the first semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond; and / or the material of the second semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

8. The preparation method of the gallium oxide solar-blind ultraviolet detector according to any one of claims 1 to 7, characterized in that, It includes the following steps: S1. Prepare a thin-film transistor and a light-emitting diode; wherein, the preparation method of the thin-film transistor includes the following steps: S11-1. Fabricate a gate electrode on the substrate; S11-2. Deposit a first dielectric layer on the substrate to cover the gate electrode; S11-3. Deposit an n-Ga2O3 layer on the surface of the first dielectric layer facing away from the substrate, and etch away a part of the n-Ga2O3 layer, leaving the n-Ga2O3 layer above the gate electrode; S11-4. Deposit a metal on the upper surface of the structure obtained in step S11-3, etch the metal layer to respectively obtain a source electrode, a drain electrode, and a first cathode; anneal; S11-5. Deposit a second dielectric layer on the upper surface of the structure obtained in step S11-4, and etch the second dielectric layer to expose the upper surface of the source electrode and the upper surface of the first cathode. The method for manufacturing the light-emitting diode includes the following steps: S12-1. Fabricate a semiconductor layer, which includes a first semiconductor layer and a second semiconductor layer; the doping types of the first semiconductor layer and the second semiconductor layer are opposite; deposit a third dielectric layer on the surface of the semiconductor layer that needs to be combined with the second dielectric layer. S12-2. Etch the third dielectric layer to obtain a first through-hole and a second through-hole that penetrate the third dielectric layer respectively. S12-3. Deposit metal on the surface of the third dielectric layer facing away from the semiconductor layer, and etch to retain the metal layer in the first through-hole and the metal layer in the second through-hole, respectively obtaining the anode and the second cathode of the light-emitting diode. S2. Combine the second dielectric layer with the third dielectric layer, make the anode directly contact the source electrode, and integrate the thin-film transistor and the light-emitting diode; the first cathode and the second cathode are directly in contact to form a whole as the cathode of the light-emitting diode.

9. The preparation method according to claim 8, characterized in that, In step S11-3, a p-type doped region is formed in the surface layer of the remaining n-Ga2O3 layer close to the second dielectric layer, and an n+ doped region is formed in the p-type doped region; when etching the metal layer in step S11-4, a base is also obtained; the base forms an ohmic contact with the p-type doped region.

10. A gallium oxide solar-blind ultraviolet detector array, characterized in that, The array includes a plurality of gallium oxide solar-blind ultraviolet detectors as described in any one of claims 1 to 7.

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