Display device

Abstract

The invention relates to a display device. The display device includes: a display panel including first and second light emitting elements alternately arranged in a first direction in odd columns, and third light emitting elements arranged in the first direction in even columns; and sensing portions disposed on the display panel, in which each of the sensing portions includes: a grid line between the nth first light emitting element and the nth second light emitting element, between the nth first light emitting element and the nth third light emitting element, and between the nth second light emitting element and the nth third light emitting element when viewed in a plan view; and conductive patterns interposed between the third light emitting elements arranged in one even column when viewed in a plan view, and wherein each of the conductive patterns has a width greater than that of each of the grid lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0162876 and Korean Patent Application No. 10-2024-0016893 filed on November 22, 2023 and February 2, 2024 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device. Background Art

[0004] Typically, electronic devices such as smartphones, digital cameras, laptops, navigation systems, or smart TVs that provide images to users include a display device to display these images. The display device generates the image and then presents it to the user through a display screen.

[0005] The display device includes a display panel generating an image and an input sensing part disposed on the display panel to detect an external input. The input sensing part detects a user's touch serving as an external input. The input sensing part includes a plurality of sensing parts sensing the external input.

[0006] A capacitance is formed by the sensing portion, and a change in the capacitance is detected when a user touches the input sensing portion. A technology for enhancing the touch sensitivity of the input sensing portion has been developed, making it easier to detect a user touch. Summary of the invention

[0007] Embodiments of the present disclosure provide a display device capable of enhancing the touch sensitivity of an input sensing portion thereof.

[0008] According to an embodiment of the present disclosure, a display device is provided, comprising: a display panel, comprising a plurality of first light-emitting elements and a plurality of second light-emitting elements alternately arranged in a first direction in odd columns, and a plurality of third light-emitting elements arranged in the first direction in even columns; and a plurality of sensing parts, arranged on the display panel, wherein each of the plurality of sensing parts comprises: a plurality of grid lines, which, when viewed in a plan view, are interposed between the nth first light-emitting element and the nth second light-emitting element, between the nth first light-emitting element and the nth third light-emitting element, and between the nth second light-emitting element and the nth third light-emitting element, wherein "n" is a natural number greater than 0; and a plurality of conductive patterns, which, when viewed in a plan view, are interposed between the third light-emitting elements arranged in an even column, and wherein a width of each of the conductive patterns is greater than a width of each of the grid lines.

[0009] According to an embodiment of the present disclosure, a display device is provided, which includes: a display panel, including a plurality of first light-emitting elements and a plurality of second light-emitting elements alternately arranged in the hth column, and a plurality of third light-emitting elements arranged in the h+1th column; and a plurality of sensing parts, arranged on the display panel, wherein each of the plurality of sensing parts includes: a plurality of grid lines, which, when viewed on a plane, are interposed between the nth first light-emitting element and the nth second light-emitting element, between the nth first light-emitting element and the nth third light-emitting element, and between the nth second light-emitting element and the nth third light-emitting element; and a plurality of conductive patterns, which, when viewed on a plane, are interposed between the third light-emitting elements, and wherein a width of each of the conductive patterns is greater than a width of each of the grid lines, wherein some of the grid lines are cut off, and wherein each of "h" and "n" is a natural number greater than 0. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1 A cross-sectional view of the display device shown.

[0013] Figure 3 yes Figure 2 A cross-sectional view of a display panel is shown.

[0014] Figure 4 yes Figure 2 A plan view of the display panel is shown.

[0015] Figure 5 It is shown Figure 4 A cross-sectional view of the configuration of any one pixel is shown.

[0016] Figure 6 is shown when viewed in plan view Figure 4 A view of an arrangement state of light emitting elements and first electrodes of pixels provided in a portion of a display area.

[0017] Figure 7 The light emitting element is shown separately but not shown Figure 6 View of the first electrode.

[0018] Figure 8 yes Figure 2 A plan view of the input sensing portion is shown.

[0019] Fig. 9yes Figure 8 FIG. 1 is an enlarged view of two first sensing portions adjacent to each other and two second sensing portions adjacent to each other.

[0020] Fig.10 It is shown Fig. 9 A view of the connection pattern shown.

[0021] Fig.11 It is shown Fig. 9 A view of the first and second sensing portions and the extended pattern is shown.

[0022] Fig.12 It is along Fig. 9 A cross-sectional view taken along line II'.

[0023] Fig.13A yes Fig. 9 An enlarged view of a local area of ​​any one of the first sensing portion and the second sensing portion is shown.

[0024] Fig. 13B is with Fig.13A The corresponding enlarged view is a view showing another shape of the conductive pattern.

[0025] Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 2 is a view illustrating cut-off patterns of first and second sensing parts according to various embodiments of the present disclosure.

[0026] Fig. 20 is a view illustrating a plan configuration of an auxiliary line connected to a second electrode according to another embodiment of the present disclosure.

[0027] Fig.21 It is schematically shown Fig. 20 A cross-sectional view of any one of the contact holes and two third light-emitting elements adjacent to the any one of the contact holes is shown.

[0028] Fig. 22 is a view illustrating a connection configuration between an auxiliary line and a common electrode according to another embodiment of the present disclosure.

[0029] Fig.23 is a view showing a structure of a display panel including a spacer according to another embodiment of the present disclosure.

[0030] Fig.24 It is schematically shown Fig.23 A cross-sectional view of any one of the spacers and a third light emitting element disposed with the spacer interposed therebetween.

[0031] Fig.25 and Fig.26 is a view showing a planar configuration of first and second sensing electrodes according to another embodiment of the present disclosure.

[0032] Fig. 27 It is along Fig.26 A cross-sectional view taken along line II-II' is shown.

[0033] Fig.28A is shown in more detail Fig. 27 A cross-sectional view of a conductive pattern and a dummy conductive pattern in FIG.

[0034] Fig.28B It is shown Fig. 27 A view of a configuration in which the conductive pattern and the dummy conductive pattern have the same width. DETAILED DESCRIPTION

[0035] In the present specification, the expression that a first component (or region, layer, portion, part, etc.) is “on”, “connected to” or “coupled to” a second component may mean that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is interposed therebetween.

[0036] In this specification, the same reference numerals may be assigned to the same components. In addition, in the drawings, the thickness, ratio, and size of components may be exaggerated.

[0037] The term "and / or" includes any and all combinations of one or more of the associated components.

[0038] Although the terms "first," "second," etc. may be used to describe various components, these components should not be construed as limited by these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0039] In addition, the terms "below", "at the lower portion", "above", "at the upper portion" are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0040] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. In addition, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the context in the relevant technology, and should not be interpreted in an ideal or overly formal manner unless explicitly defined herein.

[0041] It will also be understood that the terms “comprises,” “comprising,” “includes,” “including,” or “having” specify the presence of stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, and / or combinations thereof.

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0044] refer to Figure 1 According to an embodiment of the present disclosure, the display device DD may have a rectangular shape having a longer side extending in a first direction DR1 and a shorter side extending in a second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto, and the display device DD may have various shapes such as a circle or other polygons other than a rectangle. The first direction DR1 and the second direction DR2 are substantially perpendicular to each other while crossing each other.

[0045] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is a third direction DR3. In this specification, the meaning of "when viewed in a plan view" or "when viewed on a plane" may mean "when viewed in the third direction DR3".

[0046] The top surface of the display device DD may be referred to as a display surface DS, and may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0047] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA is intended to display an image, while the non-display area NDA does not display an image. The non-display area NDA may be an edge of the display device DD surrounding the display area DA and printed with a specific color.

[0048] The display device DD may be used for large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD may be used for small and medium-sized display devices such as personal computers, laptop computers, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers, or cameras. However, the types of display devices DD are provided for illustrative purposes only. The display device DD may be applied to other electronic devices as long as it does not deviate from the concept of the present disclosure.

[0049] Figure 2 yes Figure 1 A cross-sectional view of the display device shown.

[0050] For example, Figure 2 A cross-sectional view of the display device DD when viewed in a first direction DR1 is shown.

[0051] refer to Figure 2 , the display device DD may include a display panel DP, an input sensing part ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0052] According to an embodiment of the present disclosure, the display panel DP may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel DP is an organic light-emitting display panel.

[0053] The input sensing part ISP may be disposed on the display panel DP. The input sensing part ISP may include a plurality of sensing parts so as to sense external input in a capacitive manner. When manufacturing the display device DD, the input sensing part ISP may be directly formed on the display panel DP. However, the present disclosure is not limited thereto. The input sensing part ISP may be manufactured separately from the display panel DP and attached to the display panel DP through an adhesive layer.

[0054] The anti-reflection layer RPL may be disposed on the input sensing portion ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be disposed on the input sensing portion ISP. However, the present disclosure is not limited thereto. The anti-reflection layer RPL may be manufactured using an additional panel and attached to the input sensing portion ISP through an adhesive layer.

[0055] The anti-reflection layer RPL may be a film that prevents external light from being reflected. The anti-reflection layer RPL may reduce the reflectivity of external light incident from the top surface of the display device DD toward the display panel DP. As a result, the external light may not be visible to the user due to the anti-reflection layer RPL.

[0056] When external light directed toward the display panel DP is reflected back to the user, it may produce a mirror-like effect, enabling the user to see the external light. To prevent this phenomenon, the anti-reflection layer RPL may include a plurality of color filters presenting the same color as the pixels of the display panel DP.

[0057] The color filter may filter external light to match the color of the pixel. In this case, the external light may not be visible to the user. However, the present disclosure is not limited thereto. For example, the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflection index of the external light.

[0058] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing part ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0059] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect a lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0060] The first adhesive layer AL1 may be interposed between the display panel DP and the panel protection film PPF. For example, the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be interposed between the window WIN and the anti-reflection layer RPL. For example, the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0061] Figure 3 yes Figure 2 A cross-sectional view of a display panel is shown.

[0062] For example, Figure 3 A cross-sectional view of the display panel DP when viewed in the first direction DR1 is shown.

[0063] refer to Figure 3 The display panel DP includes a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0064] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED is disposed in the display area DA.

[0065] A plurality of pixels may be composed of a circuit element layer DP-CL and a display element layer DP-OLED. Each of the pixels may include a transistor disposed in the circuit element layer DP-CL and a light emitting element disposed in the display element layer DP-OLED to be connected to the transistor.

[0066] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign matter.

[0067] Figure 4 yes Figure 2 A plan view of the display panel is shown.

[0068] refer to Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light emitting driver EDV, and a plurality of first pads PD1.

[0069] Although the display panel DP may have a rectangular shape having longer sides extending in the first direction DR1 and shorter sides extending in the second direction DR2, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0070] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, first and second power lines PL1 and PL2, and connection lines CNL. In this case, "m" and "n" are natural numbers greater than 0.

[0071] The pixel PX may be disposed in the display area DA. The scanning driver SDV and the light emitting driver EDV may be disposed in the non-display area NDA to be adjacent to the longer sides of the display panel DP, respectively. The data driver DDV may be disposed in the non-display area NDA to be adjacent to one of the shorter sides of the display panel DP. When viewed in a plan view, the data driver DDV may be adjacent to the lower end of the display panel DP.

[0072] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 to be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 and be connected to the pixels PX and the emission driver EDV.

[0073] The first power line PL1 may extend in the first direction DR1 and may be disposed in the non-display area NDA. The first power line PL1 may be interposed between the display area DA and the light emitting driver EDV.

[0074] The connection line CNL may extend in the second direction DR2, may be arranged in the first direction DR1, and be connected to the first power line PL1 and the pixel PX. A first voltage may be applied to the pixel PX through the first power line PL1 and the connection line CNL connected to each other.

[0075] The second power line PL2 may be disposed in the non-display area NDA and extend along the longer side of the display panel DP and the shorter side of the display panel DP where the data driver DDV is not located. The second power line PL2 may be disposed outside the scan driver SDV and the light emitting driver EDV. The second power line PL2 may be connected to the pixel PX. A second voltage having a level lower than the first voltage may be applied to the pixel PX through the second power line PL2.

[0076] The first control line CSL1 may be connected to the scan driver SDV and extend toward the lower end portion of the display panel DP. The second control line CSL2 may be connected to the light emitting driver EDV and extend toward the lower end portion of the display panel DP. The data driver DDV may be interposed between the first control line CSL1 and the second control line CSL2.

[0077] The first pad PD1 may be disposed adjacent to the lower end portion of the display panel DP in the non-display area NDA and positioned closer to the lower end portion of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be connected to the first pad PD1. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the first pad PD1 corresponding to the data lines DL1 to DLn.

[0078] The display device DD may further include a timing controller for controlling the scan driver SDV, the data driver DDV, and the light emitting driver EDV, and a voltage generator for generating the first voltage and the second voltage. The timing controller and the voltage generator may be connected to the first pad PD1 through a printed circuit board.

[0079] The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages. The data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emitting driver EDV may generate a plurality of light emitting signals, and the light emitting signals may be applied to the pixels PX through the light emitting lines EL1 to ELm.

[0080] The pixel PX may receive a data voltage in response to the scan signal, and may display an image by emitting light having brightness corresponding to the data voltage in response to the light emission signal.

[0081] Figure 5 It is shown Figure 4 A cross-sectional view of the configuration of any one pixel is shown.

[0082] refer to Figure 5 , the pixel PX may include a plurality of transistors TR and TR' and a light emitting element OLED. The transistors TR and TR' and the light emitting element OLED may be disposed on a substrate SUB. Although two transistors TR and TR' are shown, the pixel PX may include more than two transistors.

[0083] The display area DA may include a light emitting area LEA corresponding to the pixel PX and a non-light emitting area NLEA adjacent to the light emitting area LEA. The light emitting element OLED may be disposed in the light emitting area LEA.

[0084] The buffer layer BFL is disposed on the substrate SUB and may be an inorganic layer. The semiconductor layers S, A, and D of the transistor TR may be disposed on the buffer layer BFL. The semiconductor layers S, A, and D may include polycrystalline silicon. However, the present disclosure is not limited thereto, and the semiconductor layers S, A, and D may include amorphous silicon.

[0085] The semiconductor layers S, A, and D may be doped with N-type dopants or P-type dopants. The semiconductor layers S, A, and D may include heavily doped regions and lightly doped regions. The heavily doped regions have a greater conductivity than the lightly doped regions and may be used as source and drain electrodes of the transistor TR. The lightly doped regions may correspond to the active (or channel) regions of the transistor TR.

[0086] The source region S, the channel region A, and the drain region D of the transistor TR may be formed of the semiconductor layers S, A, and D. The channel region A may be disposed between the source region S and the drain region D.

[0087] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S, A, and D. The gate electrode G of the transistor TR may be disposed on the first insulating layer INS1.

[0088] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the gate electrode G. The first dummy electrode DME may be disposed on the second insulating layer INS2. When viewed in a plan view, the first dummy electrode DME may be disposed over and overlap the gate electrode G. The first dummy electrode DME may form a capacitor together with the gate electrode G.

[0089] The lower metal layer BML may be disposed on the second insulating layer INS2. The lower metal layer BML may be disposed in the same layer as the first dummy electrode DME. The lower metal layer BML and the first dummy electrode DME may be patterned simultaneously with the same material. When viewed in a plan view, the lower metal layer BML may be disposed below the transistor TR' and overlap the transistor TR'.

[0090] The lower metal layer BML may receive a constant voltage. When the constant voltage is applied to the lower metal layer BML, a threshold voltage value of the transistor TR' disposed on the lower metal layer BML may remain unchanged.

[0091] The lower metal layer BML may block light incident on the transistor TR' below the lower metal layer BML. The lower metal layer BML may include a reflective metal. When external light is incident on the semiconductor layers S', A', and D' of the transistor TR', the semiconductor layers S', A', and D' of the transistor TR' may be damaged. The lower metal layer BML may block external light to prevent damage to the semiconductor layers S', A', and D' of the transistor TR'.

[0092] A lower metal layer BML may be further disposed under the transistor TR. In this case, the lower metal layer BML may be interposed between the substrate SUB and the buffer layer BFL. The lower metal layer BML may be omitted.

[0093] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the lower metal layer BML and the first dummy electrode DME. The semiconductor layers S', A', and D' of the transistor TR' may be disposed on the third insulating layer INS3. The semiconductor layers S', A', and D' may include an oxide semiconductor including a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0094] The semiconductor layers S', A' and D' may include a plurality of regions divided according to whether the metal oxide is reduced or not. The conductivity of the region where the metal oxide is reduced (referred to as the reduction region) is greater than the conductivity of the region where the metal oxide is not reduced (referred to as the non-reduction region). The reduction region may be used as a source electrode or a drain electrode of the transistor TR'. The non-reduction region may correspond to an active (or channel) region of the transistor TR'.

[0095] The source region S', the channel region A', and the drain region D' of the transistor TR' may be formed of the semiconductor layers S', A', and D'. The channel region A' may be interposed between the source region S' and the drain region D'.

[0096] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the semiconductor layers S', A' and D'. A gate electrode G' of the transistor TR' may be disposed on the fourth insulating layer INS4. A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the gate electrode G'.

[0097] The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer. For example, the buffer layer BFL, the first to fourth insulating layers INS1 and INS4 may include a silicon oxide layer, and the second insulating layer INS2 may include a silicon nitride layer.

[0098] Each of the third insulating layer INS3 and the fifth insulating layer INS5 may include a plurality of inorganic insulating layers including different materials and stacked on each other. For example, the third insulating layer INS3 may include a silicon nitride layer and a silicon oxide layer stacked sequentially, and the fifth insulating layer INS5 may include a silicon oxide layer and a silicon nitride layer stacked sequentially.

[0099] The thickness of each of the third and fifth insulating layers INS3 and INS5 may be greater than the thickness of the buffer layer BFL and each of the first, second, and fourth insulating layers INS1, INS2, and INS4. The “thickness” may be measured in the third direction DR3.

[0100] A plurality of first connection electrodes CNE1 and CNE1' may be disposed on the fifth insulating layer INS5. The first connection electrode CNE1 may be electrically connected to the source region S and the drain region D through a first contact hole CH1 formed in the first to fifth insulating layers INS1 to INS5. The first connection electrode CNE1' may be electrically connected to the source region S' and the drain region D' through a first contact hole CH1' formed in the fourth to fifth insulating layers INS4 to INS5.

[0101] A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first connection electrodes CNE1 and CNE1'. A second connection electrode CNE2 may be disposed on the sixth insulating layer INS6. The second connection electrode CNE2 may be electrically connected to the first connection electrode CNE1 connected to the drain region D through a second contact hole CH2 formed in the sixth insulating layer INS6. The first connection electrode CNE1' and the first connection electrode CNE1 connected to the source region S' and the source region S may be connected to different transistors of the pixel PX.

[0102] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second connection electrode CNE2. The sixth insulating layer INS6 and the seventh insulating layer INS7 may include an inorganic layer or an organic layer.

[0103] The fifth insulating layer INS5 may be an interlayer insulating layer. The sixth insulating layer INS6 may be a first via insulating layer. The seventh insulating layer INS7 may be a second via insulating layer.

[0104] The light emitting element OLED may be disposed on the seventh insulating layer INS7. The light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EML. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The second electrode CE is disposed on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the light emitting layer EML may be disposed between the first electrode AE ​​and the second electrode CE.

[0105] The first electrode AE ​​may be disposed on the seventh insulating layer INS7. The first electrode AE ​​may be electrically connected to the second connection electrode CNE2 through a third contact hole CH3 formed in the seventh insulating layer INS7. Therefore, the light emitting element OLED may be connected to the transistor TR through the connection electrode CNE (e.g., through the second connection electrode CNE2 and the first connection electrode CNE1 connected to the second connection electrode CNE2).

[0106] When viewed in a plan view, the third contact hole CH3 may overlap the non-emission area NLEA. The first electrode AE ​​may overlap the emission area LEA. In addition, the first electrode AE ​​may overlap a portion of the non-emission area NLEA adjacent to the emission area LEA.

[0107] The pixel defining layer PDL may be disposed on the first electrode AE ​​and the seventh insulating layer INS7. A pixel opening PX_OP for exposing a portion of the first electrode AE ​​may be formed in the pixel defining layer PDL. When viewed in a plan view, the pixel opening PX_OP may overlap the light emitting area LEA. When viewed in a plan view, the pixel defining layer PDL may overlap the non-light emitting area NLEA.

[0108] The hole control layer HCL may be interposed on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the light emitting area LEA and the non-light emitting area NLEA. The hole control layer HCL may be a common layer commonly disposed in a plurality of pixels PX. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0109] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in the pixel opening PX_OP. Therefore, the light emitting layer EML may overlap with the light emitting area LEA. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate any one of red light, green light, and blue light.

[0110] The electron control layer ECL may be disposed between the light emitting layer EML and the second electrode CE. The electron control layer ECL may be commonly disposed in the light emitting area LEA and the non-light emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer. The electron control layer ECL may be a common layer commonly disposed in a plurality of pixels PX.

[0111] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed in a plurality of pixels PX. For example, the second electrode CE may be commonly disposed on the light emitting layer EML and the pixel defining layer PDL of the pixel PX. The second electrode CE of the pixel PX may be an integrated common electrode.

[0112] The light emitting element OLED may be a portion disposed in the light emitting area LEA. In other words, portions of the hole control layer HCL, the electron control layer ECL, the first electrode AE, and the second electrode CE overlapping the light emitting area LEA may be components of the light emitting element OLED.

[0113] The layers from the buffer layer BFL to the seventh insulating layer INS7 may be the circuit element layer DP-CL. The layer in which the light emitting element OLED is disposed may be the display element layer DP-OLED.

[0114] The thin film encapsulation layer TFE may be disposed on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. The inorganic layer includes an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer includes an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0115] A first voltage may be applied to the first electrode AE, and a second voltage may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML recombine to form excitons, and the light emitting element OLED emits light as the excitons transition to a ground state. The light emitting element OLED may emit light to display an image.

[0116] Figure 6 is shown when viewed in plan view Figure 4 A view of an arrangement state of light emitting elements and first electrodes of pixels provided in a portion of a display area. Figure 7 The light emitting element is shown separately but not shown Figure 6 View of the first electrode.

[0117] refer to Figure 6 and Figure 7, the pixels PX of the display panel DP may include a plurality of first pixels PX1, a plurality of second pixels PX2, and a plurality of third pixels PX3. Hereinafter, in this specification, a "column" may correspond to a first direction DR1, and a "row" may correspond to a second direction DR2.

[0118] The first pixel PX1 and the second pixel PX2 may be arranged in the odd column C_O, and the third pixel PX3 may be arranged in the even column C_E. The first pixel PX1 and the second pixel PX2 may be alternately arranged in the first direction DR1 in each of the odd columns C_O.

[0119] Each of the first pixels PX1 may include a first light emitting element OLED1. Each of the second pixels PX2 may include a second light emitting element OLED2. Each of the third pixels PX3 may include a third light emitting element OLED3.

[0120] Each of the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 may correspond to Figure 5 Therefore, each of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may include a first electrode AE, a second electrode CE and a light emitting layer EML. The first light emitting element OLED1 may present red, the second light emitting element OLED2 may present green, and the third light emitting element OLED3 may present blue.

[0121] For example, Figure 6 As shown, the first electrodes AE of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 are shown with different reference numerals. Figure 6 The planar configuration of the first electrode AE1 in the first light emitting element OLED1, the first electrode AE2 in the second light emitting element OLED2, and the first electrode AE3 in the third light emitting element OLED3 is shown. Each of the first electrodes AE1, AE2, and AE3 can be connected to the second connection electrode CNE2 described above through a corresponding third contact hole CH3.

[0122] Each of the first electrodes AE1, AE2, and AE3 may be disposed in the light emitting area LEA and in a portion of the non-light emitting area NLEA adjacent to the light emitting area LEA. The first electrodes AE1, AE2, and AE3 may extend to protrude toward the third contact hole CH3 and overlap with the third contact hole CH3, respectively. For example, each of the first electrodes AE1, AE2, and AE3 may include an extension protruding toward its corresponding third contact hole CH3.

[0123] The first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 may be disposed in the light emitting area LEA, respectively. The pixel defining layer PDL may be disposed in the non-light emitting area NLEA around each of the light emitting areas LEA.

[0124] When viewed in a plan view, the first light emitting element OLED1 may have a triangular shape. When viewed in a plan view, the second light emitting element OLED2 may have an inverted triangular shape. The first light emitting element OLED1 and the second light emitting element OLED2 adjacent to each other may have shapes symmetrical to each other in the first direction DR1. When viewed in a plan view, the third light emitting element OLED3 may have a rhombus shape. However, the present disclosure is not limited thereto, and the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 may have various shapes.

[0125] When viewed in a plan view, an area of ​​each of the third light emitting elements OLED3 may be greater than an area of ​​each of the second light emitting elements OLED2. When viewed in a plan view, an area of ​​each of the second light emitting elements OLED2 may be greater than an area of ​​each of the first light emitting elements OLED1.

[0126] The first light emitting element OLED1 and the second light emitting element OLED2 may be disposed in an odd column C_O. The first light emitting element OLED1 and the second light emitting element OLED2 may be alternately arranged in the first direction DR1 in the odd column C_O. In the odd column C_O, the first light emitting element OLED1 may be arranged in the same row. In the odd column C_O, the second light emitting element OLED2 may be arranged in the same row. For example, the first light emitting element OLED1 may be arranged in the first row, and the second light emitting element OLED2 may be arranged in the second row.

[0127] The third light emitting element OLED3 may be disposed in the even column C_E. The third light emitting element OLED3 may be arranged in the first direction DR1 in the even column C_E. The odd column C_O and the even column C_E adjacent to each other may be referred to as the hth column and the h+1th column, respectively. In this case, "h" is a natural number greater than 0.

[0128] Hereinafter, the first diagonal direction DDR1 may be a direction crossing the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 may be a direction crossing the first diagonal direction DDR1 on a plane defined by the first direction DR1 and the second direction DR2. The first diagonal direction DDR1 and the second diagonal direction DDR2 may intersect each other while forming a perpendicular angle.

[0129] Hereinafter, the arrangement of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 in two adjacent odd columns C_O and even columns C_E will be described. In the adjacent odd columns C_O and even columns C_E, the even column C_E may be arranged on the right side of the odd column C_O in the second direction DR2.

[0130] In the odd column C_O, the kth first light emitting element OLED1_k and the kth second light emitting element OLED2_k may be disposed adjacent to each other in the first direction DR1. In the even column C_E adjacent to the odd column C_O, the kth third light emitting element OLED3_k may be disposed adjacent to the kth first light emitting element OLED1_k in the first diagonal direction DDR1, and adjacent to the kth second light emitting element OLED2_k in the second diagonal direction DDR2. In this case, "k" is a natural number greater than 0.

[0131] A distance between the kth first light emitting element OLED1_k and the kth third light emitting element OLED3_k in the first diagonal direction DDR1 and a distance between the kth second light emitting element OLED2_k and the kth third light emitting element OLED3_k in the second diagonal direction DDR2 may be a first distance GP1.

[0132] A distance between the kth first light emitting element OLED1_k and the kth second light emitting element OLED2_k in the first direction DR1 may have a second distance GP2 greater than the first distance GP1. A distance between the kth third light emitting element OLED3_k and the k+1th third light emitting element OLED3_k+1 in the first direction DR1 may have a third distance GP3 greater than the second distance GP2.

[0133] The kth first light emitting element OLED1_k, the kth second light emitting element OLED2_k, and the kth third light emitting element OLED3_k that are adjacent to each other may form a pixel group.

[0134] The arrangement direction of the first and second light emitting elements OLED1 and OLED2 relative to the third light emitting element OLED3 may vary according to the arrangement reference. For example, the odd column C_O may be disposed on the right side of the even column C_E in the second direction DR2.

[0135] According to this arrangement, the kth third light emitting element OLED3_k may be disposed adjacent to the kth second light emitting element OLED2_k in the first diagonal direction DDR1, and may be disposed adjacent to the kth first light emitting element OLED1_k in the second diagonal direction DDR2. In this case, the distance between the kth second light emitting element OLED2_k and the kth third light emitting element OLED3_k in the first diagonal direction DDR1 and the distance between the kth first light emitting element OLED1_k and the kth third light emitting element OLED3_k in the second diagonal direction DDR2 may be the first distance GP1.

[0136] Figure 8 yes Figure 2 A plan view of the input sensing portion is shown.

[0137] refer to Figure 8 The input sensing part ISP may include a plurality of sensing electrodes SE1 and SE2, a plurality of lines TX1 to TXi and RX1 to RXj, a plurality of second pads PD2, and a plurality of third pads PD3. The sensing electrodes SE1 and SE2, the lines TX1 to TXi and RX1 to RXj, and the second pads PD2 and the third pads PD3 may be disposed on the thin film encapsulation layer TFE of the display panel DP.

[0138] The plane area of ​​the input sensing portion ISP may include an active area AA and a non-active area NAA around the active area AA. The active area AA may overlap the display area DA, and the non-active area NAA may overlap the non-display area NDA.

[0139] The sensing electrodes SE1 and SE2 may be disposed in the active area AA, and the second pad PD2 and the third pad PD3 may be disposed in the non-active area NAA. When viewed in a plan view, the second pad PD2 and the third pad PD3 may be adjacent to the lower end of the input sensing portion ISP. When viewed in a plan view, the first pad PD1 may be interposed between the second pad PD2 and the third pad PD3.

[0140] Lines TX1 to TXi and RX1 to RXj may be connected to first ends of sensing electrodes SE1 and SE2 and extend to the non-active area NAA to be connected to second and third pads PD2 and PD3. A sensing controller controlling the input sensing part ISP may be connected to the second and third pads PD2 and PD3 through a printed circuit board.

[0141] The sensing electrodes SE1 and SE2 may include a plurality of first sensing electrodes SE1 extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of second sensing electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The second sensing electrodes SE2 may be insulated from the first sensing electrodes SE1 and extend to cross over the first sensing electrodes SE1. The first sensing electrodes SE1 may be transmission electrodes, and the second sensing electrodes SE2 may be reception electrodes.

[0142] The lines TX1 to TXi and RX1 to RXj may include a plurality of first lines TX1 to TXi connected to the first sensing electrode SE1 and a plurality of second lines RX1 to RXj connected to the second sensing electrode SE2. In this case, "i" and "j" are natural numbers greater than 0. The first lines TX1 to TXi may extend to the non-active area NAA and may be connected to the second pad PD2. The second lines RX1 to RXj may extend to the non-active area NAA and may be connected to the third pad PD3.

[0143] For example, when viewed in a plan view, the first lines TX1 to TXi may be disposed in the non-active area NAA to be adjacent to the lower side of the active area AA. When viewed in a plan view, the second lines RX1 to RXj may be disposed in the non-active area NAA to be adjacent to the right side of the active area AA. The first lines TX1 to TXi may be transmission wirings, and the second lines RX1 to RXj may be sensing lines (or receiving wirings).

[0144] Each of the first sensing electrodes SE1 may include a plurality of first sensing parts SP1 arranged in the first direction DR1 and a plurality of connection patterns CP connecting the first sensing parts SP1 to each other. Each of the connection patterns CP may be disposed between two first sensing parts SP1 adjacent to each other in the first direction DR1 to connect the two first sensing parts SP1 to each other.

[0145] The second sensing electrode SE2 may include a plurality of second sensing parts SP2 and a plurality of extension patterns EP extending from the second sensing parts SP2 arranged in the second direction DR2. Each of the extension patterns EP may be disposed between two second sensing parts SP2 adjacent to each other in the second direction DR2 to extend from the two second sensing parts SP2.

[0146] Each of the first sensing parts SP1 and each of the second sensing parts SP2 may be spaced apart from each other without overlapping each other and may be alternately arranged. Capacitance may be formed by the first sensing parts SP1 and the second sensing parts SP2. The extension pattern EP may be insulated from the connection pattern CP and extend to cross the connection pattern CP.

[0147] Fig. 9 yes Figure 8 FIG. 1 is an enlarged view of two first sensing portions adjacent to each other and two second sensing portions adjacent to each other. Fig.10 It is shown Fig. 9 A view of the connection pattern shown. Fig.11 It is shown Fig. 9 A view of the first and second sensing portions and the extended pattern is shown.

[0148] refer to Fig. 9 , each of the first sensing part SP1 and the second sensing part SP2 may include a plurality of mesh lines MSL and a plurality of conductive patterns CTP. In each of the first sensing part SP1 and the second sensing part SP2, the mesh lines MSL and the conductive patterns CTP may be integrally formed.

[0149] The mesh lines MSL may extend from the conductive pattern CTP in the first and second diagonal directions DDR1 and DDR2 and in the second direction DR2. A space surrounded by the mesh lines MSL and the conductive pattern CTP may be referred to as a touch opening TOP.

[0150] When viewed in a plan view, the light emitting area LEA may be disposed in the touch opening TOP. Each of the light emitting areas LEA may be Figure 5 , Figure 6 and Figure 7 For ease of explanation, the light emitting area LEA is shown. Fig. 9 Only three light emitting areas LEA adjacent to each other are shown by dotted lines in FIG. 4 ; however, each of the touch openings TOP includes a light emitting area LEA.

[0151] When viewed in a plan view, the mesh line MSL and the conductive pattern CTP may overlap the non-light emitting area NLEA without overlapping the light emitting area LEA. Therefore, when viewed in a plan view, the first sensing part SP1 and the second sensing part SP2 may overlap the non-light emitting area NLEA without overlapping the light emitting area LEA.

[0152] Since the first and second sensing parts SP1 and SP2 are disposed in the non-light emitting area NLEA, light may be normally emitted from the light emitting area LEA without being affected by the first and second sensing parts SP1 and SP2.

[0153] The extension pattern EP and the connection pattern CP may include a mesh line MSL and a conductive pattern CTP overlapping the non-light emitting area NLEA and not overlapping the light emitting area LEA like the first and second sensing parts SP1 and SP2 .

[0154] When viewed in a plan view, the mesh line MSL and the conductive pattern CTP may be disposed between the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3. Fig.13A Detailed arrangement structures of the mesh lines MSL and the conductive patterns CTP for the first, second, and third light emitting elements OLED1, OLED2, and OLED3 are described in FIG.

[0155] refer to Fig. 9 , Fig.10 and Fig.11 , the extension pattern EP and the first and second sensing parts SP1 and SP2 may be disposed in a different layer from the connection pattern CP. For example, the connection pattern CP may be disposed on the thin film encapsulation layer TFE described above, and the extension pattern EP and the first and second sensing parts SP1 and SP2 may be disposed on the connection pattern CP. The extension pattern EP, the first and second sensing parts SP1 and SP2 may be disposed in the same layer and may be formed by patterning the same material at the same time.

[0156] The connection pattern CP may include a first extension portion EX1 and a second extension portion EX2 extending in the first direction DR1 and spaced apart from each other in the second direction DR2. The first extension portion EX1 and the second extension portion EX2 may have substantially the same shape. Both sides of the first extension portion EX1 and the second extension portion EX2 opposite to each other in the first direction DR1 may overlap the first sensing portion SP1.

[0157] The first extension part EX1 and the second extension part EX2 may be connected to the first sensing part SP1 through a plurality of touch contact holes T-CH overlapping the first sensing part SP1. The touch contact holes T-CH may overlap some of the conductive patterns CTP of the first sensing part SP1. Fig.12 , a cross-sectional structure of the touch contact hole T-CH is shown in FIG.

[0158] The extension pattern EP may be disposed between the first sensing portions SP1 and may extend from the second sensing portion SP2 in the second direction DR2. The extension pattern EP may be formed integrally with the second sensing portion SP2. When viewed in a plan view, the extension pattern EP may extend to intersect the connection pattern CP. An insulating layer is interposed between the extension pattern EP and the connection pattern CP so that the extension pattern EP and the connection pattern CP may be insulated from each other.

[0159] The first sensing portion SP1 may be separated from the second sensing portion SP2 and the extension pattern EP. For example, a separation portion between the first sensing portion SP1 and the second sensing portion SP2 and a separation portion between the first sensing portion SP1 and the extension pattern EP are located at Fig.11 Indicated by dotted lines.

[0160] Fig.12 It is along Fig. 9 A cross-sectional view taken along line II' is shown.

[0161] refer to Fig.12 , the base layer BSL may be disposed on the thin film encapsulation layer TFE. The connection pattern CP may be disposed on the base layer BSL. The first touch insulating layer T-INS1 may be disposed on the connection pattern CP and the base layer BSL. The first touch insulating layer T-INS1 may be disposed on the base layer BSL to cover the connection pattern CP. The first touch insulating layer T-INS1 may include an inorganic insulating layer or an organic insulating layer.

[0162] The first sensing part SP1 and the extension pattern EP may be disposed on the first touch insulating layer T-INS1. The second sensing part SP2 integrally formed with the extension pattern EP may also be disposed on the first touch insulating layer T-INS1. The connection pattern CP may be connected to the first sensing part SP1 through a plurality of touch contact holes T-CH defined in the first touch insulating layer T-INS1.

[0163] The second touch insulation layer T-INS2 may be disposed on the first sensing part SP1, the extension pattern EP, and the first touch insulation layer T-INS1. The second touch insulation layer T-INS2 may include an organic insulation layer.

[0164] Fig.13A yes Fig. 9 An enlarged view of a local area of ​​any one of the first sensing portion and the second sensing portion is shown. Fig. 13B is with Fig.13A The corresponding enlarged view is a view showing another shape of the conductive pattern.

[0165] refer to Fig.13A , when viewed in a plan view, the mesh line MSL may be interposed between the first light emitting element OLED1 and the second light emitting element OLED2 , between the first light emitting element OLED1 and the third light emitting element OLED3 , and between the second light emitting element OLED2 and the third light emitting element OLED3 .

[0166] When viewed in a plan view, the conductive pattern CTP may be interposed between the third light emitting elements OLED3 disposed in at least one column. As described above, since the third light emitting elements OLED3 are disposed in the even columns C_E, the conductive pattern CTP may be interposed between the third light emitting elements OLED3 disposed in at least one even column C_E. The grid line MSL may extend from the conductive pattern CTP and may be formed integrally with the conductive pattern CTP.

[0167] The conductive pattern CTP may be arranged in the first direction DR1 and the second direction DR2. In other words, the conductive pattern CTP may be arranged in a plurality of rows corresponding to the second direction DR2 and in a plurality of columns corresponding to the first direction DR1. For example, each of the plurality of rows may extend in the second direction DR2, and each of the plurality of columns may extend in the first direction DR1. As for the third light emitting element OLED3, the third light emitting element OLED3 may also be arranged in a plurality of rows corresponding to the second direction DR2 and in a plurality of columns corresponding to the first direction DR1.

[0168] For example, the conductive pattern CTP is inserted between the third light emitting elements OLED3 disposed in all even columns C_E, but the embodiments of the present disclosure are not limited thereto. For example, the conductive pattern CTP may be inserted only between the third light emitting elements OLED3 disposed in some even columns C_E.

[0169] The width of each of the conductive patterns CTP may be greater than the width of each of the mesh lines MSL. The width of each of the mesh lines MSL may be a value measured in a direction perpendicular to an extending direction of each of the mesh lines MSL.

[0170] like Fig.13A As shown in FIG. 1 , the conductive pattern CTP may have a circular shape when viewed in a plan view, but the shape of the conductive pattern CTP is not limited thereto. Fig. 13B As shown, the conductive pattern CTP' may have a polygonal shape. Fig.13A As shown, when the conductive patterns CTP have a circular shape, the width of each of the conductive patterns CTP may be the diameter of each of the conductive patterns CTP.

[0171] like Fig. 13B As shown, when the conductive pattern CTP' has a polygonal shape, the width of each of the conductive patterns CTP' may be a value measured in a direction perpendicular to one side of the polygon. Fig. 13B The conductive pattern CTP' shown may have a hexagonal shape. In this case, the width of each of the conductive patterns CTP' may be a value measured in a first direction DR1 perpendicular to the sides of the conductive pattern CTP', a first diagonal direction DDR1, and a second diagonal direction DDR2.

[0172] As described above, the distance between adjacent third light emitting elements OLED3 may be the third distance GP3 and may be greater than the first distance GP1 and the second distance GP2. Therefore, the conductive pattern CTP may be provided as a conductor having a larger width between the third light emitting elements OLED3. In other words, according to an embodiment of the present disclosure, the grid line MSL may not be provided between the third light emitting elements OLED3, and the conductive pattern CTP having a larger width may be provided between the third light emitting elements OLED3.

[0173] Since the mesh line MSL is not provided between the third light emitting element OLED3 and a conductive pattern CTP having a larger width is used instead, the area of ​​the conductor of each of the first sensing part SP1 and the second sensing part SP2 can be increased. The capacitance is proportional to the area of ​​the conductor, so increasing the capacitance can improve the touch sensitivity.

[0174] According to an embodiment of the present disclosure, since each of the first sensing part SP1 and the second sensing part SP2 includes the conductive pattern CTP, capacitance formed by the first sensing part SP1 and the second sensing part SP2 may be increased. Therefore, the touch sensitivity of the input sensing part ISP may be improved.

[0175] Figures 14 to 19 2 is a view illustrating cut-off patterns of first and second sensing parts according to various embodiments of the present disclosure.

[0176] Figures 14 to 19 is with Fig.13A For ease of explanation, Fig.13A Different, in Fig.14 and Fig.15 Some of the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 are shown in FIG, and the rest of the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 are omitted. Fig.16 In FIG. 1 , the third light emitting element OLED3 is shown, and the first light emitting element OLED1 and the second light emitting element OLED2 are omitted. Figures 17 to 19 In the figure, the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 are omitted.

[0177] refer to Figures 14 to 19, some of the grid lines MSL may be cut from each of the first sensing portion SP1 and the second sensing portion SP2. Portions of some of the grid lines MSL may be cut off to form cut-off areas CA, CA1, and CA2 in each of the first sensing portion SP1 and the second sensing portion SP2. The "cut" state may be a state in which a specific portion of each of some of the grid lines MSL is removed.

[0178] Hereinafter, a detailed structure of the mesh lines MSL and various cutting patterns will be described.

[0179] refer to Fig.14 and Fig.15 The grid lines MSL may include a plurality of first grid lines MSL1, a plurality of second grid lines MSL2, and a plurality of third grid lines MSL3. The first grid lines MSL1 and the third grid lines MSL3 may extend in the second direction DR2. The second grid lines MSL2 may extend in the first diagonal direction DDR1 and the second diagonal direction DDR2.

[0180] The first mesh line MSL1 may extend from the corresponding conductive pattern CTP in the second direction DR2. The second mesh line MSL2 may extend from the corresponding conductive pattern CTP in the first diagonal direction DDR1 and the second diagonal direction DDR2. The third mesh line MSL3 may extend in the second direction DR2 from a contact point between the second mesh line MSL2 extending in the first diagonal direction DDR1 and the second mesh line MSL2 extending in the second diagonal direction DDR2.

[0181] When viewed in a plan view, in each of the odd-numbered columns C_O, each of the first mesh lines MSL1 may be interposed between the kth first light emitting element OLED1_k and the k+1th second light emitting element OLED2_k+1.

[0182] When viewed in a plan view, the second mesh line MSL2 may be disposed between the first light emitting element OLED1 and the third light emitting element OLED3 and between the second light emitting element OLED2 and the third light emitting element OLED3 .

[0183] When viewed in a plan view, in each of the odd-numbered columns C_O, each of the third mesh lines MSL3 may be interposed between the kth first light emitting element OLED1_k and the kth second light emitting element OLED2_k.

[0184] Grid lines MSL Figures 16 to 19 are identically defined in and for ease of explanation, in Figures 16 to 19The kth first light emitting element OLED1_k, the kth second light emitting element OLED2_k, the kth third light emitting element OLED3_k, and the kth second light emitting element OLED2_k and the k+1th third light emitting element OLED3_k+1 are omitted.

[0185] In the following, we will focus on Figures 14 to 19 Each of the descriptions details the cutting pattern.

[0186] refer to Fig.14 , the first grid line MSL1 may be cut. For example, the first grid line MSL1 may be cut to form an open space overlapping the k-th second light emitting element OLED2_k in the first direction DR1. The number of the cut first grid lines MSL1 may be set differently. For example, at least one of the first grid lines MSL1 may be cut. A portion of the first grid line MSL1 may be cut to form a cutoff area CA. For example, the cutoff area CA may overlap the second light emitting element OLED2 in the first direction DR1.

[0187] refer to Fig.15 , the first mesh line MSL1 may be cut off to form a cut-off area CA. Also, one of the second mesh lines MSL2 extending from each of the conductive patterns CTP may be cut off to form a cut-off area CA.

[0188] refer to Fig.16 , the first mesh line MSL1 may be cut off to form a cut-off area CA.

[0189] As described above, the third light emitting elements OLED3 may be arranged in a plurality of rows and a plurality of columns. The second grid line MSL2 adjacent to each of the even-numbered third light emitting elements OLED3_E among the third light emitting elements OLED3 arranged in the even-numbered rows R_E may be cut off to form a cut-off area CA. The even-numbered third light emitting elements OLED3_E may be sequentially arranged in the second direction DR2 in each of the even-numbered rows R_E.

[0190] refer to Fig.17 , the cut area CA may be formed by cutting the first mesh line MSL1.

[0191] As described above, the conductive patterns CTP may be arranged in a plurality of rows and a plurality of columns. The second grid line MSL2 extending from each of the even-numbered conductive patterns CTP_E among the conductive patterns CTP arranged in the even-numbered rows R_E' may be cut off to form a cut-off area CA. The even-numbered conductive patterns CTP_E may be sequentially arranged in the second direction DR2 in each of the even-numbered rows R_E'. Fig.17The cut-off area CA may be disposed between adjacent even-numbered conductive patterns CTP_E in the even-numbered row R_E′.

[0192] refer to Fig.18 , the conductive pattern CTP may include a plurality of first conductive patterns CTP1 and a plurality of second conductive patterns CTP2. The first conductive patterns CTP1 may be arranged in the first direction DR1 and the second direction DR2.

[0193] At least two second conductive patterns CTP2 may be interposed between two first conductive patterns CTP1 adjacent to each other in the first direction DR1. At least two second conductive patterns CTP2 may be interposed between two first conductive patterns CTP1 adjacent to each other in the second direction DR2. The first mesh line MSL1 and the second mesh line MSL2 extending from each of the first conductive patterns CTP1 may be cut off to form a cutoff area CA.

[0194] Two adjacent third mesh lines MSL3 between the second conductive patterns CTP2 interposed between the first conductive patterns CTP1 and adjacent to each other in the first direction DR1 may be removed. For example, entire portions of the two adjacent third mesh lines MSL3 may be cut off, thereby forming a cutoff area CA1.

[0195] The first mesh line MSL1 between the second conductive patterns CTP2 interposed between the first conductive patterns CTP1 adjacent to each other in the second direction DR2 may be referred to as a 1-1th mesh line MSL1-1. The 1-1th mesh line MSL1-1 and two third mesh lines MSL3 adjacent to the 1-1th mesh line MSL1-1 in the first direction DR1 may be cut off. The 1-1th mesh line MSL1-1 and the two third mesh lines MSL3 may be cut off to form a cutoff area CA2.

[0196] refer to Fig.19 Among the conductive patterns CTP arranged in the even row R_E', portions of the first grid line MSL1 and the second grid line MSL2 adjacent to the first side of the odd-numbered conductive pattern CTP_O, or portions of the first grid line MSL1 and the second grid line MSL2 adjacent to the second side of the odd-numbered conductive pattern CTP_O may be removed.

[0197] The first side of the conductive pattern CTP and the second side of the conductive pattern CTP may be referred to as sides opposite to each other in the second direction DR2. The odd-numbered conductive patterns CTP_O may be sequentially arranged in the second direction DR2 in each of the even rows R_E'. Portions of the first and second grid lines MSL1 and MSL2 may be removed to form a cut-off area CA.

[0198] Portions of the first and second mesh lines MSL1 and MSL2 adjacent to first sides of the odd-numbered conductive patterns CTP_O and portions of the first and second mesh lines MSL1 and MSL2 adjacent to second sides of the odd-numbered conductive patterns CTP_O may be removed alternately according to the order of the even rows R_E′.

[0199] For example, in the p-th row of the even row R_E', portions of the first and second grid lines MSL1 and MSL2 adjacent to the first side of the odd-numbered conductive pattern CTP_O may be removed. In the p+1-th row of the even row R_E', portions of the first and second grid lines MSL1 and MSL2 adjacent to the second side of the odd-numbered conductive pattern CTP_O may be removed.

[0200] refer to Figures 14 to 19 , the mesh shape of the first sensing part SP1 and the second sensing part SP2 may be visually recognized by the user according to the reflection of external light. When portions of the grid lines MSL are removed to form the cut-off areas CA, CA1, and CA2, external light may not be reflected from the cut-off areas CA, CA1, and CA2. Therefore, the mesh shape of the first sensing part SP1 and the second sensing part SP2 may be less visually recognizable.

[0201] Fig. 20 is a view illustrating a plan configuration of an auxiliary line connected to a second electrode according to another embodiment of the present disclosure. Fig.21 It is schematically shown Fig. 20 A cross-sectional view of any one of the contact holes and two third light-emitting elements adjacent to the any one of the contact holes is shown.

[0202] For example, Fig. 20 is with Figure 6 The corresponding floor plan.

[0203] refer to Fig. 20 , the display panel DP may include a plurality of auxiliary lines PL2'. The auxiliary lines PL2' may extend in the first direction DR1 and may be arranged in the second direction DR2. The auxiliary lines PL2' may extend to overlap the third light emitting element OLED3. The auxiliary lines PL2' may extend from the second power lines PL2 disposed in the non-display area NDA described above. Therefore, the auxiliary lines PL2' may receive the second voltage.

[0204] The contact hole CH may be formed between the third light emitting elements OLED3 in the first direction DR1. Fig.21 The configuration of the contact hole CH is described in detail. The auxiliary line PL2' may extend to overlap with the contact hole CH.

[0205] refer to Fig.21The cross-sectional configuration of the third light emitting element OLED3 and the transistors TR and TR' is similar to Figure 5 The configuration described in OLED3 is basically the same. Therefore, the details thereof will be omitted. In addition, the first electrode AE, the second electrode CE, the light-emitting layer EML, the electron control layer ECL and the hole control layer HCL of the third light-emitting element OLED3 are used. Figure 5 Hereinafter, the second electrode CE is referred to as a common electrode CE.

[0206] The conductive pattern CTP between the third light emitting elements OLED3 in a plan view may be disposed on the first touch insulating layer T-INS1. Therefore, when viewed in a plan view, the conductive pattern CTP may overlap the pixel defining layer PDL interposed between the third light emitting elements OLED3.

[0207] The auxiliary line PL2' may be disposed on the fifth insulating layer INS5. The auxiliary line PL2' may be disposed in the same layer as the first connection electrode CNE1. The auxiliary line PL2' may be formed by simultaneously patterning the same material as the first connection electrode CNE1. When viewed in a plan view, the auxiliary line PL2' may overlap the conductive pattern CTP. The auxiliary line PL2' may be disposed under the common electrode CE. The common electrode CE may be connected to the auxiliary line PL2' under the conductive pattern CTP.

[0208] A sixth insulating layer INS6 (or a first via insulating layer) may be disposed on the auxiliary line PL2 ′ and the fifth insulating layer INS5 , a seventh insulating layer INS7 (or a second via insulating layer) may be disposed on the sixth insulating layer INS6 , and a pixel defining layer PDL may be disposed on the seventh insulating layer INS7 .

[0209] The contact hole CH may be formed in the pixel defining layer PDL, the seventh insulating layer INS7, and the sixth insulating layer INS6. For example, portions of the pixel defining layer PDL, the seventh insulating layer INS7, and the sixth insulating layer INS6 may be removed to form the contact hole CH. When viewed in a plan view, the contact hole CH may overlap the common electrode CE and the conductive pattern CTP. The common electrode CE may be connected to the auxiliary line PL2' through the contact hole CH.

[0210] The common electrode CE may be disposed in the entire portion of the display area DA and may extend to the non-display area NDA to be connected to the second power line PL2. According to an embodiment of the present disclosure, the common electrode CE may be additionally connected to the auxiliary line PL2' in the display area DA. Since the resistance is inversely proportional to the area of ​​the conductor, when the common electrode CE is connected to the auxiliary line PL2', the resistance of the common electrode CE may be reduced.

[0211] The display panel DP may include a dummy electrode DE interposed between the sixth insulating layer INS6 and the seventh insulating layer INS7. When viewed in a plan view, the dummy electrode DE may overlap the conductive pattern CTP. The dummy electrode DE may also overlap the auxiliary line PL2'. A portion of the dummy electrode DE may protrude toward the contact hole CH and may be disposed in the contact hole CH. The dummy electrode DE may be disposed on the same layer as the second connection electrode CNE2. The dummy electrode DE and the second connection electrode CNE2 may be simultaneously formed by simultaneously patterning the same material.

[0212] In order to form the contact hole CH, portions of the pixel defining layer PDL, the seventh insulating layer INS7, and the sixth insulating layer INS6 may be removed by an etching process (eg, dry etching). During the etching process, a portion of the sixth insulating layer INS6 below the dummy electrode DE may be removed. This process may be referred to as an undercut process. Fig.21 As shown, a structure in which a portion of the dummy electrode DE protrudes toward the contact hole CH may be formed by an undercut process.

[0213] The hole control layer HCL and the electron control layer ECL may be disposed on a portion of the dummy electrode DE protruding toward the contact hole CH. In addition, the hole control layer HCL and the electron control layer ECL may be disposed on the auxiliary line PL2' exposed by the contact hole CH under the dummy electrode DE. Common layers such as the hole control layer HCL and the electron control layer ECL may be separated from each other above and below the portion of the dummy electrode DE protruding toward the contact hole CH.

[0214] The common electrode CE may be disposed on a portion of the dummy electrode DE protruding toward the contact hole CH. The common electrode CE may be disposed on the auxiliary line PL2' exposed by the contact hole CH under the dummy electrode DE. According to this configuration, a portion of the common electrode CE may be separated from the contact hole CH in the display area DA.

[0215] The common electrode CE may be disposed on a portion of the dummy electrode DE protruding toward the contact hole CH to cover the hole control layer HCL and the electron control layer ECL. The common electrode CE may be disposed on the auxiliary line PL2' to cover the hole control layer HCL and the electron control layer ECL, thereby contacting the auxiliary line PL2'. Therefore, the common electrode CE may be electrically connected to the auxiliary line PL2'.

[0216] The connection portion between the common electrode CE and the auxiliary line PL2' interposed between the third light emitting elements OLED3 (hereinafter referred to as a visibility portion corresponding to the contact hole CH) may be visible from the outside of the display device DD. In other words, visibility may be deteriorated. The conductive pattern CTP is extended to have a large width and is disposed on the visibility portion to cover the visibility portion. By blocking the visibility portion from being seen from the outside with the conductive pattern CTP, visibility is improved.

[0217] However, the embodiments of the present disclosure are not limited thereto. For example, the thickness of the conductive pattern CTP may increase in a vertical direction to better block the visibility portion from being seen from the outside.

[0218] Fig. 22 is a view illustrating a connection configuration between an auxiliary line and a common electrode according to another embodiment of the present disclosure.

[0219] For example, Fig. 22 With Fig.21 The corresponding cross-section is shown.

[0220] refer to Fig. 22 , the auxiliary line PL2' may be disposed on the fifth insulating layer INS5, and the sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the auxiliary line PL2'. The connection electrode CT1 may be disposed on the sixth insulating layer INS6. When viewed in a plan view, the connection electrode CT1 may overlap the conductive pattern CTP. The connection electrode CT1 may be disposed on the same layer as the second connection electrode CNE2. The connection electrode CT1 and the second connection electrode CNE2 may be formed by simultaneously patterning the same material.

[0221] The connection electrode CT1 may be electrically connected to the auxiliary line PL2' through the first touch contact hole CTH1 in the sixth insulating layer INS6. Therefore, the connection electrode CT1 may be disposed on the auxiliary line PL2' and may be connected to the auxiliary line PL2'.

[0222] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the connection electrode CT1. Another connection electrode CT2 may be disposed on the seventh insulating layer INS7. When viewed in a plan view, the other connection electrode CT2 may overlap the conductive pattern CTP. The other connection electrode CT2 may be disposed in the same layer as the first electrode AE. The other connection electrode CT2 and the first electrode AE ​​may be formed by simultaneously patterning the same material.

[0223] The other connection electrode CT2 may be electrically connected to the connection electrode CT1 through the second touch contact hole CTH2 defined in the seventh insulating layer INS7. Therefore, the other connection electrode CT2 may be disposed over and connected to the connection electrode CT1.

[0224] The pixel defining layer PDL may be disposed on the seventh insulating layer INS7 and the other connection electrode CT2. The electron control layer ECL, the hole control layer HCL, and the common electrode CE may be disposed on the pixel defining layer PDL.

[0225] Portions of the pixel defining layer PDL, the electron control layer ECL, and the hole control layer HCL that overlap with a portion of the other connection electrode CT2 may be removed to form a contact hole CH'. The common electrode CE may be electrically connected to the other connection electrode CT2 through the contact hole CH'. Therefore, the common electrode CE may be disposed on and connected to the other connection electrode CT2.

[0226] The common electrode CE may be connected to the auxiliary line PL2 ′ through another connection electrode CT2 and the connection electrode CT1 . Therefore, the resistance of the common electrode CE may be reduced.

[0227] The connection electrodes CT1 and CT2 connecting the common electrode CE to the auxiliary line PL2' between the third light emitting elements OLED3 in a plan view may be seen from the outside of the display device DD. In other words, visibility may be deteriorated. The conductive pattern CTP is extended to have a large width and is disposed on the connection electrodes CT1 and CT2 to cover the connection electrodes CT1 and CT2. By preventing the connection electrodes CT1 and CT2 from being seen from the outside with the conductive pattern CTP, visibility is improved.

[0228] However, the embodiments of the present disclosure are not limited thereto. For example, the thickness of the connection electrodes CT1 and CT2 may be increased in a vertical direction to better prevent the connection electrodes CT1 and CT2 from being seen from the outside.

[0229] Fig.23 is a view showing a structure of a display panel including a spacer according to another embodiment of the present disclosure. Fig.24 It is schematically shown Fig.23 A cross-sectional view of any one of the spacers and a third light emitting element disposed with the spacer interposed therebetween.

[0230] Fig.23 is with Fig.13A The corresponding floor plan, and Fig.24 is with Fig.21 The corresponding cross-sectional view.

[0231] refer to Fig.23, the conductive pattern CTP may be arranged between the third light emitting elements OLED3 arranged in some even-numbered columns C_E. At least one spacer SPC may be arranged between the third light emitting elements OLED3 arranged in other even-numbered columns C_E, instead of the conductive pattern CTP. In other words, in one row, the spacer SPC may be arranged between adjacent conductive patterns CTP.

[0232] refer to Fig.23 and Fig.24 , the spacer SPC may be disposed on the pixel defining layer PDL, and the electron control layer ECL, the hole control layer HCL and the common electrode CE may be disposed on the spacer SPC. The spacer SPC may be disposed on a portion of the pixel defining layer PDL, in which case there is no Fig.21 The conductive pattern CTP or the contact hole CH is shown. The spacer SPC may be used to maintain a gap of the display panel DP by increasing resistance to external pressure applied to the display panel DP.

[0233] Fig.25 and Fig.26 is a view showing a planar configuration of first and second sensing electrodes according to another embodiment of the present disclosure.

[0234] Fig.25 and Fig.26 Can be shown separately with Fig.10 and Fig.11 The corresponding layer.

[0235] refer to Fig.25 , the first sensing electrode SE1 and the second sensing electrode SE2 may further include a plurality of dummy patterns DMP disposed in the same layer as the connection pattern CP. The dummy pattern DMP may be spaced apart from the connection pattern CP. The dummy pattern DMP may have substantially the same shape as the first sensing part SP1 and the second sensing part SP2. For example, the dummy pattern DMP may include a dummy grid line DMSL and a dummy conductive pattern DCTP to have a grid shape.

[0236] Therefore, as referenced Fig.13A As described, the dummy grid line DMSL may be disposed between the first light emitting element OLED1 and the second light emitting element OLED2, between the first light emitting element OLED1 and the third light emitting element OLED3, and between the second light emitting element OLED2 and the third light emitting element OLED3. In addition, the dummy conductive pattern DCTP may be disposed between the third light emitting elements OLED3 arranged in even columns.

[0237] refer to Fig.25 and Fig.26The first and second sensing parts SP1 and SP2 and the extension pattern EP may be disposed on the connection pattern CP and the dummy pattern DMP. When viewed in a plan view, the dummy pattern DMP may be disposed below the first and second sensing parts SP1 and SP2 and overlap the first and second sensing parts SP1 and SP2, respectively.

[0238] A ground voltage may be applied to the dummy pattern DMP. However, the present disclosure is not limited thereto, and the dummy pattern DMP may be connected to the first sensing part SP1 and the second sensing part SP2 through a contact hole. In addition, the present disclosure is not limited thereto, and the dummy pattern DMP may be in a floating state while being separated from the peripheral conductive pattern.

[0239] According to another embodiment of the present disclosure, the input sensing part ISP may be formed of a dummy pattern DMP and a first sensing part SP1 arranged in the first direction DR1. For example, the dummy pattern DMP disposed on the lower layer may be connected in the first direction DR1 to serve as a transmission electrode, and the first sensing part SP1 disposed on the upper layer may be connected in the first direction DR1 to serve as a receiving electrode.

[0240] Fig. 27 It is along Fig.26 A cross-sectional view taken along line II-II' is shown.

[0241] For example, Fig. 27 is a cross-sectional view simultaneously showing the dummy pattern DMP and the first sensing part SP1.

[0242] refer to Fig. 27 , the dummy grid lines DMSL of the dummy pattern DMP and the dummy conductive patterns DCTP of the dummy pattern DMP may be disposed on the base layer BSL. The first touch insulating layer T-INS1 may be disposed on the base layer BSL, the dummy grid lines DMSL, and the dummy conductive patterns DCTP.

[0243] The grid line MSL and the conductive pattern CTP of the first sensing part SP1 may be disposed on the first touch insulating layer T-INS1. The grid line MSL of the first sensing part SP1 may overlap with the dummy grid line DMSL, and the conductive pattern CTP of the first sensing part SP1 may overlap with the dummy conductive pattern DCTP. The width of the dummy grid line DMSL may be smaller than the width of the grid line MSL. The width of the dummy conductive pattern DCTP may be smaller than the width of the conductive pattern CTP. Fig. 27 In the figure, the “width” may be a value measured in a horizontal direction. The second touch insulation layer T-INS2 may be disposed on the first touch insulation layer T-INS1, the mesh lines MSL, and the conductive patterns CTP.

[0244] Fig.28A is shown in more detail Fig. 27 A cross-sectional view of a conductive pattern and a dummy conductive pattern in FIG. Fig.28B It is shown Fig. 27 A view of a configuration in which the conductive pattern and the dummy conductive pattern have the same width.

[0245] refer to Fig.28A Each of the conductive patterns CTP and the dummy conductive patterns DCTP may include a first metal layer M1 and a second metal layer M2 disposed between the first metal layers M1. For example, the first metal layer M1 may include titanium (Ti), and the second metal layer M2 may include aluminum (Al).

[0246] When the user USR views the conductive pattern CTP and the dummy conductive pattern DCTP from a side, the dummy conductive pattern DCTP may not be seen by the user USR because the width of the dummy conductive pattern DCTP is smaller than the width of the conductive pattern CTP.

[0247] refer to Fig.28B , the conductive pattern CTP and the dummy conductive pattern DCTP may have the same width. In this case, when the user USR views the conductive pattern CTP and the dummy conductive pattern DCTP from the side, the dummy conductive pattern DCTP disposed under the conductive pattern CTP may be seen by the user USR.

[0248] According to an embodiment of the present disclosure, since the width of the dummy conductive pattern DCTP is smaller than the width of the conductive pattern CTP, the dummy conductive pattern DCTP may not be seen by the user USR. For example, although the dummy conductive pattern DCTP and the conductive pattern CTP have been described, the width of the dummy grid line DMSL may also be smaller than the width of the grid line MSL, and therefore, the dummy grid line DMSL may not be seen by the user USR.

[0249] In addition, the mesh line MSL and the conductive pattern CTP of the connection pattern CP disposed in the same layer as the dummy conductive pattern DCTP and the dummy mesh line DMSL may have a smaller width than those of each of the first and second sensing parts SP1 and SP2 .

[0250] According to an embodiment of the present disclosure, the sensing portion includes a grid line and a conductive pattern, and the conductive pattern can be inserted between the third light-emitting elements in a plan view. The area of ​​the conductive pattern can be enlarged between the third light-emitting elements that are spaced farther apart from each other. Therefore, the capacitance formed between the sensing portions can be increased, thereby enhancing the touch sensitivity of the input sensing portion.

[0251] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A display panel comprising a plurality of first light emitting elements and a plurality of second light emitting elements alternately arranged in a first direction in odd-numbered columns, and a plurality of third light emitting elements arranged in the first direction in even-numbered columns; as well as A plurality of sensing parts are arranged on the display panel, Wherein, each of the plurality of sensing parts comprises: a plurality of grid lines interposed between an nth first light emitting element and an nth second light emitting element, between the nth first light emitting element and an nth third light emitting element, and between the nth second light emitting element and the nth third light emitting element when viewed in a plan view, wherein "n" is a natural number greater than 0; and a plurality of conductive patterns interposed between the third light emitting elements arranged in an even-numbered column when viewed in the plan view, and Wherein, the width of each of the conductive patterns is greater than the width of each of the grid lines.

2. The display device according to claim 1, wherein: Each of the conductive patterns has a circular shape.

3. The display device according to claim 1, wherein: Each of the conductive patterns has a polygonal shape.

4. The display device according to claim 1, wherein: The grid lines and the conductive pattern are integrally formed.

5. The display device according to claim 1, wherein: Some of the grid lines are cut off.

6. The display device according to claim 1, wherein: In the odd-numbered columns and the even-numbered columns adjacent to each other, the k-th first light emitting element and the k-th second light emitting element are adjacent to each other in the first direction, The direction intersecting the first direction is the second direction. wherein, in the odd-numbered columns and the even-numbered columns adjacent to each other, the kth third light emitting element is adjacent to the kth first light emitting element in a first diagonal direction, and is adjacent to the kth second light emitting element in a second diagonal direction, Where "k" is a natural number greater than 0, wherein the first diagonal direction intersects the first direction and the second direction on a plane defined by the first direction and the second direction, and Wherein, when viewed on the plane, the second diagonal direction intersects with the first diagonal direction.

7. The display device according to claim 6, wherein: A distance between the kth first light emitting element and the kth third light emitting element in the first diagonal direction and a distance between the kth second light emitting element and the kth third light emitting element in the second diagonal direction are a first distance, and wherein a distance between the kth first light emitting element and the kth second light emitting element in the first direction is a second distance greater than the first distance, and The distance between the kth third light emitting element and the k+1th third light emitting element in the first direction is a third distance greater than the second distance.

8. The display device according to claim 6, wherein: The grid lines include: a plurality of first grid lines extending from each of the conductive patterns in the second direction; a plurality of second grid lines extending from each of the conductive patterns in the first diagonal direction and the second diagonal direction; and a plurality of third grid lines extending in the second direction from contact points between the second grid lines extending in the first diagonal direction and the second grid lines extending in the second diagonal direction, wherein, when viewed on the plane, each of the first grid lines is interposed between the kth first light emitting element and the k+1th second light emitting element in each of the odd-numbered columns, wherein, when viewed on the plane, the second grid lines are interposed between the first light emitting element and the third light emitting element, and between the second light emitting element and the third light emitting element, and Wherein, when viewed on the plane, each of the third grid lines is interposed between the kth first light emitting element and the kth second light emitting element in each of the odd-numbered columns.

9. The display device according to claim 8, wherein: At least one of the first grid lines is cut off.

10. The display device according to claim 8, wherein: One of the second mesh lines extending from each of the conductive patterns is cut off.

11. The display device according to claim 8, wherein: A second grid line adjacent to each of the even-numbered third light emitting elements among the third light emitting elements arranged in the even-numbered rows is cut off, and The even-numbered third light-emitting elements are arranged sequentially in the second direction in each of the even-numbered rows.

12. The display device according to claim 8, wherein: A second mesh line extending from each of the even-numbered conductive patterns among the conductive patterns arranged in the even-numbered rows is cut off, and The even-numbered conductive patterns are sequentially arranged in the second direction in each of the even-numbered rows.

13. The display device according to claim 8, wherein: The conductive pattern comprises: a plurality of first conductive patterns arranged in the first direction and the second direction; and at least two second conductive patterns are interposed between two first conductive patterns adjacent to each other in the first direction and between two first conductive patterns adjacent to each other in the second direction, wherein the first mesh lines and the second mesh lines extending from each of the first conductive patterns are cut off, wherein two third grid lines adjacent to each other are not arranged between the second conductive patterns interposed between the first conductive patterns adjacent to each other in the first direction, and The 1-1 grid line between the second conductive patterns interposed between the first conductive patterns adjacent to each other in the second direction and two third grid lines adjacent to the 1-1 grid line in the first direction are cut off.

14. The display device according to claim 8, wherein: A portion of the first and second grid lines adjacent to a first side of each of the odd-numbered conductive patterns among the conductive patterns arranged in the even-numbered rows or a portion of the first and second grid lines adjacent to a second side of each of the odd-numbered conductive patterns is removed, and The odd-numbered conductive patterns are sequentially arranged in each of the even-numbered rows in the second direction.

15. The display device according to claim 1, wherein: Each of the first light emitting element, the second light emitting element, and the third light emitting element comprises: a first electrode; a second electrode on the first electrode; and a light-emitting layer interposed between the first electrode and the second electrode, Wherein, the second electrode of the third light emitting element is an integrated common electrode, Wherein, the display panel further includes: an auxiliary line inserted under the common electrode and connected to the common electrode, and Wherein, when viewed on a plane, the auxiliary line overlaps with the conductive pattern.

16. The display device according to claim 15, wherein: The display panel further includes: A first via insulating layer, disposed on the auxiliary line; A second via insulating layer, disposed on the first via insulating layer; and a pixel defining layer, which is disposed on the second via insulating layer and has a pixel opening for arranging the light emitting layer, wherein the first electrode is disposed on the second via insulating layer, the pixel defining layer is disposed on the first electrode, a portion of the first electrode is exposed by the pixel opening, and the common electrode is disposed on the pixel defining layer, and Wherein, the common electrode is connected to the auxiliary line through the contact holes in the pixel defining layer, the second via insulating layer, and the first via insulating layer to overlap with each of the conductive patterns when viewed on the plane.

17. The display device according to claim 16, further comprising: a dummy electrode interposed between the first via insulating layer and the second via insulating layer and overlapping each of the conductive patterns when viewed on the plane, wherein a portion of the dummy electrode protrudes toward the contact hole, and The common electrode is disposed on the portion of the dummy electrode protruding toward the contact hole, and is disposed on the auxiliary line below the dummy electrode.

18. The display device according to claim 16, further comprising: At least one spacer is disposed on the pixel defining layer, and when viewed in the plan view, the at least one spacer is disposed between the third light emitting elements arranged in another even-numbered column other than the one even-numbered column.

19. The display device according to claim 15, wherein: The display panel further includes: A first connection electrode is disposed on and connected to the auxiliary line, and a second connection electrode, disposed on the first connection electrode, disposed in the same layer as the first electrode, and connected to the first connection electrode, wherein, when viewed on the plane, the first connection electrode and the second connection electrode overlap with each of the conductive patterns, and Wherein, the common electrode is arranged on the second connecting electrode and connected to the second connecting electrode.

20. The display device according to claim 1, further comprising: A plurality of dummy patterns are respectively arranged below the sensing part, Wherein, each of the dummy patterns comprises: a plurality of dummy grid lines, when viewed on a plane, the plurality of dummy grid lines being interposed between the nth first light emitting element and the nth second light emitting element, between the nth first light emitting element and the nth third light emitting element, and between the nth second light emitting element and the nth third light emitting element; and a plurality of dummy conductive patterns, when viewed on the plane, the plurality of dummy conductive patterns are between the third light emitting elements arranged in the one even-numbered column, and Wherein, the width of each of the dummy grid lines in the horizontal direction is smaller than the width of each of the grid lines in the horizontal direction, and the width of each of the dummy conductive patterns in the horizontal direction is smaller than the width of each of the conductive patterns in the horizontal direction.

21. A display device comprising: a display panel comprising a plurality of first light emitting elements and a plurality of second light emitting elements alternately arranged in an h-th column, and a plurality of third light emitting elements arranged in an h+1-th column; as well as A plurality of sensing parts are arranged on the display panel, Wherein, each of the plurality of sensing parts comprises: a plurality of grid lines, when viewed on a plane, the plurality of grid lines being interposed between the nth first light-emitting element and the nth second light-emitting element, between the nth first light-emitting element and the nth third light-emitting element, and between the nth second light-emitting element and the nth third light-emitting element; and a plurality of conductive patterns, the plurality of conductive patterns being interposed between the third light emitting elements when viewed on the plane, and wherein the width of each of the conductive patterns is greater than the width of each of the grid lines, wherein some of the grid lines are cut off, and Here, each of "h" and "n" is a natural number greater than 0.

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