Time delay reporting method and device

Abstract

The embodiment of the invention provides a time delay reporting method. The method can be applied to a first module. A first module may report target delays corresponding to data at a plurality of specific locations in a data stream, the plurality of specific locations being spaced by a fixed length, the cycles of the plurality of specific locations corresponding to the cycles of inserting a filling sequence in the data stream. In the embodiment of the invention, if the first module corresponds to the sending end, the target time delay corresponding to the data at the specific position is equal to the maximum time delay, and if the first module corresponds to the receiving end, the target time delay corresponding to the data at the specific position is equal to the minimum time delay. Therefore, by using the scheme, the time delay information can be accurately reported.

Description

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 1, 2024, with application number 202410243239.5 and invention name “A method and device for delay reporting”, and the Chinese patent application filed with the State Intellectual Property Office on May 8, 2024, with application number 202410565627.5 and invention name “A method and device for delay reporting”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of communications, and in particular to a delay reporting method and device. Background Art

[0003] Communication devices can exchange data with each other. A sender can send a message to a receiver, and the sender can add a message sending timestamp to the message sent to the receiver. Correspondingly, after receiving the message sent by the sender, the receiver can record the message receiving timestamp to facilitate subsequent processing measures based on the sending timestamp and the receiving timestamp. For example, in a time synchronization scenario, the receiver can perform time synchronization based on the sending timestamp and the receiving timestamp. Among them, the sender can be understood as a communication device as a sender, and the receiver can be understood as a communication device as a receiver.

[0004] The accuracy of the aforementioned sending timestamp and receiving timestamp directly affects the accuracy of the results obtained by executing subsequent processing measures. For example, in the scenario of time synchronization, the accuracy of the sending timestamp and receiving timestamp directly affects the precision of time synchronization.

[0005] Therefore, how the sending end accurately determines the sending timestamp of the message and how the receiving end accurately determines the receiving timestamp of the message are problems that need to be solved urgently. Summary of the invention

[0006] The embodiments of the present application provide a delay reporting method and device, which can accurately report the delay.

[0007] In the first aspect, the present application provides a delay reporting method, which can be applied to a first module. The first module can report the target delay corresponding to data at multiple specific positions in a data stream, where the multiple specific positions are spaced at fixed lengths, and the periods of the multiple specific positions correspond to the periods of inserting padding sequences in the data stream. In an embodiment of the present application, if the first module corresponds to a transmitting end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay, and if the first module corresponds to a receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay. It can be seen that, using this solution, delay information can be accurately reported.

[0008] In a possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks. Among them, 8712 is the period corresponding to the insertion of the filling sequence in the data stream, and 8704 is the period corresponding to the insertion of the filling sequence in the data stream. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position corresponds to 8704, and when the first module corresponds to the receiving end, the period of the specific position corresponds to 8712. Among them, the period of the specific position is an integer multiple of 8172 data blocks or an integer multiple of 8704 data blocks, which can be understood as the period corresponding to the integer multiple of the length of 8172 data blocks or the integer multiple of the length of 8704 data blocks. In a possible implementation, the data block includes 128 bits or 120 bits. For example, if the data block is a data block after forward error correction (FEC) inner code encoding, the data block includes 128 bits. If the data block has not been FEC inner code encoded, or the data block has been FEC inner code decoded, the data block includes 120 bits. As a specific example, when the first module corresponds to the transmitting end, the data block includes 120 bits, and when the first module corresponds to the receiving end, the data block includes 128 bits.

[0009] In a possible implementation, the period of the multiple specific positions is an integer multiple of any of the following values: 8704*120=1044480 bits; or, 8704*128=1114112 bits; or, 8712*128=1115136 bits, or, 8712*120=1045440 bits. Wherein, if the first module corresponds to the transmitting end, before the first module performs the check sequence (pad) increase and the pad sequence increase operation on the data stream, the period of the specific position is an integer multiple of 8704*120=1044480 bits; after the first module performs the check sequence increase operation on the data stream, the period of the specific position is an integer multiple of 8704*128=1114112 bits; after the first module further performs the check sequence increase operation on the data stream, the period of the specific position is an integer multiple of 8712*128=1115136 bits. If the first module corresponds to the receiving end, before the first module performs the check sequence deletion operation on the data stream and the padding sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8712*128=1115136 bits; after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*128=1114112 bits; after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*120=1044480 bits.

[0010] In a possible implementation, the period of the multiple specific positions may be an integer multiple of 64 data blocks or an integer multiple of 65 data blocks. Wherein, 65 is the period corresponding to after the padding sequence is inserted into the data stream, and 64 is the period corresponding to before the padding sequence is inserted into the data stream. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position is an integer multiple of 64 data blocks, and when the first module corresponds to the receiving end, the period of the specific position is an integer multiple of 65 data blocks. Wherein, the period of the specific position is an integer multiple of 64 data blocks or an integer multiple of 65 data blocks, which can be understood as the period corresponding to an integer multiple of the length of 64 data blocks or an integer multiple of the length of 65 data blocks.

[0011] In a possible implementation, each of the aforementioned 64 data blocks and 65 data blocks may include 4 bits. In this scenario, the padding sequence insertion may be to insert a 4-bit pilot signal every 64 4-bit data blocks.

[0012] In a possible implementation, the specific position may be the starting position of a data block. The starting position of a data block may be the first byte of the data block, or the first bit or the first symbol. In a scenario where the data block includes 128 bits, the data block mentioned here may be an FEC codeword.

[0013] In a specific example, the FEC codeword may be an FEC inner codeword. In other words, the aforementioned specific position may be the starting position of the FEC inner codeword.

[0014] In a possible implementation manner, the specific position is the starting position of the next data block after the filling sequence is inserted into the data stream, and the starting position is the first bit or the first symbol or the first byte of the next data block.

[0015] In a possible implementation, the data stream is a data stream obtained by FEC inner code encoding. Specifically, if the first module corresponds to the transmitting end, the first module can perform FEC inner code encoding and pad addition operations on the data entering the first module. Accordingly, in one example, the data stream mentioned here can be a data stream after performing FEC inner code encoding and pad addition operations. If the first module corresponds to the receiving end, in one example, the data stream can be a data stream sent by the transmitting end to the first module. In other words, the data stream is a data stream entering the first module, and the data stream is FEC inner code encoded and pad added at the transmitting end. In another example, considering that the receiving end can perform FEC inner code decoding on the data stream after the transmitting end sends the data stream to the receiving end, the data stream can also be a data stream obtained after the receiving end performs FEC inner code decoding on the received data stream. In other words, if the first module is a module corresponding to the receiving end, in another example, the data stream can be a data stream obtained after FEC inner code decoding.

[0016] In a possible implementation, in addition to inserting a filling sequence into the data stream, the transmitter can also insert a check sequence. Specifically, when the transmitter performs FEC inner code encoding on the data stream, an 8-bit check sequence can be inserted for every 128 bits of data. Since the transmitter inserts a 1024-bit pad every 8704 FEC inner code blocks when inserting the pad. Therefore, the period of inserting the filling sequence into the data stream by the transmitter is an integer multiple of the period of inserting the check sequence into the data stream. It is precisely because the period of inserting the filling sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream, the peak position of the large sawtooth wave overlaps with the peak position of the small sawtooth wave, and the trough position of the large sawtooth wave overlaps with the trough position of the small sawtooth wave. Therefore, the period of the aforementioned specific position can be determined based on the period of inserting the filling sequence into the data stream to determine the target delay.

[0017] In a possible implementation, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the first module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the inner FEC layer in the first module. In the case where the first module is an optical module, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the optical module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the inner FEC layer in the optical module. The inner FEC layer is a layer used to implement the inner FEC function.

[0018] In a possible implementation, in the data of the aforementioned multiple specific positions, the data of each specific position may correspond to a first delay, and therefore, the data of the aforementioned multiple specific positions may correspond to multiple first delays. Considering that the existing Institute of Electrical and Electronics Engineers (IEEE) 802.3cx Chapter 90 defines the corresponding maximum delay register and minimum delay register for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Chapter 90 for the mechanism of reporting delays at the physical layer, the maximum value and / or minimum value of the multiple first delays may be reported. In other words, the aforementioned target delay may be the maximum value and / or minimum value of the multiple first delays. For this case, the first module may also measure the first delay corresponding to the data of each specific position in the data of the multiple specific positions, and obtain multiple first delays, so as to report the maximum value and / or minimum value of the multiple first delays and realize the reporting of delay information.

[0019] In a possible implementation, a new register may be defined to report the aforementioned maximum value and / or minimum value to the second module.

[0020] As a specific example, a maximum delay register and / or a minimum delay register for transmission (transport, TX) of the inner code FEC is defined, and the TX maximum delay register is used for the module as the transmitting end to report the maximum value, and the TX minimum delay register is used for the module as the transmitting end to report the minimum value. In other words, when the first module corresponds to the transmitting end, the first module can use the TX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the TX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0021] As another specific example, a receive (RX) maximum delay register and / or an RX minimum delay register of the inner code FEC is defined, and the RX maximum delay register is used for the module as the receiving end to report the maximum value, and the RX minimum delay register is used for the module as the receiving end to report the minimum value. In other words, when the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the RX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0022] In a possible implementation, the first module may use an existing register to report the maximum value and / or minimum value to the second module. In this way, the target delay report can be implemented by using the existing register.

[0023] As a specific example, if the first module corresponds to the transmitting end, the first module can use the TX maximum delay register of the physical medium attachment (PMA) / physical media dependent (PMD) to report the maximum value to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0024] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0025] In a possible implementation, the first module reports the target delay, and in a specific implementation, the target delay can be reported to the second module. In an example, the second module can be a media access control (MAC) layer module of the communication device, so that the MAC layer module can compensate the timestamp recorded by itself based on the target delay, so that the timestamp after compensation is more accurate.

[0026] In a possible implementation, the first module may be an optical module or a physical (PHY) layer chip. The optical module or the PHY layer chip can provide an inner code FEC function.

[0027] In a possible implementation, the optical module includes an inner code FEC module, which is used to implement the inner code FEC function. The inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module. The inner code FEC encoding module is used to implement the FEC inner code encoding function, and the inner code FEC decoding module is used to implement the FEC inner code decoding function.

[0028] In the second aspect, the present application provides a delay reporting method, which can be applied to a first module, and the first module can obtain the delay jitter value of the target data passing through the first submodule in the first module. The target data is the data sent by the first module, or the target data is the data received by the first module. There is a submodule with a delay jitter of a fixed value in the first submodule. Further, based on the delay jitter value, the delay information is reported to the second module. In an embodiment of the present application, considering that the first submodule will introduce delay jitter, so that the delay of the target data passing through the first module is jittered, therefore, when the first module reports the delay information to the second module, it reports based on the delay jitter value introduced by the first submodule, so that the reported delay information is more accurate.

[0029] In a possible implementation, the first module may also determine a first delay of the target data passing through a second submodule in the first module. As an example, the second submodule may be a submodule that hardly introduces delay jitter. Accordingly, when the first module reports delay information to the second module, the delay information may be reported to the second module based on the delay jitter value and the first delay during specific implementation. In other words, the first module may report delay information to the second module based on the existence of a delay jitter value and the first delay of the target data passing through the second submodule that hardly introduces delay jitter, thereby making the delay information reported by the first module to the second module more accurate.

[0030] In a possible implementation manner, the first module may determine a target delay according to the delay jitter value and the first delay, and report the target delay as the aforementioned delay information to the second module.

[0031] In one possible implementation, if the first module corresponds to a communication device as a transmitting end, the first communication device may determine the sum of the delay jitter value and the first delay as the target delay. If the first communication device corresponds to a communication device as a receiving end, the first communication device may determine the difference obtained by subtracting the delay jitter value from the first delay as the target delay. In this way, the target delay reported by the first module can satisfy "for the transmitting end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay".

[0032] In a possible implementation, considering that the existing IEEE 802.3cx Chapter 90 defines the corresponding maximum delay register and minimum delay register for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Chapter 90 for the mechanism of reporting delay at the physical layer, the first delay may include two delays, which are the maximum delay of the target data passing through the second submodule, and the minimum delay of the target data passing through the second submodule. Correspondingly, for this case, the target delay includes: the maximum target delay obtained according to the maximum delay and the delay jitter value, and the minimum target delay obtained according to the minimum delay and the delay jitter value.

[0033] In a possible implementation, a new register may be defined to report the aforementioned maximum target delay and / or minimum target delay to the second module.

[0034] As a specific example, a TX maximum delay register and / or a TX minimum delay register of an inner code FEC is defined, and the TX maximum delay register is used for the module as the transmitting end to report the maximum target delay, and the TX minimum delay register is used for the module as the transmitting end to report the minimum target delay. In other words, when the first module corresponds to the transmitting end, the first module can use the TX maximum delay register of the inner code FEC to report the maximum target delay to the second module, and use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0035] As another specific example, an RX maximum delay register and / or an RX minimum delay register of the inner code FEC is defined, the RX maximum delay register is used for the module as the receiving end to report the maximum target delay, and the RX minimum delay register is used for the module as the receiving end to report the minimum target delay. In other words, when the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module, and use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0036] In a possible implementation, the first module may use an existing register to report the aforementioned maximum target delay and / or minimum target delay to the second module. In this way, the existing register may be used to implement the target delay report.

[0037] As a specific example, if the first module corresponds to the transmitting end, the first module can use the TX maximum delay register of the physical medium attachment (PMA) / physical media dependent (PMD) to report the maximum target delay to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0038] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0039] In a possible implementation manner, the second submodule may be a submodule of the first module other than the first submodule.

[0040] In a possible implementation, if the first module corresponds to the transmitting end, the second submodule may be, for example, a submodule in the inner code FEC module that performs operations such as convolution interleaving, distribution, and modulation coding. If the first module corresponds to the receiving end, the second submodule may be, for example, a submodule in the inner code FEC module that performs operations such as inverse convolution deinterleaving, multiplexing, and modulation decoding.

[0041] In a possible implementation, when determining the first delay of the target data passing through the second submodule in the first module, the first delay set in advance may be obtained. The first delay may be a value determined by the first module in the design phase, and the value of the first delay is related to the performance of the first module.

[0042] In a possible implementation, when determining the first delay of the target data passing through the second submodule in the first module, the delay of the target data passing through the second submodule may be counted to obtain the first delay.

[0043] In a possible implementation, the time delay of the target data passing through the second submodule can be counted in a specific implementation, and the time delay of at least one bit of the target data passing through the second submodule can be counted, so as to obtain the first time delay. For example, the target data can be sampled, and the time delay of the sampled data passing through the second submodule can be counted. For another example, the time delay of each bit of the target data passing through the second submodule can be counted, so as to obtain the first time delay.

[0044] In a possible implementation, the first module further includes a third submodule, and the first module can also determine a second delay of the target data passing through the third submodule in the first module. In a scenario where the first module determines the second delay, when the first module reports the delay information to the second module, the delay information can be reported to the second module according to the delay jitter value and the second delay, thereby accurately reporting the delay information to the second module.

[0045] In a possible implementation, the third submodule may be another submodule in the first module that is different from the first submodule and the second submodule. For example, the third submodule may include a PMA submodule and a PMD submodule.

[0046] In a possible implementation, the second module includes: a media access control MAC layer module. In a possible implementation, the delay jitter value may be a preset fixed value. For example, when the first module is an optical module, the delay jitter value may include the sum of a first jitter value and a second jitter value, and the first jitter value may be a delay jitter value introduced by adding or deleting a check sequence and interleaving or deinterleaving a data stream. The second jitter value may be a delay jitter value introduced by adding or deleting a pad. Among them, the fixed value may be, for example, a value between 4.6ns and 4.8ns.

[0047] In a possible implementation, the first submodule includes a submodule for delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence. As a specific example, for the transmitting end, the first submodule may include: a submodule for delay jitter caused by adding a check sequence, and a submodule for delay jitter caused by adding a padding sequence. Correspondingly, for the receiving end, the first submodule may include: a submodule for delay jitter caused by deleting a check sequence, and a submodule for delay jitter caused by deleting a padding sequence.

[0048] In a possible implementation, the first submodule includes a submodule for delay jitter caused by interleaving or deinterleaving of data streams. As a specific example, for a transmitting end, the first submodule may include: a submodule for delay jitter caused by interleaving of data streams. Correspondingly, for a receiving end, the first submodule may include: a submodule for delay jitter caused by deinterleaving of data streams.

[0049] In a possible implementation, the aforementioned submodule with delay jitter caused by the increase of the check sequence may be a submodule in the inner code FEC module that performs FEC inner code encoding; the aforementioned submodule with delay jitter caused by the increase of the filling sequence may be a submodule in the inner code FEC module that performs the filling sequence increase operation; the aforementioned submodule with delay jitter caused by the interleaving of the data stream may be a submodule in the inner code FEC module that performs data stream interleaving. In other words, the first submodule may include: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and filling sequence increase.

[0050] In a possible implementation, the aforementioned submodule with delay jitter caused by deletion of the check sequence may be a submodule in the inner code FEC module that performs FEC inner code decoding; the aforementioned submodule with delay jitter caused by deletion of the padding sequence may be a submodule in the inner code FEC module that performs padding sequence deletion; the aforementioned submodule with delay jitter caused by deinterleaving of the data stream may be a submodule in the inner code FEC module that performs data stream deinterleaving. In other words, the first submodule may include: a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence deletion.

[0051] In a possible implementation, both the transmitting end and the receiving end may perform a cyclic shift operation. In an example, if the shift direction corresponding to the cyclic shift operation performed by the receiving end is the same as the shift direction corresponding to the cyclic shift operation performed by the transmitting end, the first submodule may include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the delay jitter value introduced by the cyclic shift submodule may be 4.5 nanoseconds.

[0052] In a possible implementation, when the first submodule further includes a cyclic shift submodule, the delay jitter value may be the sum of the first jitter value and the second jitter value, plus the delay jitter 4.5ns introduced by the cyclic shift submodule. Since the sum of the first jitter value and the second jitter value is between 4.6ns and 4.8ns, the delay jitter value may be between (4.5ns+4.6ns=9.1ns) and (4.5ns+4.8ns=9.3ns).

[0053] In one possible implementation, the target data may correspond to the data included in a cycle of the specific position described in the first aspect above. For example, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0054] In a possible implementation manner, the data block includes 128 bits or 120 bits.

[0055] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0056] In a third aspect, an embodiment of the present application provides a delay reporting device, which includes: a sending unit, used to report the target delay corresponding to data at multiple specific positions in a data stream, the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a filling sequence in the data stream.

[0057] In one possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

[0058] In a possible implementation, the data block includes 128 bits, 120 bits, or 4 bits.

[0059] In a possible implementation, the period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

[0060] In a possible implementation manner, the specific position is a starting position of the FEC codeword, and the starting position is the first bit or the first symbol or the first byte of the FEC codeword.

[0061] In a possible implementation manner, the FEC codeword includes: an FEC inner codeword.

[0062] In a possible implementation manner, the data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

[0063] In a possible implementation manner, a period for inserting a filling sequence into the data stream is an integer multiple of a period for inserting a check sequence into the data stream.

[0064] In a possible implementation manner, the target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

[0065] In one possible implementation, the device also includes: a processing unit, used to measure the first delay corresponding to the data at each specific location among the data at the multiple specific locations, to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0066] In a possible implementation, the sending unit is used to: use the TX maximum delay register of the inner code FEC to report the maximum value; and / or use the TX minimum delay register of the inner code FEC to report the minimum value.

[0067] In a possible implementation, the sending unit is used to: use the TX maximum delay register of the physical medium attachment PMA / physical medium dependent PMD to report the maximum value; and / or use the TX minimum delay register of the PMA / PMD to report the minimum value.

[0068] In a possible implementation, the sending unit is used to: use the RX maximum delay register of the inner code FEC to report the maximum value; and / or use the RX minimum delay register of the inner code FEC to report the minimum value.

[0069] In a possible implementation, the sending unit is configured to: report the maximum value by using an RX maximum delay register of the PMA / PMD; and / or report the minimum value by using an RX minimum delay register of the PMA / PMD.

[0070] In a possible implementation manner, the sending unit is used to report the target delay corresponding to the data at the multiple specific positions in the data stream to a media access control MAC layer.

[0071] In a possible implementation manner, the device is applied to an optical module or a physical PHY layer chip.

[0072] In a possible implementation manner, the optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

[0073] In a possible implementation manner, the specific position is the starting position of the next data block after the filling sequence is inserted into the data stream, and the starting position is the first bit or the first symbol or the first byte of the next data block.

[0074] In a fourth aspect, an embodiment of the present application provides a delay reporting device, which is applied to a first module, and the device includes: a processing unit, which is used to obtain the delay jitter value of target data passing through a first submodule in the first module, the first submodule including a submodule with a delay jitter with a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; a sending unit, which is used to report the delay information to the second module according to the delay jitter value.

[0075] In a possible implementation, the processing unit is further used to determine a first delay of the target data passing through a second submodule in the first module; and the sending unit is used to report the delay information to the second module based on the delay jitter value and the first delay.

[0076] In a possible implementation manner, the sending unit is used to report to the second module a target delay obtained according to the delay jitter value and the first delay.

[0077] In a possible implementation manner, the target delay includes: the sum of the delay jitter value and the first delay; or a difference obtained by subtracting the delay jitter value from the first delay.

[0078] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained according to the maximum delay and the delay jitter value, and the minimum target delay obtained according to the minimum delay and the delay jitter value.

[0079] In one possible implementation, if the target data is data sent by the first module, the sending unit is used to: use the TX maximum delay register of the inner code forward error correction FEC to report the maximum target delay to the second module; use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0080] In one possible implementation, if the target data is data sent by the first module, the sending unit is used to: use the TX maximum delay register of the physical medium attachment PMA / physical medium related PMD to report the maximum target delay to the second module; use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0081] In one possible implementation, if the target data is data received by the first module, the sending unit is used to: use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module; use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0082] In one possible implementation, if the target data is data received by the first module, the sending unit is used to: use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module; use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0083] In a possible implementation manner, the second submodule includes: a submodule other than the first submodule.

[0084] In a possible implementation, the second submodule includes: a submodule in the inner code FEC module that performs convolution interleaving, distribution, and modulation coding operations; or a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

[0085] In a possible implementation manner, the processing unit is used to: obtain the preset first delay.

[0086] In a possible implementation, the processing unit is configured to: count a first time delay of the target data passing through the second submodule.

[0087] In a possible implementation, the counting of a delay of the target data passing through the second submodule includes: counting a delay of at least one bit of the target data passing through the second submodule to obtain the first delay.

[0088] In a possible implementation, the processing unit is further used to determine the second delay of the target data passing through the third submodule in the first module; and the sending unit is used to report the delay information to the second module based on the delay jitter value and the second delay.

[0089] In a possible implementation manner, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0090] In a possible implementation, the second module includes: a media access control MAC layer module.

[0091] In a possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0092] In a possible implementation manner, the first submodule includes: a cyclic shift submodule.

[0093] In a possible implementation, the first submodule includes a submodule having delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence.

[0094] In a possible implementation manner, the first submodule includes a submodule having delay jitter caused by interleaving or deinterleaving of data streams.

[0095] In one possible implementation, the first submodule includes: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence adding operations; or a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence removing operations.

[0096] In a possible implementation, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0097] In a possible implementation manner, the data block includes 128 bits or 120 bits.

[0098] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0099] In a fifth aspect, an embodiment of the present application provides a device. The device includes a processor, the processor is used to execute the method described in the first aspect and any one of the first aspects above; or the processor is used to execute the instructions or computer programs in the memory to execute the method described in the second aspect and any one of the second aspects above.

[0100] In one possible implementation, the device also includes a memory, the memory is used to store instructions or computer programs, and the processor is used to execute the instructions or computer programs in the memory, triggering the method described in the first aspect and any one of the first aspects above; or, the processor is used to execute the instructions or computer programs in the memory, and execute the method described in the second aspect and any one of the second aspects above.

[0101] In a sixth aspect, an embodiment of the present application provides a device, comprising an interface circuit and a processing circuit, wherein the interface circuit is used to receive and / or send data, and the processing circuit is used to perform data processing.

[0102] In an example, the device can be used to execute the method described in any one of the first aspects above. For this case:

[0103] The interface circuit is used to report the target delay corresponding to data at multiple specific positions in the data stream, the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a filling sequence in the data stream.

[0104] In one example, the processing circuit is used to measure the first delay corresponding to the data at each specific position among the data at the multiple specific positions to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0105] In yet another example, the device may be used to execute the method described in any one of the second aspects above. For this case:

[0106] The processing circuit is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule includes a submodule with a delay jitter with a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; the interface circuit is used to report the delay information to the second module according to the delay jitter value.

[0107] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, including instructions or a computer program, which, when running on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects, or, when running on a computer, enables the computer to execute the method described in the second aspect and any one of the above second aspects.

[0108] In an eighth aspect, an embodiment of the present application provides a computer program product comprising instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects, or enables the computer to execute the method described in the second aspect and any one of the above second aspects.

[0109] In the ninth aspect, an embodiment of the present application provides a chip, including an interface circuit and a processing circuit, and the chip is used to execute the method described in the first aspect and any one of the above first aspects; or, execute the method described in the second aspect and any one of the above second aspects.

[0110] In the tenth aspect, an embodiment of the present application provides an optical module, comprising an interface circuit and a processing circuit, and the optical module is used to execute the method described in the first aspect and any one of the first aspect above; or, to execute the method described in the second aspect and any one of the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0112] Figure 1a A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0113] Figure 1b A schematic diagram of the structure of another communication device provided in an embodiment of the present application;

[0114] Figure 1c A schematic diagram of a delay introduced by an FEC function provided in an embodiment of the present application;

[0115] Figure 1d A schematic diagram of the structure of another communication device provided in an embodiment of the present application;

[0116] Figure 1e A schematic diagram of a delay introduced by an inner code FEC function provided in an embodiment of the present application;

[0117] Figure 1f A schematic diagram of a delay introduced by another inner code FEC function provided in an embodiment of the present application;

[0118] Figure 1g A schematic diagram of a delay introduced by another inner code FEC function provided in an embodiment of the present application;

[0119] Figure 1h A schematic diagram of a delay introduced by an inner code FEC function provided in an embodiment of the present application;

[0120] Figure 2 A flowchart of a delay reporting method provided in an embodiment of the present application;

[0121] Figure 3 A schematic diagram of the structure of a first module provided in an embodiment of the present application;

[0122] Figure 4 A flowchart of another delay reporting method provided in an embodiment of the present application;

[0123] Figure 5 A schematic diagram of an inner code FEC processing process provided in an embodiment of the present application;

[0124] Figure 6 A schematic diagram of the structure of a delay reporting device provided in an embodiment of the present application;

[0125] Figure 7 A schematic diagram of the structure of another delay reporting device provided in an embodiment of the present application;

[0126] Figure 8 A schematic diagram of the structure of a device provided in an embodiment of the present application;

[0127] Fig. 9 A schematic diagram of the structure of a device provided in an embodiment of the present application;

[0128] Fig.10 A schematic diagram of the structure of a chip or optical module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0129] The embodiments of the present application provide a delay reporting method and device, which can accurately report the delay.

[0130] For easier understanding, the application scenarios of reporting latency are first introduced.

[0131] In the time synchronization scenario, time synchronization can be performed between communication devices by means of interactive messages. The communication device mentioned in the embodiments of the present application may be a network device such as a switch, a router, a slicing packet network (SPN) device, or an optical transmission network (OTN) device, or may be a component of a network device, such as a single board or line card or interface on a network device, or a functional module on a network device, or a chip, or a pluggable optical module on a network device, or a server, a network card on a server, or a network card of other devices, etc., which is not specifically limited in the embodiments of the present application. Communication devices may be directly connected, for example, but not limited to, via an Ethernet cable or an optical cable.

[0132] The 1588 protocol is a high-precision time synchronization protocol. The 1588 protocol can provide nanosecond (ns) level time synchronization accuracy. Currently, the International Telecommunication Union (ITU-T) G.8273.2 defines four levels (classes) of time synchronization accuracy requirements, namely class A, class B, class C and class D. Among them, the time accuracy corresponding to class A is ±100ns; the time accuracy corresponding to class B is ±70ns; the time accuracy corresponding to class C is ±30ns; and the time accuracy corresponding to class D is ±5ns. Therefore, in one example, communication devices can perform time synchronization by exchanging 1588 messages. The 1588 messages mentioned here can be understood as messages that follow the 1588 protocol.

[0133] When the communication devices exchange 1588 messages to perform time synchronization, in a specific implementation, the communication device that sends the 1588 message can add a sending timestamp in the 1588 message, and the sending timestamp indicates the time when the 1588 message was sent. Correspondingly, the communication device that receives the 1588 message will record the receiving timestamp of the 1588 message, and the receiving timestamp indicates the time when the 1588 message was received. Further, the communication device that receives the 1588 message can perform time synchronization based on the aforementioned sending timestamp and receiving timestamp. Since the sending timestamp and receiving timestamp are input parameters for time synchronization, the accuracy of the sending timestamp and the accuracy of the receiving timestamp directly affect the accuracy of time synchronization. In other words, it is particularly important to ensure the accuracy of the aforementioned sending timestamp and receiving timestamp.

[0134] Currently, the communication device records the timestamp in the following manner: the MAC layer of the communication device records the timestamp. In a specific scenario, for a communication device including an Ethernet interface, the MAC layer of the communication device may record the timestamp.

[0135] Next, in conjunction with the structure of the communication device, the method of recording the timestamp by the communication device is introduced.

[0136] See also Figure 1a , which is a schematic diagram of the structure of a communication device provided in an embodiment of the present application, including the structure of a transmitting end communication device and the structure of a receiving end communication device.

[0137] like Figure 1a As shown, whether it is a communication device as a transmitting end or a communication device as a receiving end, it can include a MAC layer and a physical layer, and the physical layer can include PCS, PMA and PMD. In addition, it can also include an application layer, and the application layer can correspond to an upper layer service, for example.

[0138] As the transmitting end, its MAC layer can generate a MAC frame and send it to the physical layer. For example, the MAC layer can receive data sent by an upstream device or an upper-layer service, and can encapsulate the data to form a MAC frame. For another example, if the MAC layer does not receive data sent by an upstream device or an upper-layer service, the MAC layer will generate a corresponding MAC frame based on the IDLE code stream.

[0139] The MAC layer of the transmitting end sends the MAC frame to the physical layer of the transmitting end. The physical layer may include PCS, PMA and PMD. The MAC layer of the transmitting end may record the timestamp of sending the MAC frame to the physical layer as the aforementioned sending timestamp.

[0140] The PCS can process the received data stream and send the processed data to the PMA. The data stream mentioned here can be a bit stream including multiple bits, and this data stream can be obtained by processing the MAC frame.

[0141] The PMA can modulate the data from the PCS into a signal supported by the channel for transmission.

[0142] The PMD is a signal transmitter, which is used to transmit the signal modulated by the PMA through the transmission medium.

[0143] The physical layer of the receiving end receives the signal transmitted on the aforementioned transmission medium, processes the signal, and then passes it to the MAC layer of the receiving end. As described above, the physical layer of the receiving end also includes the PMD, PMA, and PCS.

[0144] The PMD of the receiving end first receives the signal transmitted on the transmission medium. Then, the PMA demodulates the signal. The data obtained after the PMA demodulation is passed to the PCS, and the PCS performs corresponding operations on the received data. Among them, the operations performed by the PCS of the receiving end are the inverse operations of those performed by the PCS of the sending end. Further, the PCS can send the processed data stream to the MAC layer. At this point, after the MAC layer of the receiving end receives the data stream sent by the PCS, it can obtain the MAC frame sent by the sending end, and further process the MAC frame. For example, the MAC frame is parsed and sent to the upstream device or the upper-layer service. When the MAC of the receiving end receives the data stream processed by the PCS, the MAC layer of the receiving end can record the timestamp when it receives the data stream as the receive timestamp.

[0145] To support the high-precision time synchronization feature of 1588. The physical layer of the communication device can report the delay of the data stream passing through the physical layer to the MAC layer, so that when the MAC records the timestamp, it can compensate the recorded timestamp based on the delay of the data stream passing through the physical layer, so that the timestamp after compensation by the MAC layer is more accurate. Specifically:

[0146] For the sending end, the MAC layer can add the aforementioned delay of the data stream passing through the physical layer to the timestamp recorded by itself to obtain the send timestamp. It is not difficult to understand that this send timestamp can be considered as the timestamp when the physical layer of the sending end actually sends the data stream.

[0147] For the receiving end, the MAC layer can subtract the aforementioned delay of the data stream passing through the physical layer from the timestamp recorded by itself to obtain the receive timestamp. It is not difficult to understand that this receive timestamp can be considered as the timestamp when the physical layer of the receiving end actually receives the data stream.

[0148] As described above, the data stream transmitted at the physical layer is a bit stream including multiple bits. The physical layer cannot identify which parts of the bit stream correspond to the 1588 message. Therefore, the physical layer cannot accurately count the delay of the 1588 message. In order to solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer delay. That is, the delay of the data stream passing through the physical layer is stable near a fixed value, so that the physical layer can report the fixed value to the MAC layer, and accordingly, the MAC layer can compensate for the timestamp based on the fixed value.

[0149] However, for some communication devices, such as communication devices including 100GE Ethernet interfaces, the PCS of the physical layer includes an FEC function, and the FEC function of the PCS performs the addition and deletion of parity bits and the interleaving and deinterleaving of data streams. The addition and deletion of parity bits and the interleaving and deinterleaving of data streams will introduce delay jitter, thereby causing the delay of the data stream passing through the physical layer to be unstable. In the embodiments of the present application, the parity bit can also be referred to as a check sequence, and the two can be used interchangeably.

[0150] It should be noted that any communication device can be used as both a transmitter and a receiver. Figure 1a The roles of the sender and receiver shown can be interchanged if Figure 1a As shown, if the roles of the sending end and the receiving end are swapped, the direction of the data flow will also change accordingly, that is, the direction of the data flow can flow from the sending end after the role swap to the receiving end after the role swap.

[0151] For reference Figure 1b , Figure 1b A schematic diagram of the structure of another communication device provided in an embodiment of the present application. Figure 1b The structure of the communication device shown is similar to Figure 1a The structures of the communication devices shown are basically the same, except that Figure 1b The PCS of the communication device shown includes FEC functionality.

[0152] for Figure 1bIn the communication device shown, the sum of the delays introduced by the FEC function of the transmitter and the FEC function of the receiver is fixed. For example, the PCS of the transmitter will perform FEC encoding, and the encoding process includes adding check bits, which will introduce corresponding delay jitter. In addition, the transmitter will also perform data stream interleaving operations, which will also introduce certain delay jitter. Similarly, the PCS of the receiver will perform FEC decoding, and the decoding process includes deleting check bits, which will introduce corresponding delay jitter. In addition, the transmitter will also perform deinterleaving operations on the data stream, which will also introduce certain delay jitter. For the convenience of description, the delay caused by the implementation of the FEC function at the transmitter is called FEC_TX delay, and the delay caused by the implementation of the FEC function at the receiver is called FEC_RX delay. The FEC_TX delay and FEC_RX delay can be expressed as follows: Figure 1c shown. Figure 1c A schematic diagram of the delay introduced by an FEC function provided in an embodiment of the present application. Figure 1c The horizontal axis shows the bit stream passing through the PCS module, and the vertical axis shows the delay.

[0153] In an example, the FEC function of the PCS may also be referred to as an outer code FEC function, and the FEC codeword obtained by the PCS at the transmitting end performing FEC encoding may be referred to as an FEC outer codeword.

[0154] In addition, the current IEEE 802.3dj task force (B400G standard) defines that the physical layer supports cascade coding. Specifically, an inner code FEC is inserted between PMA and PMD for FEC inner code encoding and decoding. As an example, the FEC codeword obtained by performing FEC inner code encoding on the inner code FEC of the transmitting end can be referred to as the FEC inner code codeword.

[0155] For reference Figure 1d To understand, Figure 1d This is a schematic diagram of the structure of another communication device provided in an embodiment of the present application. Figure 1d As shown, the physical layer of the communication device supporting cascade coding includes: PCS supporting FEC function, PMA 101, PMA 102, inner code FEC and PMD. Among them, PMA 101 and PMA 102 interact through the attachment unit interface (AUI). Among them:

[0156] The PCS and PMA 101 may belong to the first chip, and the PMA 102 , the inner code FEC and the PMD may belong to the optical module.

[0157] Since the inner code FEC needs to perform operations related to the inner code, and performing operations related to the inner code will also introduce delay jitter, compared with the outer code FEC function, the inner code FEC function also includes pad addition and deletion operations.

[0158] In one example, for the transmitting end, the operations performed by the inner code FEC include: encoding, interleaving and padding sequence (pad) addition. For the receiving end, the operations performed by the inner code FEC include: pad deletion, deinterleaving and decoding. In one example, the encoding may be, for example, inserting 8-bit check bits for every 120-bit information bits (message bits), and the interleaving may be, for example, 8:1 codeword interleaving. The padding may be, for example, filling 1024 bits of data every 8704 inner code blocks (each inner code block is 128 bits). That is: inserting a pad of a length corresponding to 8 inner code blocks every 8704 inner code blocks. In addition, after the transmitting end performs the pad addition operation, the obtained data stream may be encoded by four-level pulse amplitude modulation 4 (PAM4), that is: two bits in the data stream may be used as symbols obtained after a PAM4 encoding.

[0159] In another example, for the transmitter, the operations performed by the inner code FEC include: convolution interleaving, BCH (Bose Chaudhuri Hocquenghem) encoding and padding sequence (pad) addition. For the receiver, the operations performed by the inner code FEC are the inverse operations of the inner code FEC operations performed by the transmitter, which may specifically include: pad deletion, BCH decoding and deconvolution interleaving. Among them:

[0160] The convolution interleaving operation may be, for example, sending every 40 bits of data to N delay channels (lines) in a polling manner. For example, taking the number of delay channels as 3 as an example, the three delay lines are the 0th delay line, the 1st delay line and the 2nd delay line. Among them, the 0th delay line will not perform a delay operation on the data, the 1st delay line will delay every 40 bits of data by the time corresponding to 6*40 bits, and the 2nd delay line will delay every 40 bits of data by the time corresponding to 12*40 bits. Deconvolution interleaving is the inverse process of convolution interleaving. During the deconvolution interleaving process, the 2nd delay line will not perform a delay operation on the data, the 1st delay line will delay every 40 bits of data by the time corresponding to 6*40 bits, and the 0th delay line will delay every 40 bits of data by the time corresponding to 12*40 bits.

[0161] BCH encoding, for example, may insert 16 check bits for every 110 bits of information bits. Correspondingly, BCH decoding may delete the 16 check bits for every 126 bits of coded information to obtain 110 bits of information bits.

[0162] Pad addition can be to insert a 4-bit pilot into every 64 4-bit data blocks. That is, in this scenario, pad can be a pilot. Correspondingly, pad deletion is to delete the 4-bit pilot included in every 65 4-bit data blocks (that is, delete one of the data blocks used as a pilot), and obtain 64 4-bit data blocks.

[0163] For the transmitter, the two sub-functions of adding check bits and interleaving included in the encoding process will introduce delay jitter. Correspondingly, for the receiver, the two sub-functions of deleting check bits and deinterleaving included in the decoding process will also introduce delay jitter. This causes both FEC_TX delay and FEC_RX delay to introduce delay jitter in the shape of a sawtooth wave. The sawtooth wave period is about 4.5ns (1024 / 113.4375G / 2), and the sawtooth wave amplitude is about 0.28125ns (64 / 113.4375G / 2). Please refer to Figure 1e To understand, Figure 1e A schematic diagram of the delay introduced by the inner code FEC function provided in an embodiment of the present application. In one example, Figure 1e One cycle of the sawtooth wave shown may include 8 FEC inner code words, where:

[0164] In the formula 1024 / 113.4375G / 2:

[0165] 1024 corresponds to the number of bits contained in 8 FEC inner code words. One FEC inner code word contains 128 bits.

[0166] 113.4375G corresponds to the baud rate of a single physical channel (lane);

[0167] 2 means that in the scenario where PAM4 encoding is performed on the data stream, one symbol includes 2 bits;

[0168] In the formula 64 / 113.4375G / 2:

[0169] 64 means that in 8:1 codeword interleaving, the first bit of the ninth virtual lane is located at the 65th bit in the interleaved data, and it needs to wait for the first 64 bits to be sent before it can be sent;

[0170] 113.4375G corresponds to the baud rate of a single physical channel;

[0171] 2 means that one symbol consists of 2 bits.

[0172] In addition, for the transmitter, adding this sub-function of pad will introduce delay jitter. Correspondingly, for the receiver, deleting this sub-function of pad will also introduce delay jitter. This causes FEC_TX delay and FEC_RX delay to introduce delay jitter in the shape of a sawtooth wave. The sawtooth wave period mentioned here is about 4910ns (8704*128 / 113.4375G / 2), and the sawtooth wave amplitude is about 4.5ns (1024 / 113.4375G / 2). Compared with the sawtooth wave introduced by the above-mentioned encoding process or decoding process, the sawtooth wave introduced by adding or deleting pad has a larger period and can be simply called a large sawtooth. Correspondingly, the sawtooth wave introduced by the encoding process or decoding process is called a small sawtooth. Please refer to Figure 1f To understand, Figure 1f A schematic diagram of the delay introduced by an inner code FEC function provided in an embodiment of the present application. Figure 1f The delay introduced by the padding operation at the transmitting end and the delay introduced by the de-stuffing operation at the receiving end are shown. That is to say, in the scenario of cascade coding, there is delay jitter in the aforementioned optical module due to the addition and deletion of check bits, interleaving and de-interleaving, and the addition and deletion of pads. Figure 1f The period of the sawtooth wave shown is Figure 1e Therefore, the delay introduced by the addition and deletion of check bits and the interleaving and deinterleaving (as shown above) Figure 1e As shown) and the delay caused by adding or removing pads (as shown above Figure 1f The delay after the delay of the delay of the superposition of the delay of the delay shown in Figure 1g To understand. Figure 1g A schematic diagram of the delay introduced by another inner code FEC function provided in an embodiment of the present application.

[0173] In the formula 8704*128 / 113.4375G / 2:

[0174] 8704*128 indicates the number of bits included in 8704 FEC inner code words;

[0175] 113.4375G corresponds to the baud rate of a single physical channel;

[0176] 2 means that one symbol consists of 2 bits.

[0177] In the formula 1024 / 113.4375G / 2:

[0178] 1024 means that 1024 bits of padding data are filled every 8704 inner code blocks;

[0179] 113.4375G corresponds to the baud rate of a single physical channel;

[0180] 2 means that one symbol consists of 2 bits.

[0181] about Figure 1g The sawtooth wave shown needs to be explained as follows:

[0182] The small sawtooth corresponding to the FEC_TX delay and the small sawtooth corresponding to the FEC_RX delay have the same period. In other words, the peak position of the small sawtooth corresponding to the FEC_TX delay overlaps with the peak position of the small sawtooth corresponding to the FEC_RX delay, and the trough position of the small sawtooth corresponding to the FEC_TX delay overlaps with the trough position of the small sawtooth corresponding to the FEC_RX delay. However, the number of data (e.g., the number of bits) included in one period of the small sawtooth corresponding to the FEC_TX delay may be the same as or different from the number of data included in one period of the small sawtooth corresponding to the FEC_RX delay.

[0183] Similarly, the large sawtooth corresponding to the FEC_TX delay and the large sawtooth corresponding to the FEC_RX delay have the same period. In other words, the peak position of the large sawtooth corresponding to the FEC_TX delay overlaps with the peak position of the large sawtooth corresponding to the FEC_RX delay, and the trough position of the large sawtooth corresponding to the FEC_TX delay overlaps with the trough position of the large sawtooth corresponding to the FEC_RX delay. However, the number of data (e.g., the number of bits) included in one period of the large sawtooth corresponding to the FEC_TX delay may be the same as or different from the number of data included in one period of the large sawtooth corresponding to the FEC_RX delay.

[0184] In addition, for the sender:

[0185] In one example, one cycle corresponding to the large sawtooth wave may include 8704 data blocks corresponding to the FEC inner codewords, and one data block includes 120 information bits. After the transmitter performs FEC inner code encoding, an 8-bit check sequence is added to each data block. Therefore, it can also be considered that one cycle may include 8704 data blocks, and one data block includes 128 bits. Furthermore, after the transmitter performs the pad addition operation, 8 pads corresponding to the FEC codeword lengths will be inserted in one cycle, that is, it can be considered that one cycle includes 8712 data blocks, and one data block includes 128 bits. In other words, the data included in one cycle can be considered to have the following three situations: 8704*120=1044480 bits; or, 8704*128=1114112 bits; or, 8712*128=1115136 bits.

[0186] In another example, data included in one cycle may also include: 8712*120=1045440 bits.

[0187] Those skilled in the art can easily understand that the above four lengths can all be considered as the period corresponding to a large sawtooth wave.

[0188] After the sending end performs the pad adding operation on the data stream, the data stream with the added pad can be sent to the receiving end.

[0189] For the receiving end:

[0190] One cycle corresponding to the large sawtooth wave may include 8712 data blocks corresponding to the FEC inner code words, and one data block includes 128 bits. The receiving end may perform a pad deletion operation on the data blocks corresponding to the 8712 FEC inner code words to delete the pad inserted by the transmitting end. After the receiving end performs the pad deletion operation, one cycle includes 8704 data blocks corresponding to the FEC inner code words, and one data block includes 128 bits. Further, the receiving end may perform FEC inner code decoding on the data blocks corresponding to the 8704 FEC inner code words, and the 8-bit check sequence in each data block is deleted. Therefore, after the receiving end performs FEC inner code decoding, one cycle may include 8704 data blocks, and one data block includes 120 bits. Therefore, for the receiving end, the data included in one cycle can be in the following three cases: 8712*128=1115136 bits; or 8704*128=1114112 bits; or 8704*120=1044480 bits.

[0191] In another example, data included in one cycle may also include: 8712*120=1045440 bits.

[0192] Regarding the delay jitter introduced by the FEC function or the inner code FEC function mentioned above, the IEEE 802.3cx standard stipulates that for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay. Figure 1c In the scenario shown, the delay reported by the sender is X+N, and the delay reported by the receiver is YN.

[0193] However, the IEEE 802.3cx standard does not specify a specific implementation method for the transmitter to report the maximum delay and a specific implementation method for the receiver to report the minimum delay in a scenario where the physical layer supports the concatenated coding function.

[0194] For the inner code FEC function, the factors that introduce delay jitter include the addition and deletion of check bits, interleaving and deinterleaving, and the addition and deletion of pads. For the transmitter, the delay corresponding to the data at the start position of a specific data block, and its corresponding FEC_TX delay is equivalent to the maximum delay. Similarly, for the receiver, the delay corresponding to the data at the start position of a specific data block, and its corresponding FEC_RX delay is equivalent to the minimum delay. For reference Figure 1h To understand, Figure 1h A schematic diagram of the delay introduced by the inner code FEC function provided in an embodiment of the present application. Figure 1h middle:

[0195] The data corresponding to the position circled by the hollow circle has a delay equivalent to the maximum delay. The part circled by the hollow circle corresponds to the maximum delay introduced by the addition and deletion of the check sequence and the interleaving and deinterleaving, as well as the maximum delay introduced by the addition and deletion of the padding sequence. The addition and deletion of the check sequence mentioned here refers to the addition or deletion of the check sequence, and the addition and deletion of the padding sequence refers to the addition or deletion of the padding sequence.

[0196] The data corresponding to the position circled by the solid circle has a delay equivalent to the minimum delay, because the part circled by the hollow circle corresponds to the minimum delay introduced by the addition and deletion of the check sequence and the interleaving and deinterleaving, as well as the minimum delay introduced by the addition and deletion of the padding sequence.

[0197] The data at the position encircled by the hollow circle is the data at the starting position of the specific data block. Correspondingly, the data at the position encircled by the solid circle is also the data at the starting position of the specific data block.

[0198] As mentioned above, the period of the large sawtooth is an integer multiple of the period of the small sawtooth. Therefore, Figure 1h The period of the open circles shown corresponds to the period of the large sawtooth.

[0199] As before for Figure 1g From the description, we can see that Figure 1h In the scenario shown:

[0200] In one example, one cycle of the hollow circle includes 8704 data blocks, and one data block includes 120 bits. In another example, one cycle of the hollow circle includes 8704 data blocks, and one data block includes 128 bits. In another example, one cycle of the hollow circle includes 8712 data blocks, and one data block includes 128 bits.

[0201] In one example, one cycle of the solid circle includes 8712 data blocks, and one data block includes 128 bits. In another example, one cycle of the solid circle includes 8704 data blocks, and one data block includes 128 bits. In another example, one cycle of the solid circle includes 8704 data blocks, and one data block includes 120 bits.

[0202] The data blocks may be numbered in sequence, and there may be m data blocks between two adjacent circles, and the difference between the numbers of the data blocks corresponding to the two adjacent circles may be m. In this case, the period of the positions corresponding to the aforementioned circles is also m. For example, there may be 8712 data blocks between the data blocks corresponding to the two hollow circles, and the difference between the numbers of the data blocks corresponding to the two hollow circles may be 8712. Accordingly, the period of the positions marked by the hollow circles is 8712.

[0203] In addition, the existing IEEE 802.3cx Chapter 90 requires that when the physical layer of the communication device reports the delay, each layer reports the maximum delay and the minimum delay respectively. Specifically, IEEE 802.3cx Chapter 90 defines the registers for each layer to report the maximum delay and the minimum delay. For example, IEEE 802.3cx Chapter 90 defines the TX maximum delay register of PMA / PMD, the TX minimum delay register of PMA / PMD, the RX maximum delay register of PMA / PMD, and the RX minimum delay register of PMA / PMD, where:

[0204] The TX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device is used as a transmitter;

[0205] The TX minimum delay register of PMA / PMD is used to report the minimum delay of PMA / PMD when the communication device is used as a transmitter;

[0206] The RX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device is used as a receiving end;

[0207] The RX minimum delay register of the PMA / PMD is used to report the minimum delay of the PMA / PMD when the communication device acts as a receiving end.

[0208] In view of this, an embodiment of the present application provides a delay reporting method, which can accurately report the delay in a scenario where the physical layer supports the cascade coding function, while complying with the IEEE 802.3cx standard that "for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay."

[0209] Next, the delay reporting method provided in the embodiment of the present application is introduced with reference to the accompanying drawings.

[0210] Before introducing the delay reporting method provided in the embodiment of the present application, it should be noted that:

[0211] For the communication device, it may include a physical layer module, which is used to implement the functions implemented by the aforementioned physical layer. For the physical layer, it may include multiple submodules, each of which is used to implement a specific physical layer function. For example, the physical layer module includes a PCS submodule, a PMA submodule and a PMD submodule. The PCS submodule is used to implement the functions implemented by the aforementioned PCS, the PMA submodule is used to implement the functions implemented by the aforementioned PMA, and the PMD submodule is used to implement the functions implemented by the aforementioned PMD.

[0212] In addition, the communication device may further include an optical module, and the optical module may also include corresponding submodules for implementing corresponding functions. Figure 1d For the communication device of the structure shown, the optical module may include a PMA submodule, an inner code FEC module and a PMD submodule.

[0213] In addition, time synchronization is only one application scenario provided by the embodiment of the present application, and the solution of the embodiment of the present application can also be applied to other scenarios. For example, in the flow detection scenario, the communication device can also use the solution of the embodiment of the present application to determine the sending timestamp or receiving timestamp of the message. The application scenarios of the embodiment of the present application are not listed here one by one.

[0214] See also Figure 2 , which is a flow chart of a delay reporting method provided in an embodiment of the present application.

[0215] Figure 2 The delay reporting method shown in the figure can be applied to the first module, which can be a module in a communication device. The communication device mentioned here can be a communication device as a transmitting end or a communication device as a receiving end, which is not specifically limited in the embodiment of the present application. The structure of the first module can be as follows Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first module provided in an embodiment of the present application. Figure 3 As shown, the first module includes a bit stream processing module, a delay determination module and a delay reporting module. The bit stream processing module may include an FEC module and other modules interacting with the FEC module. The delay determination module is used to determine the delay, and the delay reporting module is used to report the determined delay to the second module.

[0216] In one example, the first module may be a PHY module or an optical module. As a specific example, the structure of the communication device including the first module is Figure 1d For this case, Figure 3 The FEC module shown may be a module that implements the inner code FEC function, wherein the module that implements the inner code FEC function may also be referred to as an "inner code FEC module".

[0217] The PHY module mentioned in the embodiments of the present application may be, for example, a PHY chip for implementing a PHY function.

[0218] Figure 2 The method shown may include the following S101-S102.

[0219] S101: Determine a target delay corresponding to data at a plurality of specific positions in a data stream, wherein the plurality of specific positions are spaced at fixed lengths, and a period of the plurality of specific positions corresponds to a period of inserting a filling sequence in the data stream.

[0220] In the embodiment of the present application, the data stream is a bit stream sent by the sending end to the receiving end.

[0221] In an embodiment of the present application, the first module may report the target delay to the second module. In one example, the second module may be a MAC layer module of the communication device, so that the MAC layer module may compensate the timestamp recorded by itself based on the target delay, so that the timestamp after compensation is more accurate.

[0222] In the embodiment of the present application, if the first module is a module corresponding to the sending end, for example Figure 1d The module corresponding to the inner code FEC shown is, or Figure 1d The optical module shown includes PMA102, inner code FEC and PMD, the first module can perform FEC inner code encoding and pad adding operations on the data entering the first module. Accordingly, in one example, the data stream mentioned here can be the data stream after performing FEC inner code encoding and pad adding operations. If the first module is a module corresponding to the receiving end, in one example, the data stream can be the data stream sent by the transmitting end to the first module. In other words, the data stream is the data stream entering the first module, and the data stream is subjected to FEC inner code encoding and pad adding operations at the transmitting end.

[0223] In another example, considering that after the transmitting end sends the data stream to the receiving end, the receiving end can perform FEC inner code decoding on the data stream, therefore, the data stream can also be a data stream obtained after the receiving end performs FEC inner code decoding on the received data stream. In other words, if the first module is a module corresponding to the receiving end, in another example, the data stream can be a data stream obtained after FEC inner code decoding.

[0224] Wherein: the first module is a module corresponding to the transmitting end, which can be understood as the first module is a module in the communication device as the transmitting end; the first module is a module corresponding to the receiving end, which can be understood as the first module is a module in the communication device as the receiving end. Wherein, the first module is a module corresponding to the receiving end, which can also be understood as the first module corresponding to the receiving end, and the first module is a module corresponding to the transmitting end, which can also be understood as the first module corresponding to the transmitting end.

[0225] In an embodiment of the present application, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the first module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the inner code FEC layer in the first module. In the case where the first module is an optical module, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the optical module. Alternatively, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the inner code FEC layer in the optical module. The inner code FEC layer is a layer used to implement the inner code FEC function. In the scenario where the first module is a PHY module, the target delay is the delay of the data at the aforementioned multiple specific positions passing through the inner code FEC layer in the PHY module.

[0226] In a specific example, the optical module may include an inner code FEC module corresponding to the inner code FEC layer, so in one example, the target delay may be the delay of the data at the aforementioned multiple specific positions passing through the inner code FEC module in the optical module. Wherein, the inner code FEC module is used to implement the inner code FEC function. In a specific example, the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module, the inner code FEC encoding module is used to implement the FEC inner code encoding function, and the inner code FEC decoding module is used to implement the FEC inner code decoding function. As an example, when the communication device acts as a transmitter, the inner code FEC module includes an inner code FEC encoding module. As another example, when the communication device acts as a receiver, the inner code FEC module includes an inner code FEC decoding module. As another example, considering that a communication device can act as both a transmitter and a receiver. Therefore, the inner code FEC module may include an inner code FEC encoding module and an inner code FEC decoding module.

[0227] In the embodiments of the present application, if the first module corresponds to the sending end, the target delay corresponding to the data at the multiple specific positions is equivalent to the maximum delay. If the first module corresponds to the receiving end, the target delay corresponding to the data at the multiple specific positions is equivalent to the minimum delay. As described above for Figure 1h it can be known that the multiple specific positions may be Figure 1h the positions circled by the circles in Figure 1h i.e., the starting positions of specific data blocks. For understanding, for the sending end, the multiple specific positions may be Figure 1h the positions circled by the hollow circles in Figure 1h For the receiving end, the multiple specific positions may be Figure 1h the positions circled by the solid circles in

[0228] As described above for Figure 1h it can be known that the period of the multiple specific positions may be 8712 data blocks or 8704 data blocks. Among them, 8712 is the period corresponding to after inserting the padding sequence in the data stream, and 8704 is the period corresponding to before inserting the padding sequence in the data stream. Of course, the period of the multiple specific positions may also be an integer multiple of 8712 data blocks or an integer multiple of 8704 data blocks. For example, if the period of the specific positions is K times of 8712 data blocks or 8704 data blocks, the larger the value of K, the fewer the number of specific positions for which the delay needs to be statistically, and correspondingly, the less computing resources consumed for statistically calculating the target delay.

[0229] In an example, a data block may include 128 bits or 120 bits. For example, if the data block is a data block after FEC inner code encoding, the data block includes 128 bits. If the data block has not been FEC inner code encoded, or the data block has been FEC inner code decoded, the data block includes 120 bits. Among them, if a data block includes 128 bits, the data block may also be referred to as an FEC inner code codeword.

[0230] As described above for Figure 1h it can be known that the period of the multiple specific positions may include the following situations:

[0231] 8704 * 120 = 1044480 bits; or, 8712 * 120 = 1045440 bits; or, 8704 * 128 = 1114112 bits; or, 8712 * 128 = 1115136 bits.

[0232] Therefore, in one example, the period of the multiple specific positions may be an integer multiple of 1044480 bits, an integer multiple of 1114112 bits, or an integer multiple of 1115136 bits.

[0233] In the scenario where convolution interleaving, BCH encoding and pad insertion are performed at the transmitting end, a data block may include 4 bits, and the period of the multiple specific positions may be 65 data blocks or 64 data blocks, where 65 is the period corresponding to after the padding sequence is inserted into the data stream, and 64 is the period corresponding to before the padding sequence is inserted into the data stream.

[0234] In an embodiment of the present application, the specific position may be the starting position of a data block. The starting position of a data block may be the first byte of the data block, or the first bit or the first symbol. In the scenario where the aforementioned data block includes 128 bits, the specific data block mentioned here may be a specific FEC codeword, for example, an FEC inner codeword.

[0235] For example, in the embodiment of the present application, the specific position may be the starting position of the next data block after the padding sequence is inserted into the data stream, that is, the starting position of the first data block in the payload.

[0236] In one example, the data stream may include multiple target data, each target data may include N data blocks, and accordingly, the aforementioned specific position may be the starting position of the N data blocks. In other words, the data stream may include multiple data blocks, and the multiple data blocks may be divided into multiple groups according to N data blocks as a group, and each group corresponds to one target data. In a scenario where a data block includes 128 bits, the target data may include N FEC inner code words.

[0237] In the embodiment of the present application, in addition to inserting a fill sequence into the data stream, the sender can also insert a check sequence. Specifically, when the sender performs FEC inner code encoding on the data stream, an 8-bit check sequence can be inserted for every 120 bits of data. In the embodiment of the present application, the period of inserting the fill sequence into the data stream by the sender is an integer multiple of the period of inserting the check sequence into the data stream. For example, Figure 1h To understand, Figure 1hIn the example, the period of the small sawtooth wave corresponds to the period of inserting the check sequence in the data stream, the period of the large sawtooth wave corresponds to the period of inserting the filling sequence in the data stream, and the period of the large sawtooth wave is an integer multiple of the period of the small sawtooth wave. In one example, the period of the large sawtooth wave may be 8704 times the period of the small sawtooth wave. It is precisely because the period of inserting the filling sequence in the data stream is an integer multiple of the period of inserting the check sequence in the data stream, therefore, the peak position of the large sawtooth wave overlaps with the peak position of the small sawtooth wave, and the trough position of the large sawtooth wave overlaps with the trough position of the small sawtooth wave, so the period of the aforementioned specific position can be determined based on the period of inserting the filling sequence in the data stream to determine the target delay.

[0238] In an example, among the data at the aforementioned multiple specific locations, the data at each specific location may correspond to a first time delay. Therefore, the data at the aforementioned multiple specific locations may correspond to multiple first time delays.

[0239] In the embodiment of the present application, the multiple first time delays may be the same, or may be not completely the same, or may be completely different, and the embodiment of the present application does not make any specific limitation.

[0240] As mentioned above, the existing IEEE 802.3cx Section 90 defines the corresponding maximum delay register and minimum delay register for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Section 90 mechanism for reporting delays at the physical layer, the maximum value and / or minimum value of the multiple first delays can be reported. In other words, the aforementioned target delay can be the maximum value and / or minimum value of the multiple first delays.

[0241] As mentioned above, the multiple first time delays may be the same, or may not be completely the same, or may be completely different. When the multiple first time delays are the same, the maximum value is the same as the minimum value. When the multiple first time delays are not completely the same, or may be completely different, the maximum value is less than the minimum value.

[0242] In one example, when S101 is specifically implemented, the first module may measure the first delay corresponding to the data at each specific location among the data at the multiple specific locations to obtain multiple first delays.

[0243] If the first module corresponds to the transmitting end, then for the data stream entering the first module, 8704 data blocks (each data block includes 120 bits) can be taken as a group, and the first delay of the data at the starting position of each group of data blocks in the first module can be measured to obtain multiple first delays.

[0244] If the first module corresponds to the receiving end, then for the data stream entering the first module, 8712 data blocks (each data block includes 128 bits) can be taken as a group, and the first delay of the data at the starting position of each group of data blocks in the first module can be measured to obtain multiple first delays.

[0245] The embodiment of the present application does not specifically limit the specific implementation method of determining the first delay.

[0246] In one example, the first module may record the delay for data at a specific position in the target data, thereby determining the first delay. In another example, the first module may determine the delay of data at multiple positions in the target data passing through the first module, thereby obtaining multiple delays corresponding to each target data. The multiple positions mentioned here may include the specific position, for example, the multiple positions may be various positions in the target data. Accordingly, for any target data, the first delay may be determined from the multiple delays corresponding to the target data. That is: from the multiple delays, the delay corresponding to the specific position is extracted to obtain the first delay. For example: for the target data, the first module may determine the delay of each bit of data in the target data passing through the first module, and extract the delay of the data at the starting position in the target data passing through the first module, thereby obtaining the first delay.

[0247] The embodiment of the present application does not specifically limit the method for determining the delay of data at any position in the target data passing through the first module, and two possible implementation methods are introduced below.

[0248] In one implementation, the first module can record the first moment when it receives the data at the location, and record the second moment when it sends the data at the location, and subtract the difference between the second moment and the first moment to determine the delay of the data at the location passing through the first module.

[0249] In another example, after receiving the data at the position, the first module can cache the data at the position. Accordingly, the first module can send the cached data out in order according to the data already cached in the cache. Therefore, the position of the data at the position in the cache can represent the length of time that the data at the position needs to wait in the cache, and the length of the wait can represent the delay of the data at the position passing through the first module. Therefore, the first module can determine the delay of the data at the position passing through the first module according to the position of the data at the position in the cache.

[0250] S102: Report target delays corresponding to data at multiple specific locations in the data stream.

[0251] The first module may report the target delay to the second module using the corresponding register. In a scenario where the target delay includes the aforementioned maximum value and / or minimum value, in one example, the first module may report the maximum value and / or minimum value to the second module using the corresponding register. The following introduces several specific implementations of the first module reporting the maximum value and / or minimum value to the second module using the corresponding register.

[0252] In one example, if the first module corresponds to a transmitting end, then:

[0253] As a specific example, a new register may be defined to report the maximum value and / or minimum value to the second module. For example, a TX maximum delay register and / or a TX minimum delay register of the inner code FEC may be defined, the TX maximum delay register being used to report the maximum value, and the TX minimum delay register being used to report the minimum value. In other words, the first module may use the TX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the TX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0254] As another specific example, the first module can use the TX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum value to the second module. In this way, the existing register can be used to implement the target delay report.

[0255] In one example, if the first module corresponds to a receiving end, then:

[0256] As another specific example, a new register may be defined to report the maximum value and / or the minimum value to the second module. For example, an RX maximum delay register and / or an RX minimum delay register of the inner code FEC may be defined, the RX maximum delay register being used to report the maximum value, and the RX minimum delay register being used to report the minimum value. In other words, the first module may use the RX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the RX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0257] As another specific example, the first module may use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module may use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0258] From the above description, it can be seen that by using the solution of the embodiment of the present application, the first module can follow "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay" to accurately report the delay to the second module.

[0259] The above introduces the delay reporting method provided in the embodiment of the present application. Next, the solution provided in the embodiment of the present application is introduced in combination with specific scenarios.

[0260] Embodiment 1: Figure 2 The specific implementation of the delay reporting method shown.

[0261] In this scenario, the structure of the communication device can be adopted Figure 1d In the structure shown, the first module may be an optical module of a communication device, and the optical module includes PMA 102, inner code FEC and PMD.

[0262] For a communication device as a transmitter, its optical module can perform the following operations:

[0263] S1: Record the delay of the starting position of the i-th data block in the data stream it sends through the optical module to obtain DelayTX(1, i), where:

[0264] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0265] The value of i can be 8704, 8704*2, 8704*3, …8704*k.

[0266] S2: Determine the maximum value DelayTX_max of DelayTX(1, i) and the minimum value DelayTX_min of DelayTX(1, i).

[0267] S3: Report DelayTX_max and DelayTX_min to the MAC layer module.

[0268] In an example, DelayTX_max can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0269] In yet another example, DelayTX_max may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and DelayTX_min may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0270] For a communication device acting as a receiving end, its optical module can perform the following operations:

[0271] S1’: Record the delay of the starting position of the j-th FEC inner code block in the data stream it receives passing through the optical module, obtaining DelayRX(1, j).

[0272] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0273] The value of j can be 8712, 8712*2, 8712*3, … 8712*k.

[0274] S2’: Determine the maximum value DelayRX_max of DelayRX(1, j) and the minimum value DelayRX_min of DelayRX(1, j).

[0275] S3’: Report DelayRX_max and DelayRX_min to the MAC layer module.

[0276] In one example, DelayRX_max can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0277] In another example, DelayRX_max can be reported to the MAC layer module through the RX maximum delay register of PMA / PMD, and DelayRX_min can be reported to the MAC layer module through the RX minimum delay register of PMA / PMD.

[0278] The inventors of this application also found that if the sub-modules included in the first module include sub-modules that can introduce delay jitter, then if the first module can report based on this delay jitter value when reporting delay information to the second module, it can also accurately report delay information to the second module while following the rule in the IEEE 802.3cx standard that "for the transmitting end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay".

[0279] In view of this, the embodiments of this application also provide another Figure 2 delay reporting method parallel to the delay reporting method shown. Next, in combination with Figure 4 , this delay reporting method will be introduced. Figure 4 It is a schematic flowchart of another delay reporting method provided by the embodiments of this application.

[0280] Figure 4The method shown can be applied to the first module. Regarding the first module, please refer to the above description of the first module, and no repeated description will be made here.

[0281] Figure 4 The method shown may include the following S201-S202.

[0282] S201: Obtain a delay jitter value of target data passing through a first submodule in a first module, wherein the first submodule includes a submodule with a delay jitter having a fixed value, and the target data is data sent by the first module, or the target data is data received by the first module, wherein the delay jitter value is a preset fixed value.

[0283] Regarding the target data, the above Figure 2 The description of the target data in the method shown is not repeated here.

[0284] In an embodiment of the present application, there is a fixed value of delay jitter in the first submodule. As can be seen from the previous description of the inner code FEC function, the implementation of the inner code FEC function includes: the addition or deletion of the check sequence, data interleaving or deinterleaving, and the addition or deletion of the padding sequence will all cause delay jitter. For the transmitting end, the delay jitter introduced by the addition of the check sequence, data interleaving, and the addition of the padding sequence is the aforementioned fixed value. For the receiving end, the delay jitter introduced by the deletion of the check sequence, data deinterleaving, and the deletion of the padding sequence is also the aforementioned fixed value.

[0285] Therefore, in one example, the first submodule may include: a submodule for delay jitter caused by adding or deleting a check sequence, a submodule for delay jitter caused by adding or deleting a padding sequence, and a submodule for delay jitter caused by interleaving or deinterleaving a data stream. Alternatively, the first submodule may also include a cyclic shift submodule.

[0286] As a specific example, for the transmitting end, the first submodule may include: a submodule for delay jitter caused by the addition of a check sequence, a submodule for delay jitter caused by the addition of a filling sequence, and a submodule for delay jitter caused by the interleaving of data streams. Correspondingly, for the receiving end, the first submodule may include: a submodule for delay jitter caused by the deletion of a check sequence, a submodule for delay jitter caused by the deletion of a filling sequence, and a submodule for delay jitter caused by the deinterleaving of data streams.

[0287] In one example, the aforementioned submodule with delay jitter caused by the increase of the check sequence may be a submodule in the inner code FEC module that performs FEC inner code encoding; the aforementioned submodule with delay jitter caused by the increase of the filling sequence may be a submodule in the inner code FEC module that performs the filling sequence increase operation; the aforementioned submodule with delay jitter caused by the interleaving of the data stream may be a submodule in the inner code FEC module that performs data stream interleaving. In other words, the first submodule may include: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and filling sequence increase.

[0288] In another example, the aforementioned submodule with delay jitter caused by deletion of the check sequence may be a submodule in the inner code FEC module that performs FEC inner code decoding; the aforementioned submodule with delay jitter caused by deletion of the padding sequence may be a submodule in the inner code FEC module that performs padding sequence deletion; the aforementioned submodule with delay jitter caused by deinterleaving of the data stream may be a submodule in the inner code FEC module that performs data stream deinterleaving. In other words, the first submodule may include: a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence deletion.

[0289] In another example, the aforementioned first submodule may be a cyclic shift submodule. The cyclic shift submodule is used to perform a cyclic shift operation. As an example, the transmitting end may also perform a cyclic shift operation before performing encoding processing (e.g., inner code FEC processing), and correspondingly, the receiving end may also perform a cyclic shift operation after performing decoding processing. As another example, the transmitting end may also perform a cyclic shift operation after performing a BCH encoding operation and before performing a pilot insertion. Correspondingly, the receiving end may also perform a cyclic shift operation after performing a pilot deletion and before performing a BCH decoding operation.

[0290] In one example, if the shift direction corresponding to the cyclic shift operation performed by the receiving end is the same as the shift direction corresponding to the cyclic shift operation performed by the transmitting end, the first submodule may include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the delay jitter value introduced by the cyclic shift submodule may be 4.5 nanoseconds.

[0291] In an embodiment of the present application, the delay jitter value may be a preset fixed value. For example, when the first module is an optical module, the delay jitter value may include the sum of a first jitter value and a second jitter value, and the first jitter value may be a delay jitter value introduced by adding or deleting a check sequence and interleaving or deinterleaving a data stream. The second jitter value may be a delay jitter value introduced by adding or deleting a pad. The fixed value may be, for example, a value between 4.6ns and 4.8ns. As a specific example, according to the above description of Figure 1e , Figure 1f as well as Figure 1g From the description, it can be seen that the delay jitter value introduced by adding or deleting the check sequence and interleaving or deinterleaving the data stream is 0.28125ns, and the delay jitter value introduced by adding or deleting the pad is 4.5ns. Therefore, the delay jitter value can be 4.78125ns. In the case where the first submodule also includes a cyclic shift submodule, the aforementioned delay jitter value can be based on the sum of the aforementioned first jitter value and the second jitter value, plus the delay jitter 4.5ns introduced by the cyclic shift submodule. In other words, the aforementioned delay jitter value can be between (4.5ns+4.6ns=9.1ns) and (4.5ns+4.8ns=9.3ns).

[0292] In some examples, the delay jitter value may also be referred to as a delay variation value (variation).

[0293] S202: Report delay information to the second module according to the delay jitter value.

[0294] After determining the delay jitter value, the delay information may be reported to the second module according to the delay jitter value.

[0295] Regarding the second module, the description of the second module in the above embodiments may be referred to and will not be repeated here.

[0296] In an example, the first module may report the delay jitter value to the second module.

[0297] In another example, the first module may also determine a first delay of the target data passing through a second submodule in the first module. In an embodiment of the present application, the second submodule may be a submodule that hardly introduces delay jitter. The submodule that hardly introduces delay jitter mentioned here may also be understood as a submodule that introduces less delay jitter. In a specific example, the second submodule may be a submodule in the first module other than the first submodule.

[0298] In one example, if the first module corresponds to the transmitting end, the second submodule may be, for example, a submodule in the inner code FEC module that performs operations such as convolution interleaving, distribution, and modulation coding. The modulation coding mentioned here may be, for example, PAM4 coding. If the first module corresponds to the receiving end, the second submodule may be, for example, a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations. The modulation coding mentioned here may be, for example, PAM4 decoding. In an embodiment of the present application, there may be multiple implementation methods for determining the first delay. Two possible implementation methods are described below.

[0299] In an example, the first module may acquire a preset first delay, where the first delay may be a value determined by the first module during a design phase, and the value of the first delay is related to the performance of the first module.

[0300] In another example, the first module may be based on statistics of the first delay of the target data passing through the second submodule. Wherein, when specifically implementing the statistics of the first delay of the target data passing through the second submodule, the delay of at least one bit of the target data passing through the second submodule may be counted, thereby obtaining the first delay. For example, the target data may be sampled, and the delay of the sampled data passing through the second submodule may be counted. For another example, the delay of each bit of the target data passing through the second submodule may be counted, thereby obtaining the first delay.

[0301] For any bit of data, the delay of passing through the second submodule can be the difference between the moment when the second submodule sends the data and the moment when the second submodule receives the data, or it can be determined based on the position of the data in the cache, which is not specifically limited in the embodiments of the present application.

[0302] In a scenario where the first module determines the first delay, S202 may, in a specific implementation, report delay information to the second module according to the delay jitter value and the first delay.

[0303] As a specific example, the first module may determine the aforementioned delay jitter value and the first delay as the delay information, and report the determined delay information to the second module.

[0304] As another specific example, the first module may determine a target delay according to the delay jitter value and the first delay, and report the target delay as the aforementioned delay information to the second module.

[0305] The embodiment of the present application does not specifically limit the manner of determining the target delay according to the delay jitter value and the first delay, and the first module may calculate the delay jitter value and the first delay to obtain the target delay.

[0306] In one example, in order to make the data reported by the first module satisfy "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay", the first communication device determines the specific implementation method of determining the target delay based on the delay jitter value and the first delay, which may be related to the role of the first communication device.

[0307] In a specific example, if the first module corresponds to a communication device as a transmitting end, the first communication device may determine the sum of the delay jitter value and the first delay as the target delay. If the first communication device corresponds to a communication device as a receiving end, the first communication device may determine the difference obtained by subtracting the delay jitter value from the first delay as the target delay.

[0308] In one example, the first delay may include a delay.

[0309] In another example, considering that the existing IEEE 802.3cx Chapter 90 defines corresponding maximum delay registers and minimum delay registers for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Chapter 90 for the mechanism of reporting delay at the physical layer, the first delay may include two delays, which are the maximum delay of the target data passing through the second submodule and the minimum delay of the target data passing through the second submodule. In one example, the maximum delay is the same as the minimum delay. In another example, the maximum delay is greater than the minimum delay.

[0310] As mentioned above, the first delay may include a maximum delay and a minimum delay. In this case, the target delay determined according to the delay jitter value and the first delay may include a maximum target delay and a minimum target delay. Wherein:

[0311] The maximum target delay may be determined based on the maximum delay and the delay jitter value. Specifically, if the first module corresponds to a communication device as a transmitting end, the first communication device may determine the sum of the delay jitter value and the maximum delay as the maximum target delay, and determine the sum of the delay jitter value and the minimum delay as the minimum target delay. If the first communication device corresponds to a communication device as a receiving end, the first communication device may determine the difference obtained by subtracting the delay jitter value from the maximum delay as the maximum target delay, and determine the difference obtained by subtracting the delay jitter value from the minimum delay as the minimum target delay.

[0312] Next, a method in which the first module reports the maximum target delay and the minimum target delay to the second module is introduced.

[0313] In one example, if the first module corresponds to a transmitting end, then:

[0314] As another specific example, a new register may be defined to report the maximum target delay and the minimum target delay to the second module. For example, a TX maximum delay register and a TX minimum delay register of the inner code FEC are defined, the TX maximum delay register is used to report the maximum target delay, and the TX minimum delay register is used to report the minimum target delay. In other words, the first module may use the TX maximum delay register of the inner code FEC to report the maximum target delay to the second module, and / or, use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0315] As another specific example, the first module may use the TX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module may use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0316] In one example, if the first module corresponds to a receiving end, then:

[0317] As another specific example, a new register may be defined to report the maximum target delay and the minimum target delay to the second module. For example, an RX maximum delay register and an RX minimum delay register of the inner code FEC are defined, the RX maximum delay register is used to report the maximum target delay, and the RX minimum delay register is used to report the minimum target delay. In other words, the first module may use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module, and / or, use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0318] As another specific example, the first module may use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module may use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0319] In one example, the first module further includes a third submodule, and the first module can also determine a second delay of the target data passing through the third submodule in the first module. The third submodule mentioned here can be another submodule in the first module that is different from the first submodule and the second submodule. For example, the third submodule can include a PMA submodule and a PMD submodule.

[0320] The implementation principle of the first module determining the second delay of the target data passing through the third submodule is the same as the implementation principle of the first module determining the first delay of the target data passing through the second submodule. Therefore, for the specific implementation of "the first module determining the second delay of the target data passing through the third submodule", please refer to the description part of the first module determining the first delay in the previous text, and no repeated description will be made here.

[0321] In a scenario where the first module determines the second delay, S202 may, in specific implementation, report delay information to the second module according to the delay jitter value and the second delay.

[0322] As a specific example, the first module may determine the aforementioned delay jitter value and the second delay as the delay information, and report the determined delay information to the second module.

[0323] As another specific example, the first module may calculate the delay jitter value and the second delay, and report the calculation result to the second module as the delay information. In a specific example, if the first module corresponds to a communication device as a transmitting end, the first communication device may determine the sum of the delay jitter value and the second delay as the delay information. If the first communication device corresponds to a communication device as a receiving end, the first communication device may determine the difference obtained by subtracting the delay jitter value from the second delay as the delay information.

[0324] In this scenario, the first communication device can use the relevant registers of PMA / PMD to report the delay information to the second module. As an example, the second delay can also include a maximum delay and a minimum delay, and accordingly, the delay information can include a maximum delay value obtained based on the delay jitter value and the maximum delay of the second delay, and a minimum delay value obtained based on the delay jitter value and the minimum delay of the second delay. Further, the first communication device can use the relevant registers of PMA / PMD to report the maximum delay and the minimum delay to the second module.

[0325] Specifically, if the first module corresponds to the transmitting end, that is, the target data is the data sent by the first module, then the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with an inner code FEC function (such as an optical module), the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0326] If the first module corresponds to the receiving end, that is, the target data is the data received by the first module, then the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with an inner code FEC function (such as an optical module), the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0327] The above introduces the delay reporting method provided in the embodiment of the present application. Next, the solution provided in the embodiment of the present application is introduced in combination with specific scenarios.

[0328] Embodiment 2: Figure 4 The specific implementation of the delay reporting method shown.

[0329] In this scenario, the first module may be an optical module of a communication device, and the optical module includes the PMA 102 , an inner code FEC, and a PMD.

[0330] For this case, the operation performed by the inner code FEC can be as follows: Figure 5 As shown, Figure 5 A schematic diagram of an inner code FEC processing process provided in an embodiment of the present application. Figure 5 As shown:

[0331] For the transmitting end, its inner code FEC can perform the following operations: convolution interleaving, distribution, inner code FEC processing, interleaving, pad addition and other processing, and the other processing mentioned here may include PAM4 encoding, for example. Among them, the inner code FEC processing may be, for example, performing a check sequence addition operation. The submodule that performs check sequence addition, interleaving and pad addition is the first submodule, and the submodule that performs convolution interleaving, distribution and other processing is the second submodule.

[0332] For the receiving end, the operation performed by its inner code FEC is the inverse operation of the operation performed by the inner code FEC of the transmitting end. For example, the inner code FEC of the receiving end can perform the following operations: other processing (such as PAM4 decoding), pad deletion, deinterleaving, inner code FEC processing, multiplexing, and inverse convolution deinterleaving. Among them, the inner code FEC processing can be, for example, performing a check sequence deletion operation. The submodule that performs check sequence deletion, deinterleaving, and pad deletion is the first submodule, and the submodule that performs inverse convolution deinterleaving, merging, and other processing is the second submodule.

[0333] For a communication device as a transmitter, its optical module can perform the following operations:

[0334] S4: Obtain the delay jitter value of 4.78125.

[0335] S5: Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax1 and a minimum delay Xmin1.

[0336] S6: Report the maximum target delay Xmax1+4.78125 and the minimum target delay Xmin1+4.78125 to the MAC layer module.

[0337] In an example, Xmax1+4.78125 may be reported to the MAC layer module via the TX maximum delay register of the inner code FEC, and Xmin1+4.78125 may be reported to the MAC layer module via the TX minimum delay register of the inner code FEC.

[0338] In yet another example, Xmax1+4.78125 may be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and Xmin1+4.78125 may be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0339] For a communication device as a receiving end, its optical module can perform the following operations:

[0340] S4': obtains the delay jitter value of 4.78125.

[0341] S5': Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax2 and a minimum delay Xmin2.

[0342] S6': Report the maximum target delay Xmax2-4.78125 and the minimum target delay Xmin2-4.78125 to the MAC layer module.

[0343] In one example, Xmax2-4.78125 can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and Xmin2-4.78125 can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0344] In yet another example, Xmax2-4.78125 may be reported to the MAC layer module via the RX maximum delay register of the PMA / PMD, and Xmin2-4.78125 may be reported to the MAC layer module via the RX minimum delay register of the PMA / PMD.

[0345] It should be noted that Figure 5 The inner code FEC processing process shown in this solution is only for the convenience of understanding. In addition to the inner code FEC processing process, Figure 5 In addition to the content shown, other content may also be included. For example, after the transmitting end performs the distribution operation and before the inner code FEC processing, the transmitting end may also perform the cyclic shift operation. Correspondingly, after the receiving end performs the inner code FEC processing and before the multiplexing operation, the receiving end may also perform the cyclic shift operation. For this case:

[0346] For a communication device as a transmitter, its optical module can perform the following operations:

[0347] S7: Obtain the delay jitter value 4.78125+4.5=9.28125.

[0348] S8: Determine a first delay of target data passing through the second submodule in the first module, where the first delay includes a maximum delay Xmax3 and a minimum delay Xmin3.

[0349] S9: Report the maximum target delay Xmax3+9.28125 and the minimum target delay Xmin3+9.28125 to the MAC layer module.

[0350] In one example, the TX maximum delay register of the inner code FEC can report Xmax3 + 9.28125 to the MAC layer module, and the TX minimum delay register of the inner code FEC can report Xmin3 + 9.28125 to the MAC layer module.

[0351] In another example, the TX maximum delay register of the PMA / PMD can report Xmin3 + 9.28125 to the MAC layer module, and the TX minimum delay register of the PMA / PMD can report Xmin3 + 9.28125 to the MAC layer module.

[0352] For a communication device acting as a receiving end, its optical module can perform the following operations:

[0353] S7’: Obtain the delay jitter value 9.28125.

[0354] S8’: Determine the first delay of the target data passing through the second sub-module in the first module, where the first delay includes the maximum delay Xmax4 and the minimum delay Xmin4.

[0355] S9’: Report the maximum target delay Xmax4 - 9.28125 and the minimum target delay Xmin4 - 9.28125 to the MAC layer module.

[0356] In one example, the TX maximum delay register of the inner code FEC can report Xmax4 - 9.28125 to the MAC layer module, and the TX minimum delay register of the inner code FEC can report Xmin4 - 9.28125 to the MAC layer module.

[0357] In another example, the TX maximum delay register of the PMA / PMD can report Xmin4 - 9.28125 to the MAC layer module, and the TX minimum delay register of the PMA / PMD can report Xmin4 - 9.28125 to the MAC layer module.

[0358] Based on the delay reporting method provided in the above embodiments, the embodiments of the present application also provide a corresponding device. The following introduces the device with reference to the drawings.

[0359] See Figure 6 , which is a schematic structural diagram of a delay reporting device provided by an embodiment of the present application. Figure 6 The shown delay reporting device can be used to execute the Figure 2 shown delay reporting method.

[0360] As Figure 6 shown, the delay reporting device 600 includes: a sending unit 601.

[0361] The sending unit 601 is used to report the target delay corresponding to data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a filling sequence in the data stream.

[0362] In one possible implementation, the period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

[0363] In a possible implementation manner, the data block includes 128 bits, 120 bits, or 4 bits.

[0364] In a possible implementation, the period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

[0365] In a possible implementation manner, the specific position is a starting position of the FEC codeword, and the starting position is the first bit or the first symbol or the first byte of the FEC codeword.

[0366] In a possible implementation manner, the FEC codeword includes: an FEC inner codeword.

[0367] In a possible implementation manner, the data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

[0368] In a possible implementation manner, a period for inserting a filling sequence into the data stream is an integer multiple of a period for inserting a check sequence into the data stream.

[0369] In a possible implementation manner, the target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

[0370] In a possible implementation manner, the apparatus further includes: a processing unit 602.

[0371] The processing unit 602 is used to measure the first delay corresponding to the data at each specific position among the data at the multiple specific positions to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0372] In a possible implementation, the sending unit 601 is used to: use the TX maximum delay register of the inner code FEC to report the maximum value; and / or use the TX minimum delay register of the inner code FEC to report the minimum value.

[0373] In a possible implementation, the sending unit 602 is used to: use the TX maximum delay register of the physical medium attachment PMA / physical medium related PMD to report the maximum value; and / or use the TX minimum delay register of the PMA / PMD to report the minimum value.

[0374] In a possible implementation, the sending unit 603 is configured to: report the maximum value using the RX maximum delay register of the inner code FEC; and / or report the minimum value using the RX minimum delay register of the inner code FEC.

[0375] In a possible implementation, the sending unit 604 is configured to: report the maximum value by using the RX maximum delay register of the PMA / PMD; and / or report the minimum value by using the RX minimum delay register of the PMA / PMD.

[0376] In a possible implementation, the sending unit 605 is configured to report the target delay corresponding to the data at the multiple specific positions in the data stream to a media access control MAC layer.

[0377] In a possible implementation manner, the device is applied to an optical module or a physical PHY layer chip.

[0378] In a possible implementation manner, the optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

[0379] In a possible implementation manner, the specific position is the starting position of the next data block after the filling sequence is inserted into the data stream, and the starting position is the first bit or the first symbol or the first byte of the next data block.

[0380] See also Figure 7 , this figure is a structural schematic diagram of another delay reporting device provided in an embodiment of the present application. Figure 7 The delay reporting device shown can be used to execute the method provided in the above method embodiment. Figure 4 The latency reporting method shown.

[0381] like Figure 7 As shown, the delay reporting device 700 includes: a processing unit 701 and a sending unit 702.

[0382] The processing unit 701 is used to obtain a delay jitter value of target data passing through a first submodule in the first module, where the first submodule includes a submodule with a delay jitter having a fixed value, and the target data is data sent by the first module, or the target data is data received by the first module, wherein the delay jitter value is the preset fixed value;

[0383] The sending unit 702 is configured to report the delay information to the second module according to the delay jitter value.

[0384] In a possible implementation, the processing unit 701 is further used to determine a first delay of the target data passing through a second submodule in the first module; and the sending unit 702 is used to report the delay information to the second module based on the delay jitter value and the first delay.

[0385] In a possible implementation, the sending unit 702 is configured to report to the second module a target delay obtained according to the delay jitter value and the first delay.

[0386] In a possible implementation manner, the target delay includes: the sum of the delay jitter value and the first delay; or a difference obtained by subtracting the delay jitter value from the first delay.

[0387] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained according to the maximum delay and the delay jitter value, and the minimum target delay obtained according to the minimum delay and the delay jitter value.

[0388] In one possible implementation, if the target data is data sent by the first module, the sending unit 702 is used to: use the TX maximum delay register of the inner code forward error correction FEC to report the maximum target delay to the second module; use the TX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0389] In one possible implementation, if the target data is data sent by the first module, the sending unit 702 is used to: use the TX maximum delay register of the physical medium attached PMA / physical medium related PMD to report the maximum target delay to the second module; use the TX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0390] In one possible implementation, if the target data is data received by the first module, the sending unit 702 is used to: use the RX maximum delay register of the inner code FEC to report the maximum target delay to the second module; use the RX minimum delay register of the inner code FEC to report the minimum target delay to the second module.

[0391] In a possible implementation, if the target data is data received by the first module, the sending unit 702 is used to: use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module; use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0392] In a possible implementation manner, the second submodule includes: a submodule other than the first submodule.

[0393] In a possible implementation, the second submodule includes: a submodule in the inner code FEC module that performs convolution interleaving, distribution, and modulation coding operations; or a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

[0394] In a possible implementation manner, the processing unit 701 is used to: obtain the preset first delay.

[0395] In a possible implementation, the processing unit 701 is configured to: count a first time delay of the target data passing through the second submodule.

[0396] In a possible implementation, the counting of a first delay of the target data passing through the second submodule includes: counting a delay of at least one bit of the target data passing through the second submodule to obtain the first delay.

[0397] In a possible implementation, the processing unit 701 is further used to determine the second delay of the target data passing through the third submodule in the first module; the sending unit 702 is used to report the delay information to the second module based on the delay jitter value and the second delay.

[0398] In a possible implementation manner, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0399] In a possible implementation, the second module includes: a media access control MAC layer module.

[0400] In a possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0401] In a possible implementation manner, the first submodule includes: a cyclic shift submodule.

[0402] In a possible implementation, the first submodule includes a submodule having delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence.

[0403] In a possible implementation manner, the first submodule includes a submodule having delay jitter caused by interleaving or deinterleaving of data streams.

[0404] In one possible implementation, the first submodule includes: a submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence adding operations; or a submodule in the inner code FEC module that performs FEC inner code decoding, data stream deinterleaving, and padding sequence removing operations.

[0405] In a possible implementation, the target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

[0406] In a possible implementation manner, the data block includes 128 bits or 120 bits.

[0407] In a possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0408] See also Figure 8 , which is a structural schematic diagram of a device provided in an embodiment of the present application. Figure 8 The device 800 shown includes an interface circuit 801 and a processing circuit 802. The interface circuit 801 is used to receive and / or send data, and the processing circuit 802 is used to process data.

[0409] In an example, the device 800 can be used to perform the above method embodiments provided by Figure 2 Corresponding delay reporting method. For this case:

[0410] The interface circuit 801 is used to report the target delay corresponding to data at multiple specific positions in the data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream; in an example, the processing circuit 802 is used to measure the first delay corresponding to the data at each specific position in the data at the multiple specific positions to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value among the multiple first delays.

[0411] In another example, the device 800 can be used to perform the above method embodiment provided with Figure 4 The corresponding delay reporting method for this situation is:

[0412] The processing circuit 802 is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule includes a submodule with a delay jitter with a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value; the interface circuit 801 is used to report the delay information to the second module according to the delay jitter value.

[0413] See also Fig. 9 , which is a structural schematic diagram of a device provided in an embodiment of the present application.

[0414] In one example, Fig. 9 The device 900 shown can be used to perform the above method embodiments. Figure 2 Corresponding delay reporting method.

[0415] In another example, Fig. 9 The device 900 shown can be used to perform the above method embodiments. Figure 4 Corresponding delay reporting method.

[0416] See also Fig. 9 As shown, the device 900 includes: a processor 910. The number of processors 910 in the device 900 can be one or more. Fig. 9 A processor is used as an example. The processor 910 is used to execute the above method embodiment. Figure 2 The corresponding delay reporting method, or the processor 910 is used to execute the above method embodiment provided with Figure 4 Corresponding delay reporting method.

[0417] The processor 910 may be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. The processor 910 may include a digital signal processor (DSP). The processor 910 may further include a hardware chip. The hardware chip may be an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0418] In one example, the device 900 further includes a memory 930. The memory 930 may include a volatile memory (English: volatile memory), such as a random-access memory (RAM); the memory 930 may also include a non-volatile memory (English: non-volatile memory), such as a flash memory (English: flash memory), a hard disk drive (HDD) or a solid-state drive (SSD); the memory 930 may also include a combination of the above types of memory. When the device 900 is used to execute the above method embodiments provided with Figure 2 When the corresponding delay reporting method is used, the memory 930 may store the aforementioned target delay, for example, and when the device is used to execute the above method embodiment provided with Figure 4 Corresponding to the delay reporting method, the memory may store the aforementioned fixed value, for example.

[0419] Optionally, the memory 930 stores an operating system and a program, an executable module or a data structure, or a subset thereof, or an extended set thereof, wherein the program may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 910 may read the program in the memory 930 to implement the method provided in the embodiment of the present application.

[0420] In one example, the device 900 further includes a communication interface 920. In the embodiment of the present application, the processor 910, the communication interface 920 and the memory 930 may be connected via a bus system or other means, wherein: Fig. 9The connection via bus system 940 is taken as an example.

[0421] The communication interface 920 is used to receive and / or send data. For example, when the device 900 is used to perform the above method embodiment provided with Figure 2 When the device 900 is used to perform the delay reporting method provided in the above method embodiment, the communication interface 910 is used to report the target delay corresponding to the data at multiple specific positions in the data stream. Figure 4 In the corresponding delay reporting method, the communication interface 910 is used to report the delay information to the second module according to the delay jitter value.

[0422] The bus system 940 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus system 940 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0423] The present application also provides a chip or an optical module. The structure of the chip or the optical module can be as follows: Fig.10 See Fig.10 , which is a schematic diagram of the structure of a chip or optical module provided in an embodiment of the present application. Fig.10 The chip or optical module 1000 shown includes an interface circuit 1001 and a processing circuit 1002. The interface circuit 1001 is used to receive and / or send data, and the processing circuit 1002 is used to process data.

[0424] In an example, the chip or optical module 1000 can be used to perform the above method embodiments. Figure 2 The corresponding delay reporting method. For this situation:

[0425] The interface circuit 1001 is used to report the target delay corresponding to the data at multiple specific positions in the data stream, the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a padding sequence in the data stream. As an example, the processing circuit 1002 is used to measure the first delay corresponding to the data at each specific position in the data at the multiple specific positions to obtain multiple first delays; wherein the target delay includes the maximum value and / or minimum value of the multiple first delays.

[0426] In another example, the chip or optical module 1000 can be used to perform the above method embodiments. Figure 4 Corresponding delay reporting method. For this case:

[0427] The processing circuit 1002 is used to obtain the delay jitter value of the target data passing through the first submodule in the first module, the first submodule includes a submodule with a delay jitter of a fixed value, the target data is the data sent by the first module, or the target data is the data received by the first module, wherein the delay jitter value is the preset fixed value. The interface circuit 1001 is used to report the delay information to the second module according to the delay jitter value.

[0428] The present application embodiment provides a computer-readable storage medium, including instructions or computer programs, which, when executed on a computer, enable the computer to execute the method described in the above method embodiment. Figure 2 Corresponding delay reporting method; For example, the computer executes the above method embodiment provided with Figure 4 Corresponding delay reporting method.

[0429] The present application embodiment provides a computer program product including instructions or computer programs, which, when executed on a computer, enables the computer to execute the method described in the above method embodiment. Figure 2 Corresponding delay reporting method; For example, the computer executes the above method embodiment provided with Figure 4 Corresponding delay reporting method.

[0430] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0431] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0432] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical business division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0433] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0434] In addition, each business unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software business units.

[0435] If the integrated unit is implemented in the form of a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0436] Those skilled in the art will appreciate that in one or more of the above examples, the services described in the present invention may be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, the services may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media may be any available media that can be accessed by a general-purpose or special-purpose computer.

[0437] The above specific implementation modes further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation modes of the present invention.

[0438] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A delay reporting method, characterized in that: The method comprises: Report target delays corresponding to data at multiple specific positions in a data stream, where the multiple specific positions are spaced at fixed lengths, and a period of the multiple specific positions corresponds to a period of inserting a padding sequence in the data stream.

2. The method according to claim 1, characterized in that The period of the multiple specific positions is an integer multiple of 8712 data blocks, or the period of the multiple specific positions is an integer multiple of 8704 data blocks, or the period of the multiple specific positions is an integer multiple of 64 data blocks, or the period of the multiple specific positions is an integer multiple of 65 data blocks.

3. The method according to claim 2, characterized in that The data block includes 128 bits, 120 bits, or 4 bits.

4. The method according to claim 1, characterized in that The period of the multiple specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits, or 1044480 bits, or 1045440 bits.

5. The method according to any one of claims 1 to 4, characterized in that: The specific position is the starting position of the FEC codeword, and the starting position is the first bit, the first symbol, or the first byte of the FEC codeword.

6. The method according to claim 4 or 5, characterized in that: The FEC codeword includes: an FEC inner codeword.

7. The method according to any one of claims 1 to 6, characterized in that: The data stream is a data stream obtained by FEC inner code encoding, or the data stream is a data stream obtained by FEC inner code decoding.

8. The method according to any one of claims 1 to 7, characterized in that: The period of inserting the filling sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream.

9. The method according to any one of claims 1 to 8, characterized in that: The target delay corresponds to the delay of the data passing through the optical module, or the target delay corresponds to the delay of the data passing through the inner code FEC layer in the optical module.

10. The method according to any one of claims 1 to 9, characterized in that: The method further comprises: Measuring a first time delay corresponding to data at each specific location among the data at the multiple specific locations to obtain multiple first time delays; The target delay includes a maximum value and / or a minimum value among the multiple first delays.

11. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in a data stream, including: Using the TX maximum delay register of the inner code FEC, reporting the maximum value; and / or, Using the TX minimum delay register for inner code FEC, the minimum value is reported.

12. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in a data stream, including: using the TX Maximum Latency Register of the Physical Medium Attachment PMA / Physical Medium Dependent PMD to report the maximum value; and / or, The minimum value is reported using the TX minimum latency register of the PMA / PMD.

13. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in a data stream, including: Utilizing the RX maximum delay register of the inner code FEC to report the maximum value; and / or, Using the RX minimum delay register for inner code FEC, the minimum value is reported.

14. The method according to claim 10, characterized in that Reports the target latency for data at multiple specific locations in a data stream, including: Utilizing the RX maximum latency register of the PMA / PMD to report the maximum value; and / or, The minimum value is reported using the RX minimum latency register of the PMA / PMD.

15. The method according to any one of claims 1 to 14, characterized in that: Reports the target latency for data at multiple specific locations in a data stream, including: The target delay corresponding to the data at the multiple specific positions in the data stream is reported to the media access control MAC layer.

16. The method according to any one of claims 1 to 15, characterized in that: The method is applied to an optical module or a physical PHY layer chip.

17. The method according to claim 16, characterized in that The optical module includes an inner code FEC module, and the inner code FEC module includes an inner code FEC encoding module and / or an inner code FEC decoding module.

18. The method according to any one of claims 1 to 17, characterized in that: The specific position is the starting position of the next data block after the filling sequence is inserted into the data stream, and the starting position is the first bit or the first symbol or the first byte of the data block.

19. A delay reporting method, characterized in that: Applied to the first module, the method comprises: Obtaining a delay jitter value of target data passing through a first submodule in the first module, wherein the first submodule includes a submodule with a delay jitter having a fixed value, the target data is data sent by the first module, or the target data is data received by the first module, wherein the delay jitter value is a preset fixed value; Report the delay information to the second module according to the delay jitter value.

20. The method according to claim 19, characterized in that The method further comprises: Determine a first time delay of the target data passing through the second submodule in the first module; The reporting the delay information to the second module according to the delay jitter value includes: Report the delay information to the second module according to the delay jitter value and the first delay.

21. The method according to claim 20, characterized in that The reporting the delay information to the second module according to the delay jitter value and the first delay includes: Report a target delay obtained according to the delay jitter value and the first delay to the second module.

22. The method according to claim 21, characterized in that The target delay includes: the sum of the delay jitter value and the first delay; or, The difference obtained by subtracting the delay jitter value from the first delay.

23. The method according to claim 21 or 22, characterized in that The first delay includes: The maximum delay and the minimum delay of the target data passing through the second submodule; Accordingly, the target delay includes: A maximum target delay is obtained according to the maximum delay and the delay jitter value, and a minimum target delay is obtained according to the minimum delay and the delay jitter value.

24. The method according to claim 23, characterized in that If the target data is data sent by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Using the TX maximum delay register of the inner code forward error correction FEC, the maximum target delay is reported to the second module; The minimum target delay is reported to the second module using the TX minimum delay register of the inner code FEC.

25. The method according to claim 23, characterized in that If the target data is data sent by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Reporting the maximum target delay to the second module using a TX maximum delay register of a physical medium attachment PMA / physical medium dependent PMD; The minimum target delay is reported to the second module using the TX minimum delay register of the PMA / PMD.

26. The method according to claim 23, characterized in that If the target data is data received by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Using the RX maximum delay register of the inner code FEC, reporting the maximum target delay to the second module; The minimum target delay is reported to the second module using the RX minimum delay register of the inner code FEC.

27. The method according to claim 23, characterized in that If the target data is data received by the first module, reporting a target delay obtained according to the delay jitter value and the first delay to the second module includes: Using the RX maximum delay register of the PMA / PMD, reporting the maximum target delay to the second module; The minimum target delay is reported to the second module using the RX minimum delay register of the PMA / PMD.

28. The method according to any one of claims 20 to 27, characterized in that: The second submodule includes: Submodules other than the first submodule.

29. The method according to any one of claims 20 to 27, characterized in that: The second submodule includes: A submodule in the inner code FEC module that performs convolution interleaving, distribution, and modulation coding operations; Alternatively, a submodule in the inner code FEC module that performs inverse convolution deinterleaving, multiplexing, and modulation decoding operations.

30. The method according to any one of claims 20 to 29, characterized in that: Determining a first time delay of the target data passing through the second submodule in the first module includes: The preset first time delay is obtained.

31. The method according to any one of claims 20 to 29, characterized in that: Determining a first time delay of the target data passing through the second submodule in the first module includes: A first time delay of the target data passing through the second submodule is counted.

32. The method according to claim 31, characterized in that The counting of a first time delay of the target data passing through the second submodule includes: The delay of at least one bit of the target data passing through the second submodule is counted to obtain the first delay.

33. The method according to claim 19, characterized in that The method further comprises: Determine a second time delay of the target data passing through a third submodule in the first module; The reporting the delay information to the second module according to the delay jitter value includes: Report the delay information to the second module according to the delay jitter value and the second delay.

34. The method according to claim 33, characterized in that The third submodule includes: a PMA submodule and / or a PMD submodule.

35. The method according to any one of claims 19 to 34, characterized in that: The second module includes: Media Access Control MAC layer module.

36. The method according to any one of claims 19 to 35, characterized in that: The fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed data is between 9.1 nanoseconds and 9.3 nanoseconds.

37. The method according to claims 19-36, characterized in that The first submodule includes a submodule for delay jitter caused by adding or deleting a check sequence, or adding or deleting a padding sequence.

38. The method according to claims 19-37, characterized in that The first submodule includes a submodule in which delay jitter is caused by interleaving or deinterleaving of data streams.

39. The method according to claims 19-38, characterized in that The first submodule includes: A submodule in the inner code FEC module that performs FEC inner code encoding, data stream interleaving, and padding sequence addition operations; Alternatively, a submodule in the inner code FEC module performs FEC inner code decoding, data stream deinterleaving, and padding sequence removal operations.

40. The method according to any one of claims 19 to 39, characterized in that: The first submodule includes: Circular shift submodule.

41. The method according to any one of claims 19 to 40, characterized in that: The target data includes 8712*N data blocks, or 8704*N data blocks, where N is a positive integer.

42. The method according to claim 41, characterized in that The data block includes 128 bits or 120 bits.

43. The method according to any one of claims 19 to 40, characterized in that: The target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440*N bits, where N is a positive integer.

44. A time delay reporting device, characterized in that: The device comprises: A sending unit is used to report a target delay corresponding to data at multiple specific positions in a data stream, where the multiple specific positions are spaced at fixed lengths, and the period of the multiple specific positions corresponds to the period of inserting a filling sequence in the data stream.

45. A time delay reporting device, characterized in that: Applied to the first module, the device comprises: A processing unit, configured to obtain a delay jitter value of target data passing through a first submodule in the first module, wherein the first submodule includes a submodule having a delay jitter with a fixed value, the target data is data sent by the first module, or the target data is data received by the first module, wherein the delay jitter value is a preset fixed value; The sending unit is used to report the delay information to the second module according to the delay jitter value.

46. ​​A time delay reporting device, characterized in that: The device is used to execute the method described in any one of claims 1 to 18, or the device is used to execute the method described in any one of claims 19 to 43.

47. A time delay reporting device, characterized in that: The device includes an interface circuit and a processing circuit; The interface circuit is used to perform the data sending and / or receiving operation in any one of the methods of claims 1 to 18, and the interface circuit is used to perform the data processing operation in any one of the methods of claims 1 to 18; or The interface circuit is used to perform the data sending and / or receiving operations in any one of the methods described in claims 19 to 43, and the interface circuit is used to perform the data processing operations in any one of the methods described in claims 19 to 43.

48. The device according to claim 47, wherein the device is: Optical module, or chip.

49. A device, characterized in that include: Processor and memory; The memory is used to store instructions or computer programs; The processor is used to execute the instructions or computer program to perform the method described in any one of claims 1-43.

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