A method and apparatus for reporting latency

Abstract

The embodiment of the present application provides a time delay reporting method, which can be applied to a first module. The first module can report target time delays corresponding to data at a plurality of specific positions in a data stream, the plurality of specific positions are spaced apart by a fixed length, and the period of the plurality of specific positions corresponds to the period of inserting a padding sequence in the data stream. In the embodiment of the present application, if the first module corresponds to a sending end, the target time delay corresponding to the data at the specific position is equivalent to a maximum time delay, and if the first module corresponds to a receiving end, the target time delay corresponding to the data at the specific position is equivalent to a minimum time delay. It can be seen that, by using the scheme, time delay information can be accurately reported.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410243239.5, filed on March 1, 2024, entitled "A Time Delay Reporting Method and Apparatus", and Chinese Patent Application No. 202410565627.5, filed on May 8, 2024, entitled "A Time Delay Reporting Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a delay reporting method and apparatus. Background Technology

[0003] Communication devices can exchange data. The sending end can send messages to the receiving end, adding a sending timestamp to the message. Similarly, after receiving a message, the receiving end can record its receiving timestamp for subsequent processing. For example, in a time synchronization scenario, the receiving end can perform time synchronization based on the sending and receiving timestamps. Here, the sending end can be understood as the communication device that sends the message, and the receiving end as the communication device that receives it.

[0004] The accuracy of the aforementioned sending and receiving timestamps directly affects the accuracy of the results obtained from subsequent processing measures. For example, in a time synchronization scenario, the accuracy of the sending and receiving timestamps directly affects the precision of time synchronization.

[0005] Therefore, how the sending end can accurately determine the sending timestamp of the message and how the receiving end can accurately determine the receiving timestamp of the message are problems that urgently need to be solved. Summary of the Invention

[0006] This application provides a latency reporting method and apparatus that can accurately report latency.

[0007] Firstly, this application provides a latency reporting method, which can be applied to a first module. The first module can report the target latency corresponding to data at multiple specific locations in a data stream, where the intervals between these multiple specific locations are fixed, and the period of each of these multiple specific locations corresponds to the period of a padding sequence inserted into the data stream. In this embodiment, if the first module corresponds to a transmitting end, the target latency corresponding to the data at that specific location is equivalent to the maximum latency; if the first module corresponds to a receiving end, the target latency corresponding to the data at that specific location is equivalent to the minimum latency. Therefore, using this solution, latency information can be accurately reported.

[0008] In one possible implementation, the period of the plurality of specific positions is an integer multiple of 8712 data blocks, or the period of the plurality of specific positions is an integer multiple of 8704 data blocks. Here, 8712 is the period corresponding to the insertion of the padding sequence in the data stream, and 8704 is the period corresponding to the insertion of the padding sequence in the data stream. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position corresponds to 8704; when the first module corresponds to the receiving end, the period of the specific position corresponds to 8712. The fact that the period of the specific position is an integer multiple of 8172 data blocks or an integer multiple of 8704 data blocks can be understood as the period corresponding to an integer multiple of the length of 8172 data blocks or an integer multiple of the length of 8704 data blocks. In one possible implementation, the data block includes 128 bits or 120 bits. For example, if the data block has undergone forward error correction (FEC) encoding, then the data block consists of 128 bits. If the data block has not yet undergone FEC encoding, or if the data block has undergone FEC decoding, then the data block consists of 120 bits. As a specific example, when the first module corresponds to the transmitting end, the data block consists of 120 bits; when the first module corresponds to the receiving end, the data block consists of 128 bits.

[0009] In one possible implementation, the period of the plurality of specific positions is an integer multiple of any of the following values: 8704 * 120 = 1,044,480 bits; or 8704 * 128 = 1,114,112 bits; or 8712 * 128 = 1,115,136 bits; or 8712 * 120 = 1,045,440 bits. Specifically, if the first module corresponds to the transmitting end, before the first module performs the padding and filler sequence addition operations on the data stream, the period of the specific positions is an integer multiple of 8704 * 120 = 1,044,480 bits; after the first module performs the padding operation on the data stream, the period of the specific positions is an integer multiple of 8704 * 128 = 1,114,112 bits; and after the first module further performs the padding operation on the data stream, the period of the specific positions is an integer multiple of 8712 * 128 = 1,115,136 bits. If the first module corresponds to the receiving end, then before the first module performs the check sequence deletion and padding sequence deletion operations on the data stream, the period of the specific position is an integer multiple of 8712*128=1115136 bits; after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*128=1114112 bits; and after the first module performs the check sequence deletion operation on the data stream, the period of the specific position is an integer multiple of 8704*120=1044480 bits.

[0010] In one possible implementation, the period of the plurality of specific positions can be an integer multiple of 64 data blocks or an integer multiple of 65 data blocks. Here, 65 represents the period after inserting the padding sequence into the data stream, and 64 represents the period before inserting the padding sequence. As a specific example, when the first module corresponds to the transmitting end, the period of the specific position is an integer multiple of 64 data blocks; when the first module corresponds to the receiving end, the period of the specific position is an integer multiple of 65 data blocks. The fact that the period of the specific position is an integer multiple of 64 or 65 data blocks can be understood as the period corresponding to an integer multiple of the length of 64 or 65 data blocks.

[0011] In one possible implementation, each of the aforementioned 64 and 65 data blocks may include 4 bits. In this scenario, the padding sequence insertion could be achieved by inserting a 4-bit pilot signal every 64 4-bit data blocks.

[0012] In one possible implementation, the specific position can be the starting position of a data block. The starting position of a data block can be the first byte, the first bit, or the first symbol. In a scenario where the data block consists of 128 bits, the data block mentioned here can be an FEC codeword.

[0013] In a specific example, the FEC codeword can be an FEC internal codeword. In other words, the aforementioned specific position can be the starting position of the FEC internal codeword.

[0014] In one possible implementation, the specific position is the starting position of the next data block after the insertion of the padding sequence in the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0015] In one possible implementation, the data stream is a data stream obtained through FEC encoding. Specifically, if the first module corresponds to the sending end, the first module can perform FEC encoding and padding operations on the data entering the first module. Accordingly, in one example, the data stream mentioned here can be the data stream after performing FEC encoding and padding operations. If the first module corresponds to the receiving end, in one example, the data stream can be the data stream sent by the sending end to the first module. In other words, the data stream is the data stream entering the first module, and this data stream has undergone FEC encoding and padding operations at the sending end. In another example, considering that after the sending end sends the data stream to the receiving end, the receiving end can perform FEC encoding decoding on the data stream, therefore, the data stream can also be the data stream obtained after the receiving end performs FEC encoding decoding on the received data stream. In other words, if the first module is a module corresponding to the receiving end, in another example, the data stream can be the data stream obtained after FEC encoding decoding.

[0016] In one possible implementation, the transmitting end can insert not only a padding sequence but also a parity sequence into the data stream. Specifically, when the transmitting end performs FEC internal code encoding on the data stream, it can insert an 8-bit parity sequence for every 128 bits of data. Since the transmitting end inserts a 1024-bit pad every 8704 FEC internal code blocks, the period of the padding sequence inserted into the data stream is an integer multiple of the period of the parity sequence. Because the period of the padding sequence is an integer multiple of the period of the parity sequence, the peaks of the large sawtooth wave overlap with the peaks of the small sawtooth wave, and the troughs of the large sawtooth wave overlap with the troughs of the small sawtooth wave. Therefore, the period at the aforementioned specific position can be determined based on the period of the padding sequence inserted into the data stream, thus determining the target delay.

[0017] In one possible implementation, the target latency is the latency of data from the aforementioned multiple specific locations passing through the first module. Alternatively, the target latency is the latency of data from the aforementioned multiple specific locations passing through the inner FEC layer in the first module. When the first module is an optical module, the target latency is the latency of data from the aforementioned multiple specific locations passing through the optical module. Alternatively, the target latency is the latency of data from the aforementioned multiple specific locations passing through the inner FEC layer in the optical module. Here, the inner FEC layer is the layer used to implement the inner FEC function.

[0018] In one possible implementation, each of the aforementioned data locations at multiple specific locations can correspond to a first delay. Therefore, the data at these multiple specific locations can correspond to multiple first delays. Considering that Section 90 of the Institute of Electrical and Electronics Engineers (IEEE) 802.3cx defines corresponding maximum and minimum delay registers for each layer of the physical layer, to ensure compatibility with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays, the maximum and / or minimum value among the multiple first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the multiple first delays. In this case, the first module can also measure the first delay corresponding to the data at each of the multiple specific locations to obtain multiple first delays, so as to report the maximum and / or minimum value of the multiple first delays, thereby realizing the reporting of delay information.

[0019] In one possible implementation, a new register can be defined to report the aforementioned maximum and / or minimum values ​​to the second module.

[0020] As a concrete example, the internal code FEC defines a maximum transport (TX) delay register and / or a minimum transport (TX) delay register. The maximum transport (TX) delay register is used by the module acting as the transmitting end to report the maximum value, and the minimum transport (TX) delay register is used by the module acting as the transmitting end to report the minimum value. In other words, when the first module corresponds to the transmitting end, the first module can use the maximum transport (TX) delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum transport (TX) delay register of the internal code FEC to report the minimum value to the second module.

[0021] As another concrete example, a maximum receive (RX) delay register and / or a minimum RX delay register are defined in the internal code FEC. The maximum RX delay register is used by the module acting as the receiving end to report the maximum value, and the minimum RX delay register is used by the module acting as the receiving end to report the minimum value. In other words, when the first module corresponds to the receiving end, the first module can use the maximum RX delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum RX delay register of the internal code FEC to report the minimum value to the second module.

[0022] In one possible implementation, the first module can use existing registers to report the aforementioned maximum and / or minimum values ​​to the second module. This approach allows for the reporting of the target delay using existing registers.

[0023] As a concrete example, if the first module corresponds to the transmitting end, then the first module can use the physical medium attachment (PMA) / physical media dependent (PMD) maximum TX delay register to report the maximum value to the second module. Similarly, the first module can use the PMA / PMD minimum TX delay register to report the minimum value to the second module.

[0024] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0025] In one possible implementation, the first module reports the target latency, specifically by reporting the target latency to a second module. In one example, the second module may be a media access control (MAC) layer module of the communication device. In this way, the MAC layer module can compensate its own recorded timestamps based on the target latency, thereby making the compensated timestamps more accurate.

[0026] In one possible implementation, the aforementioned first module can be an optical module or a physical (PHY) layer chip. This optical module or PHY layer chip can provide internal code FEC functionality.

[0027] In one possible implementation, the optical module includes an internal code FEC module for implementing internal code FEC functionality. The internal code FEC module includes an internal code FEC encoding module and / or an internal code FEC decoding module. The internal code FEC encoding module implements FEC internal code encoding functionality, and the internal code FEC decoding module implements FEC internal code decoding functionality.

[0028] Secondly, this application provides a latency reporting method. This method can be applied to a first module, which can obtain the latency jitter value of target data passing through a first sub-module within the first module. The target data is either data sent by the first module or data received by the first module. The first sub-module contains a sub-module with a fixed latency jitter value. Further, based on the latency jitter value, latency information is reported to a second module. In this embodiment, considering that the first sub-module introduces latency jitter, causing jitter in the latency of the target data passing through the first module, the first module reports latency information to the second module based on the latency jitter value introduced by the first sub-module, thereby making the reported latency information more accurate.

[0029] In one possible implementation, the first module can further determine a first delay in the target data passing through the second submodule within the first module. As an example, the second submodule could be a submodule that introduces almost no latency jitter. Accordingly, in a specific implementation, the first module can report latency information to the second module based on the latency jitter value and the first delay. In other words, the first module can report latency information to the second module based on the existence of latency jitter and the first delay in the target data passing through the second submodule, which introduces almost no latency jitter, thereby making the latency information reported by the first module to the second module more accurate.

[0030] In one possible implementation, the first module can determine the target delay based on the delay jitter value and the first delay, and report the target delay as the aforementioned delay information to the second module.

[0031] In one possible implementation, if the first module corresponds to a communication device acting as a transmitter, then the first communication device can determine the target delay as the sum of the delay jitter value and the first delay. If the first communication device corresponds to a communication device acting as a receiver, then the first communication device can determine the target delay as the difference between the first delay and the delay jitter value. Using this method, the target delay reported by the first module can satisfy the condition that "for the transmitter, its reported delay is equivalent to the maximum delay, and for the receiver, its reported delay is equivalent to the minimum delay."

[0032] In one possible implementation, considering that IEEE 802.3cx Section 90 defines corresponding maximum and minimum delay registers for each layer of the physical layer, the first delay can include two delays to ensure compatibility with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays. These delays are the maximum delay of the target data passing through the second submodule and the minimum delay of the target data passing through the second submodule. Accordingly, in this case, the target delay includes: a maximum target delay obtained based on the maximum delay and the delay jitter value, and a minimum target delay obtained based on the minimum delay and the delay jitter value.

[0033] In one possible implementation, a new register can be defined to report the aforementioned maximum target latency and / or minimum target latency to the second module.

[0034] As a concrete example, the FEC (Functional Encoding Code) defines a TX maximum delay register and / or a TX minimum delay register. The TX maximum delay register is used by the transmitting module to report the maximum target delay, and the TX minimum delay register is used by the transmitting module to report the minimum target delay. In other words, when the first module corresponds to the transmitting end, the first module can use the FEC's TX maximum delay register to report the maximum target delay to the second module, and use the FEC's TX minimum delay register to report the minimum target delay to the second module.

[0035] As another concrete example, the RX maximum delay register and / or RX minimum delay register of the internal code FEC are defined. The RX maximum delay register is used by the receiving module to report the maximum target delay, and the RX minimum delay register is used by the receiving module to report the minimum target delay. In other words, when the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the internal code FEC to report the maximum target delay to the second module, and use the RX minimum delay register of the internal code FEC to report the minimum target delay to the second module.

[0036] In one possible implementation, the first module can use existing registers to report the aforementioned maximum target delay and / or minimum target delay to the second module. This approach allows for the use of existing registers to report the target delay.

[0037] As a concrete example, if the first module corresponds to the transmitting end, then the first module can use the maximum TX delay register of the Physical Medium Attachment (PMA) / Physical Media Dependent (PMD) to report the maximum target delay to the second module. Similarly, the first module can use the minimum TX delay register of the PMA / PMD to report the minimum target delay to the second module.

[0038] As another specific example, if the first module corresponds to the receiving end, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0039] In one possible implementation, the second submodule may be a submodule in the first module other than the first submodule.

[0040] In one possible implementation, if the first module corresponds to the transmitting end, the second submodule may be, for example, a submodule in the internal code FEC module that performs operations such as convolutional interleaving, distribution, and modulation coding. If the first module corresponds to the receiving end, the second submodule may be, for example, a submodule in the internal code FEC module that performs deconvolutional deinterleaving, multiplexing, and modulation decoding operations.

[0041] In one possible implementation, determining the first delay of the target data passing through the second submodule in the first module can be achieved by obtaining a pre-set first delay. This first delay can be a value determined by the first module during the design phase, and its value is related to the performance of the first module.

[0042] In one possible implementation, the first delay of the target data passing through the second sub-module in the first module can be determined by statistically analyzing the delay of the target data passing through the second sub-module, thereby obtaining the first delay.

[0043] In one possible implementation, the delay of the target data passing through the second submodule can be statistically analyzed. Specifically, this can be achieved by calculating the delay of at least one bit of the target data passing through the second submodule to obtain the first delay. For example, the target data can be sampled, and the delay of the sampled data passing through the second submodule can be calculated. Alternatively, the delay of each bit of the target data passing through the second submodule can be statistically analyzed to obtain the first delay.

[0044] In one possible implementation, the first module further includes a third sub-module, and the first module can also determine a second delay in which the target data passes through the third sub-module. In a scenario where the first module determines the second delay, the first module reports the delay information to the second module. Specifically, in this implementation, the delay information can be reported to the second module based on the delay jitter value and the second delay, thereby accurately reporting the delay information to the second module.

[0045] In one possible implementation, the third submodule can be another submodule in the first module that is different from the aforementioned first and second submodules. For example, the third submodule may include a PMA submodule and a PMD submodule.

[0046] In one possible implementation, the second module includes a Media Access Control (MAC) layer module. In another possible implementation, the latency jitter value can be a preset fixed value. For example, when the first module is an optical module, the latency jitter value can include the sum of a first jitter value and a second jitter value. The first jitter value can be the latency jitter introduced by adding or deleting check sequences, or by data stream interleaving or deinterleaving. The second jitter value can be the latency jitter introduced by adding or deleting pads. The fixed value can be, for example, a value between 4.6 ns and 4.8 ns.

[0047] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to the addition or deletion of a check sequence or a padding sequence. As a specific example, for the transmitting end, the first submodule may include a submodule that experiences latency jitter due to the addition of a check sequence and a submodule that experiences latency jitter due to the addition of a padding sequence. Correspondingly, for the receiving end, the first submodule may include a submodule that experiences latency jitter due to the deletion of a check sequence and a submodule that experiences latency jitter due to the deletion of a padding sequence.

[0048] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to data stream interleaving or deinterleaving. As a specific example, for the transmitting end, the first submodule may include a submodule that experiences latency jitter due to data stream interleaving. Correspondingly, for the receiving end, the first submodule may include a submodule that experiences latency jitter due to data stream deinterleaving.

[0049] In one possible implementation, the aforementioned submodule causing delay jitter due to the increase of the parity sequence can be a submodule within the internal code FEC module that performs FEC internal code encoding; the aforementioned submodule causing delay jitter due to the increase of the padding sequence can be a submodule within the internal code FEC module that performs the padding sequence increment operation; the aforementioned submodule causing delay jitter due to data stream interleaving can be a submodule within the internal code FEC module that performs data stream interleaving. In other words, the first submodule can include: a submodule within the internal code FEC module that performs FEC internal code encoding, data stream interleaving, and padding sequence increment.

[0050] In one possible implementation, the submodule causing delay jitter due to the deletion of the parity sequence can be a submodule within the internal code FEC module that performs FEC code decoding; the submodule causing delay jitter due to the deletion of the padding sequence can be a submodule within the internal code FEC module that performs padding sequence deletion; and the submodule causing delay jitter due to data stream deinterleaving can be a submodule within the internal code FEC module that performs data stream deinterleaving. In other words, the first submodule can include: a submodule within the internal code FEC module that performs FEC code decoding, data stream deinterleaving, and padding sequence deletion.

[0051] In one possible implementation, both the sending and receiving ends can perform cyclic shift operations. In one example, if the shift direction of the cyclic shift operation performed by the receiving end is the same as the shift direction of the cyclic shift operation performed by the sending end, then the aforementioned first submodule can include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the latency jitter introduced by the cyclic shift submodule can be 4.5 nanoseconds.

[0052] In one possible implementation, where the first submodule further includes a cyclic shift submodule, the aforementioned delay jitter value can be the sum of the first and second jitter values, plus the 4.5ns delay jitter introduced by the cyclic shift submodule. Since the sum of the first and second jitter values ​​lies between 4.6ns and 4.8ns, the aforementioned delay jitter value can be between (4.5ns + 4.6ns = 9.1ns) and (4.5ns + 4.8ns = 9.3ns).

[0053] In one possible implementation, the target data may correspond to the data included in a period of a specific location as described in the first aspect above. For example, the target data may include 8712*N data blocks or 8704*N data blocks, where N is a positive integer.

[0054] In one possible implementation, the data block comprises 128 bits or 120 bits.

[0055] In one possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0056] Thirdly, embodiments of this application provide a latency reporting device, the device comprising: a sending unit, configured to report target latency corresponding to data at multiple specific locations in a data stream, wherein the multiple specific locations are spaced at fixed intervals, and the period of the multiple specific locations corresponds to the period of a padding sequence inserted in the data stream.

[0057] In one possible implementation, the period of the plurality of specific positions is an integer multiple of 8712 data blocks, or an integer multiple of 8704 data blocks, or an integer multiple of 64 data blocks, or an integer multiple of 65 data blocks.

[0058] In one possible implementation, the data block comprises 128 bits, 120 bits, or 4 bits.

[0059] In one possible implementation, the period of the plurality of specific positions is an integer multiple of any of the following values: 1,115,136 bits, 1,114,112 bits, or 1,044,480 bits, or 1,045,440 bits.

[0060] In one possible implementation, the specific position is the start position of the FEC codeword, which is the first bit, the first symbol, or the first byte of the FEC codeword.

[0061] In one possible implementation, the FEC codeword includes: FEC internal codeword.

[0062] In one possible implementation, the data stream is a data stream obtained by FEC internal code encoding, or the data stream is a data stream obtained by FEC internal code decoding.

[0063] In one possible implementation, the period for inserting the padding sequence into the data stream is an integer multiple of the period for inserting the check sequence into the data stream.

[0064] In one possible implementation, the target latency corresponds to the latency of the data passing through the optical module, or the target latency corresponds to the latency of the data passing through the internal code FEC layer in the optical module.

[0065] In one possible implementation, the apparatus further includes: a processing unit, configured to measure a first delay corresponding to the data at each of the plurality of specific locations, to obtain a plurality of first delays; wherein the target delay includes the maximum and / or minimum value among the plurality of first delays.

[0066] In one possible implementation, the transmitting unit is configured to: report the maximum value using the TX maximum delay register of the internal code FEC; and / or, report the minimum value using the TX minimum delay register of the internal code FEC.

[0067] In one possible implementation, the transmitting unit is configured to: report the maximum value using a TX maximum delay register of the PMA / Physical Media-Associated PMD attached to the physical medium; and / or, report the minimum value using a TX minimum delay register of the PMA / PMD.

[0068] In one possible implementation, the transmitting unit is configured to: report the maximum value using the RX maximum delay register of the internal code FEC; and / or, report the minimum value using the RX minimum delay register of the internal code FEC.

[0069] In one possible implementation, the transmitting unit is configured to: report the maximum value using the RX maximum delay register of the PMA / PMD; and / or, report the minimum value using the RX minimum delay register of the PMA / PMD.

[0070] In one possible implementation, the sending unit is configured to: report the target latency corresponding to the data at the plurality of specific locations in the data stream to the Media Access Control (MAC) layer.

[0071] In one possible implementation, the device is applied to an optical module or a physical PHY layer chip.

[0072] In one possible implementation, the optical module includes an internal code FEC module, which includes an internal code FEC encoding module and / or an internal code FEC decoding module.

[0073] In one possible implementation, the specific position is the starting position of the next data block after the insertion of the padding sequence in the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0074] Fourthly, this application provides a latency reporting device applied to a first module. The device includes: a processing unit, configured to acquire the latency jitter value of target data passing through a first sub-module in the first module, wherein the first sub-module includes a sub-module with a fixed latency jitter value, the target data being data sent by the first module or data received by the first module, wherein the latency jitter value is a preset fixed value; and a sending unit, configured to report latency information to a second module based on the latency jitter value.

[0075] In one possible implementation, the processing unit is further configured to: determine a first delay in the target data passing through the second sub-module in the first module; and the sending unit is configured to: report the delay information to the second module based on the delay jitter value and the first delay.

[0076] In one possible implementation, the sending unit is configured to: report to the second module the target delay obtained based on the delay jitter value and the first delay.

[0077] In one possible implementation, the target latency includes: the sum of the latency jitter value and the first latency; or, the difference between the first latency and the latency jitter value.

[0078] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained based on the maximum delay and the delay jitter value, and the minimum target delay obtained based on the minimum delay and the delay jitter value.

[0079] In one possible implementation, if the target data is data sent by the first module, the sending unit is configured to: report the maximum target delay to the second module using the TX maximum delay register of the internal code forward error correction (FEC); and report the minimum target delay to the second module using the TX minimum delay register of the internal code FEC.

[0080] In one possible implementation, if the target data is data sent by the first module, the sending unit is configured to: report the maximum target latency to the second module using the TX maximum latency register of the Physical Medium Attachment (PMA) / Physical Medium Dependent Device (PMD); and report the minimum target latency to the second module using the TX minimum latency register of the PMA / PMD.

[0081] In one possible implementation, if the target data is data received by the first module, the sending unit is configured to: report the maximum target delay to the second module using the RX maximum delay register of the internal code FEC; and report the minimum target delay to the second module using the RX minimum delay register of the internal code FEC.

[0082] In one possible implementation, if the target data is data received by the first module, the sending unit is configured to: report the maximum target delay to the second module using the RX maximum delay register of the PMA / PMD; and report the minimum target delay to the second module using the RX minimum delay register of the PMA / PMD.

[0083] In one possible implementation, the second submodule includes: submodules other than the first submodule.

[0084] In one possible implementation, the second submodule includes: a submodule in the internal code FEC module that performs convolutional interleaving, distribution, and modulation coding operations; or, a submodule in the internal code FEC module that performs deconvolutional deinterleaving, multiplexing, and modulation decoding operations.

[0085] In one possible implementation, the processing unit is configured to: obtain a pre-set first delay.

[0086] In one possible implementation, the processing unit is configured to: calculate the first delay of the target data after passing through the second submodule.

[0087] In one possible implementation, the step of calculating the delay of the target data through the second submodule includes: calculating the delay of at least one bit of the target data through the second submodule to obtain the first delay.

[0088] In one possible implementation, the processing unit is further configured to: determine a second delay in which the target data passes through the third submodule in the first module; and the sending unit is configured to: report the delay information to the second module based on the delay jitter value and the second delay.

[0089] In one possible implementation, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0090] In one possible implementation, the second module includes a Media Access Control (MAC) layer module.

[0091] In one possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0092] In one possible implementation, the first submodule includes a cyclic shift submodule.

[0093] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to the addition or deletion of a check sequence or a padding sequence.

[0094] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to the interleaving or deinterleaving of data streams.

[0095] In one possible implementation, the first submodule includes: a submodule in the internal code FEC module that performs FEC internal code encoding, data stream interleaving, and padding sequence addition operations; or, a submodule in the internal code FEC module that performs FEC internal code decoding, data stream deinterleaving, and padding sequence deletion operations.

[0096] In one possible implementation, the target data comprises 8712*N data blocks or 8704*N data blocks, where N is a positive integer.

[0097] In one possible implementation, the data block comprises 128 bits or 120 bits.

[0098] In one possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0099] Fifthly, embodiments of this application provide an apparatus. The apparatus includes a processor configured to execute the method described in the first aspect and any one of the first aspects above; or, the processor configured to execute the instructions or computer program stored in the memory to execute the method described in the second aspect and any one of the second aspects above.

[0100] In one possible implementation, the device further includes a memory for storing instructions or computer programs, and the processor for executing the instructions or computer programs in the memory to trigger the method described in the first aspect above and any one of the first aspects above; or, the processor is configured to execute the instructions or computer programs in the memory to perform the method described in the second aspect above and any one of the second aspects above.

[0101] In a sixth aspect, embodiments of this application provide a device including an interface circuit and a processing circuit, wherein the interface circuit is used to receive and / or transmit data, and the processing circuit is used to perform data processing.

[0102] In one example, the device can be used to perform the method described in any of the first aspects above, in which case:

[0103] The interface circuit is used to report the target delay corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream.

[0104] In one example, the processing circuit is used to measure the first delay corresponding to the data at each of the plurality of specific locations to obtain a plurality of first delays; wherein, the target delay includes the maximum and / or minimum value among the plurality of first delays.

[0105] In yet another example, the device can be used to perform the method described in any of the second aspects above, in which case:

[0106] The processing circuit is used to obtain the latency jitter value of the target data after passing through the first sub-module in the first module. The first sub-module includes a sub-module with a fixed latency jitter value. The target data is data sent by the first module or data received by the first module. The latency jitter value is a preset fixed value. The interface circuit is used to report latency information to the second module according to the latency jitter value.

[0107] In a seventh aspect, embodiments of this application provide a computer-readable storage medium, including instructions or a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or, when run on a computer, causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0108] Eighthly, embodiments of this application provide a computer program product comprising instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0109] Ninthly, embodiments of this application provide a chip, including an interface circuit and a processing circuit, the chip being used to execute the method described in the first aspect above and any one of the first aspects above; or, to execute the method described in the second aspect above and any one of the second aspects above.

[0110] In a tenth aspect, embodiments of this application provide an optical module, including an interface circuit and a processing circuit, wherein the optical module is used to perform the method described in the first aspect above and any one of the first aspects above; or, to perform the method described in the second aspect above and any one of the second aspects above. Attached Figure Description

[0111] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0112] Figure 1a This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0113] Figure 1b This is a schematic diagram of the structure of another communication device provided in the embodiments of this application;

[0114] Figure 1c A schematic diagram illustrating the delay introduced by an FEC function in an embodiment of this application;

[0115] Figure 1d This is a schematic diagram of the structure of another communication device provided in the embodiments of this application;

[0116] Figure 1e A schematic diagram illustrating the delay introduced by the internal code FEC function in an embodiment of this application;

[0117] Figure 1f A schematic diagram illustrating the delay introduced by another internal code FEC function provided in the embodiments of this application;

[0118] Figure 1g A schematic diagram illustrating the delay introduced by another internal code FEC function provided in the embodiments of this application;

[0119] Figure 1h A schematic diagram illustrating the delay introduced by the internal code FEC function in an embodiment of this application;

[0120] Figure 2 A flowchart illustrating a latency reporting method provided in an embodiment of this application;

[0121] Figure 3 This is a schematic diagram of the structure of a first module provided in an embodiment of this application;

[0122] Figure 4 A flowchart illustrating another delay reporting method provided in this application embodiment;

[0123] Figure 5 A schematic diagram illustrating the processing procedure of an internal code FEC provided in an embodiment of this application;

[0124] Figure 6 This is a schematic diagram of the structure of a delay reporting device provided in an embodiment of this application;

[0125] Figure 7 A schematic diagram of another delay reporting device provided in this application embodiment;

[0126] Figure 8 This is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0127] Figure 9 This is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0128] Figure 10 This is a schematic diagram of the structure of a chip or optical module provided in an embodiment of this application. Detailed Implementation

[0129] This application provides a latency reporting method and apparatus that can accurately report latency.

[0130] To make it easier to understand, we will first introduce the application scenarios of report latency.

[0131] In time synchronization scenarios, communication devices can synchronize their time by exchanging messages. The communication devices mentioned in this application embodiment can be network devices such as switches, routers, sliced ​​packet network (SPN) devices, or optical transmission network (OTN) devices. They can also be components of network devices, such as single boards, line cards, or interfaces, functional modules, chips, pluggable optical modules, servers, network cards on servers, or network cards of other devices. This application embodiment does not impose specific limitations. Communication devices can be directly connected, for example, but not limited to, via Ethernet cables or optical fibers.

[0132] The 1588 protocol is a high-precision time synchronization protocol. It provides time synchronization accuracy at the nanosecond (ns) level. Currently, the International Telecommunication Union (ITU-T) G.8273.2 defines four classes of time synchronization accuracy requirements: Class A, Class B, Class C, and Class D. Class A corresponds to a time accuracy of ±100 ns; Class B to ±70 ns; Class C to ±30 ns; and Class D to ±5 ns. Therefore, in one example, communication devices can synchronize their time by exchanging 1588 messages. The 1588 messages mentioned here can be understood as messages conforming to the 1588 protocol.

[0133] In the implementation of time synchronization between communication devices, the sending device can add a sending timestamp to the 1588 message, indicating the time of transmission. Similarly, the receiving device records the receiving timestamp, indicating the time of reception. Furthermore, the receiving device can perform time synchronization based on these sending and receiving timestamps. Since these timestamps are input parameters for time synchronization, their accuracy directly affects the precision of the synchronization. In other words, ensuring the accuracy of the sending and receiving timestamps is crucial.

[0134] Currently, communication devices record timestamps through their MAC layer. In a specific scenario, for communication devices that include an Ethernet interface, the MAC layer can record the timestamps.

[0135] Next, we will introduce how the communication device records timestamps, taking into account its structure.

[0136] See Figure 1a The figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application, including the structure of the transmitting end communication device and the structure of the receiving end communication device.

[0137] like Figure 1a As shown, both the communication device acting as a transmitter and the communication device acting as a receiver can include a MAC layer and a physical layer. The physical layer can include PCS, PMA, and PMD. In addition, it can also include an application layer, which can correspond to upper-layer services, for example.

[0138] As the sending end, its MAC layer can generate MAC frames and send them to the physical layer. For example, the MAC layer can receive data sent by upstream devices or upper-layer services, and encapsulate the data to form MAC frames. Alternatively, if the MAC layer does not receive data from upstream devices or upper-layer services, it will generate a corresponding MAC frame based on the idle bitstream.

[0139] The MAC layer at the sending end transmits the MAC frame to the physical layer at the sending end. The physical layer may include PCS, PMA, and PMD. The MAC layer at the sending end can record the timestamp of its transmission of the MAC frame to the physical layer as the aforementioned transmission timestamp.

[0140] The PCS can process the received data stream and send the processed data to the PMA. The data stream mentioned here can be a bit stream consisting of multiple bits, which can be obtained by processing MAC frames.

[0141] PMA can modulate data from PCS into a signal that the channel supports for transmission.

[0142] PMD stands for signal transmitter, used to transmit PMA-modulated signals through a transmission medium.

[0143] The physical layer of the receiving end receives the signal transmitted through the aforementioned transmission medium, processes the signal, and then passes it to the MAC layer of the receiving end. As mentioned above, the physical layer of the receiving end also includes PMD, PMA, and PCS.

[0144] The receiving end's PMD first receives the signal transmitted on the transmission medium. Then, the PMA demodulates the signal. The data obtained after PMA demodulation is passed to the PCS, which performs corresponding operations on the received data. The operations performed by the receiving end's PCS are the inverse operations performed by the sending end's PCS. Further, the PCS can send the processed data stream to the MAC layer. Thus, after receiving the data stream sent by the PCS, the receiving end's MAC layer can obtain the MAC frame sent by the sending end and further process the MAC frame, for example, parsing the MAC frame and sending it to upstream devices or upper-layer services. When the receiving end's MAC layer receives the data stream processed by the PCS, it can record the timestamp of receiving the data stream as a reception timestamp.

[0145] To support the high-precision time synchronization feature of 1588, the physical layer of the communication device can report the latency of the data stream passing through the physical layer to the MAC layer. This allows the MAC layer to compensate for the recorded timestamps based on the latency of the data stream passing through the physical layer, resulting in more accurate timestamps after compensation by the MAC layer. Specifically:

[0146] For the sending end, the MAC layer can add the aforementioned data stream's latency through the physical layer to its own recorded timestamp to obtain a transmission timestamp. It's easy to understand that this transmission timestamp can be considered the timestamp when the sending end's physical layer actually transmits the data stream.

[0147] For the receiving end, the MAC layer can subtract the latency of the data stream passing through the physical layer from its own recorded timestamp to obtain the received timestamp. It's easy to understand that this received timestamp can be considered the timestamp when the physical layer of the receiving end actually receives the data stream.

[0148] As described above, the data stream transmitted at the physical layer is a bitstream consisting of multiple bits. The physical layer cannot identify which parts of the bitstream correspond to 1588 packets. Therefore, the physical layer cannot accurately calculate the latency of 1588 packets. To solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer latency. That is, the latency of the data stream passing through the physical layer should stabilize around a fixed value. In this way, the physical layer can report this fixed value to the MAC layer, and the MAC layer can accordingly compensate for the timestamp based on this fixed value.

[0149] However, for some communication devices, such as those including 100GE Ethernet interfaces, their physical layer PCS includes FEC functionality. The FEC function of the PCS performs operations such as adding and deleting parity bits and interleaving and deinterleaving data streams. Both these operations introduce latency jitter, resulting in unstable latency for the data stream passing through the physical layer. In this embodiment, parity bits can also be referred to as parity sequences, and the two can be used interchangeably.

[0150] It should be noted that any communication device can function as both a transmitter and a receiver. In other words, Figure 1a The roles of the sender and receiver shown can be interchanged. Figure 1a If the roles of the sender and receiver are reversed, the direction of the data flow will also change accordingly. That is, the direction of the data flow can be from the sender after the role reversal to the receiver after the role reversal.

[0151] For reference Figure 1b , Figure 1b This is a schematic diagram of another communication device provided in an embodiment of this application. Figure 1b The structure of the communication device shown is similar to Figure 1a The communication devices shown are basically the same in structure, the difference being... Figure 1b The PCS of the communication device shown includes FEC functionality.

[0152] for Figure 1bThe communication device shown has a fixed sum of delays introduced by the FEC functions at both the transmitting and receiving ends. For example, the transmitting PCS performs FEC encoding, which includes adding parity bits, introducing corresponding delay jitter. Additionally, the transmitting end performs data stream interleaving, which also introduces delay jitter. Similarly, the receiving PCS performs FEC decoding, which includes removing parity bits, introducing corresponding delay jitter. Furthermore, the transmitting end performs deinterleaving, which also introduces delay jitter. For ease of description, the delay introduced by the transmitting end's FEC function is called the FEC_TX delay, and the delay introduced by the receiving end's FEC function is called the FEC_RX delay. The FEC_TX and FEC_RX delays can be represented as follows: Figure 1c As shown. Figure 1c This is a schematic diagram illustrating the delay introduced by an FEC function in an embodiment of this application. Figure 1c The horizontal axis represents the bit stream passing through the PCS module, and the vertical axis represents the delay.

[0153] In one example, the FEC function of the PCS can also be called the external code FEC function. The FEC codeword obtained by the PCS at the sending end through FEC encoding can be called the FEC external codeword.

[0154] Furthermore, the current IEEE 802.3dj task force (B400G standard) defines physical layer support for concatenated coding. Specifically, an internal code FEC is inserted between the PMA and PMD for FEC encoding and decoding. As an example, the FEC codeword obtained by encoding the transmitter's internal code FEC using FEC internal code can be referred to as the FEC internal codeword.

[0155] For reference Figure 1d To understand, Figure 1d This is a schematic diagram of another communication device provided in an embodiment of this application. Figure 1d As shown, the physical layer of the communication device supporting concatenated coding includes: a PCS supporting FEC functionality, PMA 101, PMA102, internal code FEC, and PMD. PMA 101 and PMA102 interact via an attachment unit interface (AUI).

[0156] PCS and PMA 101 can belong to the first chip, while PMA102, internal code FEC, and PMD can belong to the optical module.

[0157] Since internal code FEC requires performing operations related to internal codes, and these operations introduce latency jitter, internal code FEC also includes pad addition and deletion operations compared to external code FEC.

[0158] In one example, for the transmitting end, the operations performed by the internal code FEC include encoding, interleaving, and padding. For the receiving end, the operations performed by the internal code FEC include pad removal, deinterleaving, and decoding. In one example, encoding could be inserting 8 parity bits for every 120 message bits, and interleaving could be 8:1 codeword interleaving. Padding could be padding 1024 bits of data every 8704 internal code blocks (each internal code block is 128 bits). That is, inserting a pad with a length of 8 internal code blocks every 8704 internal code blocks. Furthermore, after the transmitting end performs the padding operation, the resulting data stream can be encoded using pulse amplitude modulation 4 (PAM4), meaning that two bits in the data stream can be used as a symbol obtained after PAM4 encoding.

[0159] In another example, for the transmitter, the operations performed by the internal code FEC include: convolutional interleaving, BCH (Bose Chaudhuri Hocquenghem) encoding, and padding. For the receiver, the operations performed by its internal code FEC are the inverse operations of the internal code FEC performed by the transmitter, specifically including: pad removal, BCH decoding, and deconvolutional interleaving. Wherein:

[0160] Convolutional interleaving can be achieved by sending 40 bits of data in a round-robin fashion to N delay lines. For example, taking a delay line with 3 delay lines, these three delay lines are the 0th, 1st, and 2nd delay lines. The 0th delay line does not perform any delay operation, the 1st delay line delays each 40 bits of data by 6 * 40 bits, and the 2nd delay line delays each 40 bits of data by 12 * 40 bits. Deconvolutional interleaving is the reverse process. During deconvolutional interleaving, the 2nd delay line does not perform any delay operation, the 1st delay line delays each 40 bits of data by 6 * 40 bits, and the 0th delay line delays each 40 bits of data by 12 * 40 bits.

[0161] BCH encoding, for example, involves inserting 16 parity bits into every 110 bits of information. Correspondingly, BCH decoding involves removing the 16 parity bits from every 126 bits of encoded information, resulting in 110 bits of information.

[0162] Adding a pad can be done by inserting a 4-bit pilot signal every 64 4-bit data blocks. In other words, in this scenario, the pad can be a pilot signal. Correspondingly, removing a pad involves deleting the 4-bit pilot signal that is included in every 65 4-bit data blocks (i.e., deleting one of the data blocks that serves as a pilot signal), resulting in 64 4-bit data blocks.

[0163] For the transmitting end, the encoding process, including adding parity bits and interleaving, introduces latency jitter. Similarly, for the receiving end, the decoding process, including removing parity bits and deinterleaving, also introduces latency jitter. This results in sawtooth-shaped latency jitter in both the FEC_TX and FEC_RX delays. The sawtooth wave period is approximately 4.5ns (1024 / 113.4375G / 2), and the sawtooth wave amplitude is approximately 0.28125ns (64 / 113.4375G / 2). (See reference...) Figure 1e To understand, Figure 1e This is a schematic diagram illustrating the delay introduced by the internal code FEC function provided in an embodiment of this application. In one example, Figure 1e The sawtooth wave shown can include 8 FEC codewords within one period. Wherein:

[0164] In formula 1024 / 113.4375G / 2:

[0165] 1024 corresponds to the number of bits contained in 8 FEC codewords, and one FEC codeword contains 128 bits;

[0166] 113.4375G corresponds to the baud rate of a single physical lane;

[0167] 2 indicates that in the scenario of PAM4 encoding of a data stream, a symbol consists of 2 bits;

[0168] In formula 64 / 113.4375G / 2:

[0169] 64 indicates that in 8:1 codeword interleaving, the first bit of the ninth virtual lane is the 65th bit in the interleaved data, and it needs to wait for the first 64 bits to be sent before it can be sent.

[0170] 113.4375G corresponds to the baud rate of a single physical channel;

[0171] 2 indicates that a symbol consists of 2 bits.

[0172] Furthermore, for the transmitting end, adding this sub-function to the pad introduces latency jitter; similarly, for the receiving end, removing this sub-function from the pad also introduces latency jitter. This results in sawtooth-shaped latency jitter in both the FEC_TX and FEC_RX delays. The period of this sawtooth wave is approximately 4910ns (8704*128 / 113.4375G / 2), and the amplitude is approximately 4.5ns (1024 / 113.4375G / 2). Compared to the sawtooth waves introduced by the encoding or decoding processes mentioned above, the sawtooth waves introduced by adding or removing this sub-function from the pad have a larger period and can be simply referred to as large sawtooth waves. The sawtooth waves introduced by the encoding or decoding processes are correspondingly referred to as small sawtooth waves. (See reference...) Figure 1f To understand, Figure 1f This is a schematic diagram illustrating the delay introduced by the internal code FEC function in an embodiment of this application. Figure 1f The diagram illustrates the latency introduced by the padding operation at the transmitting end and the latency introduced by the depadding operation at the receiving end. In other words, in a concatenated coding scenario, the aforementioned optical module experiences latency jitter due to the addition or removal of parity bits, interleaving / deinterleaving, and padding. Figure 1f The period of the sawtooth wave shown is Figure 1e The period of the sawtooth wave shown is an integer multiple of the period. Therefore, the time delay introduced by adding or deleting check bits and interleaving / deinterleaving (as before) Figure 1e (as shown) and the delay caused by adding or deleting pads (as mentioned above) Figure 1f The latency after the summation of the latency shown can be referenced. Figure 1g To understand. Figure 1g A schematic diagram illustrating the delay introduced by another internal code FEC function provided in the embodiments of this application.

[0173] In the formula 8704*128 / 113.4375G / 2:

[0174] 8704*128 indicates the number of bits included in 8704 FEC codewords;

[0175] 113.4375G corresponds to the baud rate of a single physical channel;

[0176] 2 indicates that a symbol consists of 2 bits.

[0177] In formula 1024 / 113.4375G / 2:

[0178] 1024 means that 1024 bits of padding data are filled every 8704 internal code blocks;

[0179] 113.4375G corresponds to the baud rate of a single physical channel;

[0180] 2 indicates that a symbol consists of 2 bits.

[0181] about Figure 1g The sawtooth wave shown should be explained as follows:

[0182] The sawtooth patterns corresponding to the FEC_TX delay and the FEC_RX delay have the same period. In other words, the peak positions of the sawtooth patterns corresponding to the FEC_TX delay overlap with those corresponding to the FEC_RX delay, and the trough positions of the sawtooth patterns corresponding to the FEC_TX delay overlap with those corresponding to the FEC_RX delay. However, the number of data (e.g., the number of bits) included in one period of the sawtooth pattern corresponding to the FEC_TX delay can be the same as or different from the number of data included in one period of the sawtooth pattern corresponding to the FEC_RX delay.

[0183] Similarly, the large sawtooth patterns corresponding to the FEC_TX delay and the FEC_RX delay have the same period. In other words, the peak positions of the large sawtooth patterns corresponding to the FEC_TX delay overlap with those corresponding to the FEC_RX delay, and the trough positions of the large sawtooth patterns corresponding to the FEC_TX delay overlap with those corresponding to the FEC_RX delay. However, the number of data (e.g., the number of bits) included in one period of the large sawtooth pattern corresponding to the FEC_TX delay can be the same as or different from the number of data included in one period of the large sawtooth pattern corresponding to the FEC_RX delay.

[0184] Additionally, from the perspective of the sending end:

[0185] In one example, a period corresponding to a large sawtooth wave can include 8704 data blocks corresponding to FEC codewords, with each data block containing 120 information bits. After the transmitter performs FEC encoding, an 8-bit check sequence is added to each data block. Therefore, a period can also be considered to include 8704 data blocks, with each data block containing 128 bits. Further, after the transmitter performs a padding operation, 8 pads corresponding to the length of the FEC codeword are inserted into each period, meaning a period can be considered to include 8712 data blocks, with each data block containing 128 bits. In other words, the data included in a period can be considered to have three possibilities: 8704 * 120 = 1044480 bits; or 8704 * 128 = 1114112 bits; or 8712 * 128 = 1115136 bits.

[0186] In another example, the data included in one cycle could also include: 8712 * 120 = 1,045,440 bits.

[0187] Those skilled in the art will readily understand that all four lengths can be considered as the period corresponding to a large sawtooth wave.

[0188] After the sending end performs a padding operation on the data stream, it can send the data stream with the padded data stream to the receiving end.

[0189] For the receiving end:

[0190] One period of a large sawtooth wave can include data blocks corresponding to 8712 FEC codewords, with each data block consisting of 128 bits. The receiver can perform a pad deletion operation on these 8712 FEC codeword data blocks, removing the pads inserted by the transmitter. After the receiving end performs the pad deletion operation, one period includes 8704 FEC codeword data blocks, with each data block consisting of 128 bits. Further, the receiving end can perform FEC code decoding on these 8704 FEC codeword data blocks, deleting the 8-bit parity sequence in each data block. Therefore, after the receiving end performs FEC code decoding, one period can include 8704 data blocks, with each data block consisting of 120 bits. Therefore, for the receiving end, the data included in one cycle can be in three ways: 8712 * 128 = 1,115,136 bits; or 8704 * 128 = 1,114,112 bits; or 8704 * 120 = 1,044,480 bits.

[0191] In another example, the data included in one cycle could also include: 8712 * 120 = 1,045,440 bits.

[0192] Regarding the aforementioned latency jitter introduced by FEC or internal code FEC functions, the IEEE 802.3cx standard specifies that: for the transmitter, the reported latency is equivalent to the maximum latency; for the receiver, the reported latency is equivalent to the minimum latency. For example, in Figure 1c In the scenario shown, the delay reported by the sender is X+N, and the delay reported by the receiver is YN.

[0193] However, the IEEE 802.3cx standard does not specify the specific implementation methods for the transmitter to report the maximum latency and the receiver to report the minimum latency in scenarios where the physical layer supports concatenated coding.

[0194] For the internal code FEC function, the factors introducing latency jitter include the addition or deletion of parity bits, interleaving and deinterleaving, and padding. For the transmitter, the latency corresponding to the data at the beginning of a specific data block is equivalent to the maximum latency (FEC_TX). Similarly, for the receiver, the latency corresponding to the data at the beginning of a specific data block is equivalent to the minimum latency (FEC_RX). See reference... Figure 1h To understand, Figure 1h This is a schematic diagram illustrating the delay introduced by the internal code FEC function provided in an embodiment of this application. Figure 1h middle:

[0195] The data corresponding to the position circled by the hollow circle has a latency equivalent to the maximum latency. This is because the portion circled by the hollow circle represents the maximum latency introduced by adding or deleting check sequences and interleaving / deinterleaving, as well as the maximum latency introduced by adding or deleting padding sequences. Here, adding or deleting check sequences refers to adding or deleting check sequences, and adding or deleting padding sequences refers to adding or deleting padding sequences.

[0196] The data corresponding to the position circled by the solid circle has a latency equivalent to the minimum latency. This is because the portion circled by the hollow circle corresponds to the minimum latency introduced by adding or deleting check sequences and interleaving / deinterleaving, as well as the minimum latency introduced by adding or deleting padding sequences.

[0197] The data circled by the hollow circle represents the starting position of a specific data block. Similarly, the data circled by the solid circle also represents the starting position of a specific data block.

[0198] As mentioned earlier, the period of the large sawtooth is an integer multiple of the period of the small sawtooth. Therefore, Figure 1h The period of the hollow circle shown corresponds to the period of the large sawtooth.

[0199] As before Figure 1g As can be seen from the description, in Figure 1h In the scenario shown:

[0200] In one example, one period of the hollow circle includes 8704 data blocks, each consisting of 120 bits. In another example, one period of the hollow circle includes 8704 data blocks, each consisting of 128 bits. In yet another example, one period of the hollow circle includes 8712 data blocks, each consisting of 128 bits.

[0201] In one example, a period of solid circles includes 8712 data blocks, each consisting of 128 bits. In another example, a period of solid circles includes 8704 data blocks, each consisting of 128 bits. In yet another example, a period of solid circles includes 8704 data blocks, each consisting of 120 bits.

[0202] In this system, data blocks can be numbered sequentially, with an interval of m data blocks between two adjacent circles. This interval can be represented by the difference in numbers between the data blocks corresponding to the two adjacent circles. In this case, the period of the positions marked by the aforementioned circles is also m. For example, the interval between data blocks corresponding to two hollow circles is 8712 data blocks, which can be represented by the difference in numbers between the data blocks corresponding to the two hollow circles being 8712. Accordingly, the period of the positions marked by the hollow circles is 8712.

[0203] Furthermore, the existing IEEE 802.3cx Chapter 90 requires that when the physical layer of a communication device reports latency, each layer should report the maximum latency and minimum latency separately. Specifically, IEEE 802.3cx Chapter 90 defines the registers used by each layer to report the maximum and minimum latency. For example, IEEE 802.3cx Chapter 90 defines the TX maximum latency register, TX minimum latency register, RX maximum latency register, and RX minimum latency register for the PMA / PMD, where:

[0204] The PMA / PMD TX maximum delay register is used to report the maximum delay of the PMA / PMD when the communication device is acting as the transmitter.

[0205] The PMA / PMD's TX minimum delay register is used to report the minimum delay of the PMA / PMD when the communication device is acting as the transmitter.

[0206] The PMA / PMD's RX maximum delay register is used to report the maximum delay of the PMA / PMD when the communication device is acting as the receiver.

[0207] The RX minimum delay register of the PMA / PMD is used to report the minimum delay of the PMA / PMD when the communication device is acting as the receiver.

[0208] In view of this, embodiments of this application provide a latency reporting method that can accurately report latency in scenarios where the physical layer supports concatenated coding, and in accordance with the EEE 802.3cx standard which stipulates that "for the sender, the reported latency is equivalent to the maximum latency, and for the receiver, the reported latency is equivalent to the minimum latency,"

[0209] Next, the delay reporting method provided in the embodiments of this application will be described in conjunction with the accompanying drawings.

[0210] Before introducing the latency reporting method provided in the embodiments of this application, it should be noted that:

[0211] For a communication device, it may include a physical layer module, which implements the functions of the aforementioned physical layer. The physical layer may include multiple sub-modules, each implementing a specific physical layer function. For example, the physical layer module may include a PCS sub-module, a PMA sub-module, and a PMD sub-module. The PCS sub-module implements the functions of the aforementioned PCS, the PMA sub-module implements the functions of the aforementioned PMA, and the PMD sub-module implements the functions of the aforementioned PMD.

[0212] In addition, the communication device may also include an optical module, and the optical module may also include corresponding sub-modules to implement corresponding functions. For example, for a structure with... Figure 1d For a communication device with the structure shown, the optical module may include a PMA submodule, an internal code FEC module, and a PMD submodule.

[0213] Furthermore, time synchronization is only one application scenario provided by the embodiments of this application, and the solution of the embodiments of this application can also be applied to other scenarios. For example, in the scenario of flow detection, the communication device can also use the solution of the embodiments of this application to determine the sending timestamp or receiving timestamp of the message. The application scenarios of the embodiments of this application will not be listed and described one by one here.

[0214] See Figure 2 The figure is a flowchart illustrating a delay reporting method provided in an embodiment of this application.

[0215] Figure 2 The delay reporting method shown can be applied to the first module, which can be a module in a communication device. The communication device mentioned here can be a communication device acting as a transmitter or a communication device acting as a receiver; this application embodiment does not specifically limit its application. The structure of the first module can be as follows: Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first module provided in an embodiment of this application. Figure 3 As shown, the first module includes a bitstream processing module, a delay determination module, and a delay reporting module. The bitstream processing module may include an FEC module and other modules that interact with the FEC module. The delay determination module is used to determine the delay, and the delay reporting module is used to report the determined delay to the second module.

[0216] In one example, the first module can be a PHY module or an optical module. As a specific example, the structure of a communication device including the first module is as follows: Figure 1d The structure shown. In this case... Figure 3 The FEC module shown can be a module that implements the internal code FEC function. The module that implements the internal code FEC function can also be called an "internal code FEC module".

[0217] The PHY module mentioned in the embodiments of this application may be, for example, a PHY chip used to implement PHY functions.

[0218] Figure 2 The method shown may include the following steps S101-S102.

[0219] S101: Determine the target time delay corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream.

[0220] In this embodiment of the application, the data stream is a bit stream sent from the sending end to the receiving end.

[0221] In this embodiment, the first module can report the target latency to the second module. In one example, the second module can be the MAC layer module of a communication device. In this way, the MAC layer module can compensate for its own recorded timestamps based on the target latency, thereby making the compensated timestamps more accurate.

[0222] In this embodiment of the application, if the first module is a module corresponding to the sending end, for example, it is... Figure 1d The module corresponding to the internal code FEC shown, or, is Figure 1d The optical module shown includes PMA102, FEC internal code, and PMD. The first module can perform FEC internal code encoding and padding operations on the data entering the first module. Accordingly, in one example, the data stream mentioned here can be the data stream after performing FEC internal code encoding and padding operations. If the first module is a module corresponding to the receiving end, then in one example, the data stream can be the data stream sent from the sending end to the first module. In other words, the data stream is the data stream entering the first module, and this data stream has undergone FEC internal code encoding and padding operations at the sending end.

[0223] In another example, considering that after the sending end sends the data stream to the receiving end, the receiving end can perform FEC encoding decoding on the data stream, therefore, the data stream can also be the data stream obtained by the receiving end after performing FEC encoding decoding on the received data stream. In other words, if the first module is the module corresponding to the receiving end, then in another example, the data stream can be the data stream obtained after FEC encoding decoding.

[0224] Wherein: the first module corresponds to the sending end module, which can be understood as the first module being a module in the communication device that acts as the sending end; the first module corresponds to the receiving end module, which can be understood as the first module being a module in the communication device that acts as the receiving end. Wherein, the first module corresponding to the receiving end module can also be understood as the first module corresponding to the receiving end, and the first module corresponding to the sending end module can also be understood as the first module corresponding to the sending end.

[0225] In this embodiment, the target latency is the latency of data from the aforementioned multiple specific locations passing through the first module. Alternatively, the target latency is the latency of data from the aforementioned multiple specific locations passing through the internal code FEC layer in the first module. When the first module is an optical module, the target latency is the latency of data from the aforementioned multiple specific locations passing through the optical module. Alternatively, the target latency is the latency of data from the aforementioned multiple specific locations passing through the internal code FEC layer in the optical module. The internal code FEC layer is a layer used to implement the internal code FEC function. In the scenario where the first module is a PHY module, the target latency is the latency of data from the aforementioned multiple specific locations passing through the internal code FEC layer in the PHY module.

[0226] In a specific example, the optical module may include an internal code FEC module corresponding to the internal code FEC layer. Therefore, in one example, the target latency may be the latency of data passing through the internal code FEC module in the optical module at the aforementioned multiple specific locations. The internal code FEC module is used to implement the internal code FEC function. In a specific example, the internal code FEC module includes an internal code FEC encoding module and / or an internal code FEC decoding module. The internal code FEC encoding module is used to implement the FEC internal code encoding function, and the internal code FEC decoding module is used to implement the FEC internal code decoding function. As an example, when the communication device acts as a transmitter, the internal code FEC module includes an internal code FEC encoding module. As another example, when the communication device acts as a receiver, the internal code FEC module includes an internal code FEC decoding module. As yet another example, considering that a communication device can act as both a transmitter and a receiver, the internal code FEC module may include an internal code FEC encoding module and an internal code FEC decoding module.

[0227] In this embodiment, if the first module corresponds to the transmitting end, the target latency corresponding to the data at the multiple specific locations is equivalent to the maximum latency. If the first module corresponds to the receiving end, the target latency corresponding to the data at the multiple specific locations is equivalent to the minimum latency. As previously stated... Figure 1h As can be seen from the description, the multiple specific locations can be Figure 1h The circled area indicates the starting position of a specific data block. (See reference.) Figure 1h To understand this, from the perspective of the sending end, the multiple specific locations can be... Figure 1h The area enclosed by the hollow circle. From the perspective of the receiving end, these multiple specific locations can be... Figure 1h The positions are circled in solid circles. These specific positions are spaced at fixed intervals. Furthermore, the period of each of these specific positions corresponds to the period of the padding sequence inserted into the data stream.

[0228] As before Figure 1h As described, the period of the multiple specific positions can be either 8712 data blocks or 8704 data blocks, where 8712 is the period after inserting the padding sequence into the data stream, and 8704 is the period before inserting the padding sequence. Of course, the period of the multiple specific positions can also be an integer multiple of 8712 or 8704 data blocks. For example, if the period of the specific positions is K times 8712 or 8704 data blocks, then the larger the value of K, the fewer specific positions need to be counted for latency, and correspondingly, the less computational resources are consumed in counting the target latency.

[0229] In one example, a data block may include 128 bits or 120 bits. For instance, if the data block is encoded using FEC internal code, it includes 128 bits. If the data block has not yet been encoded using FEC internal code, or if it has been decoded using FEC internal code, it includes 120 bits. A data block consisting of 128 bits can also be referred to as an FEC internal codeword.

[0230] As before Figure 1h As can be seen from the description, the period of the multiple specific positions can include the following cases:

[0231] 8704 * 120 = 1,044,480 bits; or, 8712 * 120 = 1,045,440 bits; or, 8704 * 128 = 1,114,112 bits; or, 8712 * 128 = 1,115,136 bits.

[0232] Therefore, in one example, the period of the plurality of specific positions can be an integer multiple of 1,044,480 bits, an integer multiple of 1,114,112 bits, or an integer multiple of 1,115,136 bits.

[0233] In a scenario where convolutional interleaving, BCH encoding, and pad insertion are performed at the transmitting end, a data block may include 4 bits. The period at the multiple specific positions may be 65 data blocks or 64 data blocks, where 65 is the period corresponding to the insertion of the padding sequence in the data stream, and 64 is the period corresponding to the insertion of the padding sequence in the data stream.

[0234] In this embodiment, the specific position may be the starting position of a data block. The starting position of a data block may be the first byte, the first bit, or the first symbol. In the scenario where the aforementioned data block includes 128 bits, the specific data block mentioned here may be a specific FEC codeword, for example, an FEC internal codeword.

[0235] For example, in an embodiment of this application, the specific position may be the starting position of the next data block after the padding sequence is inserted in the data stream. That is, the starting position of the first data block in the payload data.

[0236] In one example, the data stream may include multiple target data, each target data may include N data blocks, and correspondingly, the aforementioned specific position may be the starting position of these N data blocks. In other words, the data stream may include multiple data blocks, which may be divided into multiple groups of N data blocks each, with each group corresponding to one target data. In a scenario where a data block includes 128 bits, the target data may include N FEC codewords.

[0237] In this embodiment, in addition to inserting a padding sequence into the data stream, the sending end can also insert a check sequence. Specifically, when the sending end performs FEC internal code encoding on the data stream, it can insert an 8-bit check sequence for every 120 bits of data. In this embodiment, the period of the padding sequence inserted by the sending end into the data stream is an integer multiple of the period of the check sequence inserted into the data stream. For example, it can be combined with... Figure 1h To understand, in Figure 1hIn this context, the period of the small sawtooth wave corresponds to the period of the parity sequence inserted in the data stream, and the period of the large sawtooth wave corresponds to the period of the padding sequence inserted in the data stream. The period of the large sawtooth wave is an integer multiple of the period of the small sawtooth wave. In one example, the period of the large sawtooth wave could be 8704 times the period of the small sawtooth wave. Because the period of the padding sequence inserted in the data stream is an integer multiple of the period of the parity sequence inserted in the data stream, the peak positions of the large sawtooth wave overlap with the peak positions of the small sawtooth wave, and the trough positions of the large sawtooth wave overlap with the trough positions of the small sawtooth wave. Therefore, the period at the aforementioned specific position can be determined based on the period of the padding sequence inserted in the data stream to determine the target delay.

[0238] In one example, the data from the aforementioned multiple specific locations can correspond to a first time delay for each specific location. Therefore, the data from the aforementioned multiple specific locations can correspond to multiple first time delays.

[0239] In the embodiments of this application, the plurality of first delays may be the same, or may not be completely the same or completely different, and the embodiments of this application do not make specific limitations.

[0240] As mentioned earlier, the existing IEEE 802.3cx Chapter 90 defines corresponding maximum and minimum delay registers for each layer of the physical layer. Therefore, to be compatible with the current IEEE 802.3cx Chapter 90 mechanism for reporting physical layer delays, the maximum and / or minimum value among the plurality of first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the plurality of first delays.

[0241] As mentioned above, the plurality of first delays may be the same, not exactly the same, or completely different. When the plurality of first delays are the same, the maximum value and the minimum value are the same. When the plurality of first delays are not exactly the same or completely different, the maximum value is less than the minimum value.

[0242] In one example, in a specific implementation of S101, the first module can measure the first delay corresponding to the data at each of the multiple specific locations, thus obtaining multiple first delays. For example:

[0243] If the first module corresponds to the sending end, then for the data stream entering the first module, it can be divided into groups of 8704 data blocks (each data block includes 120 bits), and the first delay of the data at the starting position in each group of data blocks within the first module can be measured to obtain multiple first delays.

[0244] If the first module corresponds to the receiving end, then for the data stream entering the first module, it can be divided into groups of 8712 data blocks (each data block includes 128 bits), and the first delay of the data at the starting position in each group of data blocks within the first module can be measured to obtain multiple first delays.

[0245] The embodiments in this application do not specifically limit the specific implementation method of determining the first delay.

[0246] In one example, the first module can record the delay of data at a specific location in the target data to determine the first delay. In another example, the first module can determine the delay of data at multiple locations in the target data after passing through the first module, thereby obtaining multiple delays corresponding to each target data. The multiple locations mentioned here can include the specific location; for example, the multiple locations can be various locations in the target data. Accordingly, for any target data, the first delay can be determined from the multiple delays corresponding to that target data. That is, the delay corresponding to the specific location is extracted from the multiple delays to obtain the first delay. For example, for target data, the first module can determine the delay of each bit data in the target data after passing through the first module, and extract the delay of data at the starting position in the target data after passing through the first module to obtain the first delay.

[0247] The method for determining the time delay of data at any position in the target data after passing through the first module is not specifically limited in the embodiments of this application. Two possible implementation methods are described below.

[0248] In one implementation, the first module can record the first moment when it receives the data at that location, and the second moment when it sends the data at that location out. The difference between the second moment and the first moment is used to determine the time delay of the data at that location passing through the first module.

[0249] In another example, after receiving data at a specific location, the first module can cache that data. Accordingly, the first module can send out the cached data in sequence, based on the already cached data. Therefore, the position of the data at that location in the cache can characterize the length of time the data at that location needs to wait in the cache, and this waiting time can characterize the latency of the data at that location passing through the first module. Thus, the first module can determine the latency of the data at that location passing through the first module based on the position of the data at that location in the cache.

[0250] S102: Report the target latency corresponding to data at multiple specific locations in the data stream.

[0251] The first module can use corresponding registers to report the target latency to the second module. In a scenario where the target latency includes the aforementioned maximum and / or minimum values, in one example, the first module can use corresponding registers to report the maximum and / or minimum values ​​to the second module. The following describes several specific implementation methods of the first module using corresponding registers to report the maximum and / or minimum values ​​to the second module.

[0252] In one example, if the first module corresponds to the sending end, then:

[0253] As a concrete example, new registers can be defined to report the maximum and / or minimum values ​​to the second module. For instance, a maximum TX delay register and / or a minimum TX delay register can be defined for the internal code FEC, where the maximum TX delay register is used to report the maximum value and the minimum TX delay register is used to report the minimum value. In other words, the first module can use the maximum TX delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum TX delay register of the internal code FEC to report the minimum value to the second module.

[0254] As another concrete example, the first module can use the PMA / PMD's TX maximum delay register to report the maximum value to the second module. Similarly, the first module can use the PMA / PMD's TX minimum delay register to report the minimum value to the second module. In this way, existing registers can be used to report the target delay.

[0255] In one example, if the first module corresponds to the receiving end, then:

[0256] As another concrete example, new registers can be defined to report the maximum and / or minimum values ​​to the second module. For example, a maximum RX delay register and / or a minimum RX delay register can be defined for the internal code FEC, where the maximum RX delay register is used to report the maximum value and the minimum RX delay register is used to report the minimum value. In other words, the first module can use the maximum RX delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum RX delay register of the internal code FEC to report the minimum value to the second module.

[0257] As another specific example, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0258] As can be seen from the above description, using the scheme of this application embodiment, the first module can accurately report the delay to the second module according to the principle that "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay".

[0259] The latency reporting method provided by the embodiments of this application has been described above. Next, the solution provided by the embodiments of this application will be described in conjunction with specific scenarios.

[0260] Example 1: Figure 2 The specific implementation of the delay reporting method shown.

[0261] In this scenario, the structure of the communication device can be adopted. Figure 1d The structure shown can be such that the first module is an optical module of a communication device, which includes PMA102, internal code FEC and PMD.

[0262] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0263] S1: Record the delay of the optical module after the starting position of the i-th data block in the transmitted data stream, and obtain DelayTX(1, i), where:

[0264] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0265] The value of i can be 8704, 8704*2, 8704*3, ... 8704*k.

[0266] S2: Determine the maximum value of DelayTX(1,i) DelayTX_max and the minimum value of DelayTX(1,i) DelayTX_min.

[0267] S3: Report DelayTX_max and DelayTX_min to the MAC layer module.

[0268] In one example, the DelayTX_max can be reported to the MAC layer module through the TX maximum delay register of the internal code FEC, and the DelayTX_min can be reported to the MAC layer module through the TX minimum delay register of the internal code FEC.

[0269] In another example, DelayTX_max can be reported to the MAC layer module via the TX maximum delay register of the PMA / PMD, and DelayTX_min can be reported to the MAC layer module via the TX minimum delay register of the PMA / PMD.

[0270] For a communication device acting as a receiver, its optical module can perform the following operations:

[0271] S1': Record the starting position of the j-th FEC code block in the received data stream after the delay of the optical module, and obtain DelayRX(1,j).

[0272] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0273] The value of j can be 8712, 8712*2, 8712*3, ..., 8712*k.

[0274] S2': Determine the maximum value of DelayRX(1,j) DelayRX_max and the minimum value of DelayRX(1,j) DelayRX_min.

[0275] S3': Report DelayRX_max and DelayRX_min to the MAC layer module.

[0276] In one example, the DelayRX_max can be reported to the MAC layer module via the RX maximum delay register of the internal code FEC, and the DelayRX_min can be reported to the MAC layer module via the RX minimum delay register of the internal code FEC.

[0277] In another example, the DelayRX_max can be reported to the MAC layer module via the RX maximum delay register of the PMA / PMD, and the DelayRX_min can be reported to the MAC layer module via the RX minimum delay register of the PMA / PMD.

[0278] The inventors of this application have also discovered that if the sub-modules included in the first module include sub-modules capable of introducing delay jitter, then if the first module can report delay information to the second module based on the delay jitter value, it can also accurately report delay information to the second module in accordance with the IEEE 802.3cx standard, which stipulates that "for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay."

[0279] Therefore, embodiments of this application also provide a method with... Figure 2 The latency reporting method shown is another latency reporting method listed alongside the one described below. Next, we will combine... Figure 4 This section introduces the delay reporting method. Figure 4 This is a flowchart illustrating another delay reporting method provided in an embodiment of this application.

[0280] Figure 4The method shown can be applied to the first module. For details about the first module, please refer to the description of the first module above. It will not be repeated here.

[0281] Figure 4 The method shown may include the following steps S201-S202.

[0282] S201: Obtain the latency jitter value of the target data after passing through the first sub-module in the first module. The first sub-module includes a sub-module with a fixed latency jitter value. The target data is data sent by the first module or data received by the first module. The latency jitter value is the preset fixed value.

[0283] Regarding the target data, the above can be used as a reference. Figure 2 The description of the target data in the method shown will not be repeated here.

[0284] In this embodiment, the first submodule contains a fixed value of latency jitter. As described above regarding the internal code FEC function, the addition or deletion of the check sequence, data interleaving or deinterleaving, and the addition or deletion of the padding sequence all contribute to latency jitter in implementing the internal code FEC function. For the transmitting end, the latency jitter introduced by adding the check sequence, data interleaving, and adding the padding sequence is the aforementioned fixed value. For the receiving end, the latency jitter introduced by deleting the check sequence, data deinterleaving, and deleting the padding sequence is also the aforementioned fixed value.

[0285] Therefore, in one example, the first submodule may include: a submodule that experiences delay jitter due to the addition or deletion of a check sequence, a submodule that experiences delay jitter due to the addition or deletion of a padding sequence, and a submodule that experiences delay jitter due to the interleaving or deinterleaving of data streams. Alternatively, the first submodule may also include a cyclic shift submodule.

[0286] As a specific example, for the sending end, the first submodule may include: a submodule that causes delay jitter due to the addition of a parity sequence, a submodule that causes delay jitter due to the addition of a padding sequence, and a submodule that causes delay jitter due to data stream interleaving. Correspondingly, for the receiving end, the first submodule may include: a submodule that causes delay jitter due to the deletion of a parity sequence, a submodule that causes delay jitter due to the deletion of a padding sequence, and a submodule that causes delay jitter due to data stream deinterleaving.

[0287] In one example, the aforementioned submodule that causes latency jitter due to the addition of the parity sequence can be a submodule within the internal code FEC module that performs FEC internal code encoding; the aforementioned submodule that causes latency jitter due to the addition of the padding sequence can be a submodule within the internal code FEC module that performs the padding sequence addition operation; the aforementioned submodule that causes latency jitter due to data stream interleaving can be a submodule within the internal code FEC module that performs data stream interleaving. In other words, the first submodule can include: a submodule within the internal code FEC module that performs FEC internal code encoding, data stream interleaving, and padding sequence addition.

[0288] In another example, the aforementioned submodule experiencing latency jitter due to the deletion of the parity sequence could be a submodule within the internal code FEC module that performs FEC internal code decoding; the aforementioned submodule experiencing latency jitter due to the deletion of the padding sequence could be a submodule within the internal code FEC module that performs the padding sequence deletion operation; and the aforementioned submodule experiencing latency jitter due to data stream deinterleaving could be a submodule within the internal code FEC module that performs data stream deinterleaving. In other words, the first submodule could include: a submodule within the internal code FEC module that performs FEC internal code decoding, data stream deinterleaving, and padding sequence deletion.

[0289] In yet another example, the aforementioned first submodule could be a cyclic shift submodule. This cyclic shift submodule is used to perform cyclic shift operations. As an example, the transmitting end can perform a cyclic shift operation before performing encoding processing (e.g., internal code FEC processing), and correspondingly, the receiving end can perform a cyclic shift operation after performing decoding processing. As yet another example, the transmitting end can perform a cyclic shift operation after performing BCH encoding and before performing pilot insertion. Correspondingly, the receiving end can perform a cyclic shift operation after performing pilot deletion and before performing BCH decoding.

[0290] In one example, if the shift direction of the cyclic shift operation performed by the receiving end is the same as the shift direction of the cyclic shift operation performed by the sending end, then the aforementioned first submodule may include a cyclic shift submodule for performing the cyclic shift operation. In this scenario, the latency jitter introduced by the cyclic shift submodule can be 4.5 nanoseconds.

[0291] In this embodiment, the latency jitter value can be a preset fixed value. For example, when the first module is an optical module, the latency jitter value can include the sum of a first jitter value and a second jitter value. The first jitter value can be the latency jitter introduced by adding or deleting the check sequence, or by data stream interleaving or deinterleaving. The second jitter value can be the latency jitter introduced by adding or deleting pads. The fixed value can be, for example, a value between 4.6ns and 4.8ns. As a specific example, based on the preceding text... Figure 1e , Figure 1f as well as Figure 1g As described, the latency jitter introduced by adding or deleting the check sequence, and by interleaving or deinterleaving the data stream, is 0.28125 ns, and the latency jitter introduced by adding or deleting the pad is 4.5 ns. Therefore, the latency jitter value can be 4.78125 ns. When the first submodule also includes a cyclic shift submodule, the aforementioned latency jitter value can be the sum of the first and second jitter values, plus the 4.5 ns latency jitter introduced by the cyclic shift submodule. That is, the aforementioned latency jitter value can be between (4.5 ns + 4.6 ns = 9.1 ns) and (4.5 ns + 4.8 ns = 9.3 ns).

[0292] In some examples, the latency jitter value can also be referred to as the latency variation value.

[0293] S202: Report the latency information to the second module based on the latency jitter value.

[0294] After determining the latency jitter value, the latency information can be reported to the second module based on the latency jitter value.

[0295] Regarding the second module, the description of the second module in the above embodiments will not be repeated here.

[0296] In one example, the first module can report the latency jitter value to the second module.

[0297] In yet another example, the first module can also determine a first delay in the target data passing through the second submodule within the first module. In embodiments of this application, the second submodule can be a submodule that introduces almost no delay jitter. The submodule that introduces almost no delay jitter mentioned herein can also be understood as a submodule that introduces minimal delay jitter. In a specific example, the second submodule can be a submodule within the first module other than the first submodule.

[0298] In one example, if the first module corresponds to the transmitting end, the second submodule may be, for example, a submodule within the internal code FEC module that performs convolutional interleaving, distribution, and modulation coding operations. The modulation coding mentioned here may be, for example, PAM4 coding. If the first module corresponds to the receiving end, the second submodule may be, for example, a submodule within the internal code FEC module that performs deconvolutional deinterleaving, multiplexing, and modulation decoding operations. The modulation coding mentioned here may be, for example, PAM4 decoding. In the embodiments of this application, determining the first delay can be implemented in multiple ways. Two possible implementations are described below.

[0299] In one example, the first module can obtain a pre-set first delay, which may be a value determined by the first module during the design phase, and the value of the first delay is related to the performance of the first module.

[0300] In another example, the first module can calculate the first delay of the target data passing through the second submodule based on statistics. Specifically, calculating the first delay of the target data passing through the second submodule can be achieved by calculating the delay of at least one bit of the target data passing through the second submodule. For example, the target data can be sampled, and the delay of the sampled data passing through the second submodule can be calculated. Alternatively, the delay of each bit of the target data passing through the second submodule can be calculated to obtain the first delay.

[0301] For any bit data, the delay after passing through the second submodule can be the difference between the time when the second submodule sends the data and the time when the second submodule receives the data, or it can be determined according to the position of the data in the buffer. This application embodiment does not make specific limitations.

[0302] In the scenario where the first module determines the first delay, in specific implementation, S202 can report delay information to the second module based on the delay jitter value and the first delay.

[0303] As a specific example, the first module can determine the aforementioned latency jitter value and the first latency as the latency information, and report the determined latency information to the second module.

[0304] As another specific example, the first module can determine the target latency based on the latency jitter value and the first latency, and report the target latency as the aforementioned latency information to the second module.

[0305] This application does not specifically limit the method of determining the target latency based on the latency jitter value and the first latency. The first module can calculate the latency jitter value and the first latency to obtain the target latency.

[0306] In one example, in order for the data reported by the first module to satisfy the condition that "for the sender, the reported latency is equivalent to the maximum latency, and for the receiver, the reported latency is equivalent to the minimum latency," the first communication device determines the specific implementation method of determining the target latency based on the latency jitter value and the first latency, which may be related to the role of the first communication device.

[0307] In a specific example, if the first module corresponds to a communication device acting as a transmitter, the first communication device can determine the target delay as the sum of the delay jitter value and the first delay. If the first communication device corresponds to a communication device acting as a receiver, the first communication device can determine the target delay as the difference between the first delay and the delay jitter value.

[0308] In one example, the first delay may include a delay.

[0309] In another example, considering that the existing IEEE 802.3cx Section 90 defines corresponding maximum and minimum delay registers for each layer of the physical layer, the first delay may include two delays to ensure compatibility with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays. These delays are the maximum delay of the target data passing through the second submodule and the minimum delay of the target data passing through the second submodule. In one example, the maximum delay and the minimum delay are the same. In another example, the maximum delay is greater than the minimum delay.

[0310] As mentioned earlier, the first delay may include a maximum delay and a minimum delay. In this case, the target delay determined based on the delay jitter value and the first delay may include a maximum target delay and a minimum target delay. Wherein:

[0311] The maximum target latency can be determined based on the maximum latency and the latency jitter value. Specifically, if the first module corresponds to a communication device acting as a transmitter, the first communication device can determine the maximum target latency as the sum of the latency jitter value and the maximum latency, and determine the minimum target latency as the sum of the latency jitter value and the minimum latency. If the first communication device corresponds to a communication device acting as a receiver, the first communication device can determine the maximum target latency as the difference between the maximum latency and the latency jitter value, and determine the minimum target latency as the difference between the minimum latency and the latency jitter value.

[0312] Next, we will introduce how the first module reports the maximum and minimum target latency to the second module.

[0313] In one example, if the first module corresponds to the sending end, then:

[0314] As another concrete example, new registers can be defined to report the maximum and minimum target delays to the second module. For instance, a maximum TX delay register and a minimum TX delay register can be defined for the internal code FEC, where the maximum TX delay register is used to report the maximum target delay, and the minimum TX delay register is used to report the minimum target delay. In other words, the first module can use the maximum TX delay register of the internal code FEC to report the maximum target delay to the second module, and / or use the minimum TX delay register of the internal code FEC to report the minimum target delay to the second module.

[0315] As another specific example, the first module can use the PMA / PMD's TX maximum delay register to report the maximum target delay to the second module. Similarly, the first module can use the PMA / PMD's TX minimum delay register to report the minimum target delay to the second module.

[0316] In one example, if the first module corresponds to the receiving end, then:

[0317] As another concrete example, new registers can be defined to report the maximum and minimum target delays to the second module. For instance, an RX maximum delay register and an RX minimum delay register can be defined for the internal code FEC, where the RX maximum delay register is used to report the maximum target delay, and the RX minimum delay register is used to report the minimum target delay. In other words, the first module can use the RX maximum delay register of the internal code FEC to report the maximum target delay to the second module, and / or use the RX minimum delay register of the internal code FEC to report the minimum target delay to the second module.

[0318] As another specific example, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum target delay to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum target delay to the second module.

[0319] In one example, the first module further includes a third submodule, which can also determine a second delay after the target data passes through the third submodule. The third submodule mentioned here can be any other submodule within the first module that differs from the aforementioned first and second submodules. For example, the third submodule may include a PMA submodule and a PMD submodule.

[0320] The implementation principle of the first module determining the second delay of the target data after passing through the third sub-module is the same as the implementation principle of the first module determining the first delay of the target data after passing through the second sub-module. Therefore, for the specific implementation of "the first module determining the second delay of the target data after passing through the third sub-module", please refer to the description of the first module determining the first delay in the previous text. It will not be described again here.

[0321] In the scenario where the first module determines the second delay, in specific implementation, S202 can report delay information to the second module based on the delay jitter value and the second delay.

[0322] As a specific example, the first module can determine the aforementioned latency jitter value and the second latency as the latency information, and report the determined latency information to the second module.

[0323] As another concrete example, the first module can calculate the latency jitter value and the second latency, and report the calculation result as the latency information to the second module. In a specific example, if the first module corresponds to a communication device at the transmitting end, the first communication device can determine the latency information as the sum of the latency jitter value and the second latency. If the first communication device corresponds to a communication device at the receiving end, the first communication device can determine the latency information as the difference obtained by subtracting the latency jitter value from the second latency.

[0324] In this scenario, the first communication device can utilize the relevant registers of the PMA / PMD to report the latency information to the second module. As an example, the second latency can also include a maximum latency and a minimum latency. Correspondingly, the latency information can include a maximum latency value obtained based on the latency jitter value and the maximum latency of the second latency, and a minimum latency value obtained based on the latency jitter value and the minimum latency of the second latency. Further, the first communication device can utilize the relevant registers of the PMA / PMD to report the maximum latency value and the minimum latency value to the second module.

[0325] Specifically, if the first module corresponds to the transmitting end, that is, the target data is data sent by the first module, then the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with internal code FEC function (e.g., an optical module), the first module can use the TX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the TX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0326] If the first module corresponds to the receiving end, that is, the target data is the data received by the first module, then: the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module. For example, when the first module is a module with internal code FEC function (e.g., an optical module), the first module can use the RX maximum delay register of the PMA / PMD to report the maximum delay value to the second module, and the first module can use the RX minimum delay register of the PMA / PMD to report the minimum delay value to the second module.

[0327] The latency reporting method provided by the embodiments of this application has been described above. Next, the solution provided by the embodiments of this application will be described in conjunction with specific scenarios.

[0328] Example 2: Figure 4 The specific implementation of the delay reporting method shown.

[0329] In this scenario, the first module can be the optical module of the communication device, which includes PMA102, internal code FEC, and PMD.

[0330] In this situation, the operation performed by the internal code FEC can be as follows: Figure 5 As shown, Figure 5 This is a schematic diagram illustrating the processing procedure of an internal code FEC provided in an embodiment of this application. For example... Figure 5 As shown:

[0331] For the transmitting end, its internal code FEC can perform the following operations: convolutional interleaving, distribution, internal code FEC processing, interleaving, padding, and other processing. The other processing mentioned here may include, for example, PAM4 encoding. Internal code FEC processing may, for example, involve performing a parity sequence increment operation. The submodule that performs parity sequence increment, interleaving, and padding is the first submodule, and the submodule that performs convolutional interleaving, distribution, and other processing is the second submodule.

[0332] For the receiving end, the operations performed by its internal code FEC are the inverse operations performed by the sending end's internal code FEC. For example, the receiving end's internal code FEC can perform the following operations: other processing (e.g., PAM4 decoding), pad deletion, deinterleaving, internal code FEC processing, multiplexing, and deconvolutional deinterleaving. Internal code FEC processing can, for example, involve performing a parity sequence deletion operation. The submodule performing parity sequence deletion, deinterleaving, and pad deletion is the first submodule, and the submodule performing deconvolutional deinterleaving, merging, and other processing is the second submodule.

[0333] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0334] S4: Get the latency jitter value 4.78125.

[0335] S5: Determine the first delay of the target data passing through the second sub-module in the first module, the first delay including the maximum delay Xmax1 and the minimum delay Xmin1.

[0336] S6: Report the maximum target delay Xmax1+4.78125 and the minimum target delay Xmin1+4.78125 to the MAC layer module.

[0337] In one example, Xmax1+4.78125 can be reported to the MAC layer module through the TX maximum delay register of the internal code FEC, and Xmin1+4.78125 can be reported to the MAC layer module through the TX minimum delay register of the internal code FEC.

[0338] In another example, Xmax1+4.78125 can be reported to the MAC layer module through the TX maximum delay register of the PMA / PMD, and Xmin1+4.78125 can be reported to the MAC layer module through the TX minimum delay register of the PMA / PMD.

[0339] For a communication device acting as a receiver, its optical module can perform the following operations:

[0340] S4': Get the latency jitter value of 4.78125.

[0341] S5': Determine the first delay of the target data passing through the second sub-module in the first module, the first delay including the maximum delay Xmax2 and the minimum delay Xmin2.

[0342] S6': Report the maximum target delay Xmax2-4.78125 and the minimum target delay Xmin2-4.78125 to the MAC layer module.

[0343] In one example, Xmax2-4.78125 can be reported to the MAC layer module through the RX maximum delay register of the internal code FEC, and Xmin2-4.78125 can be reported to the MAC layer module through the RX minimum delay register of the internal code FEC.

[0344] In another example, Xmax2-4.78125 can be reported to the MAC layer module through the RX maximum delay register of the PMA / PMD, and Xmin2-4.78125 can be reported to the MAC layer module through the RX minimum delay register of the PMA / PMD.

[0345] It should be noted that, Figure 5 For ease of understanding of the internal code FEC processing procedure shown in this scheme, the internal code FEC processing procedure includes, in addition to, the following: Figure 5 In addition to the content shown, other content may be included. For example, after the sending end performs the distribution operation and before performing the internal code FEC processing, it may also perform a cyclic shift operation. Similarly, after the receiving end performs the internal code FEC processing and before performing the multiplexing operation, it may also perform a cyclic shift operation. In this case:

[0346] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0347] S7: Get the latency jitter value 4.78125 + 4.5 = 9.28125.

[0348] S8: Determine the first delay of the target data passing through the second sub-module in the first module, the first delay including the maximum delay Xmax3 and the minimum delay Xmin3.

[0349] S9: Report the maximum target delay Xmax3+9.28125 and the minimum target delay Xmin3+9.28125 to the MAC layer module.

[0350] In one example, Xmax3+9.28125 can be reported to the MAC layer module through the TX maximum delay register of the internal code FEC, and Xmin3+9.28125 can be reported to the MAC layer module through the TX minimum delay register of the internal code FEC.

[0351] In another example, Xmin3+9.28125 can be reported to the MAC layer module through the TX maximum delay register of the PMA / PMD, and Xmin3+9.28125 can be reported to the MAC layer module through the TX minimum delay register of the PMA / PMD.

[0352] For a communication device acting as a receiver, its optical module can perform the following operations:

[0353] S7': Get the latency jitter value 9.28125.

[0354] S8': Determine the first delay of the target data passing through the second sub-module in the first module, the first delay including the maximum delay Xmax4 and the minimum delay Xmin4.

[0355] S9': Report the maximum target delay Xmax4-9.28125 and the minimum target delay Xmin4-9.28125 to the MAC layer module.

[0356] In one example, Xmax4-9.28125 can be reported to the MAC layer module through the TX maximum delay register of the internal code FEC, and Xmin4-9.28125 can be reported to the MAC layer module through the TX minimum delay register of the internal code FEC.

[0357] In another example, Xmin4-9.28125 can be reported to the MAC layer module through the TX maximum delay register of the PMA / PMD, and Xmin4-9.28125 can be reported to the MAC layer module through the TX minimum delay register of the PMA / PMD.

[0358] Based on the latency reporting method provided in the above embodiments, this application also provides a corresponding device, which is described below with reference to the accompanying drawings.

[0359] See Figure 6 The figure is a schematic diagram of the structure of a delay reporting device provided in an embodiment of this application. Figure 6 The delay reporting device shown can be used to perform the methods provided in the above embodiments. Figure 2 The delay reporting method is shown.

[0360] like Figure 6 As shown, the delay reporting device 600 includes a sending unit 601.

[0361] The sending unit 601 is used to report the target delay corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream.

[0362] In one possible implementation, the period of the plurality of specific positions is an integer multiple of 8712 data blocks, or an integer multiple of 8704 data blocks, or an integer multiple of 64 data blocks, or an integer multiple of 65 data blocks.

[0363] In one possible implementation, the data block comprises 128 bits, 120 bits, or 4 bits.

[0364] In one possible implementation, the period of the plurality of specific positions is an integer multiple of any of the following values: 1,115,136 bits, 1,114,112 bits, or 1,044,480 bits, or 1,045,440 bits.

[0365] In one possible implementation, the specific position is the start position of the FEC codeword, which is the first bit, the first symbol, or the first byte of the FEC codeword.

[0366] In one possible implementation, the FEC codeword includes: FEC internal codeword.

[0367] In one possible implementation, the data stream is a data stream obtained by FEC internal code encoding, or the data stream is a data stream obtained by FEC internal code decoding.

[0368] In one possible implementation, the period for inserting the padding sequence into the data stream is an integer multiple of the period for inserting the check sequence into the data stream.

[0369] In one possible implementation, the target latency corresponds to the latency of the data passing through the optical module, or the target latency corresponds to the latency of the data passing through the internal code FEC layer in the optical module.

[0370] In one possible implementation, the device further includes a processing unit 602.

[0371] The processing unit 602 is used to measure the first time delay corresponding to the data at each specific location in the data at the plurality of specific locations, and obtain a plurality of first time delays; wherein, the target time delay includes the maximum value and / or minimum value among the plurality of first time delays.

[0372] In one possible implementation, the transmitting unit 601 is configured to: report the maximum value using the TX maximum delay register of the internal code FEC; and / or, report the minimum value using the TX minimum delay register of the internal code FEC.

[0373] In one possible implementation, the transmitting unit 602 is configured to: report the maximum value using the TX maximum delay register of the PMA / Physical Media-Associated PMD attached to the physical medium; and / or, report the minimum value using the TX minimum delay register of the PMA / PMD.

[0374] In one possible implementation, the transmitting unit 603 is configured to: report the maximum value using the RX maximum delay register of the internal code FEC; and / or, report the minimum value using the RX minimum delay register of the internal code FEC.

[0375] In one possible implementation, the transmitting unit 604 is configured to: report the maximum value using the RX maximum delay register of the PMA / PMD; and / or, report the minimum value using the RX minimum delay register of the PMA / PMD.

[0376] In one possible implementation, the sending unit 605 is configured to: report the target latency corresponding to the data at the plurality of specific locations in the data stream to the Media Access Control (MAC) layer.

[0377] In one possible implementation, the device is applied to an optical module or a physical PHY layer chip.

[0378] In one possible implementation, the optical module includes an internal code FEC module, which includes an internal code FEC encoding module and / or an internal code FEC decoding module.

[0379] In one possible implementation, the specific position is the starting position of the next data block after the insertion of the padding sequence in the data stream, and the starting position is the first bit, the first symbol, or the first byte of the next data block.

[0380] See Figure 7 The figure is a schematic diagram of another delay reporting device provided in an embodiment of this application. Figure 7 The delay reporting device shown can be used to perform the methods provided in the above embodiments. Figure 4 The delay reporting method is shown.

[0381] like Figure 7 As shown, the delay reporting device 700 includes a processing unit 701 and a sending unit 702.

[0382] Processing unit 701 is used to obtain the latency jitter value of target data passing through the first sub-module in the first module. The first sub-module includes a sub-module with a fixed latency jitter value. The target data is data sent by the first module, or the target data is data received by the first module. The latency jitter value is the preset fixed value.

[0383] The sending unit 702 is used to report latency information to the second module based on the latency jitter value.

[0384] In one possible implementation, the processing unit 701 is further configured to: determine a first delay in the target data passing through the second sub-module in the first module; and the sending unit 702 is configured to: report the delay information to the second module based on the delay jitter value and the first delay.

[0385] In one possible implementation, the sending unit 702 is configured to: report to the second module the target delay obtained based on the delay jitter value and the first delay.

[0386] In one possible implementation, the target latency includes: the sum of the latency jitter value and the first latency; or, the difference between the first latency and the latency jitter value.

[0387] In one possible implementation, the first delay includes: the maximum delay and the minimum delay of the target data passing through the second submodule; correspondingly, the target delay includes: the maximum target delay obtained based on the maximum delay and the delay jitter value, and the minimum target delay obtained based on the minimum delay and the delay jitter value.

[0388] In one possible implementation, if the target data is data sent by the first module, then the sending unit 702 is configured to: report the maximum target delay to the second module using the TX maximum delay register of the internal code forward error correction (FEC); and report the minimum target delay to the second module using the TX minimum delay register of the internal code FEC.

[0389] In one possible implementation, if the target data is data sent by the first module, then the sending unit 702 is configured to: report the maximum target latency to the second module using the TX maximum latency register of the Physical Medium Attached PMA / Physical Medium Dependent PMD; and report the minimum target latency to the second module using the TX minimum latency register of the PMA / PMD.

[0390] In one possible implementation, if the target data is the data received by the first module, then the sending unit 702 is configured to: report the maximum target delay to the second module using the RX maximum delay register of the internal code FEC; and report the minimum target delay to the second module using the RX minimum delay register of the internal code FEC.

[0391] In one possible implementation, if the target data is data received by the first module, then the sending unit 702 is configured to: report the maximum target delay to the second module using the RX maximum delay register of the PMA / PMD; and report the minimum target delay to the second module using the RX minimum delay register of the PMA / PMD.

[0392] In one possible implementation, the second submodule includes: submodules other than the first submodule.

[0393] In one possible implementation, the second submodule includes: a submodule in the internal code FEC module that performs convolutional interleaving, distribution, and modulation coding operations; or, a submodule in the internal code FEC module that performs deconvolutional deinterleaving, multiplexing, and modulation decoding operations.

[0394] In one possible implementation, the processing unit 701 is configured to: obtain a pre-set first delay.

[0395] In one possible implementation, the processing unit 701 is used to: calculate the first delay of the target data after passing through the second submodule.

[0396] In one possible implementation, the step of calculating the first delay of the target data passing through the second submodule includes: calculating the delay of at least one bit of the target data passing through the second submodule to obtain the first delay.

[0397] In one possible implementation, the processing unit 701 is further configured to: determine the second delay of the target data passing through the third sub-module in the first module; and the sending unit 702 is configured to: report the delay information to the second module based on the delay jitter value and the second delay.

[0398] In one possible implementation, the third submodule includes: a PMA submodule and / or a PMD submodule.

[0399] In one possible implementation, the second module includes a Media Access Control (MAC) layer module.

[0400] In one possible implementation, the fixed value is between 4.6 nanoseconds and 4.8 nanoseconds, or the fixed value is 4.5 nanoseconds, or the fixed value is between 9.1 nanoseconds and 9.3 nanoseconds.

[0401] In one possible implementation, the first submodule includes a cyclic shift submodule.

[0402] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to the addition or deletion of a check sequence or a padding sequence.

[0403] In one possible implementation, the first submodule includes a submodule that experiences latency jitter due to the interleaving or deinterleaving of data streams.

[0404] In one possible implementation, the first submodule includes: a submodule in the internal code FEC module that performs FEC internal code encoding, data stream interleaving, and padding sequence addition operations; or, a submodule in the internal code FEC module that performs FEC internal code decoding, data stream deinterleaving, and padding sequence deletion operations.

[0405] In one possible implementation, the target data comprises 8712*N data blocks or 8704*N data blocks, where N is a positive integer.

[0406] In one possible implementation, the data block comprises 128 bits or 120 bits.

[0407] In one possible implementation, the target data includes: 1115136*N bits, 1114112*N bits, or 1044480*N bits, or 1045440 bits, where N is a positive integer.

[0408] See Figure 8 The figure is a schematic diagram of the structure of a device provided in an embodiment of this application. Figure 8 The device 800 shown includes an interface circuit 801 and a processing circuit 802. The interface circuit 801 is used to receive and / or transmit data, and the processing circuit 802 is used to perform data processing.

[0409] In one example, the device 800 can be used to perform the methods provided in the above embodiments. Figure 2 The corresponding latency reporting method. For this situation:

[0410] The interface circuit 801 is used to report the target delay corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream; in one example, the processing circuit 802 is used to measure the first delay corresponding to the data at each of the multiple specific locations to obtain multiple first delays; wherein the target delay includes the maximum and / or minimum value among the multiple first delays.

[0411] In yet another example, the device 800 can be used to perform the methods provided in the above embodiments. Figure 4 The corresponding latency reporting method for this situation is as follows:

[0412] The processing circuit 802 is used to obtain the delay jitter value of the target data after passing through the first sub-module in the first module. The first sub-module includes a sub-module with a fixed delay jitter value. The target data is data sent by the first module or data received by the first module. The delay jitter value is a preset fixed value. The interface circuit 801 is used to report the delay information to the second module according to the delay jitter value.

[0413] See Figure 9 The figure is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0414] In one example Figure 9 The device 900 shown can be used to perform the methods provided in the above embodiments. Figure 2 The corresponding delay reporting method.

[0415] In yet another example, Figure 9 The device 900 shown can be used to perform the methods provided in the above embodiments. Figure 4 The corresponding delay reporting method.

[0416] Please see Figure 9 As shown, device 900 includes a processor 910. The number of processors 910 in device 900 can be one or more. Figure 9 Taking a processor as an example, the processor 910 is used to execute the methods provided in the above embodiments. Figure 2 The corresponding latency reporting method, or the processor 910 is used to execute the method provided in the above embodiments. Figure 4 The corresponding delay reporting method.

[0417] Processor 910 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 910 may include a digital signal processor (DSP). Processor 910 may further include hardware chips. The aforementioned hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0418] In one example, the device 900 further includes a memory 930. The memory 930 may include volatile memory, such as random-access memory (RAM); the memory 930 may also include non-volatile memory, such as flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 930 may also include combinations of the above types of memory. When the device 900 is used to perform the above method embodiments... Figure 2 When the corresponding latency reporting method is used, the memory 930 may, for example, store the aforementioned target latency. When the device is used to execute the method provided in the above embodiments... Figure 4 In the corresponding delay reporting method, the memory may, for example, store the aforementioned fixed value.

[0419] Optionally, the memory 930 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 910 can read the programs from the memory 930 to implement the methods provided in the embodiments of this application.

[0420] In one example, the device 900 further includes a communication interface 920. In this embodiment, the processor 910, the communication interface 920, and the memory 930 can be connected via a bus system or other means. Figure 9Taking the connection between China and Israel via the 940 bus system as an example.

[0421] The communication interface 920 is used to receive and / or send data. For example, when the device 900 is used to perform the above method embodiments, Figure 2 When the corresponding latency reporting method is used, the communication interface 910 is used to report the target latency corresponding to data at multiple specific locations in the data stream. When the device 900 is used to execute the method provided in the above embodiments... Figure 4 In the corresponding delay reporting method, the communication interface 910 is used to report delay information to the second module based on the delay jitter value.

[0422] The bus system 940 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 940 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0423] This application also provides a chip or optical module, the structure of which can be as follows: Figure 10 As shown. See also Figure 10 The figure is a schematic diagram of the structure of a chip or optical module provided in an embodiment of this application. Figure 10 The chip or optical module 1000 shown includes an interface circuit 1001 and a processing circuit 1002. The interface circuit 1001 is used to receive and / or transmit data, and the processing circuit 1002 is used to perform data processing.

[0424] In one example, the chip or optical module 1000 can be used to perform the above method embodiments and Figure 2 The corresponding latency reporting method. For this situation:

[0425] The interface circuit 1001 is used to report the target latency corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream. As an example, the processing circuit 1002 is used to measure the first latency corresponding to the data at each of the multiple specific locations, thereby obtaining multiple first latencys; wherein the target latency includes the maximum and / or minimum value among the multiple first latencys.

[0426] In yet another example, the chip or optical module 1000 can be used to perform the above-described method embodiments and... Figure 4 The corresponding latency reporting method. For this situation:

[0427] The processing circuit 1002 is used to obtain the latency jitter value of the target data after passing through the first sub-module in the first module. The first sub-module includes a sub-module with a fixed latency jitter value. The target data is data sent by the first module, or the target data is data received by the first module, wherein the latency jitter value is a preset fixed value. The interface circuit 1001 is used to report latency information to the second module based on the latency jitter value.

[0428] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above-described method embodiments. For example, it causes the computer to perform the methods provided in the above-described method embodiments. Figure 2 The corresponding latency reporting method; for example, enabling the computer to execute the methods provided in the above embodiments and... Figure 4 The corresponding delay reporting method.

[0429] This application provides a computer program product comprising instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above-described method embodiments. For example, it causes the computer to perform the methods provided in the above-described method embodiments. Figure 2 The corresponding latency reporting method; for example, enabling the computer to execute the methods provided in the above embodiments and... Figure 4 The corresponding delay reporting method.

[0430] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0431] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0432] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0433] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0434] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0435] If the integrated unit is implemented as a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0436] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0437] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0438] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A delay reporting method, characterized in that, The method includes: The report specifies the target latency corresponding to data at multiple specific locations in the data stream, with a fixed interval between the multiple specific locations, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream; wherein the period of the multiple specific locations is an integer multiple of 8712 data blocks, or the period of the multiple specific locations is an integer multiple of 8704 data blocks.

2. The method according to claim 1, characterized in that, The period of the plurality of specific locations is 8712 data blocks, or the period of the plurality of specific locations is 8704 data blocks.

3. The method according to claim 1 or 2, characterized in that, The periods at the plurality of specific positions correspond to the periods in which padding sequences are inserted into the data stream, including: The period of the plurality of specific positions is the period of the insertion of the padding sequence in the data stream.

4. The method according to claim 1 or 2, characterized in that, The data block consists of 128 bits.

5. The method according to claim 1 or 2, characterized in that, The period of the plurality of specific positions is an integer multiple of any of the following values: 1115136 bits, 1114112 bits.

6. The method according to claim 1 or 2, characterized in that, The specific position is the starting position of the FEC codeword, which is the first bit, the first symbol, or the first byte of the FEC codeword.

7. The method according to claim 6, characterized in that, The FEC codewords include: FEC internal codewords.

8. The method according to claim 1 or 2, characterized in that, The data stream is either a data stream encoded using FEC internal code, or a data stream decoded using FEC internal code.

9. The method according to claim 1 or 2, characterized in that, The period of inserting the padding sequence into the data stream is an integer multiple of the period of inserting the check sequence into the data stream.

10. The method according to claim 1 or 2, characterized in that, The target latency corresponds to the latency of the data passing through the optical module, or the target latency corresponds to the latency of the data passing through the internal code FEC layer in the optical module.

11. The method according to claim 1 or 2, characterized in that, The method further includes: Measure the first time delay corresponding to the data at each of the multiple specific locations to obtain multiple first delays; The target delay includes the maximum and / or minimum value among the plurality of first delays.

12. The method according to claim 11, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: Report the maximum value using the TX maximum delay register of the internal code FEC; and / or, The minimum value is reported using the TX minimum delay register of the internal code FEC.

13. The method according to claim 11, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: The maximum TX delay register of the PMA / Physical Media-Associated PMD attached to the physical medium is reported; and / or, Report the minimum value using the TX minimum delay register of PMA / PMD.

14. The method according to claim 11, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: Report the maximum value using the RX maximum delay register of the internal code FEC; and / or, The minimum value is reported using the RX minimum delay register of the internal code FEC.

15. The method according to claim 11, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: Report the maximum value using the RX maximum delay register of the PMA / PMD; and / or, Report the minimum value using the RX minimum delay register of PMA / PMD.

16. The method according to claim 1 or 2, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: Report the target latency corresponding to the data at the multiple specific locations in the data stream to the Media Access Control (MAC) layer.

17. The method according to claim 1 or 2, characterized in that, The method is applied to optical modules or physical PHY layer chips.

18. The method according to claim 17, characterized in that, The optical module includes an internal code FEC module, which includes an internal code FEC encoding module and / or an internal code FEC decoding module.

19. The method according to claim 1 or 2, characterized in that, The specific position is the starting position of the next data block after the padding sequence is inserted in the data stream, and the starting position is the first bit, the first symbol, or the first byte of the data block.

20. A time delay reporting device, characterized in that, The device includes: A sending unit is used to report the target latency corresponding to data at multiple specific locations in a data stream, wherein the multiple specific locations are spaced at a fixed length, and the period of the multiple specific locations corresponds to the period of the padding sequence inserted in the data stream; wherein the period of the multiple specific locations is an integer multiple of 8712 data blocks, or the period of the multiple specific locations is an integer multiple of 8704 data blocks.

21. A time delay reporting device, characterized in that, The apparatus is used to perform the method according to any one of claims 1 to 19.

22. A time delay reporting device, characterized in that, The device includes an interface circuit and a processing circuit; The interface circuit is used to perform data transmission and / or reception operations in any of the methods described in claims 1 to 19, and the interface circuit is used to perform data processing operations in any of the methods described in claims 1 to 19.

23. The apparatus according to claim 22, wherein the apparatus comprises: Optical module, or chip.

24. A device, characterized in that, include: Processor and memory; The memory is used to store instructions or computer programs; The processor is configured to execute the instructions or computer program to perform the method described in any one of claims 1-19.

Images