Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises: a substrate; a plurality of gate lines; a plurality of data lines; a plurality of sub-pixel electrodes, wherein at least one of the plurality of sub-pixel electrodes comprises a first sub-pixel electrode group and a second sub-pixel electrode group; each of the first sub-pixel electrode group and the second sub-pixel electrode group comprises two sub-pixel electrode parts which are arranged along the third direction and are electrically connected; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is larger than that of the second sub-pixel electrode group, and the two sub-pixel electrode parts of the first sub-pixel electrode group are located on the same side of the two second sub-pixel electrode parts of the second sub-pixel electrode group. And the third direction is crossed with the first direction and the second direction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) and the VA mode of the liquid crystal panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A is to use a special polymer material as the alignment film to precisely control the tilt of liquid crystal molecules along the ultraviolet direction. The precision unit is picometer (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel has a simple structure without protrusions or slits. This "dream of liquid crystal technicians" was explored as early as 30 years ago. It was not until today that with the three conditions of new materials, production equipment, and a perfect processing process, this dream has come true. The simple-structured liquid crystal panel can not only improve production efficiency but also has many advantages in image quality. Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] A substrate;

[0006] A plurality of gate lines located on one side of the substrate, the plurality of gate lines extending along a first direction;

[0007] A plurality of data lines located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction;

[0008] A plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes including: a first sub-pixel electrode group, and a second sub-pixel electrode group; both the first sub-pixel electrode group and the second sub-pixel electrode group include: two sub-pixel electrode parts arranged along a third direction and electrically connected; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than that of the second sub-pixel electrode group, and the two sub-pixel electrode parts of the first sub-pixel electrode group are located on the same side of the two sub-pixel electrode parts of the second sub-pixel electrode group, and the third direction intersects with the first direction and the second direction.

[0009] In a possible implementation manner, the two sub-pixel electrode parts of the first sub-pixel electrode group are respectively: a first sub-pixel electrode part, a second sub-pixel electrode part; the two sub-pixel electrode parts of the second sub-pixel electrode group are respectively: a third sub-pixel electrode part, a fourth sub-pixel electrode part;

[0010] The second sub-pixel electrode portion is adjacent to the third sub-pixel electrode and is arranged along the first direction.

[0011] In a possible implementation manner, the first sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the second direction.

[0012] In a possible implementation manner, the fourth sub-pixel electrode portion is adjacent to the second sub-pixel electrode portion and is arranged along the second direction.

[0013] In a possible implementation manner, among the sub-pixel electrodes, the first sub-pixel electrode portion, the second sub-pixel electrode portion, and the third sub-pixel electrode portion are located on one side of the gate line to which the sub-pixel electrode is electrically connected, and the fourth sub-pixel electrode portion is located on the other side of the gate line to which the sub-pixel electrode is electrically connected.

[0014] In a possible implementation manner, the array substrate further includes: a first pixel connection portion and a second pixel connection portion;

[0015] In the same sub-pixel electrode, the first sub-pixel electrode portion and the second sub-pixel electrode portion are electrically connected through the first pixel connection portion, and the third sub-pixel electrode portion and the fourth sub-pixel electrode portion are electrically connected through the second pixel connection portion.

[0016] In a possible implementation manner, the first pixel connection portion extends along the third direction and electrically connects two opposite corners of the first sub-pixel electrode portion and the second sub-pixel electrode portion.

[0017] In a possible implementation manner, the second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein, the extension line of the second sub-connection portion is located on the side of the extension line of the first sub-connection portion close to the second sub-pixel electrode portion.

[0018] In a possible implementation manner, the array substrate further includes: a pixel driving circuit electrically connected to the sub-pixel electrode one by one, and a first trace extending along the second direction; the pixel driving circuit includes: a first transistor, a second transistor, and a third transistor;

[0019] The gate of the first transistor is electrically connected to the gate line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second sub-pixel electrode portion;

[0020] The gate of the second transistor is electrically connected to the gate line. The first pole of the second transistor multiplexes the first pole of the first transistor. The second pole of the second transistor is electrically connected to the fourth sub-pixel electrode portion.

[0021] The gate of the third transistor is electrically connected to the gate line. The first pole of the third transistor multiplexes the second pole of the second transistor. The second pole of the third transistor multiplexes part of the first trace.

[0022] In a possible implementation, the array substrate further includes: a first pixel overlapping portion electrically connected to the second sub-pixel electrode portion, and a second pixel overlapping portion electrically connected to the fourth sub-pixel electrode portion.

[0023] The orthographic projection of the first pixel overlapping portion on the substrate has an overlapping area with the orthographic projection of the second pole of the first transistor on the substrate. The second sub-pixel electrode portion is electrically connected to the second pole of the first transistor through the first pixel overlapping portion.

[0024] The orthographic projection of the second pixel overlapping portion on the substrate has an overlapping area with the orthographic projection of the second pole of the second transistor on the substrate. The fourth sub-pixel electrode portion is electrically connected to the second pole of the second transistor through the second pixel overlapping portion.

[0025] In a possible implementation, the second pixel overlapping portion includes: a first sub-overlapping portion, and a second sub-overlapping portion connecting the first sub-overlapping portion and the fourth sub-pixel electrode.

[0026] There is a gap between the first sub-overlapping portion and the fourth sub-pixel electrode.

[0027] In a possible implementation, the first pixel overlapping portion has two first sides extending along the second direction; the second pixel overlapping portion has two second sides extending along the second direction.

[0028] The orthographic projection of one of the first sides on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; the orthographic projection of one of the second sides on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

[0029] In a possible implementation, the second pole of the first transistor includes: a first main portion extending along the first direction, and a first branch portion extending from one end of the first main portion along the second direction; the orthographic projection of the first main portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the first branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

[0030] The second pole of the second transistor includes: a second main portion extending along the first direction, and a second branch portion extending from one end of the first main portion along the first direction; a positive projection of the second main portion on the substrate has an overlapping area with a positive projection of the second pixel overlapping portion on the substrate; a positive projection of the second branch portion on the substrate has an overlapping area with a positive projection of the gate line on the substrate.

[0031] In a possible implementation manner, the first trace includes: multiple first trace main portions extending along the second direction, and first trace bending portions connecting adjacent two of the first trace main portions;

[0032] A positive projection of the first trace main portion on the substrate has an overlapping area with a positive projection of a gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the substrate; a positive projection of the first trace bending portion on the substrate has an overlapping area with a positive projection of the gate line on the substrate and bends toward the side of the third transistor.

[0033] In a possible implementation manner, the array substrate further includes: multiple first common trace groups extending along the second direction; each common trace group includes: a first sub-common trace located on one side of the gate line, and a second sub-common trace located on the other side of the gate line;

[0034] The first sub-common trace includes: a first sub-common trace main portion, and a first sub-common trace convex portion extending from the first sub-common trace main portion toward the side of the gate line; the second sub-common trace includes: a second sub-common trace main portion, and a second sub-common trace convex portion extending from the second sub-common trace main portion toward the side of the gate line;

[0035] A positive projection of the first sub-common trace convex portion on the substrate has an overlapping area with a positive projection of the first pixel overlapping portion on the substrate; a positive projection of the second sub-common trace convex portion on the substrate has an overlapping area with a positive projection of the second pixel overlapping portion on the substrate.

[0036] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure, and further includes an opposing substrate disposed opposite to the array substrate, and a common electrode layer is disposed on a side of the opposing substrate facing the array substrate.

[0037] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. Description of the Drawings

[0038] Figure 1Schematic diagram of sub-pixel distribution for 1P4D;

[0039] Figure 2 Schematic diagram of the principle of dark streaks appearing in a conventional SUVA pixel design;

[0040] Figure 3A Top view schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0041] Figure 3B For Figure 3A Single film layer schematic diagram of the gate line layer in

[0042] Figure 3C For Figure 3A Single film layer schematic diagram of the data line layer in

[0043] Figure 3D For Figure 3A Single film layer schematic diagram of the active layer in

[0044] Figure 3E For Figure 3A Single film layer schematic diagram of the first insulating layer in

[0045] Figure 3F For Figure 3A Single film layer schematic diagram of the first electrode layer in

[0046] Figure 3G For Figure 3A Single film layer schematic diagram of the second insulating layer in

[0047] Figure 3H For Figure 3A Single film layer schematic diagram of the pixel electrode layer in

[0048] Figure 3I For Figure 3A Magnified schematic diagram at the dashed box S in

[0049] Figure 4 Connection schematic diagram of a sub-pixel electrode provided by an embodiment of the present disclosure;

[0050] Figure 5 Equivalent schematic diagram of a sub-pixel electrode circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0051] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] As used herein, "about" or "substantially the same" includes the stated value and means within an acceptable deviation range for the specific value as determined by one of ordinary skill in the art in view of the measurements being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference from the stated value is within one or more standard deviation ranges, or within ±30%, 20%, 10%, 5%.

[0054] In the drawings, the thicknesses of layers, films, panels, regions, etc. are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but include deviations in shape resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Additionally, the sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

[0055] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted from this disclosure.

[0056] Compared to the UV2A pixel design, Super Ultra-Violet Alignment (SUVA) is an upgraded version of UV2A, combining Figure 1 and Figure 2 as shown, wherein, Figure 1The SUVA pixel design is a 1P4D (4 domain regions in one sub-pixel) design. Compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark streaks of the pixels. However, as Figure 2 shown, there are still dark streaks in the liquid crystal region 1-2 between the liquid crystal region 1 and the liquid crystal region 2, which still affect the color shift characteristics of the panel. Therefore, a multi-domain method must be adopted to further improve the color shift.

[0057] In view of this, as shown in Figures 3A - 3I and Figure 4 , among which, Figure 3A is a top view schematic diagram of an array substrate provided by an embodiment of the present disclosure, Figure 3B is Figure 3A a single film layer schematic diagram of the gate line layer in Figure 3C is Figure 3A a single film layer schematic diagram of the data line layer in Figure 3D is Figure 3A a single film layer schematic diagram of the active layer in Figure 3E is Figure 3A a single film layer schematic diagram of the first insulating layer in Figure 3F is Figure 3A a single film layer schematic diagram of the first electrode layer in Figure 3G is Figure 3A a single film layer schematic diagram of the second insulating layer in Figure 3H is Figure 3A a single film layer schematic diagram of the pixel electrode layer in Figure 3I is Figure 3A an enlarged schematic diagram of the dashed box S in Figure 4 is a connection schematic diagram of a sub-pixel electrode provided by an embodiment of the present disclosure. An embodiment of the present invention provides an array substrate, which includes:

[0058] Substrate 1;

[0059] A plurality of gate lines 2, located on one side of the substrate 1, and the plurality of gate lines 2 extend along the first direction X;

[0060] A plurality of data lines 3, on the same side of the substrate 1 as the plurality of gate lines 2, and the plurality of data lines 3 extend in the second direction Y;

[0061] A plurality of sub-pixel electrodes 4, at least one sub-pixel electrode 4 among the plurality of sub-pixel electrodes 4 includes: a first sub-pixel electrode group PA, and a second sub-pixel electrode group PB; both the first sub-pixel electrode group PA and the second sub-pixel electrode group PB include: two sub-pixel electrode portions P0 arranged along a third direction Z and electrically connected; in the same sub-pixel electrode 4, the brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, and the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z, and the third direction Z intersects with the first direction X and the second direction Y. As Figure 3A As shown in, H represents the brighter sub-pixel electrode portion P0 in a sub-pixel electrode 4, and L represents the darker sub-pixel electrode portion P0. It should be noted that here, brighter means more backlight is transmitted, and darker means less backlight is transmitted. That is, when different sub-pixel electrode portions P0 are applied with different voltages, the pressure differences formed with the common electrode of the counter substrate are different. The greater the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the sub-pixel electrode portion P0. On the contrary, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the sub-pixel electrode portion P0.

[0062] In the embodiments of the present disclosure, the sub-pixel electrode 4 includes: a first sub-pixel electrode group PA, and a second sub-pixel electrode group PB. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, and the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z. When realizing that a sub-pixel electrode 4 includes two brighter sub-pixel electrode portions P0 and two darker sub-pixel electrode portions P0, the wiring can be simplified, the wiring complexity of the array substrate can be reduced, and thus the defect rate of the array substrate can be reduced. It is also beneficial to realize multi-domains and improve color shift; moreover, the centers of the two brighter sub-pixel electrode portions P0 and the two darker sub-pixel electrode portions P0 form a rhombus shape, so that the array substrate is bright and dark cross-distributed in both the first direction X and the second direction Y, and the horizontal and vertical dark stripe problems can also be improved.

[0063] In a possible implementation manner, the included angle formed by the third direction Z and the first direction X can be 30° to 60°, specifically, for example, it can be 45°.

[0064] Specifically, the array substrate may further include a pixel driving circuit corresponding to each sub-pixel electrode 4. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, which can be understood as that under the drive of the pixel driving circuit, the brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB.

[0065] In a possible implementation, the array substrate may include a plurality of rows of sub-pixel electrode portions extending along a first direction X and arranged along a second direction Y. Two rows of sub-pixel electrode portions may be distributed between two adjacent gate lines 2. Among them, the four sub-pixel electrode portions P0 of one sub-pixel electrode 4 may be distributed in three rows of sub-pixel electrode portions.

[0066] In a possible implementation, in combination with Figure 3A As shown, the sub-pixel electrode portion P0 may be provided with a slit F. Each sub-pixel electrode portion P0 may further include a first sub-portion P01 and a second sub-portion P02 arranged along the second direction Y. The extending directions of the slits F of the first sub-portion P01 and the second sub-portion P02 in the same sub-pixel electrode portion P0 are different.

[0067] In a possible implementation, in combination with Figure 3A As shown, in the same row of sub-pixel electrode portions, the extending directions of the slits F of two adjacent first sub-portions P01 in the first direction X are the same, and the extending directions of the slits F of two adjacent second sub-portions P02 in the first direction X are the same; in the two rows of sub-pixel electrode portions between two adjacent gate lines 2, the extending direction of the slit F of the first sub-portion P01 in one row of sub-pixel electrode portions is the same as the extending direction of the slit F of the second sub-portion P02 in the other row of sub-pixel electrode portions; the extending direction of the slit F of the second sub-portion P02 in one row of sub-pixel electrode portions is the same as the extending direction of the slit F of the first sub-portion P01 in the other row of sub-pixel electrode portions.

[0068] In a possible implementation, in combination with Figure 3A As shown, in one row of sub-pixel electrode portions, the included angle range between the extending direction of the slit F in the first sub-portion P01 and the first direction X may be 130° to 160°. Specifically, for example, it may be 145°. The included angle range between the extending direction of the slit F in the second sub-portion P02 and the first direction X may be 30° to 60°. Specifically, for example, it may be 45°; in the other row of sub-pixel electrode portions, the included angle range between the extending direction of the slit F in the first sub-portion P01 and the first direction X may be 30° to 60°. Specifically, for example, it may be 45°. The included angle range between the extending direction of the slit F in the second sub-portion P02 and the first direction X may be 130° to 160°. Specifically, for example, it may be 145°.

[0069] In a possible implementation, in combination with Figure 3A and Figure 3HAs shown, the two sub-pixel electrode parts P0 of the first sub-pixel electrode group PA are respectively: the first sub-pixel electrode part P1 and the second sub-pixel electrode part P2; the two sub-pixel electrode parts P0 of the second sub-pixel electrode group PB are respectively: the third sub-pixel electrode part P3 and the fourth sub-pixel electrode part P4; the second sub-pixel electrode part P2 is adjacent to the third sub-pixel electrode P3 and is arranged along the first direction X.

[0070] In a possible implementation manner, in combination with Figure 3A and Figure 3H As shown, the first sub-pixel electrode part P1 is adjacent to the third sub-pixel electrode part P3 and is arranged along the second direction Y.

[0071] In a possible implementation manner, in combination with Figure 3A and Figure 3H As shown, the fourth sub-pixel electrode part P4 is adjacent to the second sub-pixel electrode part P2 and is arranged along the second direction Y.

[0072] In a possible implementation manner, in combination with Figure 3A and Figure 3H As shown, in the sub-pixel electrode 4, the first sub-pixel electrode part P1, the second sub-pixel electrode part P2, and the third sub-pixel electrode part P3 are located on one side of the gate line 2 to which the sub-pixel electrode 4 is electrically connected, and the fourth sub-pixel electrode part P4 is located on the other side of the gate line 2 to which the sub-pixel electrode 4 is electrically connected.

[0073] It can be understood that the sub-pixel electrode 4 is electrically connected to the source or drain of the transistor, and the gate of the transistor is electrically connected to the gate line 2.

[0074] In a possible implementation manner, in combination with Figure 3H As shown, the array substrate further includes: a first pixel connection part 41 and a second pixel connection part 42; in the same sub-pixel electrode 4, the first sub-pixel electrode part P1 and the second sub-pixel electrode part P2 are electrically connected through the first pixel connection part 41, and the third sub-pixel electrode part P3 and the fourth sub-pixel electrode part P4 are electrically connected through the second pixel connection part 42.

[0075] In the embodiments of the present disclosure, the first sub-pixel electrode part P1 and the second sub-pixel electrode part P2 are electrically connected through the first pixel connection part 41, and the third sub-pixel electrode part P3 and the fourth sub-pixel electrode part P4 are electrically connected through the second pixel connection part 42, which can enable the first sub-pixel electrode part P1 and the second sub-pixel electrode part P2 to be connected nearby, and the third sub-pixel electrode part P3 and the fourth sub-pixel electrode part P4 to be connected nearby, simplifying the wiring of the array substrate.

[0076] In a possible implementation manner, in combination with Figure 3HAs shown, the first pixel connection portion 41 extends along the third direction Z and is electrically connected to two opposite corners of the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2. In this way, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 can be connected nearby, simplifying the wiring of the array substrate.

[0077] In a possible implementation, in combination with Figure 3H As shown, the second pixel connection portion 42 includes: a first sub-connection portion 421 extending along the second direction Y, a second sub-connection portion 422, and a third sub-connection portion 423 extending along the third direction Z and connecting the first sub-connection portion 421 and the second sub-connection portion 422; wherein, the extension line of the second sub-connection portion 422 is located on the side of the extension line of the first sub-connection portion 421 close to the second sub-pixel electrode portion P2. In this way, the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 can be connected nearby, simplifying the wiring of the array substrate.

[0078] In a possible implementation, in combination with Figures 3A - 3I and Figure 5 As shown, where Figure 5 is the equivalent circuit diagram corresponding to a sub-pixel, the array substrate further includes: a pixel driving circuit electrically connected to the sub-pixel electrodes one by one, and a first trace 5 extending along the second direction Y; the pixel driving circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; specifically, the pixel driving circuit may further include a first capacitor C1 and a second capacitor C2;

[0079] The gate of the first transistor T1 is electrically connected to the gate line 2, the first pole TA of the first transistor T1 is electrically connected to the data line 3, and the second pole TB of the first transistor T1 is electrically connected to the second sub-pixel electrode portion P2; specifically, the second pole TB of the first transistor T1 can be electrically connected to the second sub-pixel electrode portion P2 through the first via K1 and the third via K3;

[0080] The gate of the second transistor T2 is electrically connected to the gate line 2, the first pole TA of the second transistor T2 multiplexes the first pole TA of the first transistor T1, and the second pole TB of the second transistor T2 is electrically connected to the fourth sub-pixel electrode portion P4; specifically, the second pole TB of the second transistor T2 can be electrically connected to the fourth sub-pixel electrode portion P4 through the second via K2 and the fourth via K4;

[0081] The gate of the third transistor T3 is electrically connected to the gate line 2, the first pole TA of the third transistor T3 multiplexes the second pole TB of the second transistor T2, and the second pole TB of the third transistor T3 multiplexes a part of the first trace 5.

[0082] Specifically, the array substrate further includes a first liquid crystal capacitor Cpx1 and a second liquid crystal capacitor Cpx2. Among them, the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode group PA and the common electrode layer of the counter substrate, and the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode group PB and the common electrode layer of the counter substrate. The first capacitor C1 can be formed by the first sub-pixel electrode group PA and the first sub-common trace 61, and the second capacitor C2 can be formed by the second sub-pixel electrode group PB and the second sub-common trace 62.

[0083] In an embodiment of the present invention, the first sub-pixel electrode group PA can be electrically connected to the gate line 1 and the data line 3 through the first transistor T1, and the second sub-pixel electrode group PB can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2. The second pole of the third transistor T3 is electrically connected to the first trace 5, and the storage capacitor in the second capacitor C2 corresponding to the second sub-pixel electrode group PB can be released to the first trace 5 through the third transistor T3. Furthermore, the brightness of the first sub-pixel electrode group PA can be made greater than the brightness of the second sub-pixel electrode group PB, so as to achieve different bright and dark pixels within the same sub-pixel electrode 4 and achieve the display effect of 8 domains.

[0084] In a possible implementation manner, as shown in Figure 3H the array substrate further includes: a first pixel overlapping portion 43 electrically connected to the second sub-pixel electrode portion P2, and a second pixel overlapping portion 44 electrically connected to the fourth sub-pixel electrode portion P4;

[0085] The orthographic projection of the first pixel overlapping portion 43 on the substrate 1 has an overlapping area with the orthographic projection of the second pole TB of the first transistor T1 on the substrate 1, and the second sub-pixel electrode portion P2 is electrically connected to the second pole TB of the first transistor T1 through the first pixel overlapping portion 43;

[0086] The orthographic projection of the second pixel overlapping portion 44 on the substrate 1 has an overlapping area with the orthographic projection of the second pole TB of the second transistor T2 on the substrate 1, and the fourth sub-pixel electrode portion T4 is electrically connected to the second pole TB of the second transistor T2 through the second pixel overlapping portion 44.

[0087] In a possible implementation manner, as shown in Figure 3H the second pixel overlapping portion 44 includes: a first sub-overlapping portion 441, and a second sub-overlapping portion 442 connecting the first sub-overlapping portion 441 and the fourth sub-pixel electrode P4; wherein, there is a gap between the first sub-overlapping portion 441 and the fourth sub-pixel electrode P4.

[0088] In a possible implementation manner, as shown in Figure 3HAs shown, the first pixel overlapping portion 43 has two first sides w1 extending along the second direction Y; the second pixel overlapping portion 44 has two second sides w2 extending along the second direction Y; the orthographic projection of one of the first sides w1 on the substrate 1 overlaps with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1; the orthographic projection of one of the second sides w2 on the substrate 1 overlaps with the orthographic projection of the first pixel overlapping portion 43 on the substrate 1.

[0089] In a possible implementation manner, the orthographic projections of the two first sides w1 on the substrate 1 may correspond to and coincide with the orthographic projections of the two second sides w2 on the substrate 1, that is, the first pixel overlapping portion 43 and the fourth sub-pixel electrode portion P4 are aligned in the second direction Y.

[0090] In a possible implementation manner, combined with Figure 3C As shown, the second pole TB of the first transistor T1 includes: a first main portion TB11 extending along the first direction X, and a first branch portion TB12 extending from one end of the first main portion TB11 along the second direction Y; the orthographic projection of the first main portion TB11 on the substrate 1 has an overlapping area with the orthographic projection of the first pixel overlapping portion 43 on the substrate 1; the orthographic projection of the first branch portion TB12 on the substrate 1 has an overlapping area with the orthographic projection of the gate line 2 on the substrate 1;

[0091] The second pole TB of the second transistor T2 includes: a second main portion TB21 extending along the first direction X, and a second branch portion TB22 extending from one end of the second main portion TB21 along the first direction X; the orthographic projection of the second main portion TB22 on the substrate 1 has an overlapping area with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1; the orthographic projection of the second branch portion TB22 on the substrate 1 has an overlapping area with the orthographic projection of the gate line 2 on the substrate 1.

[0092] In a possible implementation manner, combined with Figure 3A 、 Figure 3H and Figure 3I As shown, the first trace 5 includes: multiple first trace main portions 51 extending along the second direction Y, and first trace bending portions 52 connecting adjacent two first trace main portions 51;

[0093] The orthographic projection of the main portion 51 of the first trace on the substrate 1 has an overlapping region with the gap between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 in the orthographic projection on the substrate 1; the orthographic projection of the bent portion 52 of the first trace on the substrate 1 has an overlapping region with the orthographic projection of the gate line 2 on the substrate 1 and is bent toward the side of the third transistor T3. In the embodiment of the present disclosure, the first trace 5 further includes a bent portion 52 of the first trace, and the bent portion 52 of the first trace faces the side of the third transistor T3. In this way, the second pole TB of the third transistor T3 is reused to avoid a large distance between the first pole TA and the second pole TB of the third transistor T3 in the first direction X, which affects the performance of the third transistor T3.

[0094] In a possible implementation manner, as shown in Figure 3B the array substrate further includes: a plurality of first common trace groups 6 extending along the second direction Y; the common trace group 6 includes: a first sub-common trace 61 located on one side of the gate line 2, and a second sub-common trace 62 located on the other side of the gate line 6;

[0095] The first sub-common trace 61 includes: a main portion 611 of the first sub-common trace, and a convex portion 612 of the first sub-common trace extending from the main portion 611 of the first sub-common trace toward the side of the gate line 2; the second sub-common trace 62 includes: a main portion 621 of the second sub-common trace, and a convex portion 622 of the second sub-common trace extending from the main portion 621 of the second sub-common trace toward the side of the gate line 2;

[0096] The orthographic projection of the convex portion 612 of the first sub-common trace on the substrate 1 has an overlapping region with the orthographic projection of the first pixel overlapping portion 43 on the substrate 1, so as to form a first capacitor C1; the orthographic projection of the convex portion 622 of the second sub-common trace on the substrate 1 has an overlapping region with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1, so as to form a second capacitor C2.

[0097] In a possible implementation manner, as shown in Figures 3A - 3H the array substrate may sequentially be provided with, on one side of the substrate 1, a gate line layer as shown in Figure 3B , a data line layer as shown in Figure 3C , an active layer as shown in Figure 3D , a first insulating layer 91 as shown in Figure 3E , a first electrode layer as shown in Figure 3F , a second insulating layer 92 as shown in Figure 3G , and a pixel electrode layer as shown in Figure 3H ;

[0098] Among them, the active layer may include an active pattern 7 corresponding to the transistor;

[0099] The first insulating layer 91 may have a first via hole K1 and a second via hole K2; the first insulating layer 91 may be a first passivation layer or an organic ORG layer;

[0100] The first electrode layer may include a first hollow L1, a second hollow L2, a third hollow L3, and a fourth hollow L4. Among them, the first hollow L1 may correspond to two sub-pixel electrode portions P0 that are the same in the first direction X; the orthographic projection of the second hollow L2 on the substrate 1 and the orthographic projection of the first via hole K1 on the substrate 1 are such that the second sub-pixel electrode portion P2 is electrically connected to the second pole TB of the first transistor T1 through the second hollow portion L2; the orthographic projection of the third hollow L3 on the substrate 1 and the orthographic projection of the second via hole K2 on the substrate 1 are such that the fourth sub-pixel electrode portion P4 is electrically connected to the second pole TB of the second transistor T2 through the third hollow L3; the orthographic projection of the fourth hollow L4 on the substrate 1 may have an overlapping area with the orthographic projection of the gate line 2 on the substrate 1 to reduce the overlapping capacitance with the gate line 2; specifically, the first electrode layer may be a transparent electrode layer, and the material of the first electrode layer may be the same as the material of the pixel electrode layer;

[0101] The second insulating layer 92 may have a third via hole K3 and a fourth via hole K4; the second insulating layer 92 may be a second passivation layer;

[0102] In the embodiment of the present disclosure, the array substrate is further provided with a first electrode layer having a first hollow L1. The orthographic projection of the first electrode layer on the substrate 1 may cover at least part of the orthographic projection of the data line 3 on the substrate 1 and may cover at least part of the orthographic projection of the gate line 2 on the substrate 1, thereby shielding the coupling capacitance between the sub-pixel electrode 4 and the data line 3, and the coupling capacitance between the sub-pixel electrode 4 and the gate line 2, and improving the transmittance of the display panel.

[0103] Based on the same inventive concept, the array substrate provided in the embodiment of the present disclosure further includes an opposing substrate disposed opposite to the array substrate, and a common electrode layer is provided on the side of the opposing substrate facing the array substrate.

[0104] Based on the same inventive concept, the embodiment of the present disclosure provides a display device, which includes a display panel as provided in the embodiment of the present disclosure. For the implementation of this display device, reference may be made to the embodiment of the above display panel, and the repeated parts will not be described again.

[0105] In specific implementation, in the embodiment of the present disclosure, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of this display device should be understood by those of ordinary skill in the art and will not be described here, nor should they be regarded as a limitation to the present disclosure.

[0106] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn of the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present disclosure.

[0107] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, comprising: a substrate; a plurality of gate lines located on one side of the substrate, the plurality of gate lines extending in a first direction; a plurality of data lines located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending in a second direction; a plurality of sub - pixel electrodes, at least one of the plurality of sub - pixel electrodes comprising: a first sub - pixel electrode group and a second sub - pixel electrode group; both the first sub - pixel electrode group and the second sub - pixel electrode group comprise: two sub - pixel electrode portions arranged along a third direction and electrically connected; in the same sub - pixel electrode, the brightness of the first sub - pixel electrode group is greater than that of the second sub - pixel electrode group, and the two sub - pixel electrode portions of the first sub - pixel electrode group are located on the same side of the two sub - pixel electrode portions of the second sub - pixel electrode group, and the third direction intersects with the first direction and the second direction.

2. The array substrate according to claim 1, wherein, the two sub - pixel electrode portions of the first sub - pixel electrode group are respectively: a first sub - pixel electrode portion and a second sub - pixel electrode portion; the two sub - pixel electrode portions of the second sub - pixel electrode group are respectively: a third sub - pixel electrode portion and a fourth sub - pixel electrode portion; the second sub - pixel electrode portion is adjacent to the third sub - pixel electrode and arranged along the first direction.

3. The array substrate according to claim 2, wherein, the first sub - pixel electrode portion is adjacent to the third sub - pixel electrode portion and arranged along the second direction.

4. The array substrate according to claim 3, wherein, the fourth sub - pixel electrode portion is adjacent to the second sub - pixel electrode portion and arranged along the second direction.

5. The array substrate according to claim 4, wherein, in the sub - pixel electrode, the first sub - pixel electrode portion, the second sub - pixel electrode portion, and the third sub - pixel electrode portion are located on one side of the gate line to which the sub - pixel electrode is electrically connected, and the fourth sub - pixel electrode portion is located on the other side of the gate line to which the sub - pixel electrode is electrically connected.

6. The array substrate according to claim 4 or 5, wherein, the array substrate further comprises: a first pixel connection portion and a second pixel connection portion; in the same sub - pixel electrode, the first sub - pixel electrode portion and the second sub - pixel electrode portion are electrically connected through the first pixel connection portion, and the third sub - pixel electrode portion and the fourth sub - pixel electrode portion are electrically connected through the second pixel connection portion.

7. The array substrate according to claim 6, wherein, the first pixel connection portion extends along the third direction and electrically connects two opposite corners of the first sub - pixel electrode portion and the second sub - pixel electrode portion.

8. The array substrate according to claim 6 or 7, wherein, The second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein, the extension line of the second sub-connection portion is located on the side of the extension line of the first sub-connection portion closer to the second sub-pixel electrode portion.

9. The array substrate according to any one of claims 5-8, wherein, the array substrate further includes: a pixel driving circuit electrically connected to the sub-pixel electrodes one by one, and a first trace extending along the second direction; the pixel driving circuit includes: a first transistor, a second transistor, and a third transistor; the gate of the first transistor is electrically connected to the gate line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second sub-pixel electrode portion; the gate of the second transistor is electrically connected to the gate line, the first pole of the second transistor multiplexes the first pole of the first transistor, and the second pole of the second transistor is electrically connected to the fourth sub-pixel electrode portion; the gate of the third transistor is electrically connected to the gate line, the first pole of the third transistor multiplexes the second pole of the second transistor, and the second pole of the third transistor multiplexes a part of the first trace.

10. The array substrate according to claim 9, wherein, the array substrate further includes: a first pixel overlapping portion electrically connected to the second sub-pixel electrode portion, and a second pixel overlapping portion electrically connected to the fourth sub-pixel electrode portion; the orthographic projection of the first pixel overlapping portion on the substrate has an overlapping area with the orthographic projection of the second pole of the first transistor on the substrate, and the second sub-pixel electrode portion is electrically connected to the second pole of the first transistor through the first pixel overlapping portion; the orthographic projection of the second pixel overlapping portion on the substrate has an overlapping area with the orthographic projection of the second pole of the second transistor on the substrate, and the fourth sub-pixel electrode portion is electrically connected to the second pole of the second transistor through the second pixel overlapping portion.

11. The array substrate according to claim 10, wherein, the second pixel overlapping portion includes: a first sub-overlapping portion, and a second sub-overlapping portion connecting the first sub-overlapping portion and the fourth sub-pixel electrode; there is a gap between the first sub-overlapping portion and the fourth sub-pixel electrode.

12. The array substrate according to claim 10 or 11, wherein, the first pixel overlapping portion has two first sides extending along the second direction; the second pixel overlapping portion has two second sides extending along the second direction; the orthographic projection of one of the first sides on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; the orthographic projection of one of the second sides on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

13. The array substrate according to any one of claims 10-12, wherein, The second pole of the first transistor includes: a first main portion extending along the first direction, and a first branch portion extending from one end of the first main portion along the second direction; the orthographic projection of the first main portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the first branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate. The second pole of the second transistor includes: a second main portion extending along the first direction, and a second branch portion extending from one end of the first main portion along the first direction; the orthographic projection of the second main portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate; the orthographic projection of the second branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

14. The array substrate according to any one of claims 9-13, wherein, The first trace includes: a plurality of first trace main portions extending along the second direction, and a first trace bending portion connecting adjacent two of the first trace main portions; The orthographic projection of the first trace main portion on the substrate has an overlapping area with the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthographic projection on the substrate; the orthographic projection of the first trace bending portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate and bends toward the side of the third transistor.

15. The array substrate according to any one of claims 10-14, wherein, The array substrate further includes: a plurality of first common trace groups extending along the second direction; each common trace group includes: a first sub-common trace located on one side of the gate line, and a second sub-common trace located on the other side of the gate line; The first sub-common trace includes: a first sub-common trace main portion, and a first sub-common trace convex portion extending from the first sub-common trace main portion toward the gate line side; the second sub-common trace includes: a second sub-common trace main portion, and a second sub-common trace convex portion extending from the second sub-common trace main portion toward the gate line side; The orthographic projection of the first sub-common trace convex portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the second sub-common trace convex portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate.

16. A display panel, wherein, It includes the array substrate according to any one of claims 1-15, and further includes an opposing substrate disposed opposite to the array substrate, and a common electrode layer is provided on the side of the opposing substrate facing the array substrate.

17. A display device, wherein, It includes the display panel according to claim 16.

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