Signal correlation operation hardware circuit structure based on random calculation and design method thereof

Abstract

The invention provides a design method of a signal correlation operation hardware circuit structure based on random calculation. The circuit structure comprises a binary data conversion circuit, a conjugate multiplication circuit and an N-input k-time scaling adder circuit. The design method comprises the following steps of: 1, setting the length of a shorter signal in two paths of complex signals as N, selecting data with the same length from the longer signal, and calculating a conjugate product result of the data and the shorter signal; 2, calculating a conjugate product result of the two random bit streams; 3, performing summation operation on a real part and an imaginary part of the random data stream by adopting an N-input random adder; 4, the random bit data stream is converted into binary data again; 5, selecting N continuous data from the long signals to be correlated again, and repeating the step 1 to the step 4 to obtain correlation values of the N data and the short signals; and repeating the step until all the data in the longer signal complete the correlation operation with the shorter signal.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and relates to a hardware circuit structure for signal correlation operations based on stochastic computing and a design method thereof. Background Art

[0002] Signal correlation operation is a basic operation method in signal processing, which is used to measure the similarity or correlation between two signals. Signal correlation can be used to calculate the cross-correlation result of a received signal and a local signal, determine the frequency difference and phase difference between the received signal and the local signal to achieve signal synchronization. Signal correlation can also be used for matched filtering to realize the demodulation of the received signal. In addition, signal correlation can be used for signal estimation and channel equalization to compensate for the distortion of the signal during transmission. In short, signal correlation plays an important role in the communication field, and its application can effectively improve the performance of the communication system.

[0003] However, in signal correlation calculations, a large number of multiplication calculations are involved. In real number multiplication calculations based on binary calculations, if two data are quantized using n bits, a total of n additions are required in the multiplication operation. In the communication field, the two signals in the correlation calculation are mainly complex signals. Compared with real number multiplication, the calculation amount of complex number multiplication is larger, and the hardware resources consumed are more significant.

[0004] Stochastic computing (SC), as a new type of computing paradigm, its basic principle lies in converting binary data into a random bit data stream, so as to use the probability value of logical value 1 in the random bit data stream to represent the information contained in the data stream. Therefore, SC converts complex binary operations into the calculation process of a single-bit data stream, and can implement complex calculation tasks through simple bit operations, greatly reducing the hardware resource overhead of the system, thereby improving the calculation efficiency of the hardware platform.

[0005] Therefore, in view of the problems of high calculation complexity and large hardware resource overhead when traditional binary calculations perform signal correlation operations, the present invention proposes a hardware circuit structure for signal correlation operations based on SC and a design method thereof, which utilizes SC to greatly simplify the complexity of the hardware circuit and reduce the hardware resource overhead of the correlation operation. Summary of the Invention

[0006] The object of the present invention is to provide a hardware circuit structure for signal correlation operations based on stochastic computing and a design method thereof, so as to reduce the resource overhead of the hardware system and improve the calculation efficiency of the system.

[0007] To achieve the above object, a hardware circuit structure for signal correlation operations based on stochastic computing proposed by the present invention includes:

[0008] A complete computing circuit structure includes several parts such as a binary data conversion circuit, a conjugate multiplication circuit, and an N-input k-fold scaled adder circuit. More specifically, the binary data conversion circuit includes a random number generator and a comparator. The conjugate multiplication circuit includes an inverter based on a NOT gate, a multiplier based on an XNOR gate, and a scaled adder based on a 2-way selector. The N-input k-fold scaled adder circuit includes a multiplier based on an XNOR gate and a two-input non-scaled adder. The two-input non-scaled adder includes a multiplexer, an adder, a subtractor, and a comparator. The specific structure of the above circuits can be seen in Appendix Figure 1 ~Appendix Figure 7 .

[0009] Based on the proposed circuit structure, two binary input data are converted into a single-bit random data stream through the binary conversion circuit. After that, the conjugate product result of the two random data streams is calculated through the random conjugate multiplication circuit. Then, after calculating the correlation result of the two input data through the N-input k-fold scaled random adder, finally, the single-bit random data stream is converted into binary data through an accumulator, a subtractor, a multiplier, and a divider.

[0010] Based on the above circuit structure, the present invention also proposes a design method for this circuit structure, and the specific steps are as follows:

[0011] Step 1, assume that the length of the shorter signal among the two complex signals is N, select data of the same length from the longer signal, and calculate the conjugate product result with the shorter signal.

[0012] In order to adopt the SC-based computing scheme, it is necessary to convert two data to be correlated with a length of N into corresponding random bit data streams through 4N binary data conversion circuits. Since the real part and the imaginary part of a complex number cannot be represented by one random bit data stream simultaneously in SC, each data stream contains two random bit sequences for the real part and the imaginary part.

[0013] The binary data conversion circuit mainly includes a random number generator and a comparator. The random number generator can generate a random number at each working clock, compare it with the binary to be converted. If the binary data is greater than the generated random number, the logical value 1 is output, otherwise the logical value 0 is input. The mathematical formula of the binary data conversion circuit can be expressed as:

[0014]

[0015] where X is the input binary data, r(t) is a series of random numbers generated by the random number generator, and x(t) is the converted random bit data stream.

[0016] In the field of communication, the binary numbers generally processed are signed numbers. To simplify the discussion, it is assumed that the range of the binary input signal is [-1, 1]. In SC, since the binary values are converted into the probability values of logical 1 in the random bit stream, and the range of the probability values is [0, 1]. Therefore, when the binary data passes through the signal conversion circuit, a mapping process occurs, and the mapping formula can be expressed as:

[0017]

[0018] where P x represents the probability value of logical 1.

[0019] Step 2: Calculate the conjugate product result of two random bit streams.

[0020] Suppose one of the two complex numbers to be multiplied conjugately is expressed as a + jb, and the other is expressed as c + jd. The calculation formula for the conjugate product of the two complex numbers can be expressed as:

[0021] (a + jb)*(c - jd) = (ac + bd) + j(bc - ad)

[0022] Therefore, an inverter, a multiplier, and a two-input adder are involved in the conjugate multiplication calculation process.

[0023] Based on the data mapping process in Step 1, the mathematical formula of the inverter can be expressed as:

[0024]

[0025] where P x is the probability value of the random bit stream corresponding to the opposite number of x and the corresponding random bit stream.

[0026] Therefore, the truth table of the inverter is:

[0027]

[0028] According to the truth table of the inverter, it can be seen that the inverter is essentially equivalent to a NOT gate circuit, as Figure 2 shown.

[0029] Next, it is necessary to use the SC multiplier to calculate the product of the binary data represented by two random bits, and its calculation formula can be expressed as:

[0030]

[0031] where P x1 and P x2 are the probability values of the random bit streams converted from the two binary data to be multiplied, and P yThe probability value of the random bit stream represented by the product result of two binary data.

[0032] The truth table corresponding to the multiplier is:

[0033] <![CDATA[P x1 > <![CDATA[P x2 > <![CDATA[P y > 0 0 1 0 1 0 1 0 0 1 1 1

[0034] Therefore, the calculation circuit of the multiplier is an exclusive-NOR gate, as Figure 3 shown. In addition, according to the calculation circuit of the inverter, the calculation circuit of the inverse multiplier is an exclusive-OR gate.

[0035] In order to obtain the final complex product result, a two-input adder is also required to perform a summation operation. Since the maximum probability in SC cannot exceed 1, in order to prevent the probability value from exceeding 1, the summation result is scaled by 1 / 2 during the addition operation, and its calculation formula can be expressed as:

[0036]

[0037] where, P x1 and P x2 are the probability values of the random bit streams converted from two binary data, and P y is the probability value of the random bit stream represented by the summation result of two binary data.

[0038] The calculation circuit of the two-input scaled adder can be equivalent to a 2-to-1 multiplexer, as Figure 4 shown, and the truth table of the two-input scaled adder is:

[0039] <![CDATA[P x1 > <![CDATA[P x2 > Sel <![CDATA[P y > 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

[0040] Therefore, based on the above inverter, multiplier and two-input adder, the conjugate multiplication calculation circuit based on SC is as Figure 5 shown.

[0041] Step 3: Use an N-input random adder to perform a summation operation on the real part and the imaginary part of the random data stream.

[0042] Since the probability value in SC cannot exceed 1, it is necessary to ensure that the summation result does not exceed 1 during the summation calculation. However, considering that the N input data cannot reach the maximum value at the same time, if the summation result is scaled to 1 / N of the original, the summation result will be too small and the accuracy of the calculation result will be low.

[0043] In order to ensure that the summation result does not exceed the range and prevent excessive scaling, an N-input adder with k-fold scaling is used for summation in this step, and its mathematical formula can be expressed as:

[0044]

[0045] Among them, represents the probability value after summing k data out of N input binary data after k-fold scaling, represents that N data streams are divided into M groups in total with every k data as a group. In the formula, represents rounding down.

[0046] Since the binary data has been scaled and biased when converting binary to random bit stream in step 1. Therefore, when summing, in order to calculate the binary summation result corresponding to the random bit data stream, the N-input k-fold scaling adder needs to subtract a constant term with a value of for correction during the calculation process.

[0047] The truth table of the N-input k-fold scaling adder in this step is as follows:

[0048]

[0049] In order to simplify the discussion in the above truth table, only the truth table data under is shown. As introduced in step 2, through a k-way selector, according to we can obtain

[0050] According to the truth table, the hardware circuit of the N-input k-fold scaling adder is as shown in Figure 6 . The N data streams of input are divided into M + 1 groups, each group contains k data, and the positions lacking in the last group are filled with zeros. Each group of k data passes through a k-way selector, and then M + 1 data streams are obtained. At each moment, the M + 1 data streams are summed, and a correction data stream with a probability value of is subtracted. After the obtained result is summed with state n , when it is greater than 0, the output result is 1, otherwise the output result is 0. Finally, according to the output result, state n is corrected, and the entire calculation process can be completed.

[0051] Step 4, convert the random bit data stream back to binary data.

[0052] Since the binary has been scaled and biased when converting to data stream in step 1, therefore, in this step, an inverse mapping process is required, and its mathematical formula can be expressed as:

[0053]

[0054] Among them, L is the length of the random bit data stream. To convert the random bit stream back to binary data, first, a counter is needed to count the number of logical 1s in the random bit data stream. Then, multiply the statistical result by 2, subtract L, and finally divide the result by L to complete the conversion process from the random bit data stream to the binary result.

[0055] Step 5: Select N consecutive data from the longer signal to be correlated again, and repeat Steps 1 to 4 to obtain the correlation values of the N data with the shorter signal. Repeat this step until all the data in the longer signal have completed the correlation operation with the shorter signal.

[0056] In the present invention, through the random conjugate multiplier circuit and the N-input k-fold scaled random adder circuit, the calculation processes of complex conjugate multiplication and complex addition in the correlation operation are effectively realized. The entire calculation process adopts a calculation method based on a single-bit random data stream, and considering the compatibility with binary calculation, a mutual conversion scheme between binary data and random bit streams is supplemented in the circuit structure, constructing a complete SC-based circuit structure.

[0057] The advantages and beneficial effects of the present invention are as follows: The method of the present invention adopts the SC scheme in the signal correlation calculation process, and realizes the hardware circuit design of signal correlation calculation through random inverters, random multipliers, and random adders, effectively reducing the resource overhead of the system and improving the calculation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a schematic diagram of the signal correlation operation circuit based on random calculation proposed by the present invention.

[0059] Figure 2 It is a schematic diagram of the binary data conversion circuit adopted by the present invention.

[0060] Figure 3 It is a schematic diagram of the random inverter circuit adopted by the present invention.

[0061] Figure 4 It is a schematic diagram of the random multiplier circuit adopted by the present invention.

[0062] Figure 5 It is a schematic diagram of the two-input scaled random adder circuit adopted by the present invention.

[0063] Figure 6 It is a schematic diagram of the random conjugate multiplier circuit adopted by the present invention.

[0064] Figure 7 It is a schematic diagram of the N-input k-fold scaled random adder circuit proposed by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0065] The present invention will be further described in detail below in conjunction with embodiments.

[0066] Suppose two complex signals to be correlated. One is [-0.8 - 0.8j, -0.6 - 0.6j, -0.4 - 0.4j, -0.2 - 0.2j], and the other is [0.2 + 0.2j, 0.4 + 0.4j, 0.6 + 0.6j]. Under this condition, Figure 1 the random adder in

[0067] Next, the specific implementation scheme proposed by the present invention will be introduced in detail.

[0068] Step 1: First, select the first 3 data [-0.8 - 0.8j, -0.6 - 0.6j, -0.4 - 0.4j] from the signal with a sequence length of 4, and select all the data [0.2 + 0.2j, 0.4 + 0.4j, 0.6 + 0.6j] from the signal with a length of 3. Use 8 random number generators, and each random number generator generates 100 random numbers respectively. Compare the real and imaginary parts of the two signals to be correlated with the results of the random number generators. Suppose the first 10 random bits corresponding to -0.8 are [0, 0, 0, 0, 1, 0, 0, 0, 0, 0], the first 10 random bits corresponding to -0.6 are [0, 0, 0, 0, 1, 0, 0, 0, 0, 1], the first 10 random bits corresponding to -0.4 are [0, 0, 1, 0, 0, 1, 0, 0, 0, 1], the first 10 random bits corresponding to 0.2 are [1, 1, 0, 1, 0, 0, 1, 1, 0, 1], the first 10 random bits corresponding to 0.4 are [1, 1, 1, 0, 1, 0, 1, 0, 1, 1], and the first 10 random bits corresponding to 0.6 are [1, 1, 1, 0, 1, 1, 1, 0, 1, 1].

[0069] Step 2: Perform conjugate complex multiplication on two random bit data streams. Through random inverters, random adders, and two-input scaled random adders, the first 10 bits of the random bit data stream corresponding to the real part of the first complex number are [00 1 0 01 0 0 1 0], the first 10 bits of the random bit data stream corresponding to the imaginary part of the first complex number are [0 1 1 1 0 0 01 1 1], the first 10 bits of the random bit data stream corresponding to the real part of the second complex number are [0 0 0 1 1 1 0 1 0 1], the first 10 bits of the random bit data stream corresponding to the imaginary part of the second complex number are [0 1 0 0 1 0 0 0 0 0], the first 10 bits of the random bit data stream corresponding to the real part of the third complex number are [0 0 1 1 0 1 0 1 0 1], and the first 10 bits of the random bit data stream corresponding to the imaginary part of the third complex number are [0 1 1 0 0 0 0 0 0 0].

[0070] Step 3: Send the real and imaginary parts of the three complex numbers into a 3-input random adder respectively. Assume the scaling factor is 2, and the probability value of the corrected data stream in the random adder is set to 1 / 4. After completing the scaled addition operation of the random data stream, the first 10 bits of the random data stream after summing the real parts are [0 0 1 1 0 1 0 1 0 1], and the first 10 bits of the random data stream after summing the imaginary parts are [0 0 1 1 0 0 0 0 0 0].

[0071] Step 4: Count the number of logical 1s in the real and imaginary parts of the random bit data stream respectively, multiply by 2, subtract 100, and then divide by 100 to obtain the signal correlation result of this calculation.

[0072] Step 5: Re-select the 2nd - 4th data [-0.6 - 0.6j, -0.4 - 0.4j, -0.2 - 0.2j] in the signal with a length of 4, and repeat Steps 1 to 4 to calculate the result of the product accumulation.

[0073] In summary, a hardware circuit structure and its design method for signal correlation operations based on random calculation proposed by the present invention effectively reduce the resource overhead of the signal correlation calculation circuit and effectively improve the calculation efficiency of the hardware system by adopting random calculation instead of the traditional binary calculation scheme.

Claims

1. A design method for a signal correlation operation hardware circuit structure based on random computing, characterized in that: The steps include: Step 1: Assume that the length of the shorter signal of the two complex signals is N, select data of the same length from the longer signal, and calculate the conjugate product result with the shorter signal; Step 2, calculating the conjugate product result of two random bit streams; Step 3, using a random adder with N inputs to perform a sum operation on the real and imaginary parts of the random data stream; Step 4, reconverting the random bit data stream into binary data; Step 5: Select N consecutive data from the longer signal to be correlated again, repeat steps 1 to 4, and obtain the correlation values ​​of the N data with the shorter signal; repeat this step until all the data in the longer signal have completed the correlation operation with the shorter signal.

2. The design method of a signal correlation operation hardware circuit structure based on random calculation according to claim 1, characterized in that: In step 1, two data to be correlated with a length of N need to be converted into corresponding random bit data streams through 4N binary data conversion circuits; since in random calculation SC, the real part and the imaginary part of a complex number cannot be simultaneously represented by one random bit stream, each data stream contains two random bit sequences of the real part and the imaginary part; The binary data conversion circuit includes a random number generator and a comparator; the random number generator generates a random number at each working clock, compares it with the binary to be converted, and outputs a logic value of 1 if the binary data is greater than the generated random number, otherwise it inputs a logic value of 0; the formula of the binary data conversion circuit is expressed as: Where X is the input binary data, r(t) is a series of random numbers generated by the random number generator, and x(t) is the converted random bit data stream.

3. The method for designing a signal correlation operation hardware circuit structure based on random calculation according to claim 1 or 2, characterized in that: Assume that the binary input signal range is [-1, 1]; in SC, since the binary value is converted into the probability value of the logic value 1 in the random bit stream, and the probability value range is [0, 1]; therefore, the binary data undergoes a mapping process when passing through the signal conversion circuit, and the mapping formula is expressed as: Among them, P x It represents the probability value of logical value 1.

4. The design method of a signal correlation operation hardware circuit structure based on random calculation according to claim 1, characterized in that: In step 2, suppose one of the two complex numbers to be conjugate multiplied is represented by a+jb and the other is represented by c+jd. The calculation formula of the conjugate product of the two complex numbers is expressed as: (a+jb)*(c-jd)=(ac+bd)+j(bc-ad) Therefore, an inverter, a multiplier, and a two-input adder are designed in the conjugate multiplication calculation process; The inverter formula is: in, is the opposite of x The probability value of the corresponding random bit stream.

5. The method for designing a signal correlation operation hardware circuit structure based on random calculation according to claim 4, characterized in that: The SC multiplier is used to calculate the product of the binary data represented by two random bits. The formula is expressed as: Among them, P x1 and P x2 is the probability value of converting two binary data to be multiplied into a random bit stream, P y It is the probability value of the random bit stream represented by the product of two binary data; In order to obtain the final complex product result, a two-input adder is required to perform a summation operation. Since the maximum probability value in SC cannot exceed 1, in order to prevent the probability value from exceeding 1, the summation result is scaled by 1 / 2 when performing the addition operation. The calculation formula is expressed as: Among them, P x1 and P x2 is the probability value of converting 2 binary data into a random bit stream, P y The probability value of the random bit stream represented by the sum of two binary data.

6. The method for designing a signal correlation operation hardware circuit structure based on random calculation according to claim 1, characterized in that: In step 3, to ensure that the summation result does not exceed the range and to prevent overscaling, a k-fold scaled N-input adder is used for summation, which is expressed as: in, It represents the probability value of k data out of N input binary data after being scaled and summed by k times. It means that after N data paths are divided into groups with every k data, there are M groups of data in total. Indicates rounding down.

7. The method for designing a signal correlation operation hardware circuit structure based on random calculation according to claim 6, characterized in that: When summing, in order to calculate the binary summation result corresponding to the random bit data stream, the N-input k-times scaling adder needs to subtract a value of The constant term of is corrected; N input data streams are divided into M+1 groups, each group contains k data, and the last group of missing positions is padded with zeros; each group of k data passes through a k-way selector, and then M+1 data streams are obtained; At each moment, the M+1 data streams are summed and a probability value is subtracted. The modified data flow is the same as the state n After the sum is calculated, if it is greater than 0, the output result is 1, otherwise it is 0. Finally, the state is adjusted according to the output result. n Make corrections and complete the entire calculation process.

8. The method for designing a signal correlation operation hardware circuit structure based on random calculation according to claim 1, characterized in that: In step 4, the binary is converted into a data stream after scaling and biasing, so an inverse mapping process is required, which is expressed as: Among them, L is the length of the random bit data stream; in order to convert the random bit stream back into binary data, a counter is first required to count the number of logical values ​​1 in the random bit data stream, then multiply the statistical result by 2 and subtract L, and finally divide the result by L to complete the conversion process from random bit data stream to binary result.

9. A signal correlation operation hardware circuit structure based on random calculation, characterized in that: include: A binary data conversion circuit, a conjugate multiplication circuit, and an N-input k-times scaling adder circuit; wherein the binary data conversion circuit includes a random number generator and a comparator; The conjugate multiplication circuit includes an inverter based on a NOT gate, a multiplier based on an XNOR gate, and a scaling adder based on a 2-way selector; the N-input k-fold scaling adder circuit includes a multiplier based on an XNOR gate and a 2-input non-scaling adder; the 2-input non-scaling adder includes a multiplexer, an adder, a subtractor, and a comparator.

10. The signal correlation operation hardware circuit structure based on random calculation according to claim 9, characterized in that: Two binary input data are converted into a single-bit random data stream through a binary conversion circuit, and then the conjugate product of the two random data streams is calculated by a random conjugate multiplier circuit. Then, the correlation result of the two input data is calculated by an N-input k-fold scaling random adder, and finally, the single-bit random data stream is converted into binary data through an accumulator, a subtractor, a multiplier and a divider.

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