Processor and operation method thereof

Abstract

The invention provides a processor and an operation method thereof. The processor comprises a first register, a decoding unit and an execution unit, wherein the first register is configured to store a first divisor judgment threshold value; the decoding unit is configured to decode a divisor instruction to obtain an operator, a first operand and a second operand. The execution unit is configured to compare the first operand with the first divisor judgment threshold to obtain a first comparison result, compare the second operand with the first divisor judgment threshold to obtain a second comparison result, and selectively output one of the first operand, the second operand and the operation result based on the first comparison result and the second comparison result. The operation result is obtained by the execution unit by executing an operation corresponding to the operator on the first operand and the second operand.

Description

Technical Field

[0001] The present invention relates to computer architecture, and particularly to a processor and its operation method. Background Art

[0002] Artificial Intelligence (AI) operations involve a large number of matrix operations, especially Neural Network (NN), where the calculations between weights, biases, and input data rely on a large number of matrix multiplications and additions. Generally speaking, AI operations significantly increase the time and space complexity as the data volume and data dimension increase. Therefore, how to optimize the efficiency of these operations is crucial for improving the performance of AI systems. Currently, common dedicated hardware such as Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and Tensor Processing Unit (TPU) are commonly used to accelerate AI operations. However, the production and use costs of these dedicated hardware are high, and none of them are acceleration methods targeted at "reducing the amount of operations".

[0003] Essentially, AI operations involve a large number of matrix multiplications and additions, and both multiplication and addition belong to a type of arithmetic operation. In addition to multiplication and addition, arithmetic operations also include subtraction and division. In addition to arithmetic operations, other common operations such as logical operations include operations such as AND, OR, and NOT. Generally speaking, since arithmetic operations involve carry operations and require more complex operation logics (such as multiplication and division), arithmetic operations take more time than logical operations.

[0004] Therefore, there is a need for a processor and an operation method to accelerate AI operations in a way of "reducing the amount of arithmetic operations". Summary of the Invention

[0005] Embodiments of the present disclosure provide a processor, including a first register, a decoding unit, and an execution unit. The first register is configured to store a first divisor judgment threshold. The decoding unit is configured to decode a divisor instruction to obtain an operator, a first operand, and a second operand. The execution unit is configured to compare the first operand with the first divisor judgment threshold to obtain a first comparison result, compare the second operand with the first divisor judgment threshold to obtain a second comparison result, and selectively output one of the first operand, the second operand, and the operation result based on the first comparison result and the second comparison result. Wherein, the operation result is obtained by the execution unit performing the operation corresponding to the operator on the first operand and the second operand.

[0006] In one embodiment, the execution unit includes a first comparator, a second comparator, an arithmetic logic unit, and a multiplexer. The first comparator is configured to compare a first operand and a first divisor judgment threshold to obtain a first comparison result; the second comparator is configured to compare a second operand and the first divisor judgment threshold to obtain a second comparison result; the arithmetic logic unit is configured to selectively perform an operation corresponding to an operator on the first operand and the second operand based on the first comparison result and the second comparison result; the multiplexer is configured to selectively output one of the first operand, the second operand, and the operation result based on the first comparison result and the second comparison result.

[0007] In one embodiment, in response to the operator corresponding to an addition operation, and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the multiplexer outputs the second operand; in response to the operator corresponding to an addition operation, and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to an addition operation, and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the second operand; in response to the operator corresponding to an addition operation, and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs an addition operation on the first operand and the second operand, and the multiplexer outputs the operation result.

[0008] In one embodiment, in response to the operator corresponding to a subtraction operation, and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs a subtraction operation on the first operand and the second operand, and the multiplexer outputs the operation result; in response to the operator corresponding to the subtraction operation, and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to a subtraction operation, and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to a subtraction operation, and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs a subtraction operation on the first operand and the second operand, and the multiplexer outputs the operation result.

[0009] In one embodiment, in response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the multiplexer outputs the second operand; in response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the second operand; in response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs a multiplication operation on the first operand and the second operand, and the multiplexer outputs the operation result.

[0010] In one embodiment, in response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs a division operation on the first operand and the second operand, and the multiplexer outputs the operation result; in response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is not greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is not greater than the first divisor judgment threshold, the multiplexer outputs the first operand; in response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs a division operation on the first operand and the second operand, and the multiplexer outputs the operation result.

[0011] In one embodiment, the processor further includes a second register. The second register is configured to store a second divisor judgment threshold. The processor is further configured to select one of the first divisor judgment threshold and the second divisor judgment threshold according to the data types of the first operand and the second operand to compare with the first operand and the second operand to obtain the first comparison result and the second comparison result.

[0012] Embodiments of the present disclosure provide an operation method, which is executed on a processor. The processor includes a first register, a decoding unit, and an execution unit. The first register is configured to store a first divisor judgment threshold. The operation method includes: using the decoding unit to decode a divisor instruction to obtain an operator, a first operand, and a second operand, and using the execution unit to perform the following steps: comparing the first operand with the first divisor judgment threshold to obtain a first comparison result; comparing the second operand with the first divisor judgment threshold to obtain a second comparison result; and selectively outputting one of the first operand, the second operand, and the operation result based on the first comparison result and the second comparison result; wherein the operation result is obtained by using the execution unit to perform an operation corresponding to the operator on the first operand and the second operand.

[0013] The processor and its operation method provided by the present disclosure improve the operation speed of the processor by reducing the number of arithmetic operations (addition, subtraction, multiplication, division). Further, by using the logical judgment of a comparator to avoid the arithmetic logic unit from performing relatively time-consuming arithmetic operations (addition, subtraction, multiplication, division), the execution time of instructions can be reduced, thereby improving the instruction execution efficiency of the processor without affecting the accuracy of the operation result. Therefore, the processor and its operation method provided by the present disclosure are quite suitable for application in AI operations with a large number of matrix operations. In addition, the processor and its operation method provided by the present disclosure can be further combined with SIMD technology to further improve the execution efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a system architecture diagram of a processor according to an embodiment of the present invention.

[0015] Figure 2 It is a data flow diagram of an operation method according to an embodiment of the present invention.

[0016] Figure 3 It is a system architecture diagram of a processor according to an embodiment of the present invention.

[0017] Figure 4 It is a data flow diagram of an operation method according to an embodiment of the present invention.

[0018]

SYMBOL DESCRIPTION

[0019] 10: Processor

[0020] 11: First register

[0021] 12: Decoding unit

[0022] 13: Execution unit

[0023] 20: Operation method

[0024] 201~203: Steps

[0025] 21: First divisor judgment threshold

[0026] 22: Divisor instruction

[0027] 23: Operator

[0028] 24: First operand

[0029] 25: Second operand

[0030] 26: First comparison result

[0031] 27: Second comparison result

[0032] 28: Operation result

[0033] 30: Processor

[0034] 33: Execution unit

[0035] 31: First comparator

[0036] 32: Second comparator

[0037] 34: Arithmetic logic unit

[0038] 35: Multiplexer

[0039] 40: Operation method

[0040] 401~404: Steps Detailed implementation manners

[0041] The following descriptions list various embodiments of the present invention, but are not intended to limit the content of the present invention. The actual scope of the invention is defined by the claims.

[0042] In the following listed embodiments, the same reference numerals will be used to represent the same or similar elements or components.

[0043] In this specification and the claims, the serial numbers, such as "first", "second", etc., are only for convenience of description, and there is no sequential precedence relationship between them.

[0044] The descriptions of the embodiments of the apparatus or system in this specification also apply to the embodiments of the method, and vice versa.

[0045] Figure 1 For a system architecture diagram of a processor 10 according to an embodiment of the present invention. As Figure 1 shown, the processor 10 includes a first register 11, a decoding unit 12, and an execution unit 13.

[0046] The decoding unit 12 can be a hardware circuit composed of logic gates for decoding instructions. The execution unit 13 can be composed of multiple sets of digital circuits, such as adders, floating-point multipliers, and shifters, etc., to perform various arithmetic operations, such as arithmetic and logical operations.

[0047] Although Figure 1 only the first register 11, the decoding unit 12, and the execution unit 13 are shown, those skilled in the art should be aware that the processor 10 may also include other common basic components, such as a control unit (CU), a memory management unit (MMU), a cache, or other registers such as general-purpose registers (GPRs), etc. However, the present disclosure does not limit this.

[0048] Figure 2 FIG. 20 is a data flow diagram of an arithmetic method 20 according to an embodiment of the present invention. The arithmetic method 20 is implemented in Figure 1 the processor 10. As Figure 2 shown, the first register 11 stores the first divisor judgment threshold 21. The following describes steps 201 to 203 of the arithmetic method 20.

[0049] In step 201, the decoding unit 12 decodes a divisor instruction 22 to obtain an operator 23, a first operand 24, and a second operand 25. The divisor instruction 22 is fetched from an instruction memory.

[0050] Generally speaking, an operator is an abstract symbol used to express an operation. For example, in arithmetic operators, the addition operator ‘+’, the subtraction operator ‘-’, the multiplication operator ‘*’, and the division operator ‘ / ’. The operator 23 can be implemented by the corresponding opcode in the divisor instruction 22. Specifically, the opcode in the divisor instruction 22 is used to indicate the operation that the execution unit 13 should perform. For example, an ADD-type instruction can correspond to the addition operator ‘+’, and then the execution unit 13 is controlled to perform an addition operation.

[0051] Generally speaking, an operand is an object of the aforementioned operator or opcode. In an instruction, common operands can be, for example, an immediate value, that is, a constant value directly given in the instruction. Or, an operand can be a value read from a register or a memory address. For example, the instruction 'ADD AX, BX' instructs the processor to perform an addition operation on the data stored in registers AX and BX. Therefore, specifically, the first operand 24 and the second operand 25 can be the immediate value specified in the divisor instruction 22, the data stored in the specified register, or the data stored in the specified memory, however, the present disclosure is not limited thereto.

[0052] In step 202, the execution unit 13 compares the first arithmetic unit 24 with the first divisor judgment threshold 21 to obtain a first comparison result 26. Similarly, the execution unit 13 compares the second arithmetic unit 25 with the first divisor judgment threshold 21 to obtain a second comparison result 27. The first comparison result 26 and the second comparison result 27 can be represented using boolean values, flags, or bit encodings, however, the present disclosure is not limited thereto. For example, a value of 1 for the first comparison result 26 represents that the first arithmetic unit 24 is greater than the second operand 25, and 0 represents that the first arithmetic unit 24 is less than or equal to the second operand 25.

[0053] In step 203, the execution unit 13 selectively outputs one of the first operand 24, the second operand 25, and an arithmetic result 28 according to the first comparison result 26 and the second comparison result 27. The arithmetic result 28 is obtained by the execution unit 13 performing an operation corresponding to the operator 23 on the first operand 24 and the second operand 25. The operation corresponding to the operator 23 can be any one of addition, subtraction, multiplication, and division.

[0054] It should be noted that the embodiments of the present disclosure do not limit that the execution unit 13 must perform the operation corresponding to the operator 23. In other words, the execution unit 13 will only perform the operation corresponding to the operator 23 when specific conditions are met. In other cases, the execution unit 13 can ignore the operation.

[0055] It is worth noting that in the embodiments of the present disclosure, the first divisor judgment threshold 21 is not specified in the divisor instruction 22. Instead, the first divisor judgment threshold 21 is specified in the first register 11. Thereby, the problem of decoding delay caused to the decoding unit 12 due to the inconsistent instruction length by recording the first divisor judgment threshold 21 in the divisor instruction 22 can be avoided, thus improving the overall execution efficiency of the processor 10.

[0056] In one embodiment, the processor 10 further includes a second register that stores a second divisor determination threshold. In step 202 of this embodiment, the processor 10 further selects one of the first divisor determination threshold 21 and the second divisor determination threshold according to the data types of the first operand 24 and the second operand 25, and compares it with the first operand 24 and the second operand 25 to obtain the first comparison result 26 and the second comparison result.

[0057] In one example, the first divisor determination threshold 21 is a threshold of a single-precision floating-point format, and the second divisor determination threshold is a threshold of a double-precision floating-point format. In step 202 of this example, the processor 10 first determines the data types of the first operand 24 and the second operand 25. If it is a float data type, the first divisor determination threshold 21 is used as the comparison object for the first operand 24 and the second operand 25. If it is a double data type, the second divisor determination threshold is used as the comparison object for the first operand 24 and the second operand 25.

[0058] In one implementation aspect, the above logic for determining the comparison object of the first operand 24 and the second operand 25 can be implemented in an operating system (OS). For example, the operating system can set a specific register of the underlying processor according to the data type of the upper-layer application instruction, and the value stored in the specific register can determine which of the first divisor determination threshold 21 and the second divisor determination threshold the execution unit 13 uses as the comparison object for the first operand 24 and the second operand 25.

[0059] Figure 3 It is a system architecture diagram of a processor 30 according to an embodiment of the present invention. As Figure 3 shown, compared with Figure 1 the execution unit 13, the execution unit 33 includes a first comparator 31, a second comparator 32, an arithmetic logic unit (ALU) 34, and a multiplexer (MUX) 35.

[0060] Same as Figure 1For the processor 10, in addition to the above elements, the processor 30 may further include other common basic elements, such as a Control Unit (CU), a Memory Management Unit (MMU), a Cache, and other registers such as General-Purpose Registers (GPRs). However, the present disclosure does not limit this.

[0061] Figure 4 FIG. 40 is a data flow diagram of an arithmetic method 40 according to an embodiment of the present invention. The arithmetic method 40 is implemented in Figure 3 the processor 30. As Figure 4 shown, steps 401-403 of the arithmetic method 40.

[0062] In step 401, the decoding unit 12 decodes a divisor instruction 22 to obtain an operator 23, a first operand 24, and a second operand 25.

[0063] In step 402, the first comparator 31 compares the first arithmetic unit 24 with the first divisor judgment threshold 21 to obtain a first comparison result 26. Similarly, the second comparator 32 compares the second arithmetic unit 25 with the first divisor judgment threshold 21 to obtain a second comparison result 27.

[0064] In step 403, the arithmetic logic unit 34 selectively performs an operation corresponding to the operator 23 on the first operand 24 and the second operand 25 according to the first comparison result 26 and the second comparison result 27.

[0065] If the first comparison result 26 and the second comparison result 27 indicate that the arithmetic logic unit 34 performs an operation corresponding to the operator 23 on the first operand 24 and the second operand 25, then the arithmetic logic unit 34 outputs the result of the operation performed on the first operand 24 and the second operand 25 as the operation result 28. The operation corresponding to the operator 23 may be any one of addition, subtraction, multiplication, and division.

[0066] If the first comparison result 26 and the second comparison result 27 do not indicate that the arithmetic logic unit 34 performs an operation corresponding to the operator 23 on the first operand 24 and the second operand 25, then the arithmetic logic unit 34 does not perform an operation corresponding to the operator 23 on the first operand 24 and the second operand 25. In one embodiment, the arithmetic logic unit 34 does not perform any operation and directly outputs a preset value (e.g., zero) as the operation result 28. In one embodiment, the arithmetic logic unit 34 does not perform any operation and does not make any output.

[0067] It should be noted that controlling the enabling and disabling of the arithmetic logic unit 34 by means of the first comparison result 26 and the second comparison result 27 helps to reduce the number of operations of the arithmetic logic unit 34. Thereby, the instruction execution time can be reduced, and even the data hazard can be reduced, thus improving the overall execution efficiency of the processor 30.

[0068] In step 404, the multiplexer 35 selectively outputs one of the first operand 24, the second operand 25, and the operation result 28 based on the first comparison result 26 and the second comparison result 27.

[0069] In a further embodiment, in addition to the first comparison result 26 and the second comparison result 27, the multiplexer 35 further refers to the operator 23 to selectively output one of the first operand 24, the second operand 25, and the operation result 28.

[0070] The following describes an embodiment where the operator 23 corresponds to an addition operation in four cases.

[0071] Case 1-1: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold, the multiplexer 35 outputs the second operand 25.

[0072] Case 1-2: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0073] Case 1-3: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the second operand 25.

[0074] Case 1-4: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs an addition operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0075] In Case 1-1, the divisor instruction 22 for adding the first operand 24 and the second operand 25 can obtain the second operand 25, so it can be regarded that the execution unit 33 performs a zero reduction operation on the first operand 24, that is, regards the first operand 24 as zero or reduces it to zero.

[0076] Similarly, in Case 1-2, the divisor instruction 22 that adds the first operand 24 and the second operand 25 can obtain the first operand 24. Therefore, it can be considered that the execution unit 33 performs a zero reduction operation on the second operand 25, that is, regards the second operand 25 as zero or reduces it to zero.

[0077] The following describes an embodiment where the operator 23 corresponds to a subtraction operation in four cases.

[0078] Case 2-1: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs a subtraction operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0079] Case 2-2: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0080] Case 2-3: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0081] Case 2-4: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs a subtraction operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0082] In Case 2-2 and 2-3, the divisor instruction 22 that subtracts the first operand 24 and the second operand 25 can obtain the first operand 24. Therefore, it can be considered that the execution unit 33 performs a zero reduction operation on the second operand 25, that is, regards the second operand 25 as zero or reduces it to zero.

[0083] The following describes an embodiment where the operator 23 corresponds to a multiplication operation in four cases.

[0084] Case 3-1: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold, the multiplexer 35 outputs the second operand 25.

[0085] Case 3-2: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0086] Case 3-3: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the second operand 25.

[0087] Case 3-4: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs a multiplication operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0088] In Case 3-1, the divisor instruction 22 for multiplying the first operand 24 and the second operand 25 can obtain the second operand 25. Therefore, it can be regarded that the execution unit 33 performs a reduction operation on the first operand 24, that is, regarding the first operand 24 as one or reducing it to one.

[0089] Similarly, in Case 3-2, the divisor instruction 22 for adding the first operand 24 and the second operand 25 can obtain the first operand 24. Therefore, it can be regarded that the execution unit 33 performs a reduction operation on the second operand 25, that is, regarding the second operand 25 as one or reducing it to one.

[0090] The following describes an embodiment in which the operator 23 corresponds to a division operation in four cases.

[0091] Case 4-1: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs a division operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0092] Case 4-2: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0093] Case 4-3: When the first comparison result 26 indicates that the first operand 24 is not greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is not greater than the first divisor judgment threshold 21, the multiplexer 35 outputs the first operand 24.

[0094] Case 4-4: When the first comparison result 26 indicates that the first operand 24 is greater than the first divisor judgment threshold 21, and the second comparison result 27 indicates that the second operand 25 is greater than the first divisor judgment threshold 21, the arithmetic logic unit 34 performs a division operation on the first operand 24 and the second operand 25, and the multiplexer 35 outputs the operation result 28.

[0095] In Case 4-2 and 4-3, the divisor instruction 22 for dividing the first operand 24 and the second operand 25 can obtain the first operand 24. Therefore, it can be regarded that the execution unit 33 performs a reduction operation on the second operand 25, that is, regards the second operand 25 as one or reduces it to one.

[0096] In an embodiment, both the first comparator 31 and the second comparator 32 execute the judgment logic of "whether it is greater than". In other words, the first comparator 31 judges whether the first operand 24 is greater than the first divisor judgment threshold 21. If it is greater, it outputs True, otherwise it outputs False. Similarly, the second comparator 32 judges whether the second operand 25 is greater than the first divisor judgment threshold 21. If it is greater, it outputs True, otherwise it outputs False.

[0097] In an example, the internal judgment logic of the multiplexer 35 is as shown in <First Table>.

[0098] <First Table>

[0099]

[0100] In an embodiment, the above-mentioned processor 10 and processor 30 can be further extended to support the Single Instruction Multiple Data (SIMD) technology. The traditional Single Instruction Single Data (SISD) technology can only perform operations on one piece of data at the same time. In contrast, the SIMD technology can accelerate calculations by performing the same operations on multiple pieces of data at the same time.

[0101] The SIMD technology usually uses vector registers to store data. Compared with general-purpose registers, vector registers can store multiple pieces of data. For example, a 256-bit vector register can store 8 32-bit integers or 4 64-bit floating-point numbers. In addition, the SIMD technology also uses multiple execution units to perform the same operations on multiple pieces of data in the vector register in parallel at the same time.

[0102] Therefore, the processor of the present disclosure may include multiple execution units and multiple vector registers, and further extend the arithmetic methods 20 and 40 of the present disclosure to each execution unit in the processor. In this way, each execution unit will respectively correspond to one piece of data in a certain vector register as its first operand, and correspond to one piece of data in another vector register as its second operand. In other words, for each operand, its first operand may be one piece of data in a certain vector register, and its second operand may be one piece of data in another vector register. Then, each execution unit performs comparison and selective output as in methods 20 and 40.

[0103] For example, the processor of the present disclosure may include a first execution unit, a second execution unit, a first register, and a second register. The first execution unit is responsible for performing arithmetic operations on the first data (its first operand) in the first vector register and the first data (its second operand) in the second vector register. The second execution unit is responsible for performing arithmetic operations on the second data (its first operand) in the first vector register and the second data (its second operand) in the second vector register. By parallel computing, the computing speed can be further improved.

[0104] The processor and its arithmetic method provided by the present disclosure improve the operation speed of the processor by reducing the number of arithmetic operations (addition, subtraction, multiplication, division). Further, by using the logical judgment of the comparator to avoid the arithmetic logic unit from performing relatively time-consuming arithmetic operations (addition, subtraction, multiplication, division), the execution time of instructions can be reduced, thereby improving the instruction execution efficiency of the processor without affecting the accuracy of the operation result. Therefore, the processor and its arithmetic method provided by the present disclosure are particularly suitable for application in AI operations with a large number of matrix operations. In addition, the processor and its arithmetic method provided by the present disclosure can be further combined with SIMD technology to further improve the execution efficiency of the processor.

[0105] The above paragraphs are described in multiple aspects. Obviously, the teachings herein can be implemented in various ways, and any specific architecture or function disclosed in the examples is only a representative case. According to the teachings herein, those skilled in the art should understand that each aspect disclosed herein can be implemented independently or two or more aspects can be implemented in combination.

[0106] Although the present disclosure has been described above with examples, it is not intended to limit the present disclosure. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the invention shall be subject to the scope defined by the appended claims.

Claims

1. A processor, comprising: A first register configured to store a first divisor determination threshold; a decoding unit configured to decode the divisor instruction to obtain an operator, a first operand, and a second operand; as well as an execution unit configured to compare the first operand with the first divisor determination threshold value to obtain a first comparison result, compare the second operand with the first divisor determination threshold value to obtain a second comparison result, and selectively output one of the first operand, the second operand and a calculation result based on the first comparison result and the second comparison result; The operation result is obtained by the execution unit by executing the operation corresponding to the operator on the first operand and the second operand.

2. The processor of claim 1 , wherein the execution unit comprises: A first comparator is configured to compare the first operand with the first divisor determination threshold to obtain the first comparison result; A second comparator is configured to compare the second operand with the first divisor determination threshold to obtain the second comparison result; an arithmetic logic unit configured to selectively perform the operation corresponding to the operator on the first operand and the second operand based on the first comparison result and the second comparison result; as well as The multiplexer is configured to selectively output one of the first operand, the second operand and the operation result based on the first comparison result and the second comparison result.

3. The processor of claim 2 , wherein in response to the operator corresponding to an addition operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, the multiplexer outputs the second operand; in, In response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; wherein, in response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the second operand; Wherein, in response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs the addition operation on the first operand and the second operand, and the multiplexer outputs the operation result.

4. The processor of claim 2 , wherein in response to the operator corresponding to a subtraction operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, the arithmetic logic unit performs the subtraction operation on the first operand and the second operand, and the multiplexer outputs the operation result; in, In response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; wherein, in response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; Wherein, in response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs the subtraction operation on the first operand and the second operand, and the multiplexer outputs the operation result.

5. The processor of claim 2 , wherein in response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, the multiplexer outputs the second operand; in, In response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; wherein, in response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the second operand; Wherein, in response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs the multiplication operation on the first operand and the second operand, and the multiplexer outputs the operation result.

6. The processor of claim 2 , wherein in response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, the arithmetic logic unit performs the division operation on the first operand and the second operand, and the multiplexer outputs the operation result; in, In response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; wherein, in response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, the multiplexer outputs the first operand; Wherein, in response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit performs the division operation on the first operand and the second operand, and the multiplexer outputs the operation result.

7. The processor of claim 1 , further comprising a second register configured to store a second divisor determination threshold value, the processor further configured to select one of the first divisor determination threshold value and the second divisor determination threshold value according to data types of the first operand and the second operand to compare with the first operand and the second operand to obtain the first comparison result and the second comparison result.

8. A computing method, executed on a processor, the processor comprising a first register, a decoding unit and an execution unit, the first register being configured to store a first divisor determination threshold, the computing method comprising: Decoding the approximation instruction using the decoding unit to obtain an operator, a first operand, and a second operand; as well as Use this execution unit to perform the following steps: Comparing the first operand with the first divisor determination threshold to obtain a first comparison result; Comparing the second operand with the first divisor determination threshold to obtain a second comparison result; as well as Based on the first comparison result and the second comparison result, selectively outputting one of the first operand, the second operand and the operation result; The operation result is obtained by using the execution unit to execute the operation corresponding to the operator on the first operand and the second operand.

9. The calculation method as claimed in claim 8, wherein the execution unit comprises a first comparator, a second comparator, a multiplexer and an arithmetic logic unit; and The calculation method also includes: Using the first comparator, comparing the first operand with the first divisor determination threshold value to obtain the first comparison result; Using the second comparator, compare the second operand with the first divisor determination threshold value to obtain the second comparison result; Using an arithmetic logic unit, selectively performing the operation corresponding to the operator on the first operand and the second operand based on the first comparison result and the second comparison result; and The multiplexer is used to selectively output one of the first operand, the second operand and the operation result based on the first comparison result and the second comparison result.

10. The computing method according to claim 9, further comprising: In response to the operator corresponding to an addition operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, using the multiplexer to output the second operand; In response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; In response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the second operand; as well as In response to the operator corresponding to the addition operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit is used to perform the addition operation on the first operand and the second operand, and the multiplexer is used to output the operation result.

11. The computing method according to claim 9, further comprising: In response to the operator corresponding to a subtraction operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, using the arithmetic logic unit to perform the subtraction operation on the first operand and the second operand, and using the multiplexer to output the operation result; In response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; In response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; as well as In response to the operator corresponding to the subtraction operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit is used to perform the subtraction operation on the first operand and the second operand, and the multiplexer is used to output the operation result.

12. The computing method according to claim 9, further comprising: In response to the operator corresponding to a multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, using the multiplexer to output the second operand; In response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; In response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the second operand; In response to the operator corresponding to the multiplication operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit is used to perform the multiplication operation on the first operand and the second operand, and the multiplexer is used to output the operation result.

13. The computing method according to claim 9, further comprising: In response to the operator corresponding to a division operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is greater than the first divisor determination threshold, using the arithmetic logic unit to perform the division operation on the first operand and the second operand, and using the multiplexer to output the operation result; In response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; In response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is not greater than the first divisor determination threshold and the second comparison result indicating that the second operand is not greater than the first divisor determination threshold, using the multiplexer to output the first operand; as well as In response to the operator corresponding to the division operation and the first comparison result indicating that the first operand is greater than the first divisor judgment threshold and the second comparison result indicating that the second operand is greater than the first divisor judgment threshold, the arithmetic logic unit is used to perform the division operation on the first operand and the second operand, and the multiplexer is used to output the operation result.

14. The computing method of claim 8, wherein the processor further comprises a second register configured to store a second divisor determination threshold, the method further comprising: According to the data types of the first operand and the second operand, one of the first divisor determination threshold and the second divisor determination threshold is selected to be compared with the first operand and the second operand to obtain the first comparison result and the second comparison result.

Images