Bus peeping module and SoC chip with embedded bus peeping module

Abstract

The invention relates to a bus peeping module and an embedded bus peeping module SoC chip. The module comprises a bus network interface unit, a peeping event unit and a core peeping device unit which are connected in sequence. The bus network interface unit is the front end of the peeping module and is used for selectively peeping different source end IP modules and receiving bus data packets; the peeping event unit is used for collecting peeping network links, counting data packets and detecting error data packets, and comprises a peeping data packet event subunit, a peeping transaction event subunit and a peeping error event subunit; and the peep unit is used for collecting information from the peep event unit, notifying the SoC in an interrupt form, or forwarding the information to the SoC in a diary form, or forwarding the information to the outside of the SoC through a tracking bus. The device has the advantages that the device is embedded in the bus, bus functions are not affected, and data and states are detected in real time.

Description

[Technical field]

[0001] The present invention relates to the technical field of chip design, and in particular to a bus snooping module and a SoC chip with an embedded bus snooping module. [Background technology]

[0002] SoC: System on Chip is a highly integrated and efficient electronic system that integrates multiple functional modules (such as processors, memory, interface controllers, etc.) into a single chip, thereby improving system performance, reducing power consumption, and reducing physical size.

[0003] NIU: Network Interface Unit, network interface unit, NIU can communicate between processors using different protocols by using a common transmission protocol.

[0004] ATB: Advanced Trace Bus, is an advanced trace bus, mainly used to transfer trace data between ARM's CoreSight components. CoreSight is a comprehensive debugging and tracing system developed by ARM, which is widely used in processors and system-on-chip (SoC) based on ARM architecture.

[0005] Chip IP: Chip intellectual property (Intellectual Property) refers to the reusable modular design unit used in integrated circuit design; the emergence of chip IP aims to improve the efficiency and reusability of integrated circuit design, allowing designers to complete design tasks faster and shorten the design cycle.

[0006] When designing a chip, it is necessary to monitor the data and status of each IP module in real time. Usually, this function is designed into the IP module, which makes the IP module design complicated and increases the area. Or, statistics are performed on a specific data in the time domain on the bus, and other data cannot be counted or the statistical time is limited. Or, one bus is monitored in a multi-channel bus, and other buses cannot be monitored. Or, it is dynamically configured to monitor on multiple groups of buses. This fixed design and dynamic allocation mode can be allocated to a relatively distant bus and cannot achieve the effect of real-time monitoring. In short, there is no unified solution under the existing technology, and most of them are external to the bus, which brings more work and difficulty to chip design, verification and software development, and is not conducive to problem location.

[0007] The present invention aims to solve the technical problems in the prior art that the IP module is complex in design and has an increased area, and that the external bus brings more work and greater difficulty to chip design and development, and makes technical improvements to the spy module and the SoC chip with an embedded spy module. [Summary of the invention]

[0008] An object of the present invention is to provide a bus snooping module embedded in a bus without affecting the bus function and capable of snooping data and status in real time.

[0009] To achieve the above object, the technical solution adopted by the present invention is a bus snooping module for snooping data and status of each IP module in real time during the design of an SoC chip; it includes a bus network interface unit, a snooping event unit, and a core snooping unit connected in sequence; the bus network interface unit is the front end of the snooping module, used to select different source IP modules for snooping and receive bus data packets; the snooping event unit is used to collect snooping network links, count data packets, and detect error data packets, including a snooping data packet event sub-unit, a snooping transaction event sub-unit, and a snooping error event sub-unit. The data packet event refers to the statistics of data packet Cycle, Packets, and Bytes. The transaction event refers to the statistics of data packet delay and suspension. The error event refers to capturing and counting data packets with error status; the snooping unit is used to collect information from the snooping event unit and notify the SoC in the form of an interruption, or forward it to the SoC in the form of a diary, or forward it to the outside of the SoC through a trace bus.

[0010] Preferably, the bus snooping module further includes a filter unit connected between the bus network interface unit and the snooping event unit; the filter unit supports filtering bus data packets transmitted by the bus network interface unit according to routing ID, address, opcode, status, length, bus read / write mode, and conditional mode, effectively meeting the snooping requirements.

[0011] Preferably, the snooping data packet event sub-unit includes an optional data packet timestamp, which is used for programmably selecting the data packet snooping point at runtime, programmably filtering the data packet link at runtime, recording the snooping network link volume and snooping network link statistics, event counting of external signals, and generating snooping network links and / or counting data packets.

[0012] Preferably, the snooping transaction event sub-unit includes an optional data packet timestamp, which is used for programmably selecting the transaction snooping point at runtime, performing transaction analysis according to the number of delays or pending transactions, event counting of external signals, and generating statistical data packets for the snooping network.

[0013] Preferably, the snooping error event sub-unit does not affect the data timing of the snooping network link. When an unprocessed error event occurs, the second error event will be ignored. It is used for programmably selecting the error snooping point at runtime, snooping message header errors, or data sequence status errors of the data carried by the message, and saving error information that can be accessed by software.

[0014] Another object of the present invention is to provide an embedded bus snooping module SoC chip that does not affect the bus function and can snoop data and status in real time.

[0015] To achieve the above-mentioned another object, the technical solution adopted by the present invention is an embedded bus snooping module SoC chip, which embeds the above-mentioned bus snooping module.

[0016] Preferably, the embedded bus snooping module SoC chip includes several IP modules, several IP module sub-buses, a main bus, and several bus snooping modules. The bus snooping module is embedded on the IP module sub-bus interface of the SoC chip in the embedded mode A, and / or embedded mode B, and / or embedded mode C; the embedded mode A means that the bus snooping module is directly embedded between the IP module and the main bus; the embedded mode B means that a snooping module can be optionally added or not added between the IP modules IP1-IPn and the common IP module sub-bus of IP1-IPn, and a snooping module is added between the common IP module sub-bus of IP1-IPn and the main bus; the embedded mode C means that the IP module IPm and the IP modules IP1-IPn converge to the same IP module sub-bus, a snooping module is added between the IP module IPm and the same IP module sub-bus, and a snooping module is added between the same IP module sub-bus and the main bus.

[0017] Preferably, the bus is a CoreConnect bus, an AMBA bus, an Avalon bus, a Wishbone bus or an OCP bus.

[0018] The beneficial effects of the bus snooping module and the embedded bus snooping module SoC chip of the present invention are as follows: it can reduce the complexity of IP module design, and does not affect the functions and designs of the chip IP modules. Chip designers can modularly add them to the bus as needed, and it can also reduce the chip area; it can snoop on bus data packets, transactions and errors, and uses 64Bit registers for statistics and hardware interrupts for real-time notification, without time limitation; it can snoop on multiple buses and multiple events simultaneously; designers can add them on the IP bus interface as needed to achieve real-time snooping and flexible configuration; it is also convenient for chip design, verification and software development, problem location, and saves labor costs.

Description of the Drawings

[0019] Figure 1 It is a block diagram of a bus snooping module.

[0020] Figure 2 It is a block diagram of an embedded bus snooping module SoC chip.

[0021] Figure 3 It is a schematic diagram of the data flow of an embedded bus snooping module SoC chip.

Detailed Implementation Modes

[0022] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely provided to better understand the present invention by showing examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but covers any modifications, substitutions, and improvements of elements, components, and algorithms without departing from the concept of the present invention. In the drawings and the following description, well-known structures and technologies are not shown so as to avoid unnecessarily obscuring the present invention.

[0023] Embodiment 1

[0024] This embodiment implements a bus snooping module.

[0025] Figure 1 It is a block diagram of a bus snooping module. As Figure 1 shown, the module of this embodiment mainly consists of a front-end bus interface NIU unit, an optional filter unit, a configurable snooping event unit, and a core snooper unit.

[0026] The NIU, the bus network interface unit, supports the five major buses of the SoC (the CoreConnect bus, AMBA bus, Avalon bus, Wishbone bus, and OCP bus applicable to the SoC). It is the front end of the snooping module and can configure the source of snooping, that is, select different source IP modules.

[0027] The filter unit supports filtering in the ways of routing ID module, address, opcode, status, and length.

[0028] The snooping event unit mainly collects transmission link, statistical data packet, and error data packet detection. It includes data packet events, transaction events, and error events.

[0029] 1. The data packet events have the following characteristics:

[0030] Runtime programmable selection of data packet snooping points;

[0031] Runtime programmable filtering of data packet links;

[0032] Recording link volume and link statistics;

[0033] Event counting of external signals;

[0034] Generating link or statistical data packets for the snooping network, or both;

[0035] Optional data packet timestamp.

[0036] 2. Transaction events have the following characteristics:

[0037] Runtime programmable selection of transaction probe points;

[0038] Transaction analysis based on latency or the number of pending transactions;

[0039] Event counting of external signals;

[0040] Generate statistical data packets for the probe network;

[0041] Optional data packet timestamp.

[0042] 3. Error events have the following characteristics:

[0043] Runtime programmable selection of error probe points;

[0044] Probe packet header errors or errors in the data sequence state carried by the packet;

[0045] Will save error information accessible to software;

[0046] The data link timing is not affected;

[0047] When a second error occurs while there is an unhandled error event, it will be ignored.

[0048] The probe unit can collect information from multiple probe events, notify the SoC in the form of interrupts, or forward it to the SoC in the form of Log (journal), or forward it to an external system through the ATB (Advanced Trace Bus).

[0049] Embodiment 2

[0050] This embodiment implements an SoC chip with an embedded bus probe module.

[0051] The chip in this embodiment embeds the bus probe module described in Embodiment 1 in the chip, on the IP module bus of the chip, to peek at the behaviors on the bus including data and status, and output this behavior through interrupts or Log. It does not affect the function of the chip IP module bus, can be added as needed, is configurable, and saves design area. The chip method in this embodiment is applicable to the CoreConnect bus, AMBA bus, Avalon bus, Wishbone bus, and OCP bus of the SoC.

[0052] In the bus snooping module embedded in the chip of this embodiment, the front-end bus interface NIU unit can match the bus protocol of the SoC; the filter unit can configure the routing ID, address, bus read / write mode and conditions to be snooped, effectively meeting the user's snooping requirements; the snooping event unit collects input link, statistics, and error packet detection, including data packet events, transaction events, and error events; the snooping unit designs hardware interrupt, Log output, and ATB forwarding, and collects information from multiple snooping events and forwards it to Trace in real time through hardware interrupt or Log output or ATB.

[0053] Figure 2 It is a block diagram of an SoC chip embedded with a bus snooping module. As Figure 2 shown, the snooping module of the SoC chip in this embodiment is embedded on the bus interface of the IP module. There are mainly three modes: Mode A: directly between the IP module and the main bus; Mode B: a snooping module can be optionally added or not added between the IP1-IPn modules and the sub-bus, and a snooping module is added between the sub-bus and the main bus; Mode C: a snooping module is added between the IPm module and the sub-bus, the IPm module and other IP1-IPn modules converge to the same sub-bus, and a snooping module is added between the sub-bus and the main bus. Or the snooping module of the chip in this embodiment is added in a combined manner of Mode A, Mode B, and Mode C.

[0054] Figure 3 It is a schematic diagram of the data flow of an SoC chip embedded with a bus snooping module. As Figure 3 shown, the snooping module needs to configure the NIU source IP module. If it is configured as the IP1 module, the snooping module is in the Master mode for IP1. If it is configured as the IP2 module and the IP3 module, the snooping module is in the Slave mode for IP1.

[0055] The filter of the snooping module can be optionally configured, and the routing ID, address, opcode, status, and length can be configured. By default, this unit is not enabled. Figure 3 The routing ID in it can be IP1-IP2, IP1-IP3, or both. The address supports 64Bit and can be the domain supported by the SoC. The opcode can be read, encapsulated read, linked read, exclusive read, write, encapsulated write, conditional write.

[0056] The snooping events can be configured separately or in combination for data packet events, transaction events, and error events.

[0057] Packet events mainly include Cycle, Packets, and Bytes statistics. Transaction events mainly include latency and suspension statistics. Error events mainly capture packet statistics with error status and save the error information accessed by the software. Event statistics are counted using a 64-bit Counter register, and the number of Counters can be configured.

[0058] Configure the probe to determine the way to forward the collected information, which can be selected in combination. The default is the interrupt mode.

[0059] A. Example of Cycle statistics of IP1 when the probe module is configured as Master:

[0060]

[0061] B. Example of Cycle statistics of IP1 when the probe module is configured as Slave:

[0062]

[0063] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware or by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, where the storage medium can be a magnetic disk, an optical disc, a Read-Only Memory (ROM), or a Random Access Memory (RAM), etc.

[0064] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the technical field, without departing from the principle of the present invention, several improvements and supplements can be made, and these improvements and supplements should also be regarded as the protection scope of the present invention.

Claims

1. A bus snooping module, used for real-time snooping of the data and status of each IP module during SoC chip design; characterized by: It includes a bus network interface unit, a snooping event unit and a core snooper unit connected in sequence; the bus network interface unit is the front end of the snooping module, which is used to select different source IP modules for snooping and receive bus data packets; the snooping event unit is used to collect snooping network links, statistical data packets, and detect error data packets, including a snooping data packet event subunit, a snooping transaction event subunit and a snooping error event subunit, the data packet event refers to data packet Cycle, Packets, Bytes statistics, the transaction event refers to data packet delay and suspension statistics, and the error event refers to capturing statistics of data packets with error states; the snooper unit is used to collect information from the snooping event unit, notify the SoC in the form of an interrupt, or forward it to the SoC in the form of a diary, or forward it to the outside of the SoC through a tracking bus.

2. A bus snooping module according to claim 1, characterized in that: Also includes a filter unit connected between the bus network interface unit and the snoop event unit; The filter unit supports routing ID, address, operation code, status, length, bus read and write mode and conditional filtering of bus data packets transmitted by the bus network interface unit, effectively meeting the snooping requirements.

3. A bus snooping module according to claim 2, characterized in that: The snooping packet event subunit includes an optional packet timestamp, which is used for programmable selection of packet snooping points at runtime, programmable filtering of packet links at runtime, recording of snooping network link volume and snooping network link statistics, event counting of external signals, and generation of snooping network link and / or statistical data packets.

4. A bus snooping module according to claim 3, characterized in that: The transaction event snooping subunit includes an optional data packet timestamp for programmable selection of transaction snooping points at run time, transaction analysis based on latency or the number of pending transactions, event counting of external signals, and generation of statistical data packets for the snooping network.

5. A bus snooping module according to claim 4, characterized in that: The error event detection subunit does not affect the timing of the network link data detection. When an unhandled error event occurs, the second error event will be ignored. It is used to programmably select error detection points at runtime, detect message header errors, or data sequence status errors carried by the message, and save error information that can be accessed by software.

6. A SoC chip with an embedded bus snooping module, characterized in that: A bus snooping module as claimed in any one of claims 1 to 5 is embedded therein.

7. The SoC chip with an embedded bus snooping module according to claim 6, characterized in that: It includes several IP modules, several IP module sub-buses, a main bus, and several bus snooping modules. The bus snooping module is embedded in the SoC chip IP module sub-bus interface in embedded mode A, and / or embedded mode B, and / or embedded mode C; the embedded mode A refers to the bus snooping module being directly embedded between the IP module and the main bus; the embedded mode B refers to the optional addition of a snooping module or no addition of a snooping module between the IP module sub-buses shared by IP modules IP1-IPn and IP1-IPn, and the addition of a snooping module between the IP module sub-bus shared by IP1-IPn and the main bus; the embedded mode C refers to the convergence of IP module IPm and IP modules IP1-IPn to the same IP module sub-bus, the addition of a snooping module between IP module IPm and the same IP module sub-bus, and the addition of a snooping module between the same IP module sub-bus and the main bus.

8. The SoC chip with an embedded bus snooping module according to claim 6, characterized in that: The bus is a CoreConnect bus, an AMBA bus, an Avalon bus, a Wishbone bus or an OCP bus.

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