Self-adaptive interrupt report control method and system for PCIE (Peripheral Component Interface Express) equipment

Abstract

The invention provides a self-adaptive interrupt reporting control method and system for PCIE (Peripheral Component Interface Express) equipment, relates to the field of computer data communication transmission, and solves various limitation problems existing in an existing interrupt reporting mechanism. The method comprises the following steps: the PCIE equipment generates an interrupt trigger signal based on an interrupt convergence mechanism; self-adaptive logic judges whether a corresponding report channel is shielded by an interrupt mask, if yes, the interrupt vector enters an interrupt suspension state, and if not, an interrupt request is initiated; priority arbitration is carried out on interrupt requests initiated by the multiple interrupt vectors at the same time, and an interrupt report is submitted to a host end if arbitration is hit; meanwhile, opening an interrupt mask corresponding to the reported interrupt request, and shielding a reporting channel of a subsequent interrupt request; and after the interrupt report processing is completed, closing the interrupt mask, and releasing the report channel of the subsequent interrupt request. According to the method, the interruption reporting process is dynamically controlled through an interactive handshake mechanism of software and hardware, and finally the self-adaptive regulation and control effect of interruption reporting is achieved.

Description

Technical Field

[0001] The present invention relates to the field of computer data communication transmission, and particularly to an adaptive interrupt reporting control method and system for PCIE devices. Background Art

[0002] In the field of information security, devices based on the high-speed serial PCI Express (PCIE) bus technology have been widely used in fields such as network security and cloud data exchange. These devices rely on hardware logic to autonomously complete data read and write operations in the host system memory, and notify the CPU for corresponding processing when the data is updated or an abnormal situation is detected. To achieve this goal, PCIE devices support multiple general interrupt delivery methods, each with its own characteristics and challenges.

[0003] Under the traditional interrupt (Legacy INTx) mechanism, the device reports an interrupt to the host system through a message transaction, which is finally converted into an INTx signal to trigger the interrupt controller to respond. However, due to the competition of the TLP transaction transmission path, the Legacy INTx method may cause the problem of interrupt loss. To avoid this situation, the host driver usually adds a read transaction flush mechanism in the interrupt service program, and uses the PCIE bus order consistency mechanism to ensure that all memory write transactions sent by the device end have been completed before the host end receives the response CPLD of this read transaction. Although this method effectively reduces the competition, it increases the complexity and potential latency.

[0004] In contrast, MSI (Message Signaled Interrupts) and MSI-X are interrupt delivery methods designed specifically for PCIE devices. They support multi-vector interrupts and simplify the interrupt processing flow. These two interrupt methods submit interrupt requests by directly writing interrupt vector numbers to specific host memory addresses through MemWrTLP, and their transmission paths are basically the same as the service data. Therefore, the PCIE bus order consistency mechanism is reasonably utilized to avoid the competition problem brought by Legacy INTx, and a more efficient and reliable interrupt processing mechanism is provided.

[0005] Regardless of the interruption method adopted, when a PCIE device faces a large amount of communication data, the host CPU may spend a large part of its performance overhead on processing frequent interrupt service programs. If the interruption reporting frequency cannot be effectively controlled, a so-called "interruption storm" will occur, thereby reducing the system's service response speed and affecting the real-time processing ability. To this end, the industry generally adopts two mechanisms to alleviate this situation: one is timeout control, that is, the frequency of generating interruptions is limited by a time counter; the other is frame count control, that is, a threshold is set, and an interruption is generated only when the number of data frames reaches this threshold. These two methods can achieve the effect of interruption aggregation and reduce the number of interruptions generated per unit time.

[0006] Although the above interruption aggregation strategy helps to reduce the CPU load, it also has certain limitations. For example, interruption timeout control cannot balance the time differences in the transmission of large and small packets. When transmitting small packets, a higher interruption timeout frequency is required to maintain a high bandwidth rate, while for large packet transmission, a lower frequency is required. Similarly, the frame count control method has a greater impact on the real-time performance of service transmission. Especially on CPUs with different performances, the frame count and timeout frequency configurations need to be adjusted according to the specific environment. In addition, when different services are running on the same CPU, the cross-impact between them may cause the preset parameters to fail, thereby affecting the overall performance.

[0007] To address these issues, the typical interruption reporting design in the prior art sets the interruption control register in the BAR space of the PCIE device through the driver program, dynamically adjusts the frame count threshold and interruption timeout time, and attempts to find the optimal configuration to adapt to different application scenarios. However, with the growth of application requirements and the development of technology, there is still a need to explore a more intelligent, flexible, and efficient interruption management scheme to further improve the system performance and ensure the real-time performance and stability of service processing. Summary of the Invention

[0008] Based on the current situation in the background technology, the purpose of the present invention is to solve the limitations such as interruption resource reuse, low response efficiency, and the risk of interruption storm existing in the existing interruption reporting mechanism and aggregation strategy. Therefore, an adaptive interruption reporting control method and system for PCIE devices are proposed. The present invention adopts the MSI / MSI-X interruption transfer method to support multi-vector interruptions, further balances the hits of multi-vector interruptions through a priority polling mechanism, and dynamically controls the interruption reporting process through the interaction handshake mechanism between the software driver program and the hardware logic, ultimately achieving the adaptive regulation effect of interruption reporting.

[0009] The present invention adopts the following technical solutions to achieve the purpose:

[0010] An adaptive interruption reporting control method for a PCIE device, comprising:

[0011] The PCIE device generates an interrupt trigger signal based on the interrupt aggregation mechanism;

[0012] The adaptive logic determines whether the reporting channel corresponding to the interrupt trigger signal is masked by its corresponding interrupt mask. If it is masked, the interrupt vector corresponding to the interrupt trigger signal enters the interrupt pending state; otherwise, an interrupt request is initiated.

[0013] Priority arbitration is performed on the interrupt requests initiated simultaneously by multiple interrupt vectors, and the interrupt requests that hit the arbitration are submitted for interrupt reporting to the host side. At the same time, the adaptive logic enables the interrupt mask of the interrupt vector corresponding to the interrupt request that hits the arbitration, and masks the reporting channel of subsequent interrupt requests of this interrupt vector;

[0014] After the host side completes the processing of the corresponding interrupt reporting, the adaptive logic closes the interrupt mask of the corresponding interrupt vector, releases the reporting channel of subsequent interrupt requests of this interrupt vector, and enables subsequent interrupt requests to continue to submit interrupt reporting to the host side after hitting the arbitration.

[0015] This design mechanism adaptively and dynamically adjusts the interrupt reporting rhythm based on the processing performance of the interrupt service program of the host side CPU, effectively avoiding the negative impact on the computer system caused by the outbreak of excessive interrupts in a short period of time; compared with the traditional mechanism that only uses frequency control and frame number control, it has the characteristics of better accuracy and adaptability.

[0016] Specifically, the PCIE device generates an interrupt trigger signal based on the interrupt aggregation mechanism, including:

[0017] Preprocessing is performed on the interrupt reporting control of the PCIE device. The preprocessing process includes frequency control and frame number control; frequency control is to control the frequency at which the PCIE device generates interrupts, and frame number control is to generate an interrupt once every time the number of data frames of the PCIE device reaches a preset threshold; when at least one of the frequency control and frame number control meets the condition for generating an interrupt, the PCIE device generates an interrupt trigger signal accordingly.

[0018] Specifically, an interrupt control register is set for the PCIE device; the driver of the PCIE device dynamically adjusts the frequency of generating interrupts and the preset threshold of data frames by controlling the interrupt control register set in the BAR space of the PCIE device.

[0019] Specifically, after the interrupt request that hits the arbitration completes the submission of interrupt reporting, the adaptive logic enables the interrupt mask of the corresponding interrupt vector and waits for the host side to process this interrupt reporting; when the host side completes the data processing of this interrupt reporting and is about to jump out after executing the interrupt service program, the host side initiates a MemWr write request message to the BAR space of the PCIE device, triggering the adaptive logic to close the interrupt mask of the corresponding interrupt vector.

[0020] Specifically, an interrupt mask register is set for the PCIE device; the adaptive logic realizes the enabling and disabling of the corresponding interrupt mask by controlling the interrupt mask register set in the BAR space of the PCIE device.

[0021] Specifically, when the interrupt mask is enabled, the reporting channel of the corresponding interrupt vector is masked, and the interrupt reporting ability is lost. If there is a corresponding interrupt trigger signal generated at this time, it enters the interrupt pending state; when the interrupt mask is disabled, the reporting channel of the corresponding interrupt vector is released, and the interrupt reporting ability is obtained, and an interrupt request is initiated when the corresponding interrupt trigger signal is generated.

[0022] Preferably, the arbitration of the interrupt requests simultaneously initiated for multiple interrupt vectors includes:

[0023] For the interrupt requests simultaneously initiated for multiple interrupt vectors, the priority arbitration module performs priority polling in a round-robin manner, determines the interrupt request that hits the arbitration according to the polling result, and submits the interrupt report to the host; the interrupt vectors corresponding to the unhit interrupt requests enter the interrupt pending state and wait for the priority polling in the next cycle; during the priority polling in the next cycle, the priority arbitration module determines the interrupt request that hits the arbitration by judging the priorities of the respective interrupt vectors.

[0024] Preferably, during the priority polling process, the priorities of the interrupt vectors corresponding to all interrupt requests are reduced by one level during the priority polling in the next cycle, but the priority of the interrupt vector that is already at the lowest priority is filled up to the highest priority during the priority polling in the next cycle; during each priority polling process, the interrupt request corresponding to the interrupt vector with the highest priority is arbitrated and hit by the priority arbitration module.

[0025] Preferably, for the interrupt vector that enters the pending state due to the interrupt trigger signal being masked by the interrupt mask, the priority arbitration module also judges the priority of this interrupt vector during the priority polling; when the interrupt trigger signal corresponding to this interrupt vector is no longer masked by the interrupt mask and the priority of this interrupt vector reaches the highest priority after being filled up, the priority arbitration module arbitrates that the interrupt request initiated by this interrupt vector hits, and submits the interrupt report to the host.

[0026] The present invention also provides a computer system, including a memory, a processor, and a computer program stored on the memory; the processor executes the computer program to implement the steps of the foregoing adaptive interrupt reporting control method for PCIE devices.

[0027] In summary, due to the adoption of the present technical solution, the beneficial effects of the present invention are as follows:

[0028] By adopting the MSI / MSI-X interrupt delivery method, the present invention not only supports multi-vector interrupts, but also introduces a priority polling mechanism to balance the triggering of multiple interrupt vectors. This method combines the handshake mechanism between software drivers and hardware logic to achieve dynamic control of the interrupt reporting process, thus achieving the effect of adaptive regulation. This design automatically adjusts the interrupt reporting rhythm according to the processing performance of the host CPU interrupt service program, effectively avoiding the negative impact on the computer system caused by the outbreak of excessive interrupts in a short period of time.

[0029] Compared with the traditional timeout control and frame count control mechanisms, the method provided by the present invention is more accurate and has better adaptability. By reasonably balancing multiple interrupt vectors, this solution solves the problem of interrupt resource reuse between different queues, ensuring that each queue can obtain independent and timely services, thereby improving the response efficiency. In addition, this method can also prevent the system performance degradation or interrupt storm phenomenon caused by a large number of concurrent interrupts, ensuring the stability and real-time performance of the system.

[0030] The priority polling design of the present invention effectively balances the submission frequencies of each interrupt vector, eliminating the resource competition problem between different interrupt vectors. This design enables the system to maintain good performance even under high load conditions and ensures that all interrupt sources have fair service opportunities. By adaptively adjusting the interrupt reporting frequency, the present invention ensures that the best system performance and response speed can be maintained under various working conditions, while significantly reducing the risk of interrupt storms. This lays a solid foundation for improving the overall efficiency of PCIE devices in fields such as network security and cloud data exchange. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the core principle process overview of the method of the present invention;

[0032] Figure 2 It is a schematic diagram of the MSI-X table of the embodiment of the method of the present invention;

[0033] Figure 3 It is a schematic circuit diagram corresponding to the interrupt aggregation mechanism of the embodiment of the method of the present invention;

[0034] Figure 4 It is a schematic diagram of the software and hardware interaction control interrupt mask of the embodiment of the method of the present invention;

[0035] Figure 5 It is a schematic diagram of the interrupt priority control process of the embodiment of the method of the present invention;

[0036] Figure 6 It is a schematic diagram of the overall process of the interrupt optimization design of the embodiment of the method of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0039] Embodiment

[0040] An adaptive interrupt reporting control method for a PCIE device. The core principle of this method can be seen in the Figure 1 overview schematic. This embodiment is introduced as follows:

[0041] The PCIE device generates an interrupt trigger signal based on an interrupt aggregation mechanism;

[0042] The adaptive logic determines whether the reporting channel corresponding to the interrupt trigger signal is masked by its corresponding interrupt mask. If it is masked, the interrupt vector corresponding to the interrupt trigger signal enters the interrupt pending state; otherwise, an interrupt request is initiated.

[0043] Priority arbitration is performed on the interrupt requests initiated simultaneously by multiple interrupt vectors, and the interrupt requests with arbitration hits are submitted for interrupt reporting to the host side. At the same time, the adaptive logic enables the interrupt mask corresponding to the interrupt vector of the interrupt request with arbitration hit, and masks the reporting channels of subsequent interrupt requests of this interrupt vector;

[0044] After the host side completes the processing of the corresponding interrupt reporting, the adaptive logic closes the interrupt mask corresponding to the interrupt vector, releases the reporting channels of subsequent interrupt requests of this interrupt vector, and enables subsequent interrupt requests to continue to submit interrupt reporting to the host side after arbitration hits.

[0045] This embodiment will detail and explain many details and principles in the above method.

[0046] Overall, interrupts are very crucial for the reception control of a computer system. The PCIE device uses interrupts to notify the operating system that new data packets have arrived. The host side system calls the device driver to execute the interrupt service routine to complete operations such as receiving and copying the data packets.

[0047] This embodiment supports interrupt submission in MSI / MSI-X mode. Both modes contribute to improving system performance and response speed. The main differences between them are as follows:

[0048] The interrupt vectors of MSI must be continuous, while MSI-X does not need to consider the continuity of interrupt vectors;

[0049] MSI supports a maximum of 32 interrupt vectors, while the number of interrupt vectors supported by MSI-X is much larger than this;

[0050] The memory mapping area of MSI interrupts is in the configuration space of the PCIE device, while the memory mapping area of MSI-X interrupts is located in the BAR (user address space) space of the PCIE device.

[0051] It can be seen that due to the different definitions of the capability structures corresponding to the configuration space, the definition of the MSI-X mode is more flexible. The core principle in the method of this embodiment is applicable to both of the above two modes. Therefore, the preferred MSI-X mode is taken as an example for introduction.

[0052] During initialization, the driver writes the memory mapping address and vector number of the interrupt vector into the MSI-X table in the BAR space. Different interrupt vectors have different memory mapping addresses and vector numbers; after the PCIE device completes the update of data to the host-side memory, it generates a corresponding first MemWr write request message and submits an interrupt according to the information such as the memory mapping address and vector number in the MSI-X table. The host-side RC is responsible for maintaining the MSI-X table mapped by the BAR space, and its configuration can be referred to the Figure 2 schematic diagram.

[0053] Figure 2 In [reference], VecCtrl: bit[0] is used to define the validity of Per_Vector_Mask, that is, the interrupt mask and the corresponding reporting channel to be introduced later; when bit[0]=1, the PCIE device cannot use this Vector to submit an interrupt request; when bit[0]=0, submission is allowed; this field is maintained by the host-side RC, and the PCIE device can only report the Vector interrupt when bit[0]=0.

[0054] MsgData is the interrupt message, which is maintained by the host-side RC and can be directly understood as the vector number corresponding to the interrupt vector; MsgAddr is the interrupt address, which is maintained by the host-side RC, that is, the memory address where the first MemWr write request message is written to the host-side RC.

[0055] During the high-speed data communication and transmission process of a PCIE device, if an interrupt is generated for each data frame, it will cause the host CPU to frequently enter the interrupt service routine, thereby consuming a large amount of system resources for interrupt processing, resulting in a large part of the host CPU's overhead being used to handle the interrupt service routine. Based on the compatibility with the traditional interrupt aggregation mechanism, this embodiment supplements the adaptive interrupt interaction masking method to optimize the control of interrupt reporting.

[0056] First, the implementation idea of the traditional interrupt aggregation mechanism applied in this embodiment is introduced as follows:

[0057] (1) Frequency control; provide a configurable frequency generator to control the frequency of interrupt generation, such as generating an interrupt once every 1 us. Although the frequency control method reduces the number of interrupts, it has drawbacks in balancing the transmission of large and small message data. Therefore, the design of frame count control is added.

[0058] (2) Frame count control; when the number of data frames of the PCIE device reaches a preset threshold, an interrupt is generated correspondingly. By using frame count control for interrupt reporting and setting an interrupt control register in the PCIE device, the driver can dynamically adjust the frequency of interrupt generation and the preset threshold of data frames by controlling the interrupt control register in the BAR space.

[0059] Figure 3 The circuit in [circuit name] shows how to specifically perform frequency control and frame count control. Among them, pd_proc_cnt is the frame counter after processing (each interrupt vector has 1, and the implementation method is the same). When the PCIE device processes 1 queue list item frame, the frame counter is incremented by 1. When the preset threshold is reached, an interrupt trigger signal is generated, and at the same time, the frame counter is cleared; the frequency counter 100ns_cnt is a timer in units of 100 ns. Every 100 ns, the frequency counter is incremented by 1. When the timeout threshold of 1 us is reached, an interrupt trigger signal is generated, and at the same time, the frequency counter is cleared.

[0060] When either of the above two controls reaches the configured threshold, an interrupt trigger is generated. This interrupt aggregation mechanism can complete coarse-grained interrupt reporting control in its design, but the generated interrupt reporting control effect is not ideal. Therefore, this embodiment uses it as the preprocessing part of the method to generate an interrupt trigger signal through this interrupt aggregation mechanism.

[0061] Based on the above coarse-grained interrupt reporting control, this embodiment adds a fine-grained interrupt control design, which can be called adaptive control based on the interactive handshake of the interrupt mask. It performs interactive handshake design through the driver and hardware logic to dynamically control the interrupt reporting. In summary: after the interrupt vector is submitted, the adaptive logic turns on the interrupt mask and shields the interrupt reporting channel; when the host driver executes the interrupt service program and completes data processing and is about to jump out, the adaptive logic is triggered to turn off the interrupt mask and release the interrupt reporting channel again by initiating a second MemWr write request message to the BAR space of the PCIE device.

[0062] In this embodiment, the adaptive logic implements the on / off control of the interrupt mask through the interrupt mask register set in the BAR space of the PCIE device. Figure 4 The indication of Figure 4 In the text box, “MASK” means mask.

[0063] After the PCIE device logic completes the update of a frame of data in the host-side memory space, it generates an interrupt trigger signal through the pre-processed interrupt aggregation mechanism. The adaptive logic determines whether this interrupt trigger signal is shielded by the opening of the interrupt mask. If it is shielded, it enters the interrupt suspension state, otherwise it initiates an interrupt request. After the interrupt request is arbitrated by the priority determination module, if it meets the current execution priority, the memory mapping address and vector number corresponding to the required interrupt vector are obtained by querying the MSI-X table, encapsulated as the first MemWr write request message, and submitted to the host-side RC for interrupt reporting. At the same time, the adaptive logic turns on the interrupt mask corresponding to the vector number to shield the subsequent reporting channel of the interrupt vector.

[0064] After the host-side RC receives the first MemWr write request message in the MSI-X mode, it triggers the driver and enters the interrupt service subroutine. It decides to copy the data frame of the corresponding table item by querying whether the return code of the linked list queue is updated. After waiting for the data frame to be processed, the interrupt service subroutine reclaims system resources and completes the interrupt mask handshake action. This operation is completed by sending a second MemWr write request message of the Poste type to the BAR space of the PCIE device. Because there is no need to wait for the CPLD message returned by the PCIE device, there is almost no bandwidth loss for business transmission.

[0065] After the PCIE device logic receives the second MemWr write request message of the interrupt mask handshake from the host side, it closes the interrupt mask of the corresponding vector number again, thereby releasing its interrupt reporting ability. It can be seen from this that in this embodiment, the opening and closing of the interrupt mask for a specific vector number are both implemented through adaptive logic, but the initiating sources are different. From the perspective of the computer system level, this processing method is a handshake interaction between the software level and the logic level.

[0066] In actual business operations, another situation needs to be considered. When the adaptive logic enables the interrupt mask and shields the interrupt reporting channel, if a new interrupt trigger signal is generated after the corresponding interrupt vector is preprocessed at this time, how should it be handled; if not responded to, in the case that there is no further interrupt trigger for the same interrupt vector, it will cause the host side to lose this part of the updated data content. Therefore, this embodiment also stores the record of the corresponding interrupt trigger signal in the case of shielding the interrupt reporting channel by adding an interrupt pending state; when the priority arbitration module polls this interrupt vector, by determining its interrupt pending state, the arbitration hit of the corresponding interrupt vector can be set and the interrupt submission can be executed, thus effectively preventing interrupt loss.

[0067] In this embodiment, for the interrupt requests initiated by multiple interrupt vectors simultaneously, the round-robin method is adopted for priority polling; among them, the priorities of the interrupt vectors corresponding to all interrupt requests are all reduced by one level in the priority polling of the next cycle, but the priority of the interrupt vector that has been at the lowest priority is filled up to the highest priority in the priority polling of the next cycle. When the priority arbitration module performs arbitration, the interrupt vectors that are not arbitrated and hit still maintain the interrupt pending state when there is an interrupt trigger signal, and wait to submit the interrupt report if they are hit in the priority polling of the next cycle. The corresponding circuit of this part can be seen Figure 5 for the schematic.

[0068] Figure 5 In, the Int_ind signal is the interrupt trigger signal generated after coarse-grained preprocessing, the Int_pengding signal identifies the interrupt pending state of a specific interrupt vector, the Int_mask is the interrupt mask control signal, and the Int_grant is the priority hit response signal of the interrupt vector.

[0069] In this embodiment, it can be seen Figure 6 for the overall process schematic. The method in this embodiment adopts a two-stage logic design before and after to control the interrupt reporting. The front stage performs coarse-grained preprocessing, and the rear stage performs fine-grained adaptive control.

[0070] Therefore, the summary of the method in this embodiment is as follows:

[0071] First, the interrupt time interval and the number of interrupt frames are pre-determined, that is, corresponding to the frequency control and the number of frames control, to determine the interrupt trigger signal generated. In the current state of the interrupt mask, the interrupt trigger signal can set the interrupt suspension state or initiate an interrupt request; the priority arbitration module will arbitrate the hit interrupt vector. The currently hit interrupt vector will turn on the corresponding interrupt mask when submitting the interrupt report, thereby shielding the subsequent interrupt reports of the same interrupt vector; the host side will turn off the interrupt mask after the interrupt service program is executed, releasing the subsequent reporting channel of the interrupt vector.

[0072] The closure of the interrupt reporting channel does not affect the generation of the interrupt trigger signal and the setting of the interrupt suspension state. Therefore, during the interrupt masking period, multiple interrupt trigger signals corresponding to the same interrupt vector will not be lost. In addition, the interrupt submission of different interrupt vectors is balanced through priority polling.

[0073] Through the entire process of the above method, the time when the computer system driver executes the interrupt service program is dynamically consistent with the interrupt reporting rhythm, thereby maximizing the processing performance of the host CPU. This design can adaptively and dynamically feedback to the PCIE device end based on the real-time interrupt service capability of the host CPU and jointly affect the rhythm of the logical interrupt reporting, effectively avoiding the interrupt storm caused by the short-term excessive interrupt reporting of the logical end. Compared with the traditional mechanism that simply uses frequency control and frame number control, further improvements make the interrupt reporting control more accurate and more adaptable.

[0074] The method of this embodiment can therefore also be effectively applied to a computer system, which may include a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the steps of the adaptive interrupt reporting control method for PCIE devices of this embodiment.

Claims

1. An adaptive interrupt reporting control method for a PCIE device, characterized in that: include: PCIE devices generate interrupt trigger signals based on the interrupt aggregation mechanism; The adaptive logic determines whether the reporting channel corresponding to the interrupt trigger signal is shielded by the corresponding interrupt mask. If it is shielded, the interrupt vector corresponding to the interrupt trigger signal enters the interrupt pending state, otherwise an interrupt request is initiated; Priority arbitration is performed on interrupt requests initiated simultaneously by multiple interrupt vectors, and the interrupt requests that are hit by arbitration are submitted to the host for interrupt reporting; at the same time, the adaptive logic turns on the interrupt mask of the interrupt vector corresponding to the interrupt request that is hit by arbitration, shielding the reporting channel of subsequent interrupt requests of the interrupt vector; After the host completes the processing of the corresponding interrupt report, the adaptive logic turns off the interrupt mask of the corresponding interrupt vector, releases the reporting channel for subsequent interrupt requests of the interrupt vector, and enables subsequent interrupt requests to continue to submit interrupt reports to the host after arbitration hits.

2. The adaptive interrupt reporting control method according to claim 1, characterized in that: The PCIE device generates an interrupt trigger signal based on an interrupt aggregation mechanism, including: The interrupt reporting control of the PCIE device is preprocessed, and the preprocessing process includes frequency control and frame number control; the frequency control is to control the frequency of the PCIE device generating interrupts, and the frame number control is to generate an interrupt each time the number of data frames of the PCIE device reaches a preset threshold; when at least one of the frequency control and the frame number control meets the conditions for generating an interrupt, the PCIE device generates an interrupt trigger signal accordingly.

3. The adaptive interrupt reporting control method according to claim 2, characterized in that: An interrupt control register is set for the PCIE device; the driver of the PCIE device dynamically adjusts the frequency of generating interrupts and the preset threshold of the data frame by controlling the interrupt control register set in the BAR space of the PCIE device.

4. The adaptive interrupt reporting control method according to claim 1, characterized in that: When the interrupt request hit by arbitration completes the interrupt report submission, the adaptive logic turns on the interrupt mask of the corresponding interrupt vector and waits for the host to process the interrupt report; After the host driver executes the interrupt service program, when it completes the data processing reported by the interrupt and is about to jump out, the host initiates a MemWr write request message to the BAR space of the PCIE device, triggering the adaptive logic and closing the interrupt mask of the corresponding interrupt vector.

5. The adaptive interrupt reporting control method according to claim 4, characterized in that: An interrupt mask register is set for the PCIE device; the adaptive logic realizes opening and closing of the corresponding interrupt mask by controlling the interrupt mask register set in the BAR space of the PCIE device.

6. The adaptive interrupt reporting control method according to claim 5, characterized in that: When the interrupt mask is turned on, the reporting channel of the corresponding interrupt vector is shielded and loses the interrupt reporting capability. If a corresponding interrupt trigger signal is generated for the interrupt vector at this time, the interrupt suspension state is entered; when the interrupt mask is turned off, the reporting channel of the corresponding interrupt vector is released, the interrupt reporting capability is obtained, and an interrupt request is initiated when the corresponding interrupt trigger signal is generated.

7. The adaptive interrupt reporting control method according to claim 1, characterized in that: The priority arbitration of interrupt requests initiated simultaneously by multiple interrupt vectors includes: For interrupt requests initiated simultaneously by multiple interrupt vectors, the priority determination module performs priority polling in a round-robin manner, determines the interrupt request that has been hit by arbitration based on the polling result, and submits the interrupt report to the host side; the interrupt vector corresponding to the missed interrupt request enters the interrupt suspension state, waiting for the priority polling of the next cycle; during the priority polling process of the next cycle, the priority determination module determines the interrupt request that has been hit by arbitration by determining the priority of each interrupt vector.

8. The adaptive interrupt reporting control method according to claim 7, characterized in that: During the priority polling process, the priority of the interrupt vectors corresponding to all interrupt requests is reduced by one level during the priority polling of the next cycle, but the priority of the interrupt vector that is already at the lowest priority is promoted to the highest priority during the priority polling of the next cycle; in each priority polling process, the interrupt request corresponding to the interrupt vector with the highest priority is arbitrated by the priority arbitration module.

9. The adaptive interrupt reporting control method according to claim 8, characterized in that: For the interrupt vector that enters the suspended state because the interrupt trigger signal is masked by the interrupt mask, the priority determination module also determines the priority of the interrupt vector when performing priority polling; when the interrupt trigger signal corresponding to the interrupt vector is no longer masked by the interrupt mask and the priority of the interrupt vector reaches the highest priority after being supplemented, the priority determination module arbitrates the interrupt request hit initiated by the interrupt vector and submits the interrupt report to the host side.

10. A computer system comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the adaptive interrupt reporting control method for a PCIE device according to any one of claims 1 to 9.

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