A high-efficiency covert channel attack and information leakage method based on multiple interrupt driving

Abstract

The application provides a high-efficiency covert channel attack and information leakage method based on multiple interrupt driving, which is called Compound-INT. Four stable and controllable interrupt types (rtc0, PMI (Performance Monitor Interrupts), MCP (Machine Check Polls), IWI (IRQ Work Interrupts), and TLB (TLB shootdowns)) are screened out by analyzing the / proc / interrupts interface in an operating system to construct an efficient covert channel. The method supports two transmission modes, single bit and multi-bit. Single bit realizes data coding by controlling the interrupt triggering frequency, and multi-bit combines synchronous and asynchronous transmission modes to improve bandwidth and anti-interference, and adapt to the complex conditions of a multi-core environment. In addition, the application realizes the leakage of the existence state of a target file in a restricted directory by using the PMI interrupt, and speculates the structure information of a deep neural network (DNN) model by using the TLB shootdowns interrupt mode, thereby expanding the application scenarios of the covert channel. Experimental results show that the method has high transmission rate, low error rate and strong robustness, and provides a new idea for the security research of the interrupt mechanism of an operating system.

Description

Technical Field

[0001] This invention relates to the field of computer security, and more particularly to methods for attacking intercept-driven covert channels and information leakage. Background Technology

[0002] The security of modern computer systems relies on the collaborative protection of hardware, operating systems, and application layers. However, the openness and flexibility of hardware interfaces also bring potential security vulnerabilities. The processor's interrupt mechanism is a crucial foundation for efficient scheduling in a computer operating system. Through interrupts, the processor can respond promptly to external devices and internal events, completing multitasking switching. However, this mechanism also provides attackers with opportunities to exploit hardware characteristics to carry out information leakage or covert channel attacks. In Linux systems, the ` / proc / interrupts` interface is a critical virtual file system that records the trigger frequency and distribution of various interrupts. Although this interface was originally designed to facilitate system performance analysis and debugging, its openness to all users allows attackers to monitor interrupt patterns, thereby inferring sensitive information at the system's lower levels.

[0003] Research indicates that different types of interrupts record important characteristics reflecting hardware and software behavior during system operation. For example, the Performance Monitoring Interrupt (PMI) reflects changes in processor performance counters, the Real-Time Clock Interrupt (RTC0) is closely related to system time management, the Machine Check Polling Interrupt (MCP) is used to catch hardware errors, and the IWI (Interrupt for Irregular Queues) is used to handle delayed IRQ task queues. These interrupt types have unique triggering patterns in the processor microarchitecture, and the distribution and frequency variations of different interrupts may be strongly correlated with the tasks executed in the system. Attackers can analyze these patterns to construct covert channels for data transmission and even achieve cross-core data leakage.

[0004] Covert channels are non-traditional communication techniques that circumvent traditional security mechanisms. They exploit the shared nature of system resources or differences in hardware behavior to establish unauthorized communication channels between the sender and receiver. For example, frequently triggering cache misses or adjusting memory access patterns can be used to encode bit information. Such covert channels are often difficult to detect by traditional firewalls or access control mechanisms, thus becoming an effective means for attackers to evade security monitoring.

[0005] Existing research on interrupt-driven covert channels primarily focuses on single, specific types of interrupts, such as heat-related, keystroke-related, and graphics-related interrupts. However, these methods often suffer from limitations such as low transmission rates, poor robustness, and susceptibility to interference. For example, research on heat-based side-channels utilizes the thermal interrupt characteristics of the processor, inferring information by monitoring changes in processor temperature. However, due to the cumulative nature of heat changes, this method suffers from low transmission rates and is easily affected by temperature fluctuations caused by other programs running. Therefore, the practical application of these methods in complex systems is somewhat limited.

[0006] On the other hand, the widespread application of deep learning models has raised concerns about their intellectual property and operational security. Modern deep learning models typically run on high-performance hardware, and their inference process involves numerous hardware events, such as memory access, cache usage, and page table updates. These hardware events not only affect the model's execution efficiency but may also leak architectural information. Recent research has shown that by monitoring these hardware events, attackers can infer the architecture of a target model, thereby threatening the model's intellectual property security. Summary of the Invention

[0007] Based on the hardware characteristics of processors, this invention proposes a method for constructing covert channels through the coordinated use of multiple interrupts, a method for fingerprinting deep neural network (DNN) model architectures based on TLB shootdowns events, and a technical solution for determining the existence of files in restricted directories based on performance monitoring interrupts (PMI). Through in-depth analysis of hardware event characteristics and system behavior patterns, this invention reveals the potential applications of processor hardware in covert communication, deep learning security, and file access judgment, providing novel technical approaches for hardware security and information protection.

[0008] In constructing covert channels, this invention fully utilizes the ` / proc / interrupts` interface of the Linux system. By monitoring the trigger frequency and distribution information of four interrupt types—Performance Monitoring Interrupt (PMI), Real-Time Clock Interrupt (rtc0), Machine Check Polling Interrupt (MCP), and Inactive Interrupt (IWI)—it reveals the unique patterns of these interrupts during system operation. These interrupts reflect changes in the state of the underlying hardware, providing a reliable foundation for constructing covert channels. In single-bit covert channels, this invention maps the number of interrupt triggers within a fixed time window to bit values, thereby achieving information encoding and transmission. In multi-bit covert channels, by designing synchronous or asynchronous triggering strategies, it utilizes combinations of various interrupt types to achieve efficient data encoding and decoding. The covert channel technology of this invention successfully achieves cross-core communication in a multi-core processor environment, significantly improving communication robustness and transmission rate, providing strong support for the practical application of covert channel technology.

[0009] In the area of ​​fingerprinting deep neural network models, this invention utilizes the memory operation characteristics reflected by TLB shootdowns events to monitor frequent page table updates and memory access operations during DNN model inference, inferring model architecture information through hardware event behavior patterns. In the offline phase, this invention systematically collects and analyzes TLB shootdowns data, extracts hardware behavior features, and trains a classifier to distinguish different deep learning model architectures. In the online phase, by monitoring TLB shootdowns events on the target machine in real time, the collected event data is input into a pre-trained classifier to achieve rapid identification of the running model architecture. Compared to traditional methods that directly access model parameters or weights, this invention's technology is more covert and versatile, applicable to various deep learning frameworks and hardware platforms, providing strong technical support for the intellectual property protection and security analysis of deep learning models.

[0010] Furthermore, this invention proposes a method for determining the existence of a file in a restricted directory based on Performance Monitoring Interrupts (PMI). PMI is a high-precision performance monitoring tool provided by the processor. During file access permission checks, failure to access a restricted directory will trigger a change in the instruction count, thus triggering a noticeable PMI event. This invention utilizes this characteristic to determine the existence of a target file by capturing and analyzing PMI data related to permission checks. This method does not require direct access to the file or escalation of privileges, exhibiting high stealth and non-intrusiveness. Furthermore, by dynamically adjusting the PMI sampling strategy, the efficiency and accuracy of file existence determination are further improved. This technology can adapt to directory structures of different sizes and levels, demonstrating good adaptability in multiple experimental scenarios.

[0011] This invention integrates three core technologies: covert channel construction, DNN model fingerprinting, and PMI-based file existence determination, fully demonstrating the broad application potential of processor hardware events in covert communication, information protection, and security analysis. In experimental verification, this invention successfully achieved efficient transmission of covert channel communication, accurate identification of various DNN model architectures, and efficient determination of file existence in restricted directories, further proving the wide applicability of hardware events in side-channel attacks and information protection. These research results not only provide important references for operating system permission management, deep learning model security, and hardware design, but also offer innovative directions for technological development in the field of hardware security. By revealing the security vulnerabilities of hardware events, this invention constructs a new technical framework, laying a theoretical foundation and providing technical support for improving the security of computer systems. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some examples of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of an efficient covert channel attack and information leakage method based on multiple interrupt-driven approaches.

[0014] Figure 2 This is a schematic diagram of the covert channel process driven by a single interrupt (four interrupts are available in total);

[0015] Figure 3 This is a schematic diagram of a multi-bit synchronous transmission process;

[0016] Figure 4 This is a schematic diagram of a multi-bit asynchronous transmission process;

[0017] Figure 5 A flowchart illustrating the process of disclosing the contents of a restricted directory;

[0018] Figure 6 This is a schematic diagram of the fingerprint recognition DNN model architecture. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Figure 2 This document describes a schematic diagram of a covert channel based on a single interrupt driver (four interrupts are available). To construct this single-bit covert channel, the following mechanism is designed: when a bit "1" needs to be sent, the sender triggers the corresponding interrupt; when a bit "0" needs to be sent, the sender does not trigger any interrupt. The receiver monitors the ` / proc / interrupts` interface, observes the changes in the target interrupt count, and compares it with a predefined threshold to determine the information transmitted by the sender.

[0021] Figure 3A schematic diagram of the multi-bit synchronous transmission process is described. First, the information to be transmitted is divided into four interrupt types, each interrupt type representing one bit of data, thus forming a four-bit data packet. Every T seconds, the sender determines whether to trigger the corresponding interrupt based on these four bits: if the bit is "1", the corresponding interrupt is triggered; if the bit is "0", it is not triggered. Simultaneously, the receiver monitors the / proc / interrupts interface to record the number of occurrences of these four interrupts every T seconds and compares them with preset thresholds to determine whether the bit transmitted for each interrupt is "0" or "1".

[0022] Figure 4 This describes a schematic diagram of a multi-bit asynchronous transmission process. The sender independently transmits information using four types of interrupts. Specifically, the sender determines whether to trigger the corresponding interrupt based on the value of each bit: if the bit value is "1", an interrupt is triggered; if the bit value is "0", no interrupt is triggered. The receiver records the changes in the interrupt count every Ti seconds through the / proc / interrupts interface and compares it with a preset threshold to determine whether the bit transmitted by the interrupt is "0" or "1".

[0023] Figure 5 This diagram illustrates the process of leaking content from a restricted directory. The directory's permissions are set so that users can write to files but are prohibited from viewing their contents; only the directory owner can access the contents. When a file is accessed via a system call, the kernel's behavior depends on whether the file exists: if the file exists, the system continues with permission checks and submits subsequent instructions; if the file does not exist, the operation terminates immediately. By utilizing the PMU, the CPU can monitor the number of instructions submitted by the kernel. Based on this characteristic, the existence of the target file in the restricted directory can be inferred by judging the number of kernel-submitted instructions, thus effectively bypassing kernel permission restrictions.

[0024] Figure 6 This paper describes a schematic diagram of the fingerprinting process for a DNN model architecture, identifying its architecture by analyzing TLB shootdown events during DNN model runtime. During DNN inference, numerous memory accesses and page table updates trigger TLB refreshes, providing crucial data for our research. The method consists of two phases: offline preparation and online classification. The offline phase collects TLB shootdown events triggered by the DNN and extracts features, training a classifier to associate TLB shootdown event data with a specific DNN architecture. The online phase runs an unknown DNN model on the target machine, monitors TLB shootdown events in real time, and uses the classifier to analyze the data to identify the model architecture.

[0025] Those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims and their equivalents, this invention is also intended to include these modifications and variations.

Claims

1. A method for efficient covert channel attacks and information leakage based on multiple interrupt-driven mechanisms, characterized in that, This method achieves covert data transmission by real-time monitoring of processor hardware events and behavioral characteristics, combined with interrupt triggering and data analysis. Specifically, it includes the following steps: S1. Utilize the processor's / proc / interrupts interface to monitor four vulnerable interrupt types, including Performance Monitoring Interrupt (PMI), Real-Time Clock Interrupt (rtc0), Machine Check Polling Interrupt (MCP), and Irresponse Interrupt (IWI), to obtain interrupt triggering frequency and distribution information. S2. Trigger the above four types of interrupts in a specific way, including calling hardware interfaces (such as perf_event_open) or adjusting system parameters to build a covert channel single-bit transmission mechanism. S3. Design a multi-bit transmission mechanism based on the combination and mode of triggering interrupts, including synchronous multi-bit transmission and asynchronous multi-bit transmission. S4. By monitoring the covert channel data stream in real time, covert information transmission across cores is achieved in a multi-core processor environment.

2. The method according to claim 1, characterized in that, The following specific operations trigger four types of interrupts: calling the hwclock command triggers a real-time clock interrupt (rtc0); using perf_event_open to configure the performance event counter and set the sampling period triggers a performance monitoring interrupt (PMI); adjusting the / sys / devices / system / machinecheck / machinecheck0 / check_interval parameter triggers a machine check polling interrupt (MCP); modifying kernel parameters or loading related modules triggers an inactive interrupt (IWI); TLB shootdowns are triggered after a processor modifies its page table to ensure that all processors' TLB entries remain consistent and up-to-date (TLB).

3. The method according to claim 1, characterized in that, The single-bit covert channel is implemented in the following way: S1. Within a fixed time window, the number of triggers is encoded into bit values ​​by triggering or not triggering an interrupt. S2. Decode single-bit data by monitoring the changes in the corresponding interrupt count in the / proc / interrupts interface.

4. The method according to claim 1, characterized in that, The construction methods of the multi-bit covert channel include: S1. Synchronous transmission: Multiple interrupt types are triggered simultaneously within a fixed time window, and multi-bit data encoding and transmission are achieved through the combination of interrupt counts. S2, Asynchronous transmission: Various interrupts are triggered independently, and parallel transmission is achieved through multiple independent channels. Even if some interrupts are restricted, other channels can still continue to transmit.

5. A method for identifying deep neural network (DNN) model architectures based on processor hardware characteristics, characterized in that, Model fingerprinting is achieved by monitoring hardware events triggered during model inference, specifically including the following steps: S1. Offline Phase: Capture TLB shootdowns events triggered during DNN model inference. Monitoring of TLB shootdowns events is accomplished by reading the / proc / interrupts interface. Collect TLB shootdown traces and train a classifier to associate TLB shootdowns data with specific DNN model architectures. S2, Online Phase: Monitor TLB shootdowns events triggered during the inference process of the black-box DNN model on the target machine in real time; input the real-time event data into the offline-trained classifier to identify the running DNN model architecture.

6. The method according to claim 5, characterized in that, The classifier design incorporates algorithms such as Support Vector Machine (SVM), Logistic Regression (LR), Random Forest (RF), k-Nearest Neighbor (k-NN), and Linear Discriminant Analysis (LDA) for model architecture fingerprinting analysis.

7. The method according to claim 6, characterized in that, The real-time sampling interval is 2 seconds to ensure that TLB shootdown traces are captured throughout the entire DNN model inference cycle.

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