Timing control system and control method thereof, display device

Abstract

The application provides a timing control system and a control method thereof, and a display device, and relates to the technical field of display, and is used for solving the problem that the timing of power-on and power-off work between each driving chip in a display product is difficult to control, the driving chip is in an uncertain state, charge residues are generated on the display panel, and the picture flickers or is abnormally displayed. In the timing control system, a control circuit provides control information to an enabling circuit and provides a basic power supply signal to a power management circuit; the enabling circuit outputs a power supply enabling signal to the power management circuit and outputs a corresponding controlled enabling signal to a controlled circuit under the control of the control information; the power management circuit enters a standby state or a working state under the control of the power supply enabling signal, and can generate a target power supply signal according to the basic power supply signal in the working state; and the controlled circuit enters the standby state or the working state under the control of the controlled enabling signal and the target power supply signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a timing control system and its control method, and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread, and correspondingly, people's requirements for the display quality of display products are also becoming increasingly higher. Display products generally include a display area and a peripheral area. The display area includes multiple sub-pixels used for display, and the peripheral area includes a driving circuit structure used to drive the sub-pixels to achieve display functions. The driving circuit structure includes various types of driving chips, and having too many driving chips can lead to the following problems: the timing of power-on and power-off operation between the various driving chips is difficult to control, and inappropriate power-on and power-off can cause the driving chips to be in an uncertain state, resulting in residual charge on the display panel, thus causing screen flickering or abnormal display. Summary of the Invention

[0003] The purpose of this invention is to provide a timing control system and its control method, as well as a display device, to solve the problem that the timing of power-on and power-off operation of various driver chips in display products is difficult to control, resulting in the driver chips being in an uncertain state, causing residual charge on the display panel, and thus causing screen flickering or abnormal display.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a timing control system, characterized in that it comprises: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit;

[0006] The control circuit is used to provide control information to the enabling circuit and to provide basic power signals to the power management circuit.

[0007] The enabling circuit is used to output a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit under the control of the control information.

[0008] The power management circuit is used to enter a standby state under the control of the power enable signal; or, under the control of the power enable signal, enter a working state, generate a target power signal according to the basic power signal, and transmit the target power signal to the corresponding controlled circuit.

[0009] The controlled circuit is used to enter a standby state or a working state under the control of the controlled enable signal and the target power signal.

[0010] Optionally, when the timing control system transitions from standby state to operating state:

[0011] The control circuit is specifically used to provide first control information to the enabling circuit, wherein the first control information indicates that a power signal is output to the enabling circuit;

[0012] The enabling circuit is specifically used to output a first power enabling signal to the power management circuit after receiving the first control information. The first power enabling signal indicates that the power management circuit enters the working state.

[0013] The power management circuit is specifically used to generate a target power signal based on the basic power signal after receiving the first power enable signal, and to transmit the target power signal to the corresponding controlled circuit.

[0014] The enabling circuit is specifically used to continue outputting a corresponding first controlled enabling signal to the controlled circuit, the first controlled enabling signal indicating that the controlled circuit enters the working state;

[0015] The controlled circuit is specifically used to enter the working state after receiving the first controlled enable signal and the target power signal;

[0016] And / or,

[0017] When the timing control system switches from the working state to the standby state:

[0018] The control circuit is specifically used to provide second control information to the enabling circuit, the second control information indicating to stop outputting power signals to the enabling circuit;

[0019] The enabling circuit is specifically used to output a corresponding second controlled enabling signal to the controlled circuit after receiving the second control information. The second controlled enabling signal indicates that the controlled circuit enters a standby state.

[0020] The enabling circuit is specifically used to continue outputting a second power enabling signal to the power management circuit, the second power enabling signal indicating that the power management circuit enters a standby state;

[0021] The power management circuit is specifically used to enter a standby state after receiving the second power enable signal, and the power management circuit stops generating the target power signal.

[0022] Optionally, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0023] When the timing control system switches from standby state to working state, the enabling circuit is specifically used to: firstly output a corresponding first controlled enable signal to the GAMMA chip, which indicates that the GAMMA chip enters the working state; and then output a corresponding first controlled enable signal to the level conversion chip, which indicates that the level conversion chip enters the working state.

[0024] And / or,

[0025] When the timing control system switches from the working state to the standby state, the enabling circuit is specifically used to: first output a corresponding second controlled enabling signal to the level conversion chip, which indicates that the level conversion chip enters the standby state; and then output a corresponding second controlled enabling signal to the GAMMA chip, which indicates that the GAMMA chip enters the standby state.

[0026] Optionally, the control circuit is further configured to provide instruction information to the enabling circuit, the instruction information indicating the timing of each power enable signal and each controlled enable signal;

[0027] The enabling circuit is used to output a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0028] Optionally, the timing control system further includes a timing control chip; the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0029] The power management circuit is used to generate a first target power signal, a second target power signal and a third target power signal based on the basic power signal, and transmits the first target power signal to the timing control chip, the second target power signal to the GAMMA chip, and the third target power signal to the level conversion chip.

[0030] Based on the above-described timing control system, a second aspect of the present invention provides a display device including the above-described timing control system.

[0031] Based on the above-described technical solution of the timing control system, a third aspect of the present invention provides a timing control method applied to a timing control system, wherein the timing control system includes: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit; the timing control method includes:

[0032] The control circuit provides control information to the enabling circuit and provides basic power signals to the power management circuit;

[0033] Under the control of the control information, the enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit.

[0034] The power management circuit enters a standby state under the control of the power enable signal; or, under the control of the power enable signal, it enters a working state, generates a target power signal based on the basic power signal, and transmits the target power signal to the corresponding controlled circuit.

[0035] The controlled circuit enters a standby state or a working state under the control of the enable signal and the target power signal.

[0036] Optionally, when the timing control system transitions from a standby state to an operating state, the timing control method specifically includes:

[0037] The control circuit provides first control information to the enabling circuit, and the first control information indicates that a power signal is output to the enabling circuit;

[0038] After receiving the first control information, the enabling circuit outputs a first power enable signal to the power management circuit, which instructs the power management circuit to enter the working state.

[0039] After receiving the first power enable signal, the power management circuit generates a target power signal based on the basic power signal and transmits the target power signal to the corresponding controlled circuit.

[0040] The enabling circuit continues to output a corresponding first controlled enabling signal to the controlled circuit, and the first controlled enabling signal indicates that the controlled circuit enters the working state;

[0041] The controlled circuit enters the working state after receiving the first controlled enable signal and the target power signal;

[0042] And / or,

[0043] When the timing control system switches from an operating state to a standby state, the timing control method specifically includes:

[0044] The control circuit provides second control information to the enabling circuit, and the second control information indicates to stop outputting power signals to the enabling circuit;

[0045] After receiving the second control information, the enabling circuit outputs a corresponding second controlled enabling signal to the controlled circuit, and the second controlled enabling signal indicates that the controlled circuit enters a standby state.

[0046] The enabling circuit continues to output a second power enabling signal to the power management circuit, and the second power enabling signal indicates that the power management circuit enters a standby state.

[0047] Upon receiving the second power enable signal, the power management circuit enters a standby state and stops generating the target power signal.

[0048] Optionally, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0049] When the timing control system transitions from a standby state to an operating state, the step of the enabling circuit continuing to output a corresponding first controlled enabling signal to the controlled circuit specifically includes:

[0050] The enabling circuit first outputs a corresponding first controlled enabling signal to the GAMMA chip, which indicates that the GAMMA chip enters the working state; the enabling circuit then outputs a corresponding first controlled enabling signal to the level conversion chip, which indicates that the level conversion chip enters the working state.

[0051] And / or,

[0052] When the timing control system switches from an operating state to a standby state, the step of the enabling circuit outputting a corresponding second controlled enabling signal to the controlled circuit after receiving the second control information specifically includes:

[0053] The enabling circuit first outputs a corresponding second controlled enabling signal to the level conversion chip, which instructs the level conversion chip to enter a standby state; the enabling circuit then outputs a corresponding second controlled enabling signal to the GAMMA chip, which instructs the GAMMA chip to enter a standby state.

[0054] Optionally, the timing control method further includes:

[0055] The control circuit provides instruction information to the enabling circuit, and the instruction information indicates the timing sequence of each power enable signal and each controlled enable signal.

[0056] The enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0057] In the technical solution provided by this invention, an enable circuit is set in the timing control system. This enable circuit is controlled by the control circuit and can output a power enable signal for controlling the power management circuit and a controlled enable signal for controlling the controlled circuits. This allows the power management circuit and each of the controlled circuits to be independently controlled by the corresponding enable signals received, i.e., switching between standby and operating states is achieved according to the specific type of the received enable signal. Therefore, the technical solution provided by this invention achieves flexible control of the power-on and power-off timing of the power management circuit and each controlled circuit by setting the enable circuit, solving the limitations of previously relying solely on power signals to control each controlled circuit, and overcoming the inability to effectively achieve independent control between each controlled circuit due to the overly simplistic control signals.

[0058] Therefore, in the technical solution provided by this invention, by setting the enabling circuit, the power-on and power-off timing of the power management circuit and each controlled circuit can be controlled in a coordinated manner, ensuring that the power management circuit and each controlled circuit operate according to the ideal timing, thus guaranteeing the stability of the system. When the timing control system is applied to display products, it can solve the problem of difficulty in controlling the power-on and power-off timing of various driver chips (i.e., controlled circuits) in display products, which leads to the driver chips being in an uncertain state, causing residual charge on the display panel, resulting in screen flickering or abnormal display.

[0059] Moreover, in the technical solution provided by the present invention, the enabling circuit is independent of each chip structure and is only controlled by the control circuit. It does not need to be powered by the power management circuit. Therefore, when the timing control system is in a standby state, the power management circuit can be controlled to be in a completely non-working standby state, that is, the power management circuit does not need to generate any power signal for external supply, thereby minimizing the power consumption of the entire timing control system. Attached Figure Description

[0060] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0061] Figure 1 A schematic diagram of the modules of a timing control system provided in an embodiment of the present invention;

[0062] Figure 2 This is a power-on and power-off schematic diagram of the timing control method provided in an embodiment of the present invention. Detailed Implementation

[0063] To further illustrate the timing control system, control method, and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0064] Please see Figure 1 and Figure 2 The present invention provides a timing control system, including: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit (such as: a GAMMA chip, a level conversion chip);

[0065] The control circuit is used to provide control information K1 to the enable circuit and a basic power signal PPVCC to the power management circuit.

[0066] The enabling circuit is used to output a power enabling signal EN1 to the power management circuit and a corresponding controlled enabling signal (such as EN2, EN3) to the controlled circuit under the control of the control information K1.

[0067] The power management circuit is used to enter a standby state under the control of the power enable signal; or, under the control of the power enable signal, enter a working state, generate a target power signal according to the basic power signal PPVCC, and transmit the target power signal to the corresponding controlled circuit.

[0068] The controlled circuit is used to enter a standby state or a working state under the control of the controlled enable signal and the target power signal.

[0069] For example, the control circuit includes a host system, the enabling circuit includes an enabling chip (EnableIC), the power management circuit includes a power management chip, and the controlled circuit includes a GAMMA chip (PGAMMA IC) and a level shifting chip (PLS), but is not limited thereto. It is worth noting that the controlled circuit may include, in addition to a GAMMA chip and a level shifting chip, a timing control chip, a source driver, a gate driver, etc.

[0070] For example, the timing control system is applied to a display device that employs Gate On Array (GOA) technology, forming shift register units (GOAs) on the array substrate of the display device. A level conversion chip is used to generate the signals required by the shift register units (GOAs). A GAMMA chip is used to generate the GAMMA voltage required by the display device.

[0071] For example, the control circuit provides control information to the enabling circuit to indicate the operating state of the enabling circuit. For instance, the control information includes outputting a power signal to the enabling circuit or stopping the output of a power signal to the enabling circuit. Based on this control information, the enabling circuit controls the type of output enabling signal. For example, it outputs a first set of enabling signals or a second set of enabling signals. The first set of enabling signals includes a first power enabling signal EN11 and a first controlled enabling signal (e.g., EN21, EN31), and the second set of enabling signals includes a second power enabling signal EN12 and a second controlled enabling signal (e.g., EN22, EN32). The first power enabling signal EN11 and the first controlled enabling signal (e.g., EN21, EN31) can be set to be high-level signals, and the second power enabling signal EN12 and the second controlled enabling signal (e.g., EN22, EN32) can be set to be low-level signals, but this is not limited to these settings.

[0072] For example, the power management circuit is controlled by two sets of signals: a power enable signal EN1 and a basic power signal PPVCC. The basic power signal PPVCC supplies power to the power management circuit, and the power management circuit can also generate a target power signal based on the basic power signal PPVCC. The power management circuit is used to enter a standby state or an operating state under the control of the power enable signal. When the power management circuit enters the standby state, it stops generating the target power signal; when the power management circuit enters the operating state, it generates the target power signal.

[0073] As can be seen from the specific structure of the timing control system described above, the timing control system provided in this embodiment of the invention includes an enable circuit. This enable circuit is controlled by the control circuit and can output a power enable signal for controlling the power management circuit and a controlled enable signal for controlling the controlled circuits. This allows the power management circuit and each of the controlled circuits to be independently controlled by the corresponding received enable signals, i.e., switching between standby and operating states is achieved based on the specific type of the received enable signal. Therefore, the timing control system provided in this embodiment of the invention achieves flexible control over the power-on and power-off timing of the power management circuit and each controlled circuit by setting the enable circuit. This solves the limitations of previously relying solely on power signals to control each controlled circuit and overcomes the problem of overly simplistic signals that prevent effective independent control between the controlled circuits.

[0074] Therefore, in the timing control system provided by this embodiment of the invention, by setting the enabling circuit, the power-on and power-off timing of the power management circuit and each controlled circuit can be controlled in a coordinated manner, ensuring that the power management circuit and each controlled circuit operate according to the ideal timing, thus guaranteeing the stability of the system. When the timing control system is applied to display products, it can solve the problem of difficulty in controlling the power-on and power-off timing of each driver chip (i.e., controlled circuit) in the display product, which leads to the driver chip being in an uncertain state, causing residual charge on the display panel, resulting in screen flickering or abnormal display.

[0075] Moreover, in the timing control system provided by the embodiments of the present invention, the enabling circuit is independent of each chip structure and is only controlled by the control circuit. It does not need to be powered by the power management circuit. Therefore, when the timing control system as a whole is in standby mode, the power management circuit can be controlled to be in a completely non-working standby mode, that is, the power management circuit does not need to generate any power signal for external supply, thereby minimizing the power consumption of the entire timing control system.

[0076] like Figure 2 As shown, in some embodiments, when the timing control system transitions from a standby state to an operating state:

[0077] The control circuit is specifically used to provide first control information to the enabling circuit, wherein the first control information indicates that a power signal is output to the enabling circuit;

[0078] The enabling circuit is specifically used to output a first power enable signal EN11 to the power management circuit after receiving the first control information. The first power enable signal EN11 indicates that the power management circuit enters the working state.

[0079] The power management circuit is specifically used to generate a target power signal based on the basic power signal PPVCC after receiving the first power enable signal EN11, and transmit the target power signal to the corresponding controlled circuit.

[0080] The enabling circuit is specifically used to continue to output a corresponding first controlled enabling signal (e.g., EN21, EN31) to the controlled circuit, and the first controlled enabling signal (e.g., EN21, EN31) indicates that the controlled circuit enters the working state.

[0081] The controlled circuit is specifically used to enter the working state after receiving the first controlled enable signal (e.g., EN21, EN31) and the target power signal;

[0082] For example, when the timing control system transitions from a standby state to an operating state, i.e., when the timing control system is powered on, the enabling circuit first outputs a first power enable signal EN11, and then outputs a first controlled enable signal (e.g., EN21, EN31). When the timing control system includes at least two controlled circuits, the first controlled enable signals (e.g., EN21, EN31) received by each controlled circuit can also have a sequential order.

[0083] For example, when the timing control system is in standby mode and operating mode, the control circuit provides the basic power signal PPVCC to the power management circuit.

[0084] In some embodiments, when the timing control system transitions from an operating state to a standby state:

[0085] The control circuit is specifically used to provide second control information to the enabling circuit, the second control information indicating to stop outputting power signals to the enabling circuit;

[0086] The enabling circuit is specifically used to output a corresponding second controlled enabling signal (e.g., EN22, EN32) to the controlled circuit after receiving the second control information. The second controlled enabling signal (e.g., EN22, EN32) indicates that the controlled circuit enters a standby state.

[0087] The enabling circuit is specifically used to continue outputting a second power enabling signal EN12 to the power management circuit, and the second power enabling signal EN12 indicates that the power management circuit enters a standby state.

[0088] The power management circuit is specifically used to enter a standby state after receiving the second power enable signal EN12, and the power management circuit stops generating the target power signal.

[0089] For example, when the timing control system switches from an operating state to a standby state, that is, when the timing control system is powered down, the enabling circuit first outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the controlled circuit, and then outputs a second power enabling signal EN12. When the timing control system includes at least two controlled circuits, the second controlled enabling signals (e.g., EN22, EN32) received by each controlled circuit can also have a sequential order.

[0090] In the timing control system provided in the above embodiments, the enabling circuit first outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the controlled circuit, and then outputs a second power enabling signal EN12, so that the controlled circuit is first in a standby state, and then the power management circuit is in a standby state. This method is beneficial to improve the discharge time of the controlled circuit, so that the controlled circuit can discharge fully. When the timing control system is applied to display products, the display products can be discharged more fully.

[0091] In the standby state, the timing control system provided in the above embodiment continues to provide the basic power signal PPVCC to the power management circuit. The enable circuit outputs the second power enable signal EN12 and the second controlled enable signal (e.g., EN22, EN32). Both the power management circuit and the controlled circuit are in standby state. This not only saves power consumption, but also allows the power management circuit and the controlled circuit to be quickly switched to the working state when the timing control system switches from standby state to working state by controlling the enable circuit to output the first power enable signal EN11 and the first controlled enable signal (e.g., EN21, EN31), thus achieving a high response speed.

[0092] In some embodiments, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0093] When the timing control system switches from standby state to working state, the enabling circuit is specifically used to: firstly output a corresponding first controlled enable signal (e.g., EN21) to the GAMMA chip, which indicates that the GAMMA chip enters the working state; and then output a corresponding first controlled enable signal (e.g., EN31) to the level conversion chip, which indicates that the level conversion chip enters the working state.

[0094] And / or,

[0095] When the timing control system switches from the working state to the standby state, the enabling circuit is specifically used to: first output a corresponding second controlled enable signal (e.g., EN32) to the level conversion chip, which indicates that the level conversion chip enters the standby state; then output a corresponding second controlled enable signal (e.g., EN22) to the GAMMA chip, which indicates that the GAMMA chip enters the standby state.

[0096] For example, the timing control system further includes a timing control chip TCON IC; the at least one controlled circuit includes a GAMMA chip and a level conversion chip; the power management circuit is used to generate a first target power signal Power1, a second target power signal Power2 and a third target power signal Power3 according to the basic power signal PPVCC, and transmit the first target power signal Power1 to the timing control chip TCON IC, transmit the second target power signal Power2 to the GAMMA chip, and transmit the third target power signal Power3 to the level conversion chip.

[0097] For example, the timing control system further includes a driver IC, and the power management circuit is also used to transmit the second target power signal Power2 to the driver IC.

[0098] For example, when the timing control system transitions from standby to operating state, the power management circuit starts working after receiving the first power enable signal EN11, generating a first target power signal Power1 which is transmitted to the timing control chip, generating a second target power signal Power2 which is transmitted to the GAMMA chip, and generating a third target power signal Power3 which is transmitted to the level conversion chip. At this time, both the GAMMA chip and the level conversion chip are waiting for the corresponding first controlled enable signal (e.g., EN21, EN31). When the GAMMA chip receives the corresponding first controlled enable signal (e.g., EN21, EN31), the GAMMA chip starts working; when the level conversion chip receives the corresponding first controlled enable signal (e.g., EN21, EN31), the level conversion chip starts working.

[0099] For example, when the timing control system switches from the working state to the standby state, the enabling circuit first outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the level conversion chip, causing the level conversion chip to enter the standby state and discharge, thus enabling the display panel to enter the discharge state according to the settings; then, the enabling circuit outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the GAMMA chip, causing the GAMMA chip to enter the standby state and discharge; finally, the enabling circuit outputs a second power enabling signal EN12 to the power management circuit, causing the power management circuit to enter the standby state and discharge, thus stopping the generation of each target power signal.

[0100] In the timing control system provided in the above embodiments, by setting the enable circuit, the power-on and power-off timing of the power management circuit and each controlled circuit can be controlled in a coordinated manner, ensuring that the power management circuit and each controlled circuit operate according to the ideal timing, thus guaranteeing the stability of the system. Simultaneously, during power-on, it ensures that each chip powers on in sequence, reducing display product startup issues such as image distortion and screen flickering. During power-off, it causes the level conversion chip controlling the discharge of the display panel to enter standby mode first, ensuring that other ICs only enter standby mode after the display panel has completely discharged, thus avoiding problems such as power-off ghosting, screen flickering, and charge accumulation in the display product.

[0101] In some embodiments, the control circuit is further configured to provide instruction information to the enabling circuit, the instruction information indicating the timing of each power enable signal and each controlled enable signal;

[0102] The enabling circuit is used to output a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0103] For example, the enabling circuit includes a register in which the instruction information is stored, but is not limited to this.

[0104] For example, the timing of each power enable signal and each controlled enable signal can be adjusted according to actual needs, thereby realizing the adjustment of the power-on and power-off sequence between chips. See details below. Figure 2 , Figure 2 In the command information, t1 represents the time interval between the first power enable signal EN11 and the first controlled enable signal EN21 when power is applied; t2 represents the time interval between the first controlled enable signal EN21 and the first controlled enable signal EN31; t3 represents the time interval between the second controlled enable signal EN32 and the second controlled enable signal EN22; and t4 represents the time interval between the second controlled enable signal EN22 and the second power enable signal EN12. By changing the command information, t1, t2, t3, and t4 can be adjusted.

[0105] For example, the control circuit can modify the internal register of the enable circuit via I2C (two-way two-wire synchronous serial bus) to adjust t1, t2, t3, and t4 to obtain different power-on and power-off sequences.

[0106] In the timing control system provided in the above embodiments, the timing of each enabling signal can be adjusted by the control circuit, resulting in higher controllability and greater flexibility.

[0107] This invention also provides a display device, including the timing control system provided in the above embodiments.

[0108] For example, the display device includes a liquid crystal display device, an organic light-emitting diode display device, etc., but is not limited to these.

[0109] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0110] The display device provided in this embodiment of the invention, when including the aforementioned timing control system, can solve the problem of difficulty in controlling the power-on and power-off timing of various driving chips (i.e., controlled circuits) in the display device, which leads to the driving chips being in an uncertain state, causing residual charge on the display panel in the display device, thereby causing screen flickering or abnormal display. The display device provided in this embodiment of the invention, when including the aforementioned timing control system, helps to reduce the overall power consumption of the display device.

[0111] This invention also provides a timing control method applied to a timing control system, the timing control system comprising: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit; the timing control method comprising:

[0112] The control circuit provides control information to the enabling circuit and provides a basic power signal PPVCC to the power management circuit.

[0113] Under the control of the control information, the enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit.

[0114] The power management circuit enters a standby state under the control of the power enable signal; or, under the control of the power enable signal, it enters a working state, generates a target power signal according to the basic power signal PPVCC, and transmits the target power signal to the corresponding controlled circuit.

[0115] The controlled circuit enters a standby state or a working state under the control of the enable signal and the target power signal.

[0116] In the timing control method provided by this invention, the enabling circuit is controlled by the control circuit and can output a power enabling signal for controlling the power management circuit and a controlled enabling signal for controlling the controlled circuit. This allows the power management circuit and each controlled circuit to be independently controlled by the received corresponding enabling signal, i.e., switching between standby and operating states is achieved based on the specific type of the received enabling signal. Therefore, the timing control method provided by this invention achieves flexible control over the power-on and power-off timing of the power management circuit and each controlled circuit by setting the enabling circuit. This solves the limitations of previously relying solely on power signals to control each controlled circuit and overcomes the problem of overly simplistic signals that prevent effective independent control between the controlled circuits.

[0117] Therefore, in the timing control method provided by this embodiment of the invention, by setting the enabling circuit, the power-on and power-off timing of the power management circuit and each controlled circuit can be controlled in a coordinated manner, ensuring that the power management circuit and each controlled circuit operate according to the ideal timing, thus guaranteeing the stability of the system. When the timing control system is applied to display products, it can solve the problem of difficulty in controlling the power-on and power-off timing of each driver chip (i.e., controlled circuit) in the display product, which leads to the driver chip being in an uncertain state, causing residual charge on the display panel, resulting in screen flickering or abnormal display.

[0118] Moreover, in the timing control method provided by the embodiments of the present invention, the enabling circuit is independent of each chip structure and is only controlled by the control circuit. It does not need to be powered by the power management circuit. Therefore, when the timing control system as a whole is in standby mode, the power management circuit can be controlled to be in a completely non-working standby mode, that is, the power management circuit does not need to generate any power signal for external supply, thereby minimizing the power consumption of the entire timing control system.

[0119] In some embodiments, when the timing control system transitions from a standby state to an operating state, the timing control method specifically includes:

[0120] The control circuit provides first control information to the enabling circuit, and the first control information indicates that a power signal is output to the enabling circuit;

[0121] After receiving the first control information, the enabling circuit outputs a first power enable signal EN11 to the power management circuit. The first power enable signal EN11 indicates that the power management circuit enters the working state.

[0122] After receiving the first power enable signal EN11, the power management circuit generates a target power signal based on the basic power signal PPVCC and transmits the target power signal to the corresponding controlled circuit.

[0123] The enabling circuit continues to output a corresponding first controlled enabling signal (e.g., EN21, EN31) to the controlled circuit, and the first controlled enabling signal (e.g., EN21, EN31) indicates that the controlled circuit enters the working state.

[0124] The controlled circuit enters the working state after receiving the first controlled enable signal (e.g., EN21, EN31) and the target power signal;

[0125] And / or, when the timing control system transitions from an operating state to a standby state, the timing control method specifically includes:

[0126] The control circuit provides second control information to the enabling circuit, and the second control information indicates to stop outputting power signals to the enabling circuit;

[0127] After receiving the second control information, the enabling circuit outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the controlled circuit. The second controlled enabling signal (e.g., EN22, EN32) indicates that the controlled circuit enters a standby state.

[0128] The enabling circuit continues to output a second power enabling signal EN12 to the power management circuit, and the second power enabling signal EN12 indicates that the power management circuit enters a standby state.

[0129] Upon receiving the second power enable signal EN12, the power management circuit enters a standby state and stops generating the target power signal.

[0130] In the timing control method provided in the above embodiments, the enabling circuit first outputs a corresponding second controlled enabling signal (e.g., EN22, EN32) to the controlled circuit, and then outputs a second power enabling signal EN12, so that the controlled circuit is first in a standby state, and then the power management circuit is in a standby state. This method is beneficial to improve the discharge time of the controlled circuit, so that the controlled circuit can discharge fully. When the timing control system is applied to display products, the display products can be discharged more fully.

[0131] In the timing control method provided in the above embodiments, in the standby state, the control circuit continues to provide the basic power signal PPVCC to the power management circuit, and the enable circuit outputs the second power enable signal EN12 and the second controlled enable signal (e.g., EN22, EN32). Both the power management circuit and the controlled circuit are in the standby state. This not only saves power consumption, but also enables the power management circuit and the controlled circuit to quickly switch to the working state when the timing control system switches from the standby state to the working state by controlling the enable circuit to output the first power enable signal EN11 and the first controlled enable signal (e.g., EN21, EN31), thus achieving a high response speed.

[0132] In some embodiments, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0133] When the timing control system transitions from a standby state to an operating state, the step of the enabling circuit continuing to output a corresponding first controlled enabling signal to the controlled circuit specifically includes:

[0134] The enabling circuit first outputs a corresponding first controlled enabling signal to the GAMMA chip, which indicates that the GAMMA chip enters the working state; the enabling circuit then outputs a corresponding first controlled enabling signal to the level conversion chip, which indicates that the level conversion chip enters the working state.

[0135] And / or,

[0136] When the timing control system switches from an operating state to a standby state, the step of the enabling circuit outputting a corresponding second controlled enabling signal to the controlled circuit after receiving the second control information specifically includes:

[0137] The enabling circuit first outputs a corresponding second controlled enabling signal to the level conversion chip, which instructs the level conversion chip to enter a standby state; the enabling circuit then outputs a corresponding second controlled enabling signal to the GAMMA chip, which instructs the GAMMA chip to enter a standby state.

[0138] In the timing control method provided in the above embodiments, by setting the enable circuit, the power-on and power-off timing of the power management circuit and each controlled circuit can be controlled in a coordinated manner, ensuring that the power management circuit and each controlled circuit operate according to the ideal timing, thus guaranteeing the stability of the system. Simultaneously, during power-on, it ensures that each chip powers on sequentially, reducing display product startup issues such as image distortion and screen flickering. During power-off, it causes the level conversion chip controlling the discharge of the display panel to enter standby mode first, ensuring that other ICs only enter standby mode after the display panel has completely discharged, thus avoiding problems such as power-off ghosting, screen flickering, and charge accumulation in the display product.

[0139] In some embodiments, the timing control method further includes:

[0140] The control circuit provides instruction information to the enabling circuit, and the instruction information indicates the timing sequence of each power enable signal and each controlled enable signal.

[0141] The enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0142] In the timing control method provided in the above embodiments, the timing of each enable signal can be adjusted by the control circuit, resulting in higher controllability and greater flexibility.

[0143] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, changes in the order of the steps are also within the scope of protection of the present invention without creative effort.

[0144] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0145] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0146] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0147] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0148] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A timing control system, characterized by, include: Control circuit, enable circuit, power management circuit and at least one controlled circuit; The control circuit is used to provide control information to the enabling circuit and to provide basic power signals to the power management circuit. The enabling circuit is used to output a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit under the control of the control information. The power management circuit is used to enter a standby state under the control of the power enable signal; or, under the control of the power enable signal, enter a working state, generate a target power signal according to the basic power signal, and transmit the target power signal to the corresponding controlled circuit. The controlled circuit is used to enter a standby state or a working state under the control of the controlled enable signal and the target power signal; When the timing control system transitions from standby state to operating state: The control circuit is specifically used to provide first control information to the enabling circuit, wherein the first control information indicates that a power signal is output to the enabling circuit; The enabling circuit is specifically used to output a first power enabling signal to the power management circuit after receiving the first control information. The first power enabling signal indicates that the power management circuit enters the working state. The power management circuit is specifically used to generate a target power signal based on the basic power signal after receiving the first power enable signal, and to transmit the target power signal to the corresponding controlled circuit. The enabling circuit is specifically used to continue outputting a corresponding first controlled enabling signal to the controlled circuit, the first controlled enabling signal indicating that the controlled circuit enters the working state; The controlled circuit is specifically used to enter the working state after receiving the first controlled enable signal and the target power signal; And / or, When the timing control system switches from the working state to the standby state: The control circuit is specifically used to provide second control information to the enabling circuit, the second control information indicating to stop outputting power signals to the enabling circuit; The enabling circuit is specifically used to output a corresponding second controlled enabling signal to the controlled circuit after receiving the second control information. The second controlled enabling signal indicates that the controlled circuit enters a standby state. The enabling circuit is specifically used to continue outputting a second power enabling signal to the power management circuit, the second power enabling signal indicating that the power management circuit enters a standby state; The power management circuit is specifically used to enter a standby state after receiving the second power enable signal, and the power management circuit stops generating the target power signal.

2. The timing control system of claim 1, wherein, The at least one controlled circuit includes a GAMMA chip and a level conversion chip; When the timing control system switches from standby state to working state, the enabling circuit is specifically used to: firstly output a corresponding first controlled enable signal to the GAMMA chip, which indicates that the GAMMA chip enters the working state; and then output a corresponding first controlled enable signal to the level conversion chip, which indicates that the level conversion chip enters the working state. And / or, When the timing control system switches from the working state to the standby state, the enabling circuit is specifically used to: first output a corresponding second controlled enabling signal to the level conversion chip, which indicates that the level conversion chip enters the standby state; and then output a corresponding second controlled enabling signal to the GAMMA chip, which indicates that the GAMMA chip enters the standby state.

3. The timing control system according to claim 1, characterized in that, The control circuit is also used to provide instruction information to the enabling circuit, the instruction information indicating the timing of each power enable signal and each controlled enable signal; The enabling circuit is used to output a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

4. The timing control system of claim 1, wherein, The timing control system further includes a timing control chip; the at least one controlled circuit includes a GAMMA chip and a level conversion chip; The power management circuit is used to generate a first target power signal, a second target power signal and a third target power signal based on the basic power signal, and transmits the first target power signal to the timing control chip, the second target power signal to the GAMMA chip, and the third target power signal to the level conversion chip.

5. A display device, characterized in that, The timing control system includes any one of claims 1 to 4.

6. A timing control method, characterized in that, The timing control method is applied to a timing control system, which includes: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit; the timing control method includes: The control circuit provides control information to the enabling circuit and provides basic power signals to the power management circuit; Under the control of the control information, the enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit. The power management circuit enters a standby state under the control of the power enable signal; or, under the control of the power enable signal, it enters a working state, generates a target power signal based on the basic power signal, and transmits the target power signal to the corresponding controlled circuit. The controlled circuit enters a standby state or a working state under the control of the enable signal and the target power signal. When the timing control system transitions from a standby state to an operating state, the timing control method specifically includes: The control circuit provides first control information to the enabling circuit, and the first control information indicates that a power signal is output to the enabling circuit; After receiving the first control information, the enabling circuit outputs a first power enable signal to the power management circuit, which instructs the power management circuit to enter the working state. After receiving the first power enable signal, the power management circuit generates a target power signal based on the basic power signal and transmits the target power signal to the corresponding controlled circuit. The enabling circuit continues to output a corresponding first controlled enabling signal to the controlled circuit, and the first controlled enabling signal indicates that the controlled circuit enters the working state; The controlled circuit enters the working state after receiving the first controlled enable signal and the target power signal; And / or, When the timing control system switches from an operating state to a standby state, the timing control method specifically includes: The control circuit provides second control information to the enabling circuit, and the second control information indicates to stop outputting power signals to the enabling circuit; After receiving the second control information, the enabling circuit outputs a corresponding second controlled enabling signal to the controlled circuit, and the second controlled enabling signal indicates that the controlled circuit enters a standby state. The enabling circuit continues to output a second power enabling signal to the power management circuit, and the second power enabling signal indicates that the power management circuit enters a standby state. Upon receiving the second power enable signal, the power management circuit enters a standby state and stops generating the target power signal.

7. The timing control method according to claim 6, characterized in that, The at least one controlled circuit includes a GAMMA chip and a level conversion chip; When the timing control system transitions from a standby state to an operating state, the step of the enabling circuit continuing to output a corresponding first controlled enabling signal to the controlled circuit specifically includes: The enabling circuit first outputs a corresponding first controlled enabling signal to the GAMMA chip, which indicates that the GAMMA chip enters the working state; the enabling circuit then outputs a corresponding first controlled enabling signal to the level conversion chip, which indicates that the level conversion chip enters the working state. And / or, When the timing control system switches from an operating state to a standby state, the step of the enabling circuit outputting a corresponding second controlled enabling signal to the controlled circuit after receiving the second control information specifically includes: The enabling circuit first outputs a corresponding second controlled enabling signal to the level conversion chip, which instructs the level conversion chip to enter a standby state; the enabling circuit then outputs a corresponding second controlled enabling signal to the GAMMA chip, which instructs the GAMMA chip to enter a standby state.

8. The timing control method according to claim 6, characterized in that, The timing control method further includes: The control circuit provides instruction information to the enabling circuit, and the instruction information indicates the timing sequence of each power enable signal and each controlled enable signal. The enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

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