Shift register, gate drive circuit, display panel and display device

Abstract

The invention discloses a shift register, a gate drive circuit, a display panel and a display device. The shift register comprises an output module, a first pull-down module and a second pull-down module, the output module is used for controlling the voltage output by the output end based on the first node and the signal of the clock signal end; the first pull-down module is used for controlling the voltage of a second node based on a first voltage signal end and a signal of the first node; the second pull-down module is used for controlling the voltage of the first node based on a second voltage signal end and a signal of the second node; the voltage of the second voltage signal end is smaller than that of the first voltage signal end. According to the embodiment of the invention, the reliability of the shift register can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel and a display device. Background Art

[0002] With the development of display technology, the application of display products is becoming more and more common, and users have more and more requirements on the display quality of display panels.

[0003] The display product includes pixels and a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, and the shift registers output scanning signals to scan and drive the pixels. How to ensure the reliability of the shift registers is a technical problem faced by those skilled in the art. Summary of the invention

[0004] The embodiments of the present application provide a shift register, a gate driving circuit, a display panel and a display device, which can improve the reliability of the shift register.

[0005] On the one hand, an embodiment of the present application provides a shift register, including: an output module, a first pull-down module, and a second pull-down module; the output module controls the voltage output by the output end based on the signal of the first node and the clock signal end; the first pull-down module controls the voltage of the second node based on the first voltage signal end and the signal of the first node; the second pull-down module controls the voltage of the first node based on the second voltage signal end and the signal of the second node; the voltage of the second voltage signal end is less than the voltage of the first voltage signal end.

[0006] On the other hand, an embodiment of the present application provides a gate driving circuit, comprising the shift register as described in the above embodiment.

[0007] On the other hand, an embodiment of the present application provides a display panel, comprising the gate driving circuit as described in the above embodiment.

[0008] On the other hand, an embodiment of the present application provides a display device, including the display panel as described in the above embodiment.

[0009] According to the shift register provided by the embodiment of the present application, the second pull-down module is connected to the second voltage signal terminal with a smaller voltage, so that when the second pull-down module is turned on, the signal of the second voltage terminal with a smaller voltage is transmitted to the first node, so that the drift in the negative direction of the threshold voltage of the transistor controlled by the first node in the output module at least partially offsets its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node in the output module; similarly, the drift in the negative direction of the threshold voltage of the transistor controlled by the first node in the first pull-down module at least partially offsets its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node in the first pull-down module; thereby reducing the characteristic changes of the transistors in the shift register and improving the reliability of the shift register. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0011] Figure 1 A schematic diagram showing a structure of a shift register provided in an embodiment of the present application is shown;

[0012] Figure 2 A schematic diagram showing a threshold voltage of a transistor in a shift register provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram showing the structure of some modules in the shift register provided in an embodiment of the present application is shown;

[0014] Figure 4 Another structural schematic diagram of a shift register provided in an embodiment of the present application is shown;

[0015] Figure 5 A schematic diagram showing a comparative example;

[0016] Figure 6 A schematic diagram showing the structure of some modules in the shift register provided in an embodiment of the present application is shown;

[0017] Figure 7 Another structural schematic diagram of some modules in the shift register provided in an embodiment of the present application is shown;

[0018] Figure 8 Another structural schematic diagram of a shift register provided in an embodiment of the present application is shown;

[0019] Fig. 9 A timing diagram of a shift register provided in an embodiment of the present application is shown;

[0020] Fig.10A schematic diagram showing a structure of a gate drive circuit provided in an embodiment of the present application is shown;

[0021] Fig.11 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0022] Fig.12 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] The term “connect” may mean “electrically connected” or “not electrically connected via an intermediate transistor.” The term “drive” may mean “control” or “operate.” The display panel may be a display device or a module / part of a display device.

[0028] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0029] When the ambient temperature and operating temperature of display products are high, the reliability requirements for display products are also high.

[0030] The inventor of the present application conducted a reliability experiment on the display product under high temperature and found that applying high voltage (stress) to the transistors in the shift register caused the threshold voltage (Vth) of the transistor to drift, thereby causing the characteristics of the transistor to change and even causing the shift register to fail.

[0031] In order to solve the above technical problems, the embodiments of the present application provide a shift register, a gate driving circuit, a display panel and a display device. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, the shift register VSR provided in the embodiment of the present application includes an output module 1 , a first pull-down module 21 , and a second pull-down module 22 .

[0033] The output module 1 is connected to the first node PU, the clock signal terminal CK, and the output terminal GOUT. The output module 1 controls the voltage outputted by the output terminal GOUT based on the signals of the first node PU and the clock signal terminal CK.

[0034] The first pull-down module 21 is connected to the first voltage signal terminal VGL1, the first node PU, and the second node PD. The first pull-down module 21 controls the voltage of the second node PD based on the signals of the first voltage signal terminal VGL1 and the first node PU.

[0035] The second pull-down module 22 is connected to the second voltage signal terminal VGL2, the second node PD, and the first node PU. The second pull-down module 22 controls the voltage of the first node PU based on the signals of the second voltage signal terminal VGL2 and the second node PD.

[0036] The voltage of the second voltage signal terminal VGL2 is lower than the voltage of the first voltage signal terminal VGL1 .

[0037] Exemplarily, the output module 1, the first pull-down module 21, and the second pull-down module 22 all include transistors. The first node PU is connected to the control end of the output module 1 and the control end of the first pull-down module 21, and the second node PD is connected to the control end of the second pull-down module 22. Exemplarily, the voltage of the first voltage signal terminal VGL1 and the voltage of the second voltage signal terminal VGL2 are both negative voltages. The transistors in the output module 1, the first pull-down module 21, and the second pull-down module 22 are N-type transistors. For example, the transistors in the output module 1, the first pull-down module 21, and the second pull-down module 22 are indium gallium zinc oxide (IGZO) type transistors. Of course, the transistors in the shift register may also be other types of transistors, for example, A-Si transistors.

[0038] Please refer to Figure 2 and Figure 3 , Figure 2 The horizontal axis represents time, and the vertical axis represents threshold voltage. Figure 3 In the example, the transistors controlled by the first node PU in the output module 1 and the first pull-down module 21 are respectively the first transistor T1 and the third transistor T3, and the first transistor T1 and the third transistor T3 are IGZO or A-Si type transistors.

[0039] The working process of the shift register includes a first period A and a second period B. In the first period A, the first node PU is at a conduction level, the first transistor T1 and the third transistor T3 are turned on, at this time, the Vgs (gate-source voltage difference) of the first transistor T1 is greater than 0, the Vgs of the third transistor T3 is also greater than 0, and the threshold voltages of the first transistor T1 and the third transistor T3 drift toward the first direction (forward drift).

[0040] In the second period B, the second node PD is at the on level, the second pull-down module 22 is turned on, the voltage of the second voltage signal terminal VGL2 is transmitted to the first node PU, the first transistor T1 and the third transistor T3 are disconnected, and since the voltage of the second voltage signal terminal VGL2 is smaller than the voltage of the first voltage signal terminal VGL1, the gate voltage of the first transistor T1 is smaller than the source voltage of the first transistor T1, the gate voltage of the third transistor T3 is smaller than the source voltage of the first transistor T1, the Vgs of the first transistor T1 is smaller than 0, and the Vgs of the third transistor T3 is also smaller than 0. For IGZO or A-Si type transistors, their Vgs is less than 0 for a long time, and their threshold voltage drifts in the second direction (negative drift), and the second direction is opposite to the first direction. For example, the first direction is the direction in which the threshold voltage increases, and the second direction is the direction in which the threshold voltage decreases. The direction in which the threshold voltage increases can also be called the positive drift of the threshold voltage, and the direction in which the threshold voltage decreases can also be called the negative drift of the threshold voltage. That is to say, in the embodiment of the present application, in the first time period, the transistors controlled by the first node PU in the output module 1 and the first pull-down module 21 are equivalent to being applied with positive bias temperature stress (Positive Bias Temperature Stress, PBTS), so that the threshold voltage of the transistors controlled by the first node PU in the output module 1 and the first pull-down module 21 is positively drifted. In the second time period B, the transistors controlled by the first node PU in the output module 1 and the first pull-down module 21 are equivalent to being applied with negative bias temperature stress (Negative Bias Temperature Stress, NBTS), so that the threshold voltage of the transistors controlled by the first node PU in the output module 1 and the first pull-down module 21 is negatively drifted.

[0041] In this way, the drift in the negative direction of the threshold voltage of the transistor controlled by the first node PU in the output module 1 can at least partially offset its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node PU in the output module 1. Similarly, the drift in the negative direction of the threshold voltage of the transistor controlled by the first node PU in the first pull-down module 21 can at least partially offset its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node PU in the first pull-down module 21.

[0042] If the second pull-down module 22 (i.e., the third transistor T3) is also connected to the first voltage signal terminal VGL1, then in the second time period B, the Vgs of the first transistor T1 and the third transistor T3 are equal to 0, and the threshold voltages of the first transistor T1 and the third transistor T3 cannot drift negatively, resulting in that the positive drift of the threshold voltages of the first transistor T1 and the third transistor T3 in the first time period cannot be offset, and further, the characteristics of the first transistor T1 and the third transistor T3 cannot be restored.

[0043] In summary, according to the shift register provided by the embodiment of the present application, the second pull-down module is connected to the second voltage signal terminal with a smaller voltage, so that when the second pull-down module is turned on, the signal of the second voltage terminal with a smaller voltage is transmitted to the first node, so that the drift in the negative direction of the threshold voltage of the transistor controlled by the first node in the output module at least partially offsets its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node in the output module; similarly, the drift in the negative direction of the threshold voltage of the transistor controlled by the first node in the first pull-down module at least partially offsets its drift in the positive direction, thereby restoring the characteristics of the transistor controlled by the first node in the first pull-down module; thereby reducing the characteristic changes of the transistors in the shift register and improving the reliability of the shift register.

[0044] In some embodiments, Figure 4 As shown, the shift register VSR also includes a pull-down control module 3, which is connected to the third voltage signal terminal VGH, the fourth voltage signal terminal VR and the second node PD. The pull-down control module 3 controls the voltage of the second node PD based on the signals of the third voltage signal terminal VGH and the fourth voltage signal terminal VR. The voltage of the fourth voltage signal terminal VR is less than the voltage of the third voltage signal terminal VGH.

[0045] Exemplarily, the voltage of the fourth voltage signal terminal VR and the voltage of the third voltage signal terminal VGH are both positive voltages. The third voltage signal terminal VGH is connected to the control terminal of the pull-down control module 3 .

[0046] The second pull-down module 22 and the pull-down control module 3 both include transistors. For example, the transistors in the second pull-down module 22 and the pull-down control module 3 are both N-type transistors.

[0047] To better understand the beneficial effects of the embodiments of the present application, please refer to Figures 5 to 7 , taking the transistor of the second pull-down module 22 as the fourth transistor T4, the transistor in the pull-down control module 3 as the fifth transistor T5, and taking the voltage of the first voltage signal terminal VGL1 as -10V, the voltage of the second voltage signal terminal VGL2 as -13V, the voltage of the third voltage signal terminal VGH as 15V, and the voltage of the fourth voltage signal terminal VR as 9.9V as an example. Vgs is the voltage difference between the gate of the fourth transistor T4 and its source, and Vgs can be used to represent the voltage stress applied to the fourth transistor T4.

[0048] Figure 5 In the embodiment, the second pull-down module 22 is connected to the first voltage signal terminal VGL1, and the pull-down control module 3 is connected to the third voltage signal terminal VGH. Figure 5In the embodiment, Vgs=(VGH-Vth)-VGL1, where Vth represents the threshold voltage of the fifth transistor T5, for example, Vth=2.1, then Vgs=(15-2.1)-(-10)=22.9V.

[0049] Figure 6 In order to solve the drift problem of the threshold voltage of the transistors in the input module and the first pull-down module, the second voltage signal terminal VGL2 with a voltage smaller than the first voltage signal terminal VGL1 is introduced in this embodiment, the second pull-down module 22 is connected to the second voltage signal terminal VGL2, and the pull-down control module 3 is connected to the third voltage signal terminal VGH. Figure 6 In the embodiment, Vgs=(VGH-Vth)-VGL2, where Vth represents the threshold voltage of the fifth transistor T5, for example, Vth=2.1, then Vgs=(15-2.1)-(-13)=25.9V.

[0050] contrast Figure 5 and Figure 6 It can be seen that the voltage pressure on the fourth transistor T4 of the second pull-down module 22 is greater. In other words, the second pull-down module 22 is connected to the second voltage signal terminal VGL2 with a smaller voltage. Although it can solve the drift problem of the threshold voltage of the transistors in the input module and the first pull-down module, it will also cause the threshold voltage drift problem of the fourth transistor T4 in the second pull-down module 22 due to the large voltage pressure.

[0051] For example, to alleviate the voltage pressure on the fourth transistor T4 of the second pull-down module 22, refer to Figure 7 In this embodiment, a fourth voltage signal terminal VR having a voltage lower than that of the third voltage signal terminal VGH is introduced, the second pull-down module 22 is connected to the second voltage signal terminal VGL2, and the pull-down control module 3 is connected to the third voltage signal terminal VGH and the fourth voltage signal terminal VR. Figure 7 In, Vgs=VR-VGL2, Vgs=9.9-(-13)=22.9V.

[0052] In this embodiment, the pull-down control module is connected to the fourth voltage signal terminal, and the voltage of the fourth voltage signal terminal is smaller than the voltage of the third voltage signal terminal. This can alleviate the voltage pressure on the transistor in the second pull-down module, thereby avoiding large characteristic changes in the transistor in the second pull-down module, thereby improving the reliability of the shift register.

[0053] In some embodiments, please refer to Figure 4The shift register VSR also includes an input module 4, which is connected to the first trigger signal terminal IN1, the second trigger signal terminal IN2, the first voltage signal terminal VGL1, the third voltage signal terminal VGH, and the first node PU. The input module 4 controls the voltage of the first node PU based on the signals of the first trigger signal terminal IN1, the second trigger signal terminal IN2, the first voltage signal terminal VGL1, and the third voltage signal terminal VGH.

[0054] For example, when the signal of the first trigger signal terminal IN1 is at the on level, the input module 4 transmits the voltage of the third voltage signal terminal VGH to the first node PU. When the signal of the second trigger signal terminal IN2 is at the on level, the input module 4 transmits the signal of the first voltage signal terminal VGL1 to the first node PU.

[0055] For example, the first voltage signal terminal VGL1 is a negative voltage, and the third voltage signal terminal VGH is a positive voltage. It is understandable that the conduction level of the first trigger signal terminal IN1 and the conduction level of the second trigger signal terminal IN2 do not overlap in time.

[0056] In some embodiments, please refer to Figure 4 The shift register VSR further includes a reset module 5, which is connected to the reset signal terminal RESET, the first voltage signal terminal VGL1, the first node PU and the second node PD. The reset module 5 controls the voltages of the first node PU and the second node PD based on the signals of the reset signal terminal RESET and the first voltage signal terminal VGL1.

[0057] For example, when the reset signal terminal RESET is at the on level, the reset module 5 transmits the voltage of the first voltage signal terminal VGL1 to the first node PU and the second node PD, thereby resetting the first node PU and the second node PD.

[0058] In some embodiments, please refer to Figure 4 The shift register VSR further includes a closing module 6, which is connected to the closing signal terminal Goff, the first voltage signal terminal VGL1 and the output terminal GOUT. The closing module 6 controls the voltage of the output terminal GOUT based on the signals of the closing signal terminal Goff and the first voltage signal terminal VGL1.

[0059] For example, when the off signal terminal Goff is at the on level, the off module 6 transmits the voltage of the first voltage signal terminal VGL1 to the output terminal GOUT, so that the output terminal of the shift register cannot output the enable signal, that is, the shift register is turned off.

[0060] In some embodiments, Figure 8As shown, the shift register VSR further includes a capacitor C, which is connected between the first node PU and the output terminal GOUT. The capacitor C has a coupling effect, which can make the transistor controlled by the first node PU more fully conductive.

[0061] In some embodiments, Figure 8 As shown, the output module includes a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is connected to the clock signal terminal CK, the second electrode of the first transistor T1 is connected to the output terminal GOUT, and the gate of the first transistor T1 is connected to the first node PU. The first electrode of the second transistor T2 is connected to the first voltage signal terminal VGL1, the second electrode of the second transistor T2 is connected to the output terminal GOUT, and the gate of the second transistor T2 is connected to the second node PD.

[0062] It is understandable that the transistor controlled by the first node PU in the output module is the first transistor T1.

[0063] When the first node PU is at an on level, the first transistor T1 is turned on, and the signal of the clock signal terminal CK is transmitted to the output terminal GOUT. When the second node PD is at an on level, the second transistor T2 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the output terminal GOUT.

[0064] In some embodiments, Figure 8 As shown, the first pull-down module includes a third transistor T3, and the second pull-down module includes a fourth transistor T4. The first electrode of the third transistor T3 is connected to the first voltage signal terminal VGL1, the second electrode of the third transistor T3 is connected to the second node PD, and the gate of the third transistor T3 is connected to the first node PU. The first electrode of the fourth transistor T4 is connected to the second voltage signal terminal VGL2, the second electrode of the fourth transistor T4 is connected to the first node PU, and the gate of the fourth transistor T4 is connected to the second node PD.

[0065] When the first node PU is at the on level, the third transistor T3 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the second node PD. When the second node PD is at the on level, the fourth transistor T4 is turned on, and the signal of the second voltage signal terminal VGL2 is transmitted to the first node PU.

[0066] In some embodiments, Figure 8 As shown, the pull-down control module includes a fifth transistor T5; a first electrode of the fifth transistor T5 is connected to the fourth voltage signal terminal VR, a second electrode of the fifth transistor T5 is connected to the second node PD, and a gate of the fifth transistor T5 is connected to the third voltage signal terminal VGH.

[0067] The voltage of the third voltage signal terminal VGH is a fixed positive voltage, so that the fifth transistor T5 remains turned on, and the signal of the fourth voltage signal terminal VR is transmitted to the second node PD.

[0068] In some embodiments, Figure 8 As shown, the input module includes a sixth transistor T6 and a seventh transistor T7. A first electrode of the sixth transistor T6 is connected to the third voltage signal terminal VGH, a second electrode of the sixth transistor T6 is connected to the first node PU, and a gate of the sixth transistor T6 is connected to the first trigger signal terminal IN1. A first electrode of the seventh transistor T7 is connected to the first voltage signal terminal VGL1, a second electrode of the seventh transistor T7 is connected to the first node PU, and a gate of the seventh transistor T7 is connected to the second trigger signal terminal IN2.

[0069] When the first trigger signal terminal IN1 is at the on level, the sixth transistor T6 is turned on, and the signal of the third voltage signal terminal VGH is transmitted to the first node PU. When the second trigger signal terminal IN2 is at the on level, the seventh transistor T7 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the first node PU.

[0070] In some embodiments, Figure 8 As shown, the reset module includes an eighth transistor T8 and a ninth transistor T9. A first electrode of the eighth transistor T8 is connected to the first voltage signal terminal VGL1, a second electrode of the eighth transistor T8 is connected to the first node PU, and a gate of the eighth transistor T8 is connected to the reset signal terminal RESET. A first electrode of the ninth transistor T9 is connected to the first voltage signal terminal VGL1, a second electrode of the ninth transistor T9 is connected to the second node PD, and a gate of the ninth transistor T9 is connected to the reset signal terminal RESET.

[0071] When the reset signal terminal RESET is at the on level, the eighth transistor T8 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the first node PU. When the reset signal terminal RESET is at the on level, the ninth transistor T9 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the second node PD.

[0072] In some embodiments, Figure 8 As shown, the shutdown module includes a tenth transistor T10; a first electrode of the tenth transistor T10 is connected to the first voltage signal terminal VGL1, a second electrode of the tenth transistor T10 is connected to the output terminal GOUT, and a gate of the tenth transistor T10 is connected to the shutdown signal terminal Goff.

[0073] When the off signal terminal Goff is at the on level, the tenth transistor T10 is turned on, and the signal of the first voltage signal terminal VGL1 is transmitted to the output terminal GOUT.

[0074] The present application embodiment provides a shift register, such as Figure 8 As shown, the shift register includes a first transistor T1, a third transistor T3 and a fourth transistor T4; the first electrode of the first transistor T1 is connected to the clock signal terminal CK, the second electrode of the first transistor T1 is connected to the output terminal GOUT, and the gate of the first transistor T1 is connected to the first node PU. The first electrode of the third transistor T3 is connected to the first voltage signal terminal VGL1, the second electrode of the third transistor T3 is connected to the second node PD, and the gate of the third transistor T3 is connected to the first node PU. The first electrode of the fourth transistor T4 is connected to the second voltage signal terminal VGL2, the second electrode of the fourth transistor T4 is connected to the first node PU, and the gate of the fourth transistor T4 is connected to the second node PD. The voltage of the second voltage signal terminal VGL2 is less than the voltage of the first voltage signal terminal VGL1.

[0075] In some embodiments, Figure 8 As shown, the shift register further includes a second transistor T2, a first electrode of the second transistor T2 is connected to the first voltage signal terminal VGL1, a second electrode of the second transistor T2 is connected to the output terminal GOUT, and a gate of the second transistor T2 is connected to the second node PD.

[0076] In some embodiments, Figure 7 As shown, the shift register further includes a fifth transistor T5; a first electrode of the fifth transistor T5 is connected to the fourth voltage signal terminal VR, a second electrode of the fifth transistor T5 is connected to the second node PD, and a gate of the fifth transistor T5 is connected to the third voltage signal terminal VGH. The voltage of the fourth voltage signal terminal VR is less than the voltage of the third voltage signal terminal VGH.

[0077] In some embodiments, Figure 8 As shown, the shift register further includes a sixth transistor T6 and a seventh transistor T7. A first electrode of the sixth transistor T6 is connected to the third voltage signal terminal VGH, a second electrode of the sixth transistor T6 is connected to the first node PU, and a gate of the sixth transistor T6 is connected to the first trigger signal terminal IN1. A first electrode of the seventh transistor T7 is connected to the first voltage signal terminal VGL1, a second electrode of the seventh transistor T7 is connected to the first node PU, and a gate of the seventh transistor T7 is connected to the second trigger signal terminal IN2.

[0078] In some embodiments, Figure 8As shown, the shift register further includes an eighth transistor T8 and a ninth transistor T9. A first electrode of the eighth transistor T8 is connected to the first voltage signal terminal VGL1, a second electrode of the eighth transistor T8 is connected to the first node PU, and a gate of the eighth transistor T8 is connected to the reset signal terminal RESET. A first electrode of the ninth transistor T9 is connected to the first voltage signal terminal VGL1, a second electrode of the ninth transistor T9 is connected to the second node PD, and a gate of the ninth transistor T9 is connected to the reset signal terminal RESET.

[0079] In some embodiments, Figure 8 As shown, the shift register further includes a tenth transistor T10; a first electrode of the tenth transistor T10 is connected to the first voltage signal terminal VGL1, a second electrode of the tenth transistor T10 is connected to the output terminal GOUT, and a gate of the tenth transistor T10 is connected to the off signal terminal Goff.

[0080] Exemplarily, the gate drive circuit includes a plurality of cascaded shift registers, the clock signal terminal includes a first clock signal terminal CK1 and a second clock signal terminal CK2, and the timing of the first clock signal terminal CK1 and the second clock signal terminal CK2 are opposite. Among them, the shift registers of odd stages are connected to the first clock signal terminal CK1, and the shift registers of even stages are connected to the second clock signal terminal CK2.

[0081] Combine the following Figure 8 and Fig. 9 , taking the case where the shift register is connected to the first clock signal terminal CK1 and each transistor of the shift register is an N-type transistor as an example, the working process of the shift register is introduced:

[0082] In the initial stage d0, the reset signal terminal RESET and / or the shutdown signal terminal Goff are at a high level, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned on, and the low level of the first voltage signal terminal VGL1 is transmitted to the first node PU, the second node PD and the output terminal OUT.

[0083] In the first stage d1, the first trigger signal terminal IN1 is at a high level, the second trigger signal terminal IN2 is at a low level, the sixth transistor T6 is turned on, the high voltage of the third voltage signal terminal VGH is transmitted to the first node PU, the first transistor T1 is turned on, and the low level of the first clock signal terminal CK1 is transmitted to the output terminal OUT; in addition, the third transistor T3 is turned on, and the low level of the first voltage signal terminal VGL1 is transmitted to the second node PD.

[0084] In the second stage d2, the first clock signal terminal CK1 is at a high level, the first trigger signal terminal IN1, the second trigger signal terminal IN2, the reset signal terminal RESET and the shutdown signal terminal Goff are all at low levels, the first transistor T1 remains turned on, and the signal output by the output terminal OUT changes from a low level to a high level; in addition, due to the coupling effect of the capacitor C, the voltage of the first node PU jumps to a higher voltage, so that the first transistor T1 is turned on more fully.

[0085] In the third stage d3, the second trigger signal terminal IN2 is at a high level, the seventh transistor T7 is turned on, the low voltage of the first voltage signal terminal VGL1 is transmitted to the first node PU, and the first transistor T1 and the third transistor T3 are turned off. The fifth transistor T5 transmits the voltage of the fourth voltage signal terminal VR to the second node PD, the fourth transistor T4 and the second transistor T2 are turned on, and the low voltage of the first voltage signal terminal VGL1 is transmitted to the output terminal GOUT.

[0086] In the fourth stage d4 and the fifth stage d5, the first trigger signal terminal IN1, the second trigger signal terminal IN2, the reset signal terminal RESET and the shutdown signal terminal Goff are all low level, the second transistor T2 remains turned on, and the output terminal GOUT keeps outputting a low level.

[0087] Thereafter, the fourth stage d4 and the fifth stage d5 are repeatedly executed.

[0088] For example, please refer to Figure 2 and Fig. 9 The first period A includes the first stage d1 and the second stage d2, and the second period B includes the third stage d3 and the stages thereafter.

[0089] In the first stage d1 and the second stage d2, the first transistor T1 and the third transistor T3 are turned on. At this time, the Vgs of the first transistor T1 is greater than 0, and the Vgs of the third transistor T3 is also greater than 0, and the threshold voltages of the first transistor T1 and the third transistor T3 drift positively.

[0090] In the third stage d3 and the subsequent stages, since the voltage of the second voltage signal terminal VGL2 is smaller than the voltage of the first voltage signal terminal VGL1, the gate voltage of the first transistor T1 is smaller than the source voltage of the first transistor T1, the gate voltage of the third transistor T3 is smaller than the source voltage of the first transistor T1, the Vgs of the first transistor T1 is smaller than 0, and the Vgs of the third transistor T3 is also smaller than 0. For IGZO or A-Si type transistors, their Vgs is smaller than 0 for a long time, and their threshold voltages drift negatively. The drift in the negative direction of the threshold voltages of the first transistor T1 and the third transistor T3 at least partially offsets the drift in the positive direction, thereby restoring the characteristics of the first transistor T1 and the third transistor T3, and providing the reliability of the shift register.

[0091] In addition, the fourth voltage signal terminal VR with a voltage lower than the third voltage signal terminal VGH is introduced in the embodiment of the present application, the second pull-down module 22 is connected to the second voltage signal terminal VGL2, and the pull-down control module 3 is connected to the third voltage signal terminal VGH and the fourth voltage signal terminal VR. Figure 7 For example, Vgs=VR-VGL2, Vgs=9.9-(-13)=22.9V. In this way, the threshold voltage drift problem of the fourth transistor T4 caused by the high voltage pressure can be solved.

[0092] It should be noted that the transistors in the embodiments of the present application are described by taking N-type transistors as an example. Those skilled in the art can appropriately deform the shift register provided in the embodiments of the present application and replace the N-type transistors with P-type transistors. For N-type transistors, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are turned off / disconnected. For P-type transistors, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are turned off / disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off / disconnect the transistor.

[0093] The present application also provides a gate drive circuit. Fig.10As shown, the gate drive circuit 100 includes the shift register VSR described in any of the above embodiments. The gate drive circuit provided in the embodiment of the present application has the beneficial effects of the shift register provided in the embodiment of the present application. For details, please refer to the specific description of the shift register in the above embodiments, which will not be repeated in this embodiment.

[0094] Exemplarily, the gate drive circuit 100 includes a plurality of cascaded shift registers VSR. The first trigger signal terminal IN1 of the first-stage shift register VSR is connected to the driver chip through the trigger signal line STV, and the first trigger signal terminal IN1 of the i+1-stage shift register VSR is connected to the output terminal GOUT of the i-stage shift register VSR. In other words, the trigger signal output by the driver chip serves as the first trigger signal of the first-stage shift register VSR, and the signal at the output terminal GOUT of the i-stage shift register VSR serves as the first trigger signal of the i+1-stage shift register VSR.

[0095] The output terminal GOUT of the i+1th shift register VSR is connected to the second trigger signal terminal IN2 of the i-th shift register VSR, that is, the signal of the output terminal GOUT of the i+1th shift register VSR serves as the second trigger signal of the i-th shift register VSR.

[0096] The odd-numbered shift register VSR is connected to the first clock signal terminal CK1 through a first wiring, and the even-numbered shift register VSR is connected to the second clock signal terminal CK2 through a second wiring.

[0097] The present application also provides a display panel, including the gate driving circuit described in the above embodiment. Fig.11 As shown, the display panel 200 includes a gate driving circuit 100, and the gate driving circuit 100 includes the shift register VSR described in any of the above embodiments. The display panel provided in the embodiment of the present application has the beneficial effects of the shift register provided in the embodiment of the present application. For details, please refer to the specific description of the shift register in the above embodiments, which will not be repeated in this embodiment.

[0098] The display panel 200 includes sub-pixels, and the output end of the shift register VSR is connected to the sub-pixels. The multiple shift registers of the gate driving circuit 100 can scan multiple rows of sub-pixels row by row.

[0099] Exemplarily, the display panel includes a liquid crystal display panel. Of course, the display panel may also include other types of display panels.

[0100] The present application also provides a display device, including the display panel provided by the present application. Fig.12 , Fig.12It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.11 The provided display device 1000 includes the display panel 200 provided by any of the above embodiments of the present application. Fig.12 The embodiment only takes the vehicle-mounted display device as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a mobile phone or other display device with a display function, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0101] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A shift register, characterized in that: It includes an output module, a first pull-down module, and a second pull-down module; The output module controls the voltage outputted by the output terminal based on the signal of the first node and the clock signal terminal; The first pull-down module controls the voltage of the second node based on the first voltage signal terminal and the signal of the first node; The second pull-down module controls the voltage of the first node based on the second voltage signal terminal and the signal of the second node; The voltage of the second voltage signal terminal is lower than the voltage of the first voltage signal terminal.

2. The shift register according to claim 1, characterized in that: The shift register further includes a pull-down control module, which controls the voltage of the second node based on the signals of the third voltage signal terminal and the fourth voltage signal terminal; The voltage of the fourth voltage signal terminal is lower than the voltage of the third voltage signal terminal.

3. The shift register according to claim 1 or 2, characterized in that: The shift register further includes: The input module controls the voltage of the first node based on signals at the first trigger signal terminal, the second trigger signal terminal, the first voltage signal terminal and the third voltage signal terminal.

4. The shift register according to claim 1 or 2, characterized in that: The shift register further includes: A reset module controls the voltages of the first node and the second node based on signals at a reset signal terminal and the first voltage signal terminal.

5. The shift register according to claim 1 or 2, characterized in that: The shift register further includes: The closing module controls the voltage of the output terminal based on the signal of the closing signal terminal and the signal of the first voltage signal terminal.

6. The shift register according to claim 1 or 2, characterized in that: The shift register further includes: A capacitor is connected between the first node and the output terminal.

7. The shift register according to claim 1 or 2, characterized in that: The output module includes a first transistor and a second transistor; A first electrode of the first transistor is connected to the clock signal terminal, a second electrode of the first transistor is connected to the output terminal, and a gate of the first transistor is connected to the first node; A first electrode of the second transistor is connected to the first voltage signal terminal, a second electrode of the second transistor is connected to the output terminal, and a gate of the second transistor is connected to the second node.

8. The shift register according to claim 1 or 2, characterized in that: The first pull-down module includes a third transistor, and the second pull-down module includes a fourth transistor; A first electrode of the third transistor is connected to the first voltage signal terminal, a second electrode of the third transistor is connected to the second node, and a gate of the third transistor is connected to the first node; A first electrode of the fourth transistor is connected to the second voltage signal terminal, a second electrode of the fourth transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node.

9. The shift register according to claim 2, characterized in that: The pull-down control module includes a fifth transistor; A first electrode of the fifth transistor is connected to the fourth voltage signal terminal, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the third voltage signal terminal.

10. The shift register according to claim 3, characterized in that: The input module includes a sixth transistor and a seventh transistor; A first electrode of the sixth transistor is connected to the third voltage signal terminal, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the first trigger signal terminal; A first electrode of the seventh transistor is connected to the first voltage signal terminal, a second electrode of the seventh transistor is connected to the first node, and a gate of the seventh transistor is connected to the second trigger signal terminal.

11. The shift register according to claim 4, characterized in that: The reset module includes an eighth transistor and a ninth transistor; A first electrode of the eighth transistor is connected to the first voltage signal terminal, a second electrode of the eighth transistor is connected to the first node, and a gate of the eighth transistor is connected to the reset signal terminal; A first electrode of the ninth transistor is connected to the first voltage signal terminal, a second electrode of the ninth transistor is connected to the second node, and a gate of the ninth transistor is connected to the reset signal terminal.

12. The shift register according to claim 5, characterized in that: The shutdown module includes a tenth transistor; A first electrode of the tenth transistor is connected to the first voltage signal terminal, a second electrode of the tenth transistor is connected to the output terminal, and a gate of the tenth transistor is connected to the shutdown signal terminal.

13. A gate drive circuit, characterized in that: Comprising the shift register as claimed in any one of claims 1 to 12.

14. A display panel, characterized in that: Comprising the gate driving circuit as claimed in claim 13.

15. A display device, characterized in that: Comprising the display panel as claimed in claim 14.

Images