Display device

Abstract

An embodiment relates to a display device including: a display panel including a display area provided with pixels and a non-display area surrounding the display area; a level shifter disposed at at least one side of the non-display area and configured to generate a gate clock signal and an inversion signal having a phase opposite to a phase of the gate clock signal; a control signal line configured to transmit the gate clock signal output from the level shifter to the pixel; and an inversion signal line configured to receive an inversion signal from the level shifter, where the inversion signal line is disposed in a closed loop shape surrounding the display area in the non-display area.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0167063, filed on November 27, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that prevents electromagnetic interference (EMI) by increasing the cancellation efficiency between a gate signal and an inverted signal applied to a display panel. Background art

[0004] Generally, a display device includes: a display panel provided with pixels; a gate driver for providing a gate signal to the pixels through gate lines; a data driver for applying a data signal to the pixels through data lines; and a timing controller for controlling the operations of the gate driver and the data driver.

[0005] In the case where the display device has a large area / high resolution, the number of control signals applied from the timing controller to the gate driver and / or the data driver increases. In particular, when signals are transmitted through a large number of control signal lines in a small area to achieve a narrow bezel, the noise caused by electromagnetic interference (EMI) between the signals increases. The gate clock signal applied in the form of a square wave may greatly generate noise. Summary of the invention

[0006] Embodiments are directed to providing a display device that reduces noise on a display panel by using a field cancellation technique with an inverted signal.

[0007] Embodiments are also directed to providing a display device that forms an inverted signal line in the same closed - loop shape as the signal line to which the original signal is applied, and the inverted signal is applied to the inverted signal line.

[0008] Embodiments are also directed to providing a display device that reduces the load difference between the signal line to which the original signal is applied and the inverted signal line by connecting the inverted signal line to which the inverted signal is applied to a dummy pixel.

[0009] A display device according to one embodiment may include: a display panel including a display area provided with pixels and a non-display area surrounding the display area; a level shifter provided at at least one side of the non-display area and configured to generate a gate clock signal and an inverted signal having a phase opposite to that of the gate clock signal; a control signal line configured to send the gate clock signal output from the level shifter to the pixels; and an inverted signal line configured to receive the inverted signal from the level shifter, wherein the inverted signal line may be provided in a closed-loop shape surrounding the display area in the non-display area.

[0010] The display device may further include a gate driver configured to output a gate signal to the pixels in response to the gate clock signal.

[0011] The gate driver may receive the gate clock signal through a gate control line and output the gate signal through a gate line, and the control signal line may include the gate control line and the gate line.

[0012] The display device may further include dummy pixels provided in the non-display area and connected to the inverted signal line.

[0013] The dummy pixels may be provided on the other side of the display panel opposite to the level shifter.

[0014] The dummy pixels may be provided on the side of the display panel facing the level shifter.

[0015] The dummy pixels may be configured with the same number and the same type of circuit elements as the pixels.

[0016] Each of the dummy pixels may include: a dummy light emission control circuit including a dummy light emission element and at least one circuit element configured to control the light emission of the dummy light emission element; and a dummy switching transistor having a gate electrode connected to the inverted signal line and a source electrode and a drain electrode that are electrically short-circuited.

[0017] The dummy light emission control circuit may include: a dummy light emission element formed of a dummy liquid crystal cell connected between the dummy switching transistor and a common electrode; and a dummy storage capacitor connected between the dummy liquid crystal cell and the common electrode. The dummy switching transistor may be connected between the dummy liquid crystal cell and the common electrode.

[0018] The display device may further include one or more switching elements connected to the inverted signal line and configured to disconnect and connect the inverted signal line.

[0019] One or more switching elements may be disposed between the pseudo pixels at a predetermined interval.

[0020] The pseudo pixels may be grouped into a plurality of pseudo pixel groups, each pseudo pixel group including the same or different numbers of pseudo pixels, and one or more switching elements may be disposed between the pseudo pixel groups.

[0021] The gate driver may be composed of stage circuits configured to receive a gate start signal or a carry signal output from a previous stage and receive a gate clock signal, and output a gate signal to one or more corresponding pixel rows.

[0022] One or more switching elements may be configured to turn off according to a carry signal output from the corresponding stage circuit to disconnect the inverted signal line.

[0023] The display panel may be divided into a plurality of display blocks, each display block including one or more pixel rows, and one or more switching elements may be configured to receive a carry signal from a stage circuit connected to the last pixel row of the corresponding display block.

[0024] The display device may further include: a reset transistor having one electrode connected to a gate conduction voltage and a gate electrode configured to receive a gate start signal; a first node receiving a carry signal from a stage circuit connected to the last pixel row of the first display block; a control transistor connected between the other electrode of the reset transistor and the first node in a diode connection; and a capacitor connected between the first node and a ground voltage.

[0025] One or more switching elements may be configured as a first switching element having a source electrode and a drain electrode connected to an inverted signal line between a first pseudo pixel group and a second pseudo pixel group, and a gate electrode connected to the first node.

[0026] The first switching element may be turned on in response to a gate conduction voltage applied to the first node through the reset transistor and the control transistor, and turned off in response to a carry signal applied to the first node at a gate off level to electrically isolate the second pseudo pixel group from the inverted signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram schematically showing the structure of a display device according to an embodiment.

[0028] Figure 2 is a plan view of a display device according to a first embodiment.

[0029] Figure 3 is applied to Figure 2Waveform diagrams of signals of signal lines and inverted signal lines.

[0030] Figure 4 is a schematic plan view of a display device according to a second embodiment.

[0031] Figure 5 is Figure 4 an enlarged view of a part of the display device shown.

[0032] Figure 6 is Figure 5 a circuit diagram of the pixel shown.

[0033] Figure 7 is Figure 5 a circuit diagram of the dummy pixel shown.

[0034] Figure 8A and Figure 8B is a diagram showing the field cancellation improvement effect of the display device according to the second embodiment.

[0035] Figure 9 is a schematic plan view of a display device according to a third embodiment.

[0036] Figure 10 is a schematic plan view of a display device according to a fourth embodiment.

[0037] Figure 11 schematically shows Figure 10 the structure of the gate driver.

[0038] Figure 12 is Figure 10 an enlarged view of a part of the display device shown.

[0039] Figure 13 is applied to Figure 12 the waveform diagram of the signal of the control circuit shown.

[0040] Figures 14A to 14D is a diagram for describing the field cancellation improvement effect of the display device according to the fourth embodiment. Detailed Embodiments

[0041] Hereinafter, embodiments will be described with reference to the drawings. In the specification, when a first component (or region, layer, part, etc.) is described as being "on", "connected" or "coupled to" a second component, this means that the first component can be directly connected / coupled to the second component, or a third component can be disposed between the first component and the second component.

[0042] Like reference numerals indicate like components. Additionally, in the drawings, for the purpose of effectively describing the technical content, the thickness, ratio, and dimensions of components are exaggerated. The term "and / or" includes all one or more combinations that can be defined by the associated configuration.

[0043] Terms such as first and second can be used to describe various components, but these components are not limited by these terms. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0044] Terms such as "below", "beneath", "above", and "on top of" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described with respect to the direction marked in the drawings.

[0045] It should be understood that terms such as "including" or "having" are intended to specify the existence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and do not preclude the possibility of the existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0046] Figure 1 is a block diagram schematically showing the structure of a display device according to an embodiment.

[0047] Referring to Figure 1 , the display device 100 according to an embodiment may include a display panel 110 and a driving unit for driving the display panel 110. The driving unit may include a data driver 120, a gate driver 130, a level shifter 140, etc., and also includes a timing controller 150 for controlling the data driver 120 and the gate driver 130.

[0048] The display panel 110 includes data lines DL, gate lines GL intersecting the data lines DL, and an array of pixels defined in the intersecting regions of the data lines DL and the gate lines GL.

[0049] Each pixel P may include a transistor connected to the corresponding data line DL and gate line GL, a storage capacitor, and a light-emitting element connected to the data line DL, the gate line GL, and the storage capacitor. Each pixel P may emit light under the control of the transistor in response to the amount of current flowing through the light-emitting element.

[0050] The timing controller 150 may perform an overall control function related to driving the display panel 110, and control the operations of the data driver 120 and the gate driver 130. The timing controller 150 receives an image signal RGB and a timing signal CS sent from an external system (not shown), and generates a data control signal DCS and a gate control signal GCS. The timing signal CS may include a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, a clock signal, etc. The data control signal DCS is output to the data driver 120, and the gate control signal GCS is output to the level shifter 140. The timing controller 150 generates digital image data DATA based on the image signal sent from the external system, and outputs the digital image data DATA to the data driver 120.

[0051] The level shifter 140 may convert the gate control signal GCS having a digital signal voltage level input from the timing controller 150 into a signal having an analog voltage level. For example, the level shifter 140 converts a high logic voltage into a gate high voltage, and converts a low logic voltage (or a low potential input voltage) into a gate low voltage. Accordingly, the level shifter 140 may generate a gate clock signal GCLK and a gate start signal GST based on the gate control signal GCS received from the timing controller 150, and output the gate clock signal GCLK and the gate start signal GST to the gate control line GCL.

[0052] The data driver 120 converts the digital image data DATA into an analog data voltage according to the data control signal DCS. The data driver 120 may apply the analog data voltage to the corresponding pixel P through the data line DL. In one embodiment, a multiplexer (not shown) may be provided between the data driver 120 and the data line DL. The multiplexer may distribute the data voltage input from the data driver 120 to the data line DL under the control of the timing controller 150.

[0053] The gate driver 130 may output gate signals in sequence for one horizontal period through the gate line GL in response to the gate clock signal GCLK and the gate start signal GST input from the level shifter 140. For example, the gate driver 130 may provide a gate signal to the gate line GL by sequentially outputting one or more gate clock signals GCLK to the gate line GL at a predetermined controlled timing. In response to the gate signal, the pixel rows connected to each gate line GL may be turned on for one horizontal period.

[0054] The display device 100 according to one embodiment may be a display device including a backlight unit such as a liquid crystal display (LCD) device, and may be a self-emitting display device such as an organic light emitting diode (OLED) display device, a quantum dot display device, and a micro light emitting diode (LED) display device.

[0055] When the display device 100 is an OLED display device, each pixel P may include an OLED that emits light by itself as a light-emitting element. When the display device 100 is a quantum dot display device, each pixel P may include a light-emitting element formed of quantum dots, which are semiconductor crystals that emit light by themselves. When the display device 100 is a micro-LED display device, each pixel P may include a micro-LED as a light-emitting element, and the micro-LED emits light by itself and is made of an inorganic material. When the display device 100 is a nano-LED display device, each pixel P may include a nano-LED as a light-emitting element, and the nano-LED emits light by itself and is made of an inorganic material.

[0056] Figure 2 is a plan view of the display device according to the first embodiment.

[0057] Referring to Figure 2 , the display panel 110 may include a display area DA for displaying an image, and a non-display area NDA near the display area DA that does not display an image.

[0058] The display area DA includes data lines DL (see Figure 1 ), gate lines GL intersecting the data lines DL, and an array of pixels P defined in the intersection regions of the data lines DL and the gate lines GL (see Figure 1 ).

[0059] The pixels P disposed in the display area DA may include red (R), green (G), and blue (B) pixels for color implementation. In addition to RGB pixels, the pixel P may further include white pixels. However, this embodiment is not limited thereto, and the pixel P may include cyan, magenta, and yellow pixels.

[0060] At least some of the drivers may be mounted on or connected to the non-display area NDA. For example, the data driver 120 may be connected to one side of the non-display area NDA, and the gate driver 130 may be mounted on one side of the non-display area NDA.

[0061] The data driver 120 may be composed of one or more driver integrated circuits DIC. The driver integrated circuit may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, etc. The driver integrated circuit may further include an analog-to-digital converter.

[0062] The driver integrated circuit can be connected to the display panel 110 in a tape automated bonding (TAB) type, connected to the bonding pads of the display panel 110 in a chip on glass (COG) type or a chip on panel (GOP) type, or connected to the display panel 110 in a chip on film (COF) type. In this case, the driver integrated circuit can be mounted on a circuit film connected to the non-display area NDA of the display panel 110.

[0063] The data driver 120 can be connected to one side (e.g., the upper side or the lower side) of the display panel 110, as shown. Depending on the driving method, panel design method, etc., the data driver 120 can be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or connected to two or more of the four side surfaces of the display panel 110.

[0064] The gate driver 130 can be composed of stage circuits, and the stage circuits are connected to a plurality of gate lines GL one by one. The gate driver 130 can be configured to be mounted on the non-display area NDA of the display panel 110 in an in-panel gate type.

[0065] The gate driver 130 can be disposed on one side of the display panel 110 or on both sides (e.g., the left side and the right side) of the display panel 110, as shown. Depending on the driving method, panel design method, etc., the gate driver 130 can be disposed on both sides (e.g., the left side and the right side) of the display panel 110 as shown, or connected to two or more of the four side surfaces of the display panel 110.

[0066] In one embodiment, one or more inverted signal lines RL can be provided in the non-display area NDA. The inverted signal line RL is configured to receive an inverted signal of a predetermined original signal. For example, the inverted signal line RL can receive an inverted signal having an inverted phase of the gate clock signal GCLK (see Figure 1 ).

[0067] The inverted signal line RL can be provided adjacent to the control signal line to which the original signal is applied, and can have substantially the same shape as the control signal line. For example, the control signal line can include a gate control line GCL to which the gate clock signal GCLK is applied and a gate line GL to which the gate clock signal GCLK is provided as a gate signal. In this embodiment, the inverted signal line RL can be provided adjacent to the gate control line GCL and the gate line GL.

[0068] As shown, in an embodiment where the gate driver 130 is disposed on both sides of the display panel 110, the gate control lines GCL and the gate lines GL may form a closed loop. In this embodiment, the reverse signal line RL may be disposed in the non-display area NDA along the edge of the display panel 110 and arranged in a closed-loop shape surrounding the display area DA.

[0069] The reverse signal line RL may be formed of the same material and / or have the same electrical characteristics as the control signal line to which the original signal is applied. In Figure 2 , an example is shown in which two reverse signal lines RL are disposed in the non-display area NDA, but this embodiment is not limited thereto.

[0070] The display device 100 may include a control printed circuit board CPCB for mounting control components and various electrical devices.

[0071] The level shifter 140 and the timing controller 150 may be mounted on the control printed circuit board CPCB. The level shifter 140 and the timing controller 150 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and processors.

[0072] The control printed circuit board CPCB may be electrically connected to a circuit film or the like on which a driver integrated circuit is mounted through at least one connection cable CBL. Here, the connection cable CBL may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

[0073] The level shifter 140 may be connected to the gate driver 130 through the gate control line GCL. The level shifter 140 may output a gate clock signal GCLK, a gate start signal GST (see Figure 1 ) and the like to the gate driver 130 through the gate control line GCL.

[0074] In one embodiment, the level shifter 140 may also be connected to the reverse signal line RL. The level shifter 140 may output a predetermined reverse signal through the reverse signal line RL. For example, the level shifter 140 may apply a reverse signal whose phase is opposite to the phase of the gate clock signal GCLK applied to the gate control line GCL.

[0075] Hereinafter, the waveforms of the original signal and the reverse signal respectively applied to the control signal line and the reverse signal line RL will be described in detail.

[0076] Figure 3 is a waveform diagram of the signals applied to the Figure 2 signal line and the reverse signal line. Specifically, Figure 3shows gate clock signals GCLK1 to GCLK4 applied to a gate control line GCL (see Figure 2 ), and an inverted signal PGCLK applied to an inverted signal line RL (see Figure 2 ).

[0077] The gate clock signals GCLK1 to GCLK4 may be alternately applied to stage circuits constituting a gate driver 130 (see Figure 2 ). The gate clock signals GCLK1 to GCLK4 may be square wave signals (pulse signals) that repeat a conduction voltage and a turn-off voltage. In this case, the length (pulse width) of the conduction voltage of the gate clock signals GCLK1 to GCLK4 may be about 1H (one horizontal period) or less than 1H.

[0078] The gate clock signals GCLK1 to GCLK4 may have the same waveform and may be phase-shifted signals. For example, the second gate clock signal GCLK2 may be a signal having the same waveform as the first clock signal GCLK1 and phase-shifted (phase-delayed) at a predetermined interval (about 1H), the third gate clock signal GCLK3 may be a signal having the same waveform as the second clock signal GCLK2 and phase-shifted (phase-delayed) at a predetermined interval (about 1H), and the fourth gate clock signal GCLK4 may be a signal having the same waveform as the third clock signal GCLK3 and phase-shifted (phase-delayed) at a predetermined interval (about 1H).

[0079] The inverted signal PGCLK may be a signal having a phase opposite to the phases of the gate clock signals GCLK1 to GCLK4 (180-degree phase). For example, the inverted signal PGCLK may be composed of a plurality of inverted clock signals, each having a phase inverted with respect to each of the gate clock signals GCLK1 to GCLK4. Alternatively, the inverted signal PGCLK may be composed of one inverted clock signal having a phase inverted with respect to the sum signal of the gate clock signals GCLK1 to GCLK4, as shown. Alternatively, the inverted signal PGCLK may be composed of one or more inverted clock signals, each having a phase inverted with respect to the sum signal of at least two of the gate clock signals GCLK1 to GCLK4.

[0080] Since the gate clock signals GCLK1 to GCLK4 are square wave signals that cause EMI, a peak current is generated on the gate control line GCL when the potential is reversed, resulting in EMI. In this case, when an inverted signal PGCLK having a phase opposite to that of the gate clock signals GCLK1 to GCLK4 is output, the electromagnetic field of the inverted signal PGCLK cancels or compensates the electromagnetic field of the peak current, thereby minimizing, reducing, or eliminating EMI.

[0081] In Figure 2 the embodiment shown, the inverted signal line RL to which the inverted signal PGCLK is applied has a closed-loop shape surrounding the display area DA, and has the same or a similar shape as the closed loop formed by the gate control lines GCL to which the gate clock signals GCLK1 to GCLK4 are applied and the gate lines GL connected to the gate control lines GCL. Compared with the case where the inverted signal line RL has a bar-shaped structure with an opening at a predetermined position, this type of inverted signal line RL has a length closer to that of the signal line to which the original signal is applied. As the length deviation between the signal line of the original signal and the inverted signal line RL decreases, the deviation of the electromagnetic field radiation generated from the two lines can be reduced, so that the field cancellation efficiency can be increased and the EMI can be reduced.

[0082] Figure 4 is a plan view of a display device according to a second embodiment.

[0083] Referring to Figure 4 , the display panel 210 may include a display area DA for displaying an image, and a non-display area NDA near the display area DA that does not display an image.

[0084] The display area DA includes data lines DL (see Figure 1 ), gate lines GL intersecting the data lines DL, and an array of pixels P defined in the intersecting areas of the data lines DL and the gate lines GL (see Figure 1 ).

[0085] At least some of the drivers may be mounted on or connected to the non-display area NDA. For example, the data driver 220 may be connected to one side of the non-display area NDA, and the gate driver 230 may be mounted on one side of the non-display area NDA.

[0086] In one embodiment, one or more inverted signal lines RL may be provided in the non-display area NDA. The inverted signal line RL is configured to receive an inverted signal of a predetermined original signal. For example, the inverted signal line RL may receive an inverted signal having an inverted phase of the gate clock signal GCLK.

[0087] The inverted signal line RL may be set adjacent to the control signal line to which the original signal is applied and may have substantially the same shape as the control signal line. For example, the inverted signal line RL may be set adjacent to the gate control line GCL to which the gate clock signal GCLK is applied and the gate line GL to which the gate clock signal GCLK is provided as a gate signal. As shown, in an embodiment where the gate driver 230 is disposed on both sides of the display panel 210, the gate control line GCL and the gate line GL may form a closed loop. In this embodiment, the inverted signal line RL may be disposed in the non-display area NDA along the edge of the display panel 210 and may be disposed in a closed-loop shape surrounding the display area DA.

[0088] The inverted signal line RL may be formed of the same material and / or have the same electrical characteristics as the control signal line to which the original signal is applied. In Figure 4 it, an example in which two inverted signal lines RL are disposed in the non-display area NDA is shown, but this embodiment is not limited thereto.

[0089] The non-display area NDA also includes an array of dummy pixels DP connected to the inverted signal line RL. The dummy pixels DP may have the same arrangement as the pixels P disposed in the display area DA. For example, the dummy pixels DP may be aligned in a substantially straight line with adjacent pixels P in the row direction and the column direction. The number of pixels P disposed in one pixel row may be equal to the number of dummy pixels DP disposed in one dummy pixel row. However, this embodiment is not limited thereto.

[0090] In one embodiment, the dummy pixels DP may be disposed on a side where no driving units (e.g., the data driver 220, the gate driver 230, the level shifter 240, and the timing controller 250) are disposed. In the shown embodiment, the dummy pixels DP are disposed on a side opposite to the level shifter 240 and the timing controller 250 and are disposed away from the level shifter 240 and the timing controller 250. However, this embodiment is not limited thereto.

[0091] At least some of the drivers may be mounted on or connected to the non-display area NDA. For example, the data driver 220 may be connected to one side of the non-display area NDA, and the gate driver 230 may be mounted on one side of the non-display area NDA.

[0092] The display device 200 may include a control printed circuit board CPCB for mounting control components and various electrical devices.

[0093] The level shifter 240 and the timing controller 250 may be mounted on the control printed circuit board CPCB.

[0094] The level shifter 240 can be connected to the gate driver 230 through the gate control line GCL. The level shifter 240 can output a gate clock signal GCLK, a gate start signal GST, etc. to the gate driver 230 through the gate control line GCL.

[0095] In one embodiment, the level shifter 240 can also be connected to the reverse signal line RL. The level shifter 240 can output a predetermined reverse signal through the reverse signal line RL. For example, the level shifter 240 can apply a reverse signal whose phase is opposite to that of the gate clock signal GCLK applied to the gate control line GCL.

[0096] Figure 5 is Figure 4 an enlarged view of a part of the shown display device. Specifically, Figure 5 it shows a part of the pixel P connected to the gate line GL in the display area DA and a part of the dummy pixel DP connected to the reverse signal line RL in the non-display area NDA.

[0097] Referring to Figure 5 , the pixel P can include at least one switching transistor TR and a light emission control circuit LC. The light emission control circuit LC can include, for example, a light emitting element, a driving transistor for controlling the light emission of the light emitting element, at least one capacitor, a compensation circuit, etc. The light emitting element can be, for example, a liquid crystal cell, an organic light emitting diode, a micro LED, etc.

[0098] The switching transistor TR of the pixel P can have a gate electrode connected to the gate line GL, one electrode connected to the light emission control circuit LC, and another electrode connected to the data line DL. The switching transistor TR is turned on according to a gate signal of a gate conduction level (e.g., a gate low voltage) applied to the gate line GL, and sends the data voltage applied to the data line DL to the light emission control circuit LC. The light emitting element provided in the light emission control circuit LC can be controlled to emit light with a brightness corresponding to the data voltage.

[0099] The dummy pixel DP can include at least one dummy switching transistor DTR and a dummy light emission control circuit DLC. The dummy light emission control circuit DLC can include, for example, a light emitting element, a driving transistor for controlling the light emission of the light emitting element, at least one capacitor, a compensation circuit, etc. The light emitting element can be, for example, a liquid crystal cell, an organic light emitting diode, a micro LED, etc.

[0100] In this case, the pseudo-emission control circuit DLC of the pseudo-pixel DP and the emission control circuit LC of the pixel P may be composed of the same number and type of circuit elements. Therefore, the load deviation between the following can be minimized or at least reduced: the inverted signal line RL connected to the pseudo-pixel DP, and the gate control line GCL (see Figure 4 ) and the gate line GL directly or indirectly connected to the pixel P.

[0101] The pseudo-switching transistor DTR of the pseudo-pixel DP may have a gate electrode connected to the inverted signal line RL and one electrode connected to the pseudo-emission control circuit DLC. Compared with the pixel P, the other electrode of the pseudo-switching transistor DTR is connected to the common voltage instead of the data line DL. In other words, the pseudo-switching transistor DTR of the pseudo-pixel DP has a structure in which the source electrode and the drain electrode are electrically short-circuited. Therefore, when the pixel P is driven, the pseudo-pixel DP is configured to output substantially black light to prevent interference with the displayed image.

[0102] The following will refer to Figure 6 and Figure 7 to describe the specific circuit configurations of the pixel P and the pseudo-pixel DP.

[0103] Figure 6 is Figure 5 the circuit diagram of the pixel shown.

[0104] In one embodiment, the display device 200 (see Figure 4 ) may be a liquid crystal display device, and the pixel P may be configured to charge the liquid crystal cell Clc to a data voltage corresponding to the image data DATA (see Figure 1 ). In this embodiment, the pixel P may include a switching transistor TR, a storage capacitor Cst, and a liquid crystal cell Clc.

[0105] The switching transistor TR includes a gate electrode connected to the gate line GL, a drain electrode connected to the data line DL, and a source electrode connected to the pixel electrode of the liquid crystal cell Clc. The switching transistor TR may be an n-channel field effect transistor. However, the type of the switching transistor TR is not limited, and the switching transistor TR may be a p-channel field effect transistor.

[0106] The liquid crystal cell Clc includes a pixel electrode connected to the source electrode of the switching transistor TR, and a common electrode to which the common voltage Vcom is applied.

[0107] The storage capacitor Cst includes a first electrode connected to the source electrode of the switching transistor TR, and a second electrode to which the common voltage Vcom is applied.

[0108] When a gate signal having a gate conduction level is applied to a gate line GL, a data voltage corresponding to a corresponding pixel P can be applied to a data line DL. The data voltage is sent through a switching transistor TR in an on state to a pixel electrode of a liquid crystal cell Clc and a first electrode of a storage capacitor Cst. In this case, the liquid crystal cell Clc and the storage capacitor Cst can be charged with charges corresponding to a difference between the data voltage and a common voltage Vcom. The arrangement of liquid crystal molecules in the liquid crystal cell Clc is changed by an electric field between the pixel electrode and the common electrode, thereby changing and emitting light incident from the outside.

[0109] Figure 7 is Figure 5 a circuit diagram of the pseudo pixel shown.

[0110] Referring to Figure 7 , a pseudo pixel DP according to an embodiment can include a pseudo switching transistor DTR, a pseudo storage capacitor DCst, and a pseudo liquid crystal cell DClc.

[0111] The pseudo switching transistor DTR includes a gate electrode connected to an inverted signal line RL, a drain electrode receiving the common voltage Vcom, and a source electrode connected to a pixel electrode of the pseudo liquid crystal cell DClc. The pseudo switching transistor DTR can be an n-channel field effect transistor. However, the type of the pseudo switching transistor DTR is not limited, and the pseudo switching transistor DTR can be a p-channel field effect transistor.

[0112] The pseudo liquid crystal cell DClc includes a pixel electrode connected to the source electrode of the pseudo switching transistor DTR, and a common electrode to which the common voltage Vcom is applied.

[0113] The pseudo storage capacitor DCst includes a first electrode connected to the source electrode of the pseudo switching transistor DTR, and a second electrode to which the common voltage Vcom is applied.

[0114] Since such a pseudo pixel DP is configured not to receive a data voltage and has a structure in which the source electrode and the drain electrode of the pseudo switching transistor DTR are electrically short-circuited, the pseudo pixel DP is configured not to output an image or emit black light when the pixel P is driven.

[0115] Figure 8A and Figure 8B are diagrams showing an improvement effect of field cancellation of a display device according to a second embodiment.

[0116] As shown in Figure 2In the illustrated embodiment, when the inverted signal line RL is in a no-load state, the loads of the gate control line GCL and the gate line GL to which the original signal is applied are different from the load of the inverted signal line RL. Additionally, due to the different loads, the gate clock signal GCLK and the inverted signal PGCLK, which are the original signals, have different slew rates, as Figure 8A shown. Accordingly, the field cancellation efficiency between the gate clock signal GCLK and the inverted signal PGCLK is reduced.

[0117] In Figures 4 to 7 the embodiment, the dummy pixel DP is connected to the inverted signal line RL, thereby minimizing the load deviation of the gate control line GCL and the gate line GL to which the original signal is applied. Accordingly, as Figure 8B shown, the gate clock signal GCLK and the inverted signal PGCLK to which the original signal is applied can have substantially the same slew rate, and thus, the field cancellation efficiency between the gate clock signal GCLK and the inverted signal PGCLK can be increased.

[0118] Figure 9 is a plan view of a display device according to a third embodiment.

[0119] Referring to Figure 9 , the display panel 310 may include a display area DA for displaying an image, and a non-display area NDA near the display area DA that does not display an image.

[0120] The display area DA includes data lines DL (see Figure 1 ), gate lines GL intersecting the data lines DL, and an array of pixels P (see Figure 1 ) defined in the intersecting regions of the data lines DL and the gate lines GL.

[0121] At least some of the drivers may be mounted on or connected to the non-display area NDA. For example, the data driver 320 may be connected to one side of the non-display area NDA, and the gate driver 330 may be mounted on one side of the non-display area NDA.

[0122] In one embodiment, one or more inverted signal lines RL may be provided in the non-display area NDA. The inverted signal line RL is configured to receive an inverted signal of a predetermined original signal. For example, the inverted signal line RL may receive an inverted signal having an opposite phase to the gate clock signal GCLK.

[0123] The inverted signal line RL can be set adjacent to the control signal line to which the original signal is applied and can have substantially the same shape as the control signal line. For example, the inverted signal line RL can be set adjacent to the gate control line GCL to which the gate clock signal GCLK is applied and the gate line GL to which the gate clock signal GCLK is provided as a gate signal. As shown, in an embodiment where the gate driver 330 is disposed on both sides of the display panel 310, the gate control line GCL and the gate line GL can form a closed loop. In this embodiment, the inverted signal line RL can be disposed in the non-display area NDA along the edge of the display panel 310 and can be disposed in a closed-loop shape surrounding the display area DA.

[0124] The inverted signal line RL can be formed of the same material and / or have the same electrical characteristics as the control signal line to which the original signal is applied. In Figure 9 it, an example is shown in which two inverted signal lines RL are disposed in the non-display area NDA, but this embodiment is not limited thereto.

[0125] The non-display area NDA also includes an array of dummy pixels DP connected to the inverted signal line RL. The dummy pixels DP can have the same arrangement as the pixels P disposed in the display area DA. For example, the dummy pixels DP can be aligned in a substantially straight line with adjacent pixels P in the row direction and the column direction. The number of pixels P disposed in one pixel row can be equal to the number of dummy pixels DP disposed in one dummy pixel row. However, this embodiment is not limited thereto.

[0126] In one embodiment, the dummy pixels DP are disposed on the side facing the level shifter 340 and the timing controller 350. Thus, the dummy pixels DP are disposed adjacent to the level shifter 340 and the timing controller 350.

[0127] At least some of the drivers can be mounted on or connected to the non-display area NDA. For example, the data driver 320 can be connected to one side of the non-display area NDA, and the gate driver 330 can be mounted on one side of the non-display area NDA.

[0128] The display device 300 can include a control printed circuit board CPCB for mounting control components and various electrical devices.

[0129] The level shifter 340 and the timing controller 350 can be mounted on the control printed circuit board CPCB.

[0130] The level shifter 340 can be connected to the gate driver 330 through the gate control line GCL. The level shifter 340 can output the gate clock signal GCLK, the gate start signal GST, etc. to the gate driver 330 through the gate control line GCL.

[0131] In one embodiment, the level shifter 340 may also be connected to the inverted signal line RL. The level shifter 340 may output a predetermined inverted signal through the inverted signal line RL. For example, the level shifter 340 may apply an inverted signal whose phase is opposite to the phase of the gate clock signal GCLK applied to the gate control line GCL.

[0132] Figure 10 is a plan view of a display device according to a fourth embodiment.

[0133] Referring to Figure 10 , the display panel 410 may include a display area DA for displaying an image, and a non-display area NDA near the display area DA that does not display an image.

[0134] The display area DA includes data lines DL (see Figure 1 ), gate lines GL intersecting the data lines DL. And an array of pixels P defined in the intersection regions of the data lines DL and the gate lines GL (see Figure 1 ).

[0135] The display area DA may be divided into a plurality of display blocks DB1 to DB4. The display blocks DB1 to DB4 may be divided according to the distance from the level shifter 440. Each of the display blocks DB1 to DB4 may include one or more pixel rows.

[0136] In the illustrated embodiment, the display area DA is divided into four display blocks DB1 to DB4. When the column resolution of the display panel 410 is 1080 px, each of the display blocks DB1 to DB4 may include 270 pixel rows.

[0137] However, this embodiment is not limited thereto, and the sizes of the display blocks DB1 to DB4 and / or the number of pixel rows included in the display blocks DB1 to DB4 may be selected in various ways according to the size and resolution of the display panel 410.

[0138] At least some of the drivers may be mounted on or connected to the non-display area NDA. For example, the data driver 420 may be connected to one side of the non-display area NDA, and the gate driver 430 may be mounted on one side of the non-display area NDA.

[0139] The gate driver 430 may be composed of stage circuits that are connected to the plurality of gate lines GL one-to-one. The stage circuits are configured to provide gate signals to the pixel rows of the display blocks DB1 to DB4 corresponding to them one-to-one. The following will refer to Figure 11Describe the structure of the gate driver 430 in more detail. The gate driver 430 can be configured to be mounted on the non-display area NDA of the display panel 410 in an in-panel gate type.

[0140] In one embodiment, one or more inverted signal lines RL may be provided in the non-display area NDA. The inverted signal line RL is configured to receive an inverted signal of a predetermined original signal. For example, the inverted signal line RL may receive an inverted signal having an inverted phase of the gate clock signal GCLK.

[0141] The inverted signal line RL may be provided adjacent to the control signal line to which the original signal is applied, and may have substantially the same shape as the control signal line. For example, the inverted signal line RL may be provided adjacent to the gate control line GCL to which the gate clock signal GCLK is applied and the gate line GL to which the gate clock signal GCLK is provided as a gate signal. As shown, in the embodiment where the gate driver 430 is provided on both sides of the display panel 410, the gate control line GCL and the gate line GL may form a closed loop. In this embodiment, the inverted signal line RL may be provided in the non-display area NDA along the edge of the display panel 410 and arranged in a closed-loop shape surrounding the display area DA.

[0142] The inverted signal line RL may be formed of the same material and / or have the same electrical characteristics as the control signal line to which the original signal is applied. In Figure 10 it, an example of one inverted signal line RL provided in the non-display area NDA is shown, but this embodiment is not limited thereto.

[0143] The non-display area NDA further includes an array of dummy pixels DP connected to the inverted signal line RL. The dummy pixels DP may have the same arrangement as the pixels P provided in the display area DA. For example, the dummy pixels DP may be aligned in a substantially straight line with adjacent pixels P in the row direction and the column direction. The number of pixels P provided in one pixel row may be equal to the number of dummy pixels DP provided in one dummy pixel row. However, this embodiment is not limited thereto.

[0144] In one embodiment, the non-display area NDA further includes one or more switching elements SW1 to SW3 that are connected to the inverted signal line RL to disconnect or close the inverted signal line RL. The switching elements SW1 to SW3 may be, for example, thin film transistors. In this case, the switching elements SW1 to SW3 may be turned on or off in response to a carry signal and / or a gate start signal GST output from the level shifter 440 and / or the gate driver 430.

[0145] As shown, when the level shifter 440 and / or the gate driver 430 are disposed on both sides of the non-display area NDA, the switching elements SW1 to SW3 can be symmetrically disposed on both sides of the non-display area NDA, and the symmetric switching elements SW1 to SW3 can be controlled together in the same manner.

[0146] One or more switching elements SW1 to SW3 are disposed between the pseudo pixels DP at a predetermined interval. For example, one or more switching elements SW1 to SW3 can be disposed between the pseudo pixel groups DG1 to DG3 composed of one or more pseudo pixels DP. The pseudo pixel groups DG1 to DG3 can be grouped to include the same or different numbers of pseudo pixels DP.

[0147] The switching elements SW1 to SW3 are turned off or on between the gate electrodes of two adjacent pseudo pixels DP to disconnect or connect the inverted signal line RL. According to the on / off of the switching elements SW1 to SW3, the number of pseudo pixel groups DG1 to DG3 (the number of pseudo pixels DP) receiving the inverted signal PGCLK through the inverted signal line RL can be controlled. For example, in the illustrated embodiment, when the first switching element SW1 to the third switching element SW3 are all turned on, the inverted signal PGCLK can be applied to the pseudo pixels DP of the first pseudo pixel group DG1 to the third pseudo pixel group DG3. When the third switching element SW3 is turned off and only the first switching element SW1 and the second switching element SW2 are turned on, the inverted signal PGCLK can be applied to the pseudo pixels DP of the first pseudo pixel group DG1 and the second pseudo pixel group DG2. When the second switching element SW2 and the third switching element SW3 are turned off and only the first switching element SW1 is turned on, the inverted signal PGCLK can be applied only to the pseudo pixels DP of the first pseudo pixel group DG1.

[0148] Since the number of pseudo pixels DP to which the inverted signal PGCLK is applied is controlled as described above, the load and the effective length of the inverted signal line RL can be adjusted. By such a control method, the electromagnetic field radiation generated from the inverted signal line RL can be controlled more effectively, and the conversion rate deviation between the original signal and the inverted signal can be reduced more effectively.

[0149] The on / off of the switching elements SW1 to SW3 can be determined corresponding to the activated display blocks DB1 to DB4. In other words, the on / off of the switching elements SW1 to SW3 can be determined according to the positions of the display blocks DB1 to DB4 to which the gate clock signal GCLK (gate signal), which is the original signal, is applied.

[0150] The display blocks DB1 to DB4 have different distances from the level shifter 440 according to their arrangements. Accordingly, for each of the display blocks DB1 to DB4, the loads and transition rates of the signal lines connecting the display blocks DB1 to DB4 to the level shifter 440 may be different. Accordingly, by turning on / off the switching elements SW1 to SW3, the loads and transition rates of the inverted signal line RL are adaptively adjusted according to the loads and transition rates of the signal lines to which the original signal is applied, thereby improving the field cancellation effect.

[0151] For example, when the original signal is applied to the first display block DB1 having the maximum load of the signal line, the first switching element SW1 to the third switching element SW3 are all turned on, thereby maximizing the load of the inverted signal line RL. Conversely, when the original signal is applied to the fourth display block DB4 having the minimum load of the signal line, the first switching element SW1 to the third switching element SW3 are all turned off, thereby minimizing or at least reducing the load of the inverted signal line RL.

[0152] At least some of the drivers may be mounted on the non-display area NDA or connected to the non-display area NDA. For example, the data driver 420 may be connected to one side of the non-display area NDA, and the gate driver 430 may be mounted on one side of the non-display area NDA.

[0153] The display device 400 may include a control printed circuit board CPCB for mounting control components and various electrical devices.

[0154] The level shifter 440 and the timing controller 450 may be mounted on the control printed circuit board CPCB.

[0155] The level shifter 440 may be connected to the gate driver 430 through the gate control line GCL. The level shifter 440 may output a gate clock signal GCLK, a gate start signal GST, etc. to the gate driver 430 through the gate control line GCL.

[0156] In one embodiment, the level shifter 440 may also be connected to the inverted signal line RL. The level shifter 440 may output a predetermined inverted signal through the inverted signal line RL. For example, the level shifter 440 may apply an inverted signal whose phase is opposite to the phase of the gate clock signal GCLK applied to the gate control line GCL.

[0157] Figure 11 is schematically shown Figure 10 of the structure of the gate driver.

[0158] Referring to Figure 11 the gate driver 430 may include a plurality of stage circuits ST1 to ST4. For ease of description, Figure 11Four-stage circuits ST1 to ST4 included in the gate driver 430 are shown, but other numbers of stage circuits may be included in the gate driver 430.

[0159] The second-stage circuit ST2 may be dependently connected to the first-stage circuit ST1, the third-stage circuit ST3 may be dependently connected to the second-stage circuit ST2, and the fourth-stage circuit ST4 may be dependently connected to the third-stage circuit ST3. The first-stage circuit ST1 to the fourth-stage circuit ST4 may have substantially the same configuration.

[0160] The stage circuits ST1 to ST4 may be connected to the corresponding gate lines GL1 to GL4 one-to-one and may output gate signals in response to the gate clock signals GCLK1 to GCLK4.

[0161] The first-stage circuit ST1 may receive the gate start signal GST. Additionally, the second-stage circuit ST2 to the fourth-stage circuit ST4 may each receive a carry signal (i.e., one of the first carry signal CR1 to the third carry signal CR3) output from the previous stage circuits ST1 to ST3. For example, the second-stage circuit ST2 may receive the first carry signal CR1 output from the first-stage circuit ST1, the third-stage circuit ST3 may receive the second carry signal CR2 output from the second-stage circuit ST2, and the fourth-stage circuit ST4 may receive the third carry signal CR3 output from the third-stage circuit ST3.

[0162] Additionally, the stage circuits ST1 to ST4 may alternately receive one or more of the gate clock signals GCLK1 to GCLK4. For example, the i-th stage circuit may receive the first gate clock signal GCKL1 (i is an integer greater than zero), the i + 1-th stage circuit may receive the second gate clock signal GCLK2, the i + 2-th stage circuit may receive the third gate clock signal GCLK3, and the i + 3-th stage circuit may receive the fourth gate clock signal GCLK4.

[0163] In the present embodiment, as shown, the first-stage circuit ST1 may receive the first gate clock signal GCKL1, the second-stage circuit ST2 may receive the second gate clock signal GCLK2, the third-stage circuit ST3 may receive the third gate clock signal GCLK3, and the fourth-stage circuit ST4 may receive the fourth gate clock signal GCLK4.

[0164] The gate clock signals GCLK1 to GCLK4 may have the same waveform and may be phase-shifted signals. For example, the second gate clock signal GCLK2 may be a signal having the same waveform as the first clock signal GCLK1 and phase-shifted (phase-delayed) at a predetermined interval (about 1H), the third gate clock signal GCLK3 may be a signal having the same waveform as the second clock signal GCLK2 and phase-shifted (phase-delayed) at a predetermined interval (about 1H), and the fourth gate clock signal GCLK4 may be a signal having the same waveform as the third clock signal GCLK3 and phase-shifted (phase-delayed) at a predetermined interval (about 1H).

[0165] In addition, the power supply voltages VDD and VSS required for the driver stage circuits ST1 to ST4 may be applied to the stage circuits ST1 to ST4. For example, the high-potential drive voltage VDD and the low-potential drive voltage VSS may be applied to the stage circuits ST1 to ST4. The high-potential drive voltage VDD and the low-potential drive voltage VSS may have a DC voltage level. Here, the voltage level of the high-potential drive voltage VDD may be set to be higher than the voltage level of the low-potential drive voltage VSS.

[0166] In addition, the reset signal SWT may be applied to the stage circuits ST1 to ST4. A gate-on voltage may be applied to all the gate lines GL1 to GL4 according to the reset signal SWT to initialize the pixel P.

[0167] The stage circuits ST1 to ST4 may output gate signals. The gate signals output from the stage circuits ST1 to ST4 may be respectively supplied to the corresponding gate lines GL1 to GL4.

[0168] The stage circuits ST1 to ST4 may also output carry signals CR1 to CR4. The carry signals CR1 to CR4 output from the stage circuits ST1 to ST4 may be respectively supplied to the next-stage circuits ST2 to ST4. For example, the first carry signal CR1 output from the first stage circuit ST1 may be supplied to the second stage circuit ST2, the second carry signal CR2 output from the second stage circuit ST2 may be supplied to the third stage circuit ST3, the third carry signal CR3 output from the third stage circuit ST3 may be supplied to the fourth stage circuit ST4, and the fourth carry signal CR4 output from the fourth stage circuit ST4 may be supplied to a fifth stage circuit (not shown).

[0169] Except for the type of received signal, the stage circuits ST1 to ST4 included in the gate driver 430 may have substantially the same configuration. For example, except for receiving an input signal (i.e., the start signal GST or the carry signals CR1 to CR4 of the previous stage circuit), the first stage circuit ST1, which is the first stage circuit for receiving the start signal GST, and the remaining stage circuits (e.g., the second stage circuit ST2 to the fourth stage circuit ST4) for receiving the carry signals CR1 to CR4 of the previous stage circuit may have substantially the same circuit configuration and may operate in substantially the same manner.

[0170] Figure 12 is Figure 10 an enlarged view of a part of the shown display device. Specifically, Figure 12 shows a connection portion between the gate driver 430 and the switching elements SW1 to SW3.

[0171] Referring to Figure 12 , the gate driver 430 and the switching elements SW1 to SW3 may be connected through a control circuit CC. The control circuit CC may include a first node N1 to a third node N3, storage capacitors C1 to C3, a reset transistor RTR, and control transistors CTR1 to CTR3.

[0172] The first node N1 to the third node N3 are respectively connected to the corresponding stage circuits STi, STj, and STk (i, j, and k are integers greater than zero and satisfy the condition i < j < k) of the gate driver 430. The first node N1 to the third node N3 are configured to receive the carry signals CRi, CRj, and CRk output from the stage circuits STi, STj, and STk. Here, the stage circuits STi, STj, and STk may be the stage circuits STi, STj, and STk connected to the last pixel row of each of the display blocks DB1 to DB4. When the stage circuits STi, STj, and STk sequentially output the carry signals CRi, CRj, and CRk at the gate high voltage VGH, the gate high voltage VGH is sent to the first node N1 to the third node N3.

[0173] One electrode of the storage capacitors C1 to C3 is connected to the first node N1 to the third node N3 in a one-to-one manner. The other electrodes of the storage capacitors C1 to C3 may be connected to the ground voltage. The storage capacitors C1 to C3 may store a voltage corresponding to the carry signals CR1 to CR3 or the gate conduction voltage applied to the first node N1 to the third node N3, thereby stabilizing the voltage at the first node N1 to the third node N3.

[0174] The reset transistor RTR is connected between the gate conduction voltage and the gate electrodes of the control transistors CTR1 to CTR3. In the illustrated embodiment, the control transistors CTR1 to CTR3 and the switching elements SW1 to SW3 are p-channel field effect transistors. In the present embodiment, the gate conduction voltage is the gate low voltage VGL.

[0175] However, the present embodiment is not limited thereto. In another embodiment, the control transistors CTR1 to CTR3 and the switching elements SW1 to SW3 may be n-channel field effect transistors. In this embodiment, the gate conduction voltage is the gate high voltage VHL.

[0176] The gate electrode of the reset transistor RTR is configured to receive the gate start signal GST. When the gate start signal GST is applied to the first-stage circuit ST1 of the gate driver 430 (see Figure 11 ), the reset transistor RTR receives the gate start signal GST through the gate electrode. The reset transistor RTR is turned on by the gate start signal GST to send the gate conduction voltage to the gate electrodes of the control transistors CTR1 to CTR3.

[0177] The control transistors CTR1 to CTR3 are respectively connected in a diode-connected manner between the reset transistor RTR and the first node N1 to the third node N3. The gate electrodes of the control transistors CTR1 to CTR3 are connected to the reset transistor RTR. When the gate conduction voltage is applied through the reset transistor RTR, the control transistors CTR1 to CTR3 are turned on in response to the gate conduction voltage to send the gate conduction voltage to the first node N1 to the third node N3. The switching elements SW1 to SW3 may all be turned on in response to the gate conduction voltage.

[0178] The switching elements SW1 to SW3 are provided at predetermined intervals between the pseudo pixels DP. For example, the switching elements SW1 to SW3 may be provided between the pseudo pixel groups DG1 to DG3 composed of one or more pseudo pixels DP. The pseudo pixel groups DG1 to DG3 may be grouped to include the same or different numbers of pseudo pixels DP.

[0179] The source electrodes and drain electrodes of the switching elements SW1 to SW3 are connected to the inverted signal line RL. The gate electrodes of the switching elements SW1 to SW3 are connected one-to-one to the first node N1 to the third node N3 of the control circuit CC. When the carry signals CR1 to CR3 of the gate high voltage VGH are sequentially output to the first node N1 to the third node N3, the switching elements SW1 to SW3 can be sequentially turned off in response to the carry signals CR1 to CR3. The storage capacitors C1 to C3 store the voltages corresponding to the carry signals CR1 to CR3, and maintain the voltages at the first node N1 to the third node N3 as the gate high voltage VGH. When the voltages at the first node N1 to the third node N3 are maintained, the switching elements SW1 to SW3 can maintain the off state.

[0180] When the switching elements SW1 to SW3 are turned off, the spaces between the dummy pixel groups DG1 to DG3 can be opened. In other words, by sequentially turning off the switching elements SW1 to SW3, the dummy pixel groups DG1 to DG3 can be sequentially separated from the inverted signal line RL.

[0181] Figure 13 is applied to Figure 12 The waveform diagram of the signal of the control circuit shown. Figures 14A to 14D is a diagram for describing the field cancellation improvement effect of the display device according to the fourth embodiment.

[0182] Refer to together Figure 12 and Figure 13 , the driving of the gate driver 430 can be started, and the gate start signal GST can be applied to the first-stage circuit ST1 during the first period t1 (see Figure 11 ). Then, the reset transistor RTR can be turned on in response to the gate start signal GST, and the gate low voltage VGL can be applied to the control transistors CTR1 to CTR3 through the reset transistor RTR.

[0183] The control transistors CTR1 to CTR3 can send the gate low voltage VGL to the first node N1 to the third node N3. The storage capacitors C1 to C3 connected to the first node N1 to the third node N3 are charged to the gate low voltage VGL.

[0184] The switching elements SW1 to SW3 are turned on in response to the voltages at the first node N1 to the third node N3. Then, the first dummy pixel group DG1 to the third dummy pixel group DG3 are short-circuited, and the first dummy pixel group DG1 to the third dummy pixel group DG3 are all electrically connected to the inverted signal line RL.

[0185] In this case, as Figure 14AAs shown, the load of the inverted signal line RL can be maximized, and the conversion rate of the electromagnetic radiation of the inverted signal PGCLK can be minimized (level 4).

[0186] After the gate start signal GST, the stage circuits constituting the gate driver 430 sequentially output a gate signal and a carry signal at a gate high voltage VGH. The stage circuits ST1 to STi connected to the first display block DB1 can be sequentially driven, and the i-th carry signal CRi at the high voltage VGH can be output from the i-th stage circuit STi finally connected to the first display block DB1 during the second period t2.

[0187] The i-th carry signal CRi is supplied to the third node N3. The third storage capacitor C3 connected to the third node N3 is charged to the gate high voltage VGH corresponding to the i-th carry signal CRi.

[0188] The third switching element SW3 is turned off in response to the voltage at the third node N3. Then, the space between the third pseudo-pixel group DG3 and the second pseudo-pixel group DG2 is opened, and the third pseudo-pixel group DG3 is electrically separated from the inverted signal line RL.

[0189] In this case, compared with the first period t1, the load of the inverted signal line RL can be reduced, and as Figure 14B shown, the conversion rate of the electromagnetic radiation of the inverted signal PGCLK can increase corresponding to the load reduction level (level 3).

[0190] During the third period t3, the j-th carry signal CRj at the high voltage VGH can be output from the j-th stage circuit STj finally connected to the second display block DB2.

[0191] The j-th carry signal CRj is supplied to the second node N2. The second storage capacitor C2 connected to the second node N2 is charged to the gate high voltage VGH corresponding to the j-th carry signal CRj.

[0192] The second switching element SW2 is turned off in response to the voltage at the second node N2. Then, the space between the second pseudo-pixel group DG2 and the first pseudo-pixel group DG1 is opened, and the second pseudo-pixel group DG2 is electrically separated from the inverted signal line RL.

[0193] In this case, compared with the second period t2, the load of the inverted signal line RL can be reduced, and as Figure 14C shown, the conversion rate of the electromagnetic radiation of the inverted signal PGCLK can increase corresponding to the load reduction level (level 2).

[0194] During the fourth period t4, the k-th carry signal CRk at a high voltage VGH can be output from the k-th stage circuit STk that was last connected to the third display block DB3.

[0195] The k-th carry signal CRk is supplied to the first node N1. The first storage capacitor C1 connected to the first node N1 is charged to the gate high voltage VGH corresponding to the k-th carry signal CRk.

[0196] The first switching element SW1 is turned off in response to the voltage at the first node N1. Then, the space between the first pseudo-pixel group DG1 and the inverted signal line RL is opened, and the first pseudo-pixel group DG1 is electrically separated from the inverted signal line RL.

[0197] In this case, the load of the inverted signal line RL can be minimized, and as Figure 14D shown, the conversion rate of the electromagnetic radiation of the inverted signal PGCLK can be maximized (level 1).

[0198] In Figures 14A to 14D , the load of the inverted signal line PGCLK (which depends on the number of pseudo-pixels DP connected to the inverted signal line RL) and the conversion rate of the electromagnetic radiation of the inverted signal PGCLK can be as shown in Table 1 accordingly.

[0199] [Table 1]

[0200] Level Number of pseudo-pixels Load (%) Rise time (ns) Fall time (ns) 4 All 100％ 231 292 3 1 / 2 50％ 99.88 105.5 2 1 / 4 25％ 75.15 80.55 1 0 0％ 57.88 59.99

[0201] Since the number of pseudo-pixels DP to which the inverted signal PGCLK is applied is controlled as described above, the load and the physical length of the inverted signal line RL can be adjusted. Through such a control method, the electromagnetic field radiation generated from the inverted signal line RL can be controlled more effectively, and the conversion rate deviation between the original signal and the inverted signal can be reduced more effectively.

[0202] According to an embodiment of the display device, the radiation deviation between the inverted signal and the original signal can be removed by forming the inverted signal line to which the inverted signal is applied in the same closed-loop shape as the signal line to which the original signal is applied.

[0203] According to an embodiment of the display device, the waveform deviation caused by the load difference between the signal line to which the original signal is applied and the inverted signal line can be removed by connecting the inverted signal line to which the inverted signal is applied to the pseudo-pixel.

[0204] According to an embodiment of the display device, the field cancellation efficiency between the original signal and the inverted signal can be increased, and the electromagnetic interference prevention effect can be improved.

[0205] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains will be able to understand that the above-described technical configuration of the present invention can be implemented in other specific forms without changing its technical spirit or basic characteristics. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive. In addition, the scope of the present invention is defined by the claims to be described herein rather than the detailed description. Further, the meaning and scope of the claims and all variations or modifications derived from the equivalent concept should be construed as being included within the scope of the present invention.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area provided with pixels and a non-display area surrounding the display area; a level shifter at at least one side of the non-display area and configured to generate a gate clock signal and an inversion signal having a phase opposite to that of the gate clock signal; a control signal line configured to transmit the gate clock signal output from the level shifter to the pixel; as well as an inverting signal line configured to receive the inverting signal from the level shifter, Wherein, the inverting signal line is in a closed loop shape surrounding the display area in the non-display area. 2 . The display device according to claim 1 , further comprising a gate driver configured to output a gate signal to the pixel in response to the gate clock signal.

3. The display device according to claim 2, wherein: The gate driver receives the gate clock signal through a gate control line and outputs one of the gate signals through a gate line, and The control signal line includes the gate control line and the gate line. 4 . The display device according to claim 2 , further comprising a dummy pixel in the non-display area and connected to the inversion signal line.

5. The display device according to claim 4, wherein: The dummy pixel is at another side of the display panel opposite to the level shifter.

6. The display device according to claim 4, wherein: The dummy pixel is at a side of the display panel facing the level shifter.

7. The display device according to claim 4, wherein: The dummy pixels include the same number and type of circuit elements as the pixels.

8. The display device according to claim 4, wherein: Each of the dummy pixels comprises: a dummy light emitting control circuit, the dummy light emitting control circuit comprising a dummy light emitting element and at least one circuit element configured to control light emission of the dummy light emitting element; and A dummy switching transistor has a gate electrode connected to the inverting signal line, and a source electrode and a drain electrode which are electrically short-circuited.

9. The display device according to claim 8, wherein: The pseudo light emitting control circuit comprises: The dummy light emitting element includes a dummy liquid crystal unit connected between the dummy switch transistor and a common electrode; and a dummy storage capacitor connected between the dummy liquid crystal unit and the common electrode, and Wherein, the dummy switch transistor is connected between the dummy liquid crystal unit and the common electrode. 10 . The display device according to claim 4 , further comprising one or more switching elements connected to the inversion signal line and configured to open and close the inversion signal line.

11. The display device according to claim 10, wherein: The one or more switching elements are located between the dummy pixels at predetermined intervals.

12. The display device according to claim 10, wherein: The pseudo pixels are grouped into a plurality of pseudo pixel groups, each pseudo pixel group includes the same or different number of pseudo pixels, and The one or more switching elements are each disposed between the dummy pixel groups.

13. The display device according to claim 12, wherein: The gate driver is composed of a stage circuit configured to receive a gate start signal or a carry signal output from a previous stage and the gate clock signal, and output one of the gate signals to one or more corresponding pixel rows.

14. The display device according to claim 13, wherein: The one or more switch elements are configured to be turned off according to a carry signal output from a corresponding stage circuit to disconnect the inversion signal line.

15. The display device according to claim 14, wherein: The display panel is divided into a plurality of display blocks, each display block includes one or more pixel rows, and The one or more switching elements are configured to receive a carry signal from a stage circuit connected to a last pixel row of a corresponding display block.

16. The display device according to claim 15, further comprising: a reset transistor having one electrode connected to a gate-on voltage and a gate electrode configured to receive the gate-start signal; a first node receiving a carry signal from a stage circuit connected to a last pixel row of a first display block; a control transistor connected between the other electrode of the reset transistor and the first node in a diode connection; as well as a capacitor connected between the first node and a ground voltage, The one or more switching elements are configured as a first switching element having a source electrode and a drain electrode connected to the inversion signal line between the first dummy pixel group and the second dummy pixel group, and a gate electrode connected to the first node.

17. The display device according to claim 16, wherein: The first switching element is turned on in response to the gate-on voltage applied to the first node through the reset transistor and the control transistor, and is turned off in response to a carry signal of a gate-off level applied to the first node to electrically separate the second dummy pixel group from the inverting signal line.

18. The display device according to claim 1, wherein: The inversion signal line and the control signal line have the same material, or the same electrical characteristics, or the same material and electrical characteristics.

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