Multistage digital beam forming compatible circuit system and method

Abstract

The invention belongs to the technical field of radar and digital chip design, and discloses a multilevel digital beam forming compatible circuit system and method. By configuring different parameters and weights, the optical fiber beam forming circuit can be used as a first-stage digital beam forming circuit to sequentially carry out operations such as weight multiplication, beam forming in the optical fibers and beam forming between the optical fibers on multi-channel data input by each optical fiber, so that first-stage digital beam forming is realized, and beam data is output. The digital beam forming circuit can also be used as a secondary digital beam forming circuit to group optical fibers from primary digital beam forming output and then carry out secondary synthesis on beam data transmitted by the optical fibers with the same serial number in each group of optical fibers, so that beam data grouping synthesis operation between the optical fibers is realized, and cascade connection of digital beam chips is further realized.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of digital chip design, and particularly to a multi-level digital beam synthesis compatible circuit system and method. Background Art

[0002] At present, domestic digital beam synthesis technology mainly relies on FPGA (Field Programmable Gate Array) to implement. Due to its flexibility and reconfigurability, FPGA has been widely used in the early development stage of digital beam synthesis. However, with the continuous improvement of the requirements for device reliability, miniaturization, processing performance, and low power consumption in application fields such as radar, communication, and sonar, the limitations of FPGA have gradually emerged. For example, the power consumption of FPGA is relatively high, especially in high-density computing scenarios, making it difficult to meet the low power consumption requirements of portable devices or long-running systems; at the same time, the physical size of FPGA is relatively large, which is not conducive to the miniaturization and integration of devices; in addition, although FPGA has a certain degree of flexibility in processing complex algorithms, its performance often cannot compare with that of dedicated chips, especially in scenarios with extremely high real-time requirements. Therefore, the development of dedicated digital beam synthesis chips (ASIC) has become an inevitable trend in the industry.

[0003] When implementing digital beam synthesis with FPGA, usually the first-level beam synthesis circuit and the second-level beam synthesis circuit are designed as two sets of independent circuits and are respectively deployed in two FPGAs. Although this design meets the functional requirements to a certain extent, it also brings problems such as waste of hardware resources, increased system complexity, and signal transmission delay. More importantly, developing independent first-level and second-level dedicated digital beam synthesis chips, although it can further improve performance and energy efficiency, due to the high development cost, long development cycle of dedicated chips, and the need to face a series of non-technical issues such as tape-out risks, process selection, and supply chain management, the feasibility of developing two dedicated chips separately is limited.

[0004] On the other hand, if the first-level and second-level beam synthesis circuits are integrated into a dedicated digital beam synthesis chip, although it can reduce the number of chips, lower system complexity and cost, it will also bring new challenges. First, integrating more functional modules will lead to a significant increase in chip power consumption, especially in high-frequency and high-computation-load scenarios, and the power consumption problem may become a key factor restricting chip performance; second, the integration of the first-level and second-level beam synthesis circuits will occupy more chip area, which will not only increase the manufacturing cost but also may affect the packaging and heat dissipation design of the chip; in addition, the first-level and second-level circuits may involve different clock domains, data streams, and control logics, and complex problems such as timing consistency and signal integrity need to be solved during integration, further increasing the design difficulty and risk. Summary of the Invention

[0005] The present invention aims to solve the problem of increased power consumption and area caused by the independent existence of the first- and second-level beamforming circuits in a dedicated digital beamforming chip. It provides a multi-level digital beamforming compatible circuit architecture to integrate the first- and second-level beamforming circuits without increasing the number of multipliers and adders, thereby reducing the power consumption and area of the entire chip.

[0006] To achieve the above object, the present invention provides a multi-level digital beamforming compatible circuit system, including a weighting module and an inter-fiber beamforming module; The weighting module includes a weighting sub-module and an intra-fiber beamforming sub-module; The weighting sub-module includes a number of parallel computing paths, and weight data is pre-stored in each computing path; During the first-level beamforming, the weight data is the coefficient for generating beam data from channel data; During the second-level beamforming, the weight data is the synthesis coefficient of optical fibers with different serial numbers in each group of optical fibers; When the system acts as a first-level digital beamforming circuit, the weighting sub-module copies and distributes the channel data input by the optical fiber to different computing paths for parallel weighting operations, and then outputs the beam data in parallel; When the system acts as a second-level digital beamforming circuit, the weighting sub-module copies and distributes the beam data to different computing paths for parallel weighting operations, and then outputs the beam data in parallel; The intra-fiber beamforming sub-module receives the multiple beam data output by the weighting sub-module, and then performs a hierarchical addition and synthesis operation before outputting; The inter-fiber beamforming module receives the multiple beam data output by multiple weighting modules, and performs an addition and synthesis operation on the multiple beam data according to the principle of adding the same serial numbers.

[0007] Further, each computing path includes 1 complex multiplier and 2 ping-pong operation weight RAMs.

[0008] The present invention also provides a multi-level digital beamforming compatible circuit method, including the following steps: Step 1: Use a multi-level digital beamforming compatible circuit system, which includes a weighting module and an inter-fiber beamforming module, and the weighting module includes a weighting sub-module and an intra-fiber beamforming sub-module; Step 2: Divide the weighting sub-module into a number of parallel computing paths. The system first configures parameters according to functional and performance requirements, and the parameters include the number of channels, the number of beams, and the number of beams in a single computing path; Step 3: Pre-store weight data in each computing path; During the first-level beamforming, the weight data is the coefficient for generating beam data from channel data; When performing secondary beam synthesis, the weight data is the synthesis coefficient of optical fibers with different serial numbers in each group of optical fibers; Step 4: When the system serves as a primary digital beam synthesis circuit, the weight multiplication sub-module copies and distributes the channel data input by the optical fibers to different calculation paths for parallel weight multiplication operations, and then outputs the beam data in parallel; When the system serves as a secondary digital beam synthesis circuit, the weight multiplication sub-module copies and distributes the beam data to different calculation paths for parallel weight multiplication operations, and then outputs the beam data in parallel; Step 5: The in-fiber beam synthesis sub-module receives the multiplexed beam data output by the weight multiplication sub-module, and then performs a hierarchical summation synthesis operation and outputs; Step 6: The inter-fiber beam synthesis module receives the multiplexed beam data output by multiple weighting modules, and performs an addition synthesis operation on the multiplexed beam data according to the principle of adding the same serial numbers, realizing multi-level digital beam synthesis.

[0009] Furthermore, each calculation path in Step 2 includes 1 complex multiplier and 2 ping-pong operation weight RAMs.

[0010] Furthermore, in the primary digital beam synthesis operation in Step 4, assuming the number of channels is C, the number of beams is B, and the number of beams in a single calculation path is S, the data of each channel is copied into P copies, where P = B / S, and distributed to P calculation paths. Each calculation path stores S weights and is responsible for calculating S beams. The actual number of paths participating in the operation is X = C×P, and the outputs of the remaining paths are set to 0, where 0 means discarded.

[0011] Furthermore, in the secondary digital beam synthesis operation in Step 4, assuming there are K groups of input optical fibers, and each group of input optical fibers has N optical fibers, then the beam data input by the optical fibers with the same serial number in each group of optical fibers is synthesized, that is, all the data of the 0th optical fiber is added, all the data of the 1st optical fiber is added,..., all the data of the (N - 1)th optical fiber is added, and finally the multiplexed secondary digital beam synthesis result is output.

[0012] Furthermore, in the secondary digital beam synthesis operation in Step 4, assuming the number of channels is 1, the number of beams is N, and the number of beams in a single calculation path is 1, each calculation path pre-stores 1 weight, and a total of N calculation paths participate in the operation, and the outputs of the remaining calculation paths are set to 0, where 0 means discarded; Among all the groups of input optical fibers, the weight of the i-th calculation path of the i-th optical fiber is set to 1, where 0 ≤ i ≤ N - 1, and the weights of the remaining calculation paths are all set to 0. In this case, the weight multiplication sub-module realizes copying the input channel data to the i-th of the N outputs, and the remaining N - 1 outputs are all 0, where 0 means discarded.

[0013] Further, in the first-level digital beam synthesis operation in step 5, assuming the number of channels is C, the number of beams is B, and the number of beams in a single calculation path is S, then all the beams generated from different channels of a single optical fiber are synthesized into B beams, which are output through P calculation paths, where P = B / S, and each calculation path outputs S beams.

[0014] Further, in the second-level digital beam synthesis operation in step 5, finally, 1 effective beam is synthesized and output through the i-th path among N paths, and the rest output 0. Here, the effective beam means that the number of beams is the same as the number of beams input by a single optical fiber, and 0 indicates discard.

[0015] Further, in the first-level digital beam synthesis operation in step 6, finally, B beams are synthesized and output through P calculation paths, and each calculation path outputs S beams; In the second-level digital beam synthesis operation in step 6, assuming there are K groups of input optical fibers in total, and each group of input optical fibers has N optical fibers, then finally N beams are synthesized.

[0016] Beneficial effects: The present invention provides a multi-level digital beam synthesis compatible circuit system and method. Through ingenious circuit design, the computing units in the first-level and second-level beam synthesis circuits, such as multipliers and adders, are shared and reused. On the premise of ensuring functional integrity, the repeated configuration of hardware resources is reduced, thereby effectively reducing the power consumption and area of the chip. The multi-level digital beam synthesis compatible circuit architecture of the present invention is not only applicable to the current first-level and second-level beam synthesis requirements, but also has good compatibility and scalability, and can support the integration of more levels of beam synthesis. Description of the Drawings

[0017] Figure 1 is the functional block diagram of the weighting module involved in the embodiment of the present invention; Figure 2 is the functional block diagram of the inter-fiber beam synthesis module involved in the embodiment of the present invention; Figure 3 is the data flow diagram of the first-level beam synthesis involved in the embodiment of the present invention; Figure 4 is the data flow diagram of the second-level digital beam synthesis involved in the embodiment of the present invention. Detailed Embodiments Embodiment 1

[0018] Combined with Figures 1-4 , taking 32 parallel calculation paths of each weighting module as an example, the implementation schemes of the first-level digital beam synthesis circuit architecture and the second-level digital beam synthesis circuit architecture are respectively described.

[0019] (I) First-level digital beam synthesis technical solution Taking the number of input optical fibers as 16, the number of beams as 128, the number of beams in a single computing path as 16, the number of input channels per optical fiber as 4, the number of output optical fibers as 8, and the number of beams output per optical fiber as 16 as an example, the first-level digital beam synthesis technical solution corresponding to the present invention will be specifically described.

[0020] The functional block diagram of the weighting module is as Figure 1 shown. In the figure, X represents that each weighting sub-module actually uses X computing paths, and P represents that each weighting module outputs P-channel beam data. The first-level beam synthesis data stream is as Figure 3 shown. In the figure, C0W0 represents the 0th weight value of the 0th channel, D0C0 represents the data of the 0th channel of the 0th range gate, C0B0 represents the 0th beam generated after multiplying the data of the 0th channel by the weight, F0B0 represents the 0th beam generated after weighting the data of the 0th channel of the 0th input optical fiber, and B0 represents the 0th beam after the first-level digital beam synthesis.

[0021] Before the weight value and channel data are input, the external inputs parameters such as the number of channels 4, the number of beams 128, and the number of beams in a single computing path 16 through the control interface. According to these parameter values, it can be known that the data of 4 channels are each copied 8 times and are respectively input into 8 computing paths, and each computing path respectively performs the multiplication operation of the data of 16 beams of each range gate channel. After the parameters are recorded by the module, the external inputs the weight value data in the order of the channel and beam dimensions. These weight values are sequentially distributed into 32 computing paths and stored in the RAM. The specific storage situation is as follows: The weight values of the 0th to 15th beams corresponding to channel 0 are stored in the RAM addresses 0 to 15 of path 0, the weight values of the 16th to 31st beams are stored in the RAM addresses 0 to 15 of path 1,..., and the weight values of the 112th to 127th beams are stored in the RAM addresses 0 to 15 of path 7; The weight values of the 0th to 15th beams corresponding to channel 1 are stored in the RAM addresses 0 to 15 of path 8, the weight values of the 16th to 31st beams are stored in the RAM addresses 0 to 15 of path 8,..., and the weight values of the 112th to 127th beams are stored in the RAM addresses 0 to 15 of path 15; The weight values of the 0th to 15th beams corresponding to channel 2 are stored in the RAM addresses 0 to 15 of path 16, the weight values of the 16th to 31st beams are stored in the RAM addresses 0 to 15 of path 17,..., and the weight values of the 112th to 127th beams are stored in the RAM addresses 0 to 15 of path 23; The weight values of the 0th to 15th beams corresponding to channel 3 are stored in the RAM addresses 0 to 15 of path 24, the weight values of the 16th to 31st beams are stored in the RAM addresses 0 to 15 of path 25,..., and the weight values of the 112th to 127th beams are stored in the RAM addresses 0 to 15 of path 31.

[0022] After a set of weights is stored, multi-channel data is input externally in the order of the dimension of the range gate and the channel. They are copied and distributed to 32 weight-multiplying calculation paths. After all the channel data of the same range gate are copied and distributed, each calculation path reads the weights in the RAM simultaneously and multiplies them with the channel data input to each path to obtain the beam data responsible for each calculation. The specific situation of channel data copying and distribution is as follows: The data of channel 0 is copied and distributed to the 0th to 7th calculation paths; the data of channel 1 is copied and distributed to the 8th to 15th calculation paths; the data of channel 2 is copied and distributed to the 16th to 23rd calculation paths; the data of channel 3 is copied and distributed to the 24th to 31st calculation paths.

[0023] The channel data input by each optical fiber forms 32-way beam data after weight multiplication, and then through in-fiber beam synthesis, the same beams of different channels are added to form 8-way beam data output. Specifically, the 0th output outputs the 0th to 15th beams, the 1st output outputs the 16th to 31st beams, and so on, and the 7th output outputs the 112th to 127th beams.

[0024] The functional block diagram of the inter-fiber beam synthesis module is as Figure 2 shown. In the figure, P represents the 8-way beam data output by the corresponding weighting module of each optical fiber. After the operations of the corresponding weighting modules of 16 input optical fibers, a total of 16×8 = 128-way beam data converges to the inter-fiber beam synthesis module. Each way includes 16 beams. The latter forms 8-way beam data after multi-stage addition according to the principle of adding the same-way beams, and each way contains 16 beams.

[0025] Finally, 8-way beam data is output by 8 output optical fibers. Each way includes 16 beam data, which is the final output result of the first-level digital beam synthesis.

[0026] (2) Second-level digital beam synthesis technical solution Taking the 8 output optical fibers after the above first-level digital beam synthesis as a group, assuming there are 4 groups in total, that is, K = 4, N = 8 as an example, which is used as the input of the second-level digital beam synthesis circuit, the corresponding second-level digital beam synthesis technical solution of the present invention will be specifically described.

[0027] The data stream of the second-level digital beam synthesis is as Figure 4As shown in the figure, in the figure, W = {1, 0, 0, 0, 0, 0, 0, 0}' means that the weights of the 0th to 7th calculation paths of the multiplication weight sub-module are 1, 0, 0, 0, 0, 0, 0, 0 respectively; F0B0 represents the 0th beam input by the 0th optical fiber; {F0B0, 0, 0, 0, 0, 0, 0, 0}' represents the 8 data output in parallel by the 0th optical fiber weighting module, where the output of path 0 is equal to the input of the weighting module, and the outputs of the remaining paths are 0; B0(F0 + F8 + F16 + F24) represents the 0th beam data of the sum of the beam data input by the 0th optical fiber in each group.

[0028] In the secondary digital beam synthesis, external input beam data, but still set the parameter values according to the parameter setting method of the primary beam synthesis: the number of channels is 1, the number of beams is 8, and the number of beams in a single calculation path is 1. Before inputting the beam data (corresponding to the channel data input during the primary beam synthesis), pre-store the weights of the corresponding weighting modules of each optical fiber as follows: In each group of optical fibers, the weights of the first 8 calculation paths of the multiplication weight sub-module of the 0th optical fiber are (1, 0, 0, 0, 0, 0, 0, 0), the weights of the first 8 calculation paths of the multiplication weight sub-module of the 1st optical fiber are (0, 1, 0, 0, 0, 0, 0, 0),..., the weights of the first 8 calculation paths of the multiplication weight sub-module of the 7th optical fiber are (0, 0, 0, 0, 0, 0, 0, 1).

[0029] After the multiplication weight and in-fiber beam synthesis operations, the output results of the corresponding weighting modules of each group of optical fibers are as follows: For the 0th group of optical fibers: the 0th optical fiber weighting module outputs (the beam data of the 0th optical fiber in the 0th group, 0, 0, 0, 0, 0, 0, 0), the 1st optical fiber weighting module outputs (0, the beam data of the 1st optical fiber in the 0th group, 0, 0, 0, 0, 0, 0),..., the 7th optical fiber weighting module outputs (0, 0, 0, 0, 0, 0, 0, 0, the beam data of the 7th optical fiber in the 0th group); …… For the 3rd group of optical fibers: the 0th optical fiber weighting module outputs (the beam data of the 0th optical fiber in the 3rd group, 0, 0, 0, 0, 0, 0, 0), the 1st optical fiber weighting module outputs (0, the beam data of the 1st optical fiber in the 3rd group, 0, 0, 0, 0, 0, 0),..., the 7th optical fiber weighting module outputs (0, 0, 0, 0, 0, 0, 0, 0, the beam data of the 7th optical fiber in the 3rd group).

[0030] The inter-fiber beam synthesis module adds the outputs of the weighting modules of the above four groups of optical fibers to obtain the secondary digital beam synthesis result: (the sum of all the beam data of the 0th optical fiber in each group of optical fibers, the sum of all the beam data of the 1st optical fiber in each group of optical fibers,..., the sum of all the beam data of the 7th optical fiber in each group of optical fibers), realizing the secondary digital beam synthesis operation.

[0031] The present invention provides a multi-level digital beam synthesis compatible circuit system and method. By configuring different parameters and weights, it can be used as a first-level digital beam synthesis circuit to perform operations such as weighting, in-fiber beam synthesis, and inter-fiber beam synthesis on the multi-channel data input by each optical fiber in sequence, so as to achieve first-level digital beam synthesis and output beam data. It can also be used as a second-level digital beam synthesis circuit to group the optical fibers output from the first-level digital beam synthesis, and then perform secondary synthesis on the beam data transmitted by the optical fibers with the same serial number in each group of optical fibers, so as to achieve the operation of inter-fiber beam data grouped synthesis, and further achieve the cascading of digital beam chips.

[0032] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features. However, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A multi-stage digital beamforming compatible circuit system, characterized in that: It includes a weighting module and an inter-fiber beamforming module; The weighting module includes a weighting submodule and an intra-fiber beamforming submodule; The weight multiplication submodule includes a number of parallel calculation paths, and weight value data is pre-stored in each calculation path; In the first-level beam synthesis, the weight data is the coefficient of the channel data generating beam data; in the second-level beam synthesis, the weight data is the synthesis coefficient of the optical fibers with different serial numbers in each group of optical fibers; When the system is used as a first-level digital beam synthesis circuit, the multiplication submodule copies and distributes the channel data input by the optical fiber to different calculation paths, performs parallel multiplication operations, and then outputs the beam data in parallel; When the system is used as a secondary digital beamforming circuit, the weighted submodule copies and distributes the beam data to different calculation paths, performs parallel weighted multiplication operations, and then outputs the beam data in parallel; The intra-fiber beam synthesis submodule receives the multi-channel beam data output by the weighting submodule, and then performs hierarchical addition synthesis operation and outputs the data; The inter-fiber beam synthesis module receives the multi-channel beam data output by the multiple weighting modules, and performs addition synthesis operation on the multi-channel beam data according to the principle of adding the same sequence number.

2. The multi-stage digital beamforming compatible circuit system according to claim 1, characterized in that: Each computation path includes a complex multiplier and two ping-pong weight RAMs.

3. A multi-stage digital beamforming compatible method, characterized in that: The following steps are involved: Step 1: using a multi-stage digital beamforming compatible circuit system, the system comprising a weighting module and an inter-fiber beamforming module, the weighting module comprising a multiplication submodule and an intra-fiber beamforming submodule; Step 2: Divide the weighted submodule into several parallel computing paths. The system first configures parameters according to the functional and performance requirements. The parameters include the number of channels, the number of beams, and the number of beams of a single computing path. Step 3: Pre-store weight data in each calculation path; In the first-level beam synthesis, the weight data is the coefficient of the channel data to generate beam data; In the case of secondary beam synthesis, the weight data is the synthesis coefficient of the optical fibers with different serial numbers in each group of optical fibers; Step 4: When the system is used as a first-level digital beamforming circuit, the multiplication submodule copies and distributes the channel data input by the optical fiber to different calculation paths, performs parallel multiplication operations, and then outputs the beam data in parallel; When the system is used as a secondary digital beamforming circuit, the weighted submodule copies and distributes the beam data to different calculation paths, performs parallel weighted multiplication operations, and then outputs the beam data in parallel; Step 5: The intra-fiber beam synthesis submodule receives the multi-channel beam data output by the weighting submodule, and then performs hierarchical addition synthesis operation and outputs it; Step 6: The inter-fiber beam synthesis module receives the multi-channel beam data output by the multiple weighting modules, and performs addition synthesis operation on the multi-channel beam data according to the principle of adding the same sequence number, so as to realize multi-level digital beam synthesis.

4. The multi-stage digital beamforming compatible method according to claim 3, characterized in that: Each computation path in step 2 includes a complex multiplier and two ping-pong weight RAMs.

5. The multi-stage digital beamforming compatible method according to claim 3, characterized in that: In the first-level digital beamforming operation in step 4, the number of channels is set to C, the number of beams is set to B, and the number of beams of a single calculation path is set to S. The data of each channel is copied into P copies, P = B / S, and distributed to P calculation paths. Each calculation path stores S weights and is responsible for calculating S beams. The number of paths actually involved in the operation is X = C × P, and the outputs of the remaining paths are set to 0.

6. The multi-stage digital beamforming compatible method according to claim 3, characterized in that: In the secondary digital beam synthesis operation in step 4, it is assumed that there are K groups of input optical fibers, each group of input optical fibers has N optical fibers, and the beam data input through the optical fibers with the same sequence number in each group of optical fibers are synthesized, and finally multiple secondary digital beam synthesis results are output.

7. The multi-stage digital beamforming compatible method according to claim 6, characterized in that: In the secondary digital beamforming operation in step 4, the number of channels is set to 1, the number of beams is set to N, the number of beams of a single calculation path is set to 1, each calculation path stores 1 weight, a total of N calculation paths participate in the operation, and the outputs of the remaining calculation paths are set to 0; Among all groups of input optical fibers, the i-th calculation path weight of the i-th optical fiber is set to 1, where 0≤i≤N-1, and the remaining calculation path weights are set to 0. In this case, the multiplication submodule realizes the copying of the input channel data to the i-th channel of N outputs, and the remaining N-1 outputs are all 0.

8. The multi-stage digital beamforming compatible method according to claim 3 or 5, characterized in that: In the first-level digital beam synthesis operation in step 5, the number of channels is set to C, the number of beams is set to B, and the number of beams in a single calculation path is set to S. Then all beams generated by different channel data of a single optical fiber are synthesized into B beams and output in P calculation paths, P = B / S, and each calculation path outputs S beams.

9. The multi-stage digital beamforming compatible method according to claim 7, characterized in that: In the secondary digital beam synthesis operation in step 5, one effective beam is finally synthesized and output through the i-th path among N paths, and the rest are output as 0, where an effective beam means that the number of beams is the same as the number of beams input by a single optical fiber.

10. The multi-stage digital beamforming compatible method according to claims 5 and 6, characterized in that: In the first-level digital beamforming operation in step 6, B beams are finally synthesized and divided into P calculation paths for output, and each calculation path outputs S beams; In the secondary digital beam synthesis operation in step 6, it is assumed that there are K groups of input optical fibers, each group of input optical fibers has N optical fibers, and N beams are finally synthesized.

Images