Data acquisition system and method based on MLVDS communication interface

Abstract

The invention discloses a data acquisition system and method based on an MLVDS communication interface, and belongs to the technical field of MLVDS communication buses, the system comprises a sensor network, a control master node, an MLVDS transmission bus and a transmission slave node; the method comprises the following steps: collecting target information through a sensor of a transmission slave node; the collection control unit based on the FPGA preprocesses the collected data and controls the ADC to carry out data collection; the MLVDS communication module based on the FPGA communicates with the MLVDS interface chip, and the MLVDS interface chip transmits data to the control main node through an MLVDS bus; and the control master node controls and manages the plurality of functional slave nodes through the MLVDS bus, and is responsible for receiving and storing collected data output by each functional slave module. According to the data acquisition system and method based on the MLVDS communication interface, an efficient and stable acquisition process is ensured; the method is suitable for a high-bandwidth and high-precision data acquisition system, and can be widely applied to the fields of industrial control, medical equipment, automotive electronics and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of MLVDS communication buses, and in particular to a data acquisition system and method based on an MLVDS communication interface. Background Art

[0002] In the prior art, Chinese Patent CN201921524295.7 discloses a multi-node data transmission system based on MLVDS, and the technical problem it solves is the problem that the traditional data acquisition and processing system cannot effectively achieve the synchronization and real-time performance of data during the transmission and storage processes. Through the conversion function of the MLVDS-USB3.0 converter, the high-speed upload of the acquired data and the issuance of instructions between the control multi-node acquisition device and the host computer are realized. The converter can flexibly implement a variety of transmission protocols without changing the hardware system architecture, and has a simple hardware circuit, strong versatility, and stable transmission. However, the FPGA main control module is directly connected to the MLVDS communication module, resulting in the direct upload of data after the sensor signal acquisition is completed, and the preprocessing of the acquired data is insufficient. Summary of the Invention

[0003] The object of the present invention is to provide a data acquisition system and method based on an MLVDS communication interface, which can ensure an efficient and stable acquisition process; is applicable to high-bandwidth and high-precision data acquisition systems, and can be widely applied to fields such as industrial control, medical equipment, and automotive electronics.

[0004] To achieve the above object, the present invention provides a data acquisition system based on an MLVDS communication interface, including a sensor network, a control master node, an MLVDS transmission bus, and a transmission slave node; the control master node is composed of an FPGA, a memory, and an MLVDS interface circuit; the transmission slave node is composed of an FPGA, an MLVDS interface circuit, and an acquisition conditioning circuit.

[0005] Preferably, the acquisition conditioning circuit includes an amplification circuit, a filtering circuit, a shaping conditioning circuit, and an ADC acquisition circuit.

[0006] The present invention also provides a data acquisition method based on an MLVDS communication interface, including the following steps: S1. The host computer sends a data reading instruction and sends an address selection signal; S2. When each node receives that the bus address matches its own address, it starts the data acquisition operation; each node collects target data through the connected sensors, and performs noise removal processing on the collected data through a preprocessing circuit, and the preprocessing circuit includes an amplification circuit and a filtering circuit; S3. After the preprocessing is completed, the acquisition control unit based on FPGA controls the ADC acquisition circuit to sample the analog signal, and the ADC acquisition circuit converts the preprocessed analog signal into a digital signal; S4. FPGA encodes the digital signal collected by the ADC acquisition circuit into a differential signal based on the MLVDS standard and prepares to transmit the data through the MLVDS communication module; S5. The master controller transmits the differential signal through the MLVDS bus via the MLVDS communication interface. After the data transmission is completed, the bus enable is pulled high through the control signal to release the data transmission bus, thus completing the data acquisition process.

[0007] Preferably, the specific process of sending the address selection signal in S1 is as follows: S11. Wait for the master station address parameter: The slave node is in a waiting state, waiting for the master station to send a connection instruction through the bus; S12. Configure the address parameter: The master node reads the default address of the slave node. The default address of the node is unique in the entire network and is stored in the non-volatile memory; The master node maps the address information for the slave node in the address stack in the bus manager; S13. Receive the configuration parameter and execute the configuration: After the connection is established, enter the initialization phase; The master node, according to the configuration requirements of the host computer for each slave node, such as the number of data bytes, the number of input and output nodes, and the transmission speed; Then send the communication configuration parameter to the slave node and specify the working state of the slave node; During the initialization, the slave node will obtain the address information of the master node; S14. Data exchange with the host: After receiving the communication instruction, the slave node enters the data exchange state according to the MLVDS bus communication protocol and performs periodic data exchange with the master station.

[0008] Preferably, the specific process of preprocessing the acquired data in S2 is as follows: S21. Signal acquisition and amplification: Amplify the sensor signal through an operational amplifier and ensure that the signal amplitude is suitable for sampling by the ADC acquisition circuit, adapting to the input range of the ADC acquisition circuit; S22. Noise removal: Use a filter circuit to remove the high-frequency noise of the amplified data signal to ensure a pure signal; S23. Shaping and conditioning: Ensure that the signal meets the input requirements of the ADC acquisition circuit through amplitude limiting, removing DC drift, and adding a signal bias.

[0009] Preferably, the specific process of ROM table sampling in S3 is as follows: S31. After the system is powered on, first clear the counter; When receiving the data acquisition instruction, the counter selects the corresponding channel according to the content of the ROM table, and the ROM table address is incremented by 1 for each bit of data read; S32. After the counter collects data, pull down the level of the CVNST pin of the ADC chip to start the analog-to-digital conversion process; S33. During the data collection process, the BYTE pin will switch between high and low levels; when the BYTE pin is at a high level, collect the high eight-bit data; when the BYTE pin is at a low level, collect the low eight-bit data; S34. When the counter is full, pack and send the stored data in a predetermined frame format, and at the same time clear the counter to prepare for the next round of data collection.

[0010] Preferably, the specific implementation steps are as follows: Step 1: First, transfer the collected data into the master node through the MLVDS communication interface; Step 2: Control the MLVDS interface chip of the master node to be responsible for receiving the transmitted MLVDS signal and decoding it; Step 3: Store the decoded data in the data buffer, and store it in the SDRAM and FLASH memories through the DDR controller and the FLASH controller; Step 4: After receiving the data upload command, the host computer retrieves the data stored in the memory and uploads it to the upper computer through the RJ45 network interface; Step 5: After the data upload is completed, send an end transmission command to the slave node.

[0011] Preferably, during the data transmission in Step 1, if an error code appears at the receiving end, it will cause an exception when the upper computer software reads the data; when the upper computer discovers the error code, it sends an instruction to request retransmission of the data; if the receiving end detects that the received data does not match the data at the sending end, it sends a retransmission instruction to the sending end, requesting retransmission of the error packet.

[0012] Therefore, the present invention adopts the above-mentioned data acquisition system and method based on the MLVDS communication interface, which ensures an efficient and stable acquisition process; it is applicable to high-bandwidth and high-precision data acquisition systems and can be widely used in fields such as industrial control, medical equipment, and automotive electronics.

[0013] Next, through the drawings and embodiments, the technical solutions of the present invention will be further described in detail. Description of the Drawings

[0014] Figure 1 is a flowchart of an embodiment of a data acquisition system and method based on the MLVDS communication interface of the present invention; Figure 2 is a flowchart of the implementation of the transmission address selection signal in an embodiment of a data acquisition system and method based on the MLVDS communication interface of the present invention; Figure 3 It is the flowchart of the pre - processing of the collected data in an embodiment of a data acquisition system and method based on the MLVDS communication interface of the present invention; Figure 4 It is the schematic diagram of the system device in an embodiment of a data acquisition system and method based on the MLVDS communication interface of the present invention. Detailed implementation manners

[0015] The technical solution of the present invention will be further described below through the accompanying drawings and embodiments.

[0016] Unless otherwise defined, the technical terms or scientific terms used in the present invention should have the ordinary meanings understood by those of ordinary skill in the field to which the present invention belongs.

[0017] Embodiment 1 As Figure 1 shown, the present invention provides a data acquisition method based on the MLVDS communication interface, including the following steps; S1. The host computer sends a data reading instruction and an address selection signal; S2. When each node receives that the bus address matches its own address, it starts the data acquisition operation. The node collects the target data through the connected sensor, and performs noise removal processing on the collected data through a pre - processing circuit (including an amplification circuit and a filtering circuit); S3. After the pre - processing is completed, the acquisition control unit based on FPGA controls the ADC acquisition circuit to sample the analog signal, and the ADC acquisition circuit converts the pre - processed analog signal into a digital signal; S4. The FPGA encodes the digital signal collected by the ADC acquisition circuit into a differential signal based on the MLVDS standard, and prepares to transmit the data through the MLVDS communication module; S5. The master controller transmits the differential signal through the MLVDS bus through the MLVDS communication interface, and after the data transmission is completed, it raises the bus enable through the control signal to release the data transmission bus, thereby completing the data acquisition process.

[0018] The data acquisition method based on the MLVDS communication interface provided by the present invention is used to ensure signal synchronization and data integrity during the high - speed data transmission process, which helps to improve the accuracy and reliability of data acquisition. Specifically, it involves using the multi - channel parallel transmission technology and taking advantage of the high - bandwidth characteristic of the MLVDS interface to achieve high - speed and low - latency data acquisition, reduce data loss and interference, and improve the overall performance and stability of the system. As follows: First, the FPGA (Field Programmable Gate Array) controller is selected for its powerful hardware parallel processing ability. It can process multiple data streams simultaneously, making it particularly suitable for high-speed data acquisition and real-time processing. In the application of the MLVDS interface, the FPGA can receive and transmit data through multiple parallel channels, significantly improving the throughput and efficiency of data processing.

[0019] Secondly, the FPGA directly processes data through hardware without the need to schedule tasks through the operating system or software interrupts, thus achieving extremely low latency. By processing data with the FPGA, the system can respond to data changes within milliseconds, monitor sensor signals in real time, and ensure high real-time performance of data acquisition and processing.

[0020] Finally, compared with other controllers, the FPGA can provide high-precision timing control and data synchronization functions, which are particularly crucial for multi-channel data transmission in the MLVDS protocol. In the data acquisition scenario of high-speed transmission, the FPGA can efficiently synchronize the data acquisition signals of each sensor, ensuring the accuracy and consistency of data, and avoiding data disorder and loss.

[0021] After the data acquisition, first the host computer sends a data read instruction and selects the address signal. After each node receives the matching address signal, it starts data acquisition. The sensor collects the target data and removes noise through the preprocessing circuit. Then, the acquisition control unit based on the FPGA controls the ADC acquisition circuit to sample the analog signal and convert the collected analog signal into a digital signal. Next, the FPGA encodes the digital signal into a differential signal according to the MLVDS standard and prepares to transmit the data through the MLVDS communication module. Finally, the main controller transmits the data to the bus through the MLVDS interface and releases the data bus through the control signal to complete the data acquisition process.

[0022] The present invention selects the data acquisition method of the MLVDS communication interface bus by analyzing various data acquisition methods. MLVDS is a high-speed differential signal transmission standard that can provide high-bandwidth and high-rate data transmission. Compared with traditional serial communication interfaces, MLVDS supports high-speed data transmission of multiple parallel channels, can process multiple data streams simultaneously, and is suitable for complex multi-sensor systems. Compared with the single-channel transmission in traditional methods, the multi-channel parallel characteristic of MLVDS can collect data from multiple sensors at the same time and ensure high-precision synchronization between channels. This greatly improves the transmission rate of the data acquisition system and is especially suitable for application scenarios with high real-time requirements. The MLVDS communication interface can ensure stable and efficient data transmission in a short time, while traditional communication interfaces may cause delays or bottlenecks due to bandwidth limitations. And because MLVDS uses differential signal transmission, compared with single-ended signal transmission, it has stronger anti-interference ability against electromagnetic interference and is suitable for operating in complex electromagnetic environments.

[0023] The MLVDS communication interface protocol includes a data transmission protocol and control signals. These control signals can include data valid signals, bus enable signals, address selection signals, etc., and are used to control the timing during the data transmission process and the interaction between nodes.

[0024] The present invention uses the MLVDS communication interface to send address selection signals. First, the slave node is in a waiting state, waiting for the master node to send a "connection" instruction and read the default address to complete the configuration. Subsequently, the master node sends communication parameters to the slave node according to the configuration requirements of the host computer and specifies the working state. The slave node enters the initialization stage and obtains the master node address. Finally, after receiving the instruction, the slave node performs periodic data exchange with the master node according to the MLVDS bus protocol. As Figure 2 shown, the specific process of sending the address selection signal is as follows: S11. Wait for the master station address parameter: The slave node is in a waiting state, waiting for the master station to send a "connection" instruction through the bus; S12. Configure the address parameter: The master node reads the default address of the slave node. This address is unique in the entire network and is stored in a non-volatile memory (such as EPROM). The master node maps the address information for the slave node in the address stack of the bus manager; S13. Receive the configuration parameter and execute the configuration: After the connection is established, enter the initialization stage. The master node sends the necessary communication configuration parameters to the slave node according to the configuration requirements of the host computer for each slave node (such as the number of data bytes, the number of input / output nodes, the transmission speed, etc.) and specifies the working state of the slave node. During initialization, the slave node will obtain the address information of the master node for subsequent data management; S14. Data Exchange with the Host: After receiving the communication instruction, the slave node enters the data exchange state according to the MLVDS bus communication protocol and performs periodic data exchange with the master station.

[0025] The data preprocessing circuit receives the sensor signal through the input signal acquisition module. Subsequently, the amplification circuit adjusts the gain of the signal to make it reach the level range suitable for sampling by the ADC acquisition circuit. Next, the filtering and noise removal circuit removes the high-frequency and low-frequency noises in the signal to improve the signal quality. The filtered signal is subjected to amplitude limiting, DC drift removal, and level matching through the signal shaping and conditioning circuit to ensure that the signal meets the input requirements of the ADC acquisition circuit. The entire preprocessing process ensures the quality and stability of the acquired signal, thereby improving the accuracy and reliability of data acquisition.

[0026] During the preprocessing of data acquisition, various technical problems may be encountered, such as noise interference, signal amplitude mismatch, DC drift, timing issues, and nonlinear distortion. The present invention can effectively solve these problems by designing filtering, amplification, and conditioning circuits, adopting appropriate noise removal and timing control techniques, and reasonably selecting sensors and ADCs, ensuring the stability, accuracy, and efficiency of the system. As Figure 3 shown, the specific process of preprocessing the acquired data is as follows: S21. Signal Acquisition and Amplification: The sensor signal is amplified by an operational amplifier to ensure that the signal amplitude is suitable for sampling by the ADC acquisition circuit and adapts to the input range of the ADC acquisition circuit; S22. Noise Removal: A filtering circuit is used to remove the high-frequency noise of the amplified data signal to ensure that the signal is pure, facilitating subsequent data acquisition by the ADC acquisition circuit; S23. Shaping and Conditioning: Through amplitude limiting, DC drift removal, and signal biasing, ensure that the signal meets the input requirements of the ADC acquisition circuit.

[0027] To meet the requirement of cyclic acquisition of multi-channel signals with different frequencies in the design, the present invention adopts a data acquisition method based on the ROM table lookup method to achieve rapid switching between acquisition channels, thereby completing the efficient cyclic acquisition of sensor data. Specifically, in the design, an IP core inside the FPGA is used to generate a ROM table, which stores the switch selection signals for controlling the analog signal switching and the analog switch chip selection signals. During the data acquisition process, when data needs to be read, the system first reads the channel information in the ROM table to determine the source of the signal to be acquired currently. Once the acquisition channel needs to be switched, the system only needs to read the information of the corresponding channel in the ROM table to achieve rapid switching and continue to acquire data from the next channel. By cyclically reading the channel information in the ROM table, the present invention can efficiently and accurately complete the acquisition of signals from different channels without causing timing chaos, ensuring the stability and reliability of the acquisition process. Therefore, adopting the ROM table lookup method as the control logic design for data acquisition not only improves the working efficiency of the system but also ensures the orderly and synchronous acquisition of signals from each channel. The specific process of ROM table sampling is as follows: S31. After the system is powered on, the counter is first cleared. When a data acquisition instruction is received, the counter selects the corresponding channel according to the content of the ROM table, and the ROM table address is incremented by 1 for each bit of data read; S32. When the counter has acquired enough data, the level of the CVNST pin of the ADC chip is pulled low to start the analog-to-digital conversion process; S33. During the data acquisition process, the BYTE pin will switch between high and low levels. When the level of the BYTE pin is high, the high eight bits of data are acquired; when the level of the BYTE pin is low, the low eight bits of data are acquired; S34. When the counter reaches its maximum value, the stored data is packed and sent in a predetermined frame format, and at the same time, the counter is cleared to prepare for the next round of data acquisition.

[0028] A data acquisition method based on the MLVDS communication interface according to the present invention has the following specific implementation process: (1) First, the acquired data is transmitted into the main node through the MLVDS communication interface; (2) The MLVDS interface chip of the main node is controlled to receive the transmitted MLVDS signal and decode it; (3) The decoded data is stored in the data buffer and stored in the SDRAM and FLASH memories through the DDR controller and the FLASH controller; (4) After receiving the data upload command, the host retrieves the data stored in the memory and uploads it to the upper computer through the RJ45 network interface; (5) After the data upload is completed, an end transmission command is sent to the slave node; As Figure 4 shown, a data acquisition system based on the MLVDS communication interface generally consists of a sensor network, a control master node, an MLVDS transmission bus, and transmission slave nodes; the control master node consists of an FPGA, a memory, and an MLVDS interface circuit; the transmission slave nodes consist of an FPGA, an MLVDS interface circuit, and an acquisition conditioning circuit, and the acquisition conditioning circuit includes an amplification circuit, a filtering circuit, a shaping conditioning circuit, and an ADC acquisition circuit.

[0029] Therefore, the present invention adopts the above-mentioned data acquisition system and method based on the MLVDS communication interface, integrating knowledge in multiple fields such as MLVDS communication bus technology, data acquisition and processing technology, and communication interface technology. During the data acquisition process, it ensures the accuracy of the acquired data, thereby reducing the error rate of the data received by the host computer; it not only helps the MLVDS communication interface maintain an efficient and stable acquisition process, but also is applicable to high-bandwidth and high-precision data acquisition systems, and can be widely applied in fields such as industrial control, medical equipment, and automotive electronics.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that they can still modify or equivalently replace the technical solutions of the present invention, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A data acquisition system based on MLVDS communication interface, characterized in that: It includes a sensor network, a control master node, an MLVDS transmission bus and a transmission slave node; the control master node is composed of an FPGA, a memory, and an MLVDS interface circuit; the transmission slave node is composed of an FPGA, an MLVDS interface circuit and an acquisition and conditioning circuit.

2. The data acquisition system based on the MLVDS communication interface according to claim 1, characterized in that: The acquisition and conditioning circuit includes an amplification circuit, a filtering circuit, a shaping and conditioning circuit, and an ADC acquisition circuit.

3. A data acquisition method based on the MLVDS communication interface according to any one of claims 1-2, characterized in that: The following steps are involved: S1, the host computer sends a data read instruction and sends an address selection signal; S2, when each node receives a bus address that matches its own address, it starts the data collection operation; each node collects target data through the connected sensor, and removes noise from the collected data through a preprocessing circuit, which includes an amplification circuit and a filtering circuit; S3, after the preprocessing is completed, the FPGA-based acquisition control unit controls the ADC acquisition circuit to sample the analog signal, and the ADC acquisition circuit converts the preprocessed analog signal into a digital signal; S4, FPGA encodes the digital signal collected by the ADC acquisition circuit into a differential signal based on the MLVDS standard, and prepares for data transmission through the MLVDS communication module; S5. The main controller transmits the differential signal through the MLVDS bus via the MLVDS communication interface, and after the data transmission is completed, the bus enable is pulled high by the control signal to release the data transmission bus, thereby completing the data acquisition process.

4. The data acquisition method of the data acquisition system based on the MLVDS communication interface according to claim 3 is characterized in that: The specific process of sending the address selection signal in S1 is as follows: S11, waiting for the master station address parameter: the slave node is in a waiting state, waiting for the master station to send a connection instruction through the bus; S12, configure address parameters: the master node reads the default address of the slave node, the default address of the node is unique in the entire network and is stored in a non-volatile memory; the master node maps the address information for the slave node in the address stack in the bus manager; S13, receiving configuration parameters and executing configuration: After the connection is established, the initialization phase begins; the master node sends communication configuration parameters to the slave node and specifies the working state of the slave node according to the configuration requirements of the host computer for each slave node, such as the number of data bytes, the number of input and output nodes, and the transmission speed; during the initialization period, the slave node will obtain the address information of the master node; S14, data exchange with the host: After receiving the communication instruction, the slave node enters the data exchange state according to the MLVDS bus communication protocol and performs periodic data exchange with the master station.

5. The data acquisition method of the data acquisition system based on the MLVDS communication interface according to claim 3, characterized in that: The specific process of preprocessing the collected data in S2 is as follows: S21, signal acquisition and amplification: amplify the sensor signal through the operational amplifier, and ensure that the signal amplitude is suitable for sampling by the ADC acquisition circuit and adapts to the input range of the ADC acquisition circuit; S22, noise removal: use filtering circuit to remove high-frequency noise of the amplified data signal to ensure signal purity; S23, Shaping and Conditioning: Ensure that the signal meets the input requirements of the ADC acquisition circuit by limiting, removing DC drift and adding bias to the signal.

6. The data acquisition method of the data acquisition system based on the MLVDS communication interface according to claim 3, characterized in that: The specific process of ROM table sampling in S3 is as follows: S31, after the system is powered on, the counter is first cleared; when receiving the data acquisition instruction, the counter selects the corresponding channel according to the content of the ROM table, and the ROM table address is incremented by 1 every time a bit of data is read; S32, when the counter collects data, the CVNST pin level of the ADC chip is pulled low to start the analog-to-digital conversion process; S33, during data acquisition, the BYTE pin switches between high and low levels; When the BYTE pin level is high, the upper eight bits of data are collected; when the BYTE pin level is low, the lower eight bits of data are collected; S34. When the counter is full, the stored data is packaged and sent according to a predetermined frame format, and the counter is cleared to prepare for the next round of data collection.

7. The data acquisition method of the data acquisition system based on the MLVDS communication interface according to claim 3, characterized in that: The specific implementation steps are as follows: Step 1: First, the collected data is transferred to the master node through the MLVDS communication interface; Step 2: The MLVDS interface chip of the control master node is responsible for receiving the transmitted MLVDS signal and decoding it; Step 3: Store the decoded data into the data buffer, and then store it into the SDRAM and FLASH memories through the DDR controller and the FLASH controller; Step 4: After receiving the data upload command, the host takes out the data stored in the memory and uploads it to the host computer through the RJ45 network port; Step 5: After the data upload is completed, send an end transmission command to the slave node.

8. The data acquisition method of the data acquisition system based on the MLVDS communication interface according to claim 7, characterized in that: During the data transmission process in step 1, if a bit error occurs at the receiving end, the host computer software will be abnormal when reading data; When the host computer finds a bit error, it sends a command to request retransmission of the data; if the receiving end detects that the received data does not match the data of the sending end, it sends a retransmission command to the sending end, requesting the retransmission of the erroneous data packet.

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