Semiconductor device with channel structure

Abstract

A semiconductor device having a channel structure is provided. The semiconductor device may include: a bit line extending in a first horizontal direction; a molded structure on the bit line; a channel structure including a horizontal portion in contact with an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode on the channel structure; and a bond pad structure on the vertical channel portion and electrically connected to the channel structure. The vertical channel portion may be in contact with a side surface of the molded structure. At least a portion of the vertical channel portion may overlap the molded structure in a second horizontal direction. The second horizontal direction may intersect the first horizontal direction.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0167066 filed on November 27, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device having a channel structure. Background Art

[0003] As the demand for high performance, high speed and / or multifunctionality of semiconductor devices increases, the integration of semiconductor devices is increasing. When finely patterned semiconductor devices are manufactured in response to the trend of high integration of semiconductor devices, it is necessary to realize patterns with fine widths or fine intervals. Summary of the invention

[0004] Example embodiments provide a semiconductor device including a channel structure contacting a protrusion or a recess of a molding structure.

[0005] According to example embodiments, a semiconductor device may include: a bit line extending in a first horizontal direction; a mold structure on the bit line; a channel structure including a horizontal portion in contact with an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode on the channel structure; and a bonding pad structure on the vertical channel portion and electrically connected to the channel structure. The vertical channel portion may contact a side surface of the mold structure. At least a portion of the vertical channel portion may overlap the mold structure in a second horizontal direction. The second horizontal direction may intersect the first horizontal direction.

[0006] According to example embodiments, a semiconductor device may include: a bit line extending in a first horizontal direction; a mold structure on the bit line and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; a channel structure including a horizontal portion contacting an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode on the channel structure; and a bonding pad structure on the vertical channel portion and electrically connected to the channel structure. The mold structure may include a first portion and a second portion alternately arranged in the second horizontal direction. A lower surface of the first portion of the mold structure may have a first horizontal width in the first horizontal direction. A lower surface of the second portion of the mold structure may have a second horizontal width in the first horizontal direction. The second width may be different from the first horizontal width. The vertical channel portions may be spaced apart from each other in the second horizontal direction. The vertical channel portion may contact a side surface of the mold structure.

[0007] According to example embodiments, a semiconductor device may include: a lower structure including a circuit element; a bit line on the lower structure and extending in a first horizontal direction; a mold structure on the bit line and extending in a second horizontal direction intersecting the first horizontal direction; a channel structure including a horizontal portion contacting an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode on the channel structure; a dielectric structure extending between the channel structure and the gate electrode in a second horizontal direction; an upper insulating structure spaced apart from the mold structure and covering the gate electrode and the bit line; an upper covering layer covering the mold structure and the upper insulating structure; a bonding pad structure penetrating the upper covering layer and electrically connected to the channel structure; and an information storage structure on the bonding pad structure. The vertical channel portion may contact a side surface of the mold structure. At least a portion of the vertical channel portion may overlap the mold structure in the second horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1A is a plan view of a semiconductor device according to example embodiments.

[0010] Figure 1B It is along Figure 1A 0 is a vertical cross-sectional view taken along line II′ of the semiconductor device shown in FIG.

[0011] Figure 1C It is along Figure 1A 1 is a vertical cross-sectional view taken along line II-II′ of the semiconductor device shown in FIG.

[0012] Figure 1D It is along Figure 1A 1 is a vertical cross-sectional view taken along line III-III′ of the semiconductor device shown in FIG.

[0013] Figure 2 yes Figure 1A An enlarged view of a portion of a semiconductor device is shown in FIG.

[0014] Figures 3 to 5 is a plan view of a semiconductor device according to example embodiments.

[0015] Figure 6 is a plan view of a semiconductor device according to example embodiments.

[0016] Figure 7 yes Figure 6 An enlarged view of a portion of a semiconductor device is shown in FIG.

[0017] Figures 8 to 10 is a plan view of a semiconductor device according to example embodiments.

[0018] FIG. 11A to FIG. 15D 1 is a plan view and a vertical cross-sectional view shown according to a process sequence, illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0020] Figure 1A is a plan view of a semiconductor device according to example embodiments. Figure 1B It is along Figure 1A 0 is a vertical cross-sectional view taken along line II′ of the semiconductor device shown in FIG. Figure 1C It is along Figure 1A 1 is a vertical cross-sectional view taken along line II-II′ of the semiconductor device shown in FIG. Figure 1D It is along Figure 1A 1 is a vertical cross-sectional view taken along line III-III′ of the semiconductor device shown in FIG.

[0021] Reference Figures 1A to 1D , the semiconductor device 100 according to example embodiments may include a lower structure LS, a bit line 50, an upper structure US, and an information storage structure 87. The lower structure LS may include a substrate 3, a circuit element TR, a peripheral plug 20, a peripheral interconnection 23, a first peripheral insulating layer 30, and a second peripheral insulating layer 32.

[0022] The substrate 3 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 3 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0023] The circuit element TR may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit. The circuit element TR may include a peripheral transistor. For example, the peripheral transistor may include a gate structure 12 disposed on a peripheral active region 9a defined by an isolation region 9b in the substrate 3, and a peripheral source / drain region 15 disposed in the peripheral active region 9a on both sides of the gate structure 12.

[0024] The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers (eg, a first conductive layer 12b1 and a second conductive layer 12b2 on the first conductive layer 12b1).

[0025] The peripheral plug 20 is connected to the peripheral source / drain region 15 and may extend vertically, and the peripheral interconnect 23 may be disposed on the peripheral plug 20. The peripheral interconnect 23 may be electrically connected to the circuit element TR through the peripheral plug 20. The first peripheral insulating layer 30 may surround the side surface of the peripheral gate electrode 12b and the side surface of the peripheral plug 20. The second peripheral insulating layer 32 may be disposed on the first peripheral insulating layer 30, and may surround the peripheral plug 20 and the peripheral interconnect 23. The upper surface of the second peripheral insulating layer 32 may be coplanar with the upper surface of the peripheral interconnect 23.

[0026] In an example embodiment, the peripheral plug 20 and the peripheral interconnect 23 may include a metal layer and a barrier layer covering the side surface and the lower surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer may include a metal material such as W or Mo. The first peripheral insulating layer 30 and the second peripheral insulating layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than a predetermined value, or a combination thereof.

[0027] The semiconductor device 100 may further include an etch stop layer 40 disposed on the lower structure LS. The etch stop layer 40 may cover the peripheral interconnection 23 and the second peripheral insulating layer 32. The etch stop layer 40 may include SiBN, SiCN, SiN, or a combination thereof.

[0028] The bit line 50 may be disposed on the lower structure LS. The bit line 50 may extend in the X direction and may be spaced apart from each other in the Y direction. The semiconductor device 100 may further include a bit line plug 53 disposed under the bit line 50, and a bit line insulating layer 56 surrounding the bit line 50 and the bit line plug 53. The bit line 50 may be electrically connected to the lower structure LS through the bit line plug 53.

[0029] The bit line 50 may include a metal layer, and a barrier layer covering the side surface and the lower surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer may include a metal material such as W or Mo. The bit line plug 53 may include the same material as that of the peripheral plug 20 and the peripheral interconnect 23. The bit line insulating layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than a predetermined value, or a combination thereof.

[0030] The semiconductor device 100 may further include shielding patterns 60 extending in the X direction and spaced apart from each other in the Y direction. The shielding patterns 60 may be alternately arranged with the bit lines 50 in the Y direction. The lower surface of the shielding pattern 60 may be located at a level lower than that of the lower surface of the bit line 50, and the upper surface of the shielding pattern 60 may be located at a level lower than that of the upper surface of the bit line 50. The shielding pattern 60 may reduce the capacitance between the bit lines 50.

[0031] The shielding pattern 60 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0032] The upper structure US may be disposed on the bit line 50. The upper structure US may include a mold structure MS, a channel structure 73, a gate electrode 79, an upper insulating structure 81, an upper capping layer 82, and a bonding pad structure 83.

[0033] The mold structure MS may be disposed on the bit line 50. In a plan view, the mold structures MS may extend in the Y direction and may be spaced apart from each other in the X direction. The mold structure MS may include a lower mold layer M2 and an upper mold layer M1. The upper mold layer M1 may be disposed on the lower mold layer M2, and the lower mold layer M2 and the upper mold layer M1 may extend in the Y direction.

[0034] In one example embodiment, the mold structure MS may further include a protrusion M3. The protrusion M3 may protrude from both sides (e.g., the side surfaces of both sides) of the mold structure MS in the X direction. For example, the protrusions M3 may be spaced apart from each other in the X direction and the Y direction, and may be provided with a lower mold layer M2 and an upper mold layer M1 interposed therebetween. In one example embodiment, the mold structure MS may include a first portion P1 and a second portion P2 disposed adjacent to the first portion P1 in the Y direction. The first portion P1 and the second portion P2 may be alternately disposed in the Y direction. For example, a portion of the mold structure MS that does not include the protrusion M3 may be referred to as the first portion P1, and a portion of the mold structure MS that includes the protrusion M3 may be referred to as the second portion P2. The first portion P1 may have a first width W1 in the X direction, and the second portion P2 may have a second width W2 greater than the first width W1. In this case, the first width W1 and the second width W2 may represent the horizontal width of the lower surface of the mold structure MS.

[0035] The lower mold layer M2 and the upper mold layer M1 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an example embodiment, the lower mold layer M2 and the upper mold layer M1 may include different materials. For example, the lower mold layer M2 may include silicon oxide, and the upper mold layer M1 may include silicon nitride. The protrusion M3 may include the same material as the lower mold layer M2 and the upper mold layer M1, and may be continuous in material. For example, the lower portion of the protrusion M3 may extend from one side of the lower mold layer M2 in the X direction, and may include the same material as the lower mold layer M2. The upper portion of the protrusion M3 may extend from one side of the upper mold layer M1 in the X direction, and may include the same material as the upper mold layer M1.

[0036] The channel structure 73 may be disposed on the bit line 50. The channel structure 73 may include a horizontal portion 73L contacting and electrically connected to the bit line 50, and a vertical channel portion 73S extending upward in the X direction from one end of the horizontal portion 73L. The lower surface of the horizontal portion 73L may contact the bit line 50, and the horizontal portion 73L may be electrically connected to the bit line 50. In an example embodiment, the vertical channel portion 73S may extend in a direction inclined to the vertical direction (Z direction), but is not limited thereto. The channel structures 73 may be spaced apart from each other in the X direction and the Y direction.

[0037] Figure 2 yes Figure 1A An enlarged view of a portion A of a semiconductor device is shown in FIG.

[0038] Further references Figure 2 , the channel structure 73 may contact the protrusion M3. The channel structure 73 may contact the side surface of the second portion P2 of the mold structure MS, and may partially contact the side surface of the first portion P1. For example, the vertical channel portion 73S of the channel structure 73 may surround the outer side surface of the protrusion M3. For example, a portion of the vertical channel portion 73S of the channel structure 73 may overlap the protrusion M3 in the Y direction. In an example embodiment, the distance between the vertical channel portions 73S adjacent in the Y direction may be smaller than the distance between the second portions P2 of the mold structure MS adjacent in the Y direction.

[0039] The vertical channel portion 73S of the channel structure 73 may include an extension portion 73a, a first curved portion 73b, and a second curved portion 73c. ​​In an example embodiment, the vertical channel portion 73S of the channel structure 73 may be curved. The extension portion 73a may extend in the Y direction, and the first curved portion 73b and the second curved portion 73c may extend from the extension portion 73a (for example, may be provided at both ends of the extension portion 73a and may extend from both ends of the extension portion 73a), and may extend in a direction intersecting the Y direction. In an example embodiment, the first curved portion 73b and the second curved portion 73c may extend in the X direction and overlap with the protrusion M3 in the Y direction.

[0040] The vertical channel portion 73S may include a first side surface S1 perpendicular to the X direction, and a second side surface S2 and a third side surface S3 disposed on both sides (e.g., both ends) of the first side surface S1. The first side surface S1, the second side surface S2, and the third side surface S3 may contact a side surface of the mold structure MS (e.g., the protrusion M3 of the mold structure MS). The second side surface S2 and the third side surface S3 may face each other and intersect the first side surface S1 at an angle. Figure 2 , the angle between the first side surface S1 and the second side surface S2 and the angle between the first side surface S1 and the third side surface S3 are shown as 90 degrees, but are not limited thereto. According to example embodiments, the shape of the protrusion M3 and the shape of the vertical channel portion 73S may vary. In some embodiments, the protrusion M3 and the vertical channel portion 73S may have rounded side surfaces.

[0041] exist Figure 1B , the channel structures 73 are shown to be spaced apart from each other in the X direction between the mold structures MS, but example embodiments are not limited thereto. In some embodiments, the horizontal portions 73L of the channel structures 73 adjacent and facing each other in the X direction may extend in the horizontal direction and be integrally formed.

[0042] The channel structure 73 may be formed of a semiconductor material such as silicon. The channel structure 73 may be formed of single crystal silicon or polycrystalline silicon. However, the channel structure 73 is not limited to semiconductor materials such as silicon, and may be formed of other semiconductor materials that may be used as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer or a two-dimensional material layer that may be used as a channel region of a transistor.

[0043] The oxide semiconductor layer may be indium gallium zinc oxide (IGZO). However, example embodiments are not limited thereto. For example, the oxide semiconductor layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), oxide At least one of indium gallium zinc (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), indium tin zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and indium gallium silicon oxide (InGaSiO).

[0044] The two-dimensional material layer may include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, and a hexagonal boron nitride (Hbn) material layer that may have semiconductor properties. For example, the two-dimensional material layer may include at least one of BiOSe, Crl, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials that can form two-dimensional materials.

[0045] When viewed in a plan view, the gate electrode 79 may intersect the bit line 50. For example, the gate electrodes 79 may extend in the Y direction on the side surface of the mold structure MS and may be spaced apart from each other in the X direction. The gate electrode 79 may be disposed on the channel structure 73. For example, the gate electrode 79 may overlap the horizontal portion 73L of the channel structure 73 in the vertical direction. The upper end of the gate electrode 79 may be located at a level lower than that of the upper surface of the mold structure MS. At least one of the gate electrodes 79 may be a cell gate electrode or a word line.

[0046] The upper structure US may further include a dielectric structure 76 between the gate electrode 79 and the channel structure 73 (e.g., extending between the gate electrode 79 and the channel structure 73 in the Y direction). The dielectric structure 76 may be disposed between the gate electrode 79 and the vertical channel portion 73S, and between the gate electrode 79 and the horizontal portion 73L. In an example embodiment, a portion of the dielectric structure 76 may cover the upper surface of the upper mold layer M1, but is not limited thereto.

[0047] In one example, each dielectric structure 76 may be a tunnel dielectric layer that does not include an information storage layer. For example, each dielectric structure 76 may include at least one of silicon oxide and a high-k dielectric material. The high-k dielectric material may include a metal oxide or a metal oxynitride. For example, the high-k dielectric material may be composed of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 Each dielectric structure 76 may be formed of a single layer or multiple layers of the materials described above.

[0048] In another example, each dielectric structure 76 may include an information storage layer and a dielectric layer. For example, each dielectric structure 76 may have a polarization characteristic depending on an electric field, and may include a ferroelectric layer having a residual polarization due to a dipole even in the absence of an external electric field. The polarization state within the ferroelectric layer may be used to record data. Therefore, each dielectric structure 76 may include a ferroelectric layer, which may be referred to as an information storage layer. The ferroelectric layer that may serve as an information storage layer may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may be a ferroelectric material based on HfO, the Zr-based compound may include a ferroelectric material based on ZrO, and the Hf-Zr-based compound may include a ferroelectric material based on hafnium zirconium oxide (HZO). The ferroelectric layer that may serve as an information storage layer may include a ferroelectric material doped with impurities such as at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr. For example, the ferroelectric layer that may serve as an information storage layer may be a ferroelectric layer in which HfO 2 、ZrO 2 A material in which at least one of HZrO and ZrO is doped with at least one of impurities C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr.

[0049] In the dielectric structure 76, the information storage layer is not limited to the above-mentioned material types, and may include a material capable of storing information.

[0050] The upper insulating structure 81 may be disposed between the mold structures MS and may cover the gate electrode 79. In an example embodiment, the upper insulating structure 81 may (e.g., partially) cover the bit line 50. The upper insulating structures 81 may extend in the Y direction and may be spaced apart from each other in the X direction. In an example embodiment, the upper insulating structure 81 may be spaced apart from the mold structures MS. In an example embodiment, the upper insulating structure 81 may be alternately arranged with the mold structures MS in the X direction.

[0051] The upper insulating structure 81 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than a predetermined value, or a combination thereof. The upper insulating structure 81 may be composed of a single layer or a plurality of layers.

[0052] The upper cover layer 82 may cover the mold structure MS and the upper insulating structure 81 and may extend in a horizontal direction. The upper cover layer 82 may contact an upper surface of the mold structure MS and an upper surface of the upper insulating structure 81. The upper cover layer 82 may include silicon nitride.

[0053] The bonding pad structure 83 may be disposed on the channel structure 73, and may penetrate the upper cover layer 82 and contact the vertical channel portion 73S of the channel structure 73. For example, a portion of the bonding pad structure 83 may extend below the upper cover layer 82 and contact the vertical channel portion 73S of the channel structure 73. The lower end of the bonding pad structure 83 may be located at a level lower than that of the upper surface of the mold structure MS. The bonding pad structure 83 may be electrically connected to the bit line 50 through the channel structure 73.

[0054] The bonding pad structure 83 may include a metal nitride, a metal, or a combination thereof. The metal nitride may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal may include a metallic material such as W or Mo.

[0055] The upper structure US may further include an insulating pattern 86 disposed on the upper cover layer 82 and disposed between the bonding pad structures 83. The insulating pattern 86 may cover the side surfaces of the bonding pad structures 83 and electrically insulate the bonding pad structures 83 from each other. The insulating pattern 86 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than a predetermined value, or a combination thereof. For example, the insulating pattern 86 may include silicon oxide.

[0056] The information storage structure 87 may be disposed on the upper structure US. The information storage structure 87 may include a first electrode 88a electrically connected to and in contact with the bonding pad structure 83, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0057] In one example, the information storage structure 87 may be a capacitor storing information in a DRAM. For example, the dielectric layer 88b of the information storage structure 87 may be a capacitor dielectric layer of a DRAM, and the dielectric layer 88b may include a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0058] In another example, the information storage structure 87 may be a structure storing information of a memory other than a DRAM. For example, the information storage structure 87 may be a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer 88b may be a ferroelectric layer capable of recording data using a polarization state. In another example, the dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. In this case, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material.

[0059] In one example embodiment, if the dielectric structure 76 includes an information storage layer, the information storage structure 87 may be omitted.

[0060] Figures 3 to 5 is a plan view of a semiconductor device according to example embodiments.

[0061] Reference Figure 3 , the semiconductor device 100a may include a vertical channel portion 73S of the channel structure 73 disposed on one side (e.g., side surface) of the mold structure MS and contacting the protrusion M3. In an example embodiment, the vertical channel portion 73S of the channel structure 73 may include an end extending in the Y direction on one side (e.g., along the side surface of the mold structure MS) of the mold structure MS. For example, the vertical channel portion 73S of the channel structure 73 may include an extension portion 73a, a first bent portion 73b, a second bent portion 73c, a first end portion 73d, and a second end portion 73e. The first end portion 73d and the second end portion 73e may extend in the Y direction from one end of the first bent portion 73b and the second bent portion 73c, respectively. The first end portion 73d and the second end portion 73e may contact the first portion P1 of the mold structure MS, and may overlap the protrusion M3 as a part of the second portion P2 in the Y direction.

[0062] Reference Figure 4 , the semiconductor device 100b may include a vertical channel portion 73S of the channel structure 73 disposed on one side of the mold structure MS and contacting the protrusion M3. In an example embodiment, the protrusion M3 may have a tapered shape in which the horizontal width of the protrusion M3 in the Y direction decreases as the distance from the central axis of the mold structure MS extending in the Y direction increases. For example, in a plan view, the protrusion M3 may have a trapezoidal shape. The vertical channel portion 73S of the channel structure 73 may include an extension portion 73a, a first bent portion 73b, and a second bent portion 73c, and the first bent portion 73b and the second bent portion 73c may extend in a direction between the X direction and the Y direction.

[0063] Reference Figure 5, the semiconductor device 100c may include a vertical channel portion 73S of the channel structure 73 disposed on one side of the mold structure MS and in contact with the protrusion M3. In an example embodiment, the vertical channel portion 73S of the channel structure 73 may include an end portion extending in the Y direction on one side of the mold structure MS. In addition, in an example embodiment, the protrusion M3 may have a tapered shape in which the horizontal width of the protrusion M3 in the Y direction decreases as the distance from the central axis of the mold structure MS extending in the Y direction increases. For example, the vertical channel portion 73S of the channel structure 73 may include a first end portion 73d and a second end portion 73e extending in the Y direction from one end of the first curved portion 73b and the second curved portion 73c, respectively.

[0064] Figure 6 is a plan view of a semiconductor device according to example embodiments. Figure 7 yes Figure 6 An enlarged view of a portion B of the semiconductor device shown in FIG.

[0065] Reference Figure 6 and Figure 7 , the mold structure MS of the semiconductor device 100d may include a recess M4 on the side surface. The recess M4 may be provided on both sides of the mold structure MS, and both sides of the mold structure MS may be recessed in the X direction. For example, the recesses M4 may be spaced apart from each other in the X direction and the Y direction, and may be provided with a lower mold layer M2 and an upper mold layer M1 between the recesses M4. In an example embodiment, the mold structure MS may include a first portion P1 and a second portion P2 disposed adjacent to the first portion P1 in the Y direction. The first portion P1 and the second portion P2 may be alternately disposed in the Y direction. For example, a portion of the mold structure MS that does not include the recess M4 may be referred to as the first portion P1, and a portion of the mold structure MS that includes the recess M4 may be referred to as the second portion P2. A width W3 of the first portion P1 in the X direction may be greater than a width W4 of the second portion P2 in the X direction. In this case, the widths W3 and W4 may represent the horizontal width of the lower surface of the mold structure MS.

[0066] The vertical channel portion 73S of the channel structure 73 may contact the recess M4. The channel structure 73 may contact one side of the second portion P2 of the mold structure MS, and may partially contact the first portion P1. For example, a portion of the vertical channel portion 73S of the channel structure 73 may be disposed in the recess M4. For example, the vertical channel portion 73S may fill (e.g., may completely fill) the recess M4, and may protrude from one side of the mold structure MS (e.g., the second portion P2 of the mold structure MS) in the X direction. A portion of the vertical channel portion 73S of the channel structure 73 may overlap the mold structure MS in the Y direction.

[0067] In a plan view, the vertical channel portion 73S of the channel structure 73 may have a rectangular shape. However, the shape and structure of the vertical channel portion 73S are illustrative and are not limited thereto.

[0068] The vertical channel portion 73S may include a first side surface S1 perpendicular to the X direction, and a second side surface S2 and a third side surface S3 disposed on both sides (e.g., both ends) of the first side surface S1. The first side surface S1, the second side surface S2, and the third side surface S3 may contact a side surface of the mold structure MS (e.g., the recess M4 of the mold structure MS). The second side surface S2 and the third side surface S3 may face each other and intersect the first side surface S1 at an angle. Figure 7 , the angle between the first side surface S1 and the second side surface S2 and the angle between the first side surface S1 and the third side surface S3 are shown as 90 degrees, but are not limited thereto. According to example embodiments, the shape of the recess M4 and the shape of the vertical channel portion 73S may vary. In some embodiments, the protrusion M3 and the vertical channel portion 73S may have rounded side surfaces.

[0069] Figures 8 to 10 is a plan view of a semiconductor device according to example embodiments.

[0070] Reference Figure 8 , the semiconductor device 100e may include a vertical channel portion 73S of the channel structure 73 disposed on one side of the mold structure MS and contacting the recess M4. In an example embodiment, the vertical channel portion 73S of the channel structure 73 may include an end extending in the Y direction on one side of the mold structure MS. For example, the vertical channel portion 73S of the channel structure 73 may include a first end 73d and a second end 73e. The first end 73d and the second end 73e may contact the first portion P1 of the mold structure MS and may not overlap the mold structure MS as a part of the second portion P2 in the Y direction.

[0071] Reference Fig. 9, the semiconductor device 100f may include a vertical channel portion 73S of the channel structure 73 disposed on one side of the mold structure MS and contacting the recess M4. In an example embodiment, the vertical channel portion 73S may not completely fill the recess M4, and a portion of the dielectric structure 76 may be disposed in the recess M4. For example, the vertical channel portion 73S of the channel structure 73 may include an extension portion 73a, a first curved portion 73b, and a second curved portion 73c. ​​The extension portion 73a may extend in the Y direction, and the first curved portion 73b and the second curved portion 73c may be disposed at both ends of the extension portion 73a and extend in a direction intersecting the Y direction. In an example embodiment, the first curved portion 73b and the second curved portion 73c may extend in the X direction, but are not limited thereto. In some embodiments, the first curved portion 73b and the second curved portion 73c may extend in a direction between the X direction and the Y direction.

[0072] Reference Fig.10 , the semiconductor device 100g may include a vertical channel portion 73S of the channel structure 73 disposed on one side of the mold structure MS and contacting the recess M4. In an example embodiment, the vertical channel portion 73S of the channel structure 73 may include an end extending in the Y direction on one side of the mold structure MS. In addition, in an example embodiment, the vertical channel portion 73S may not completely fill the recess M4, and a portion of the dielectric structure 76 may be disposed in the recess M4. For example, the vertical channel portion 73S of the channel structure 73 may include a first end 73d and a second end 73e.

[0073] FIG. 11A to FIG. 15D 1 is a plan view and a vertical cross-sectional view shown according to a process sequence, illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0074] In detail, Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A is with Figure 1A The corresponding floor plan. Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B is with Figure 1B The corresponding vertical section view. Fig. 11C , Fig. 12C , Fig. 13C and Fig. 15C is with Figure 1C The corresponding vertical section view. Fig.11D , Fig.13D , Fig. 14C and Fig.15D is with Figure 1DThe corresponding vertical section view.

[0075] Reference FIG. 11A to FIG. 11D , a lower structure LS may be formed. The lower structure LS may include Figures 1B to 1D The substrate 3, the circuit element TR on the substrate 3, the peripheral interconnect 23 and the peripheral plug 20 electrically connected to the circuit element TR, the first peripheral insulating layer 30 surrounding one side of the peripheral plug 20 and one side of the circuit element TR, and the second peripheral insulating layer 32 surrounding the peripheral interconnect 23 and the peripheral plug 20.

[0076] An etch stop layer 40 may be formed on the lower structure LS. The etch stop layer 40 may cover the peripheral interconnection 23 and the second peripheral insulating layer 32.

[0077] The bit line 50, the bit line plug 53, the bit line insulating layer 56, and the shielding pattern 60 may be formed on the etch stop layer 40. For example, the bit line plug 53 may be formed to penetrate the etch stop layer 40 and contact the peripheral interconnect 23, and the bit line 50 may be formed on the bit line plug 53. An insulating material may be deposited to cover the bit line plug 53 and the bit line 50, and the shielding pattern 60 may be formed on the insulating material. Thereafter, the bit line insulating layer 56 may be formed by further depositing the insulating material to cover the shielding pattern 60. The bit line 50 may extend in the X direction and may be spaced apart from each other in the Y direction. The shielding pattern 60 may extend in the X direction and may be spaced apart from each other in the Y direction. The shielding pattern 60 may be arranged alternately with the bit line 50 in the Y direction.

[0078] Reference FIG. 12A to FIG. 12C , a mold structure MS may be formed on the bit line 50 and the bit line insulating layer 56. After sequentially stacking lower and upper insulating materials to cover the bit line 50 and the bit line insulating layer 56, the lower and upper insulating materials may be patterned to form a lower mold layer M2 and an upper mold layer M1.

[0079] The lower insulating material and the upper insulating material may be patterned to include protrusions M3. For example, the protrusions M3 may protrude from both sides of the mold structure MS in the X direction. For example, the protrusions M3 may be spaced apart from each other in the X direction and the Y direction, and may be disposed with the lower mold layer M2 and the upper mold layer M1 between the protrusions M3.

[0080] The mold structures MS may extend in the Y direction and may be spaced apart from each other in the X direction. In one example embodiment, the mold structure MS may have a tapered shape in which a horizontal width in the X direction decreases upward, but is not limited thereto.

[0081] In one example embodiment, the lower mold layer M2 and the upper mold layer M1 may include different materials. For example, the lower mold layer M2 may include silicon oxide, and the upper mold layer M1 may include silicon nitride. In some embodiments, the lower mold layer M2 and the upper mold layer M1 may include the same material and may be integrally formed.

[0082] Reference FIG. 13A to FIG. 13D , a channel material layer 73p and a sacrificial layer SL may be formed. The channel material layer 73p may be formed to cover the bit line 50, the bit line insulating layer 56, and the mold structure MS. For example, the channel material layer 73p may conformally cover the mold structure MS. The sacrificial layer SL may be formed to cover the channel material layer 73p.

[0083] Reference FIG. 14A to FIG. 14C The upper mold layer M1, the channel material layer 73p, and the sacrificial layer SL may be planarized and patterned. The channel material layer 73p and the sacrificial layer SL may be planarized so that the upper surface of the mold structure MS is exposed, and the upper surface of the channel material layer 73p and the upper surface of the sacrificial layer SL may be coplanar with the upper surface of the mold structure MS.

[0084] Furthermore, the channel material layer 73p and the sacrificial layer SL may be patterned by an anisotropic etching process and may partially expose an upper surface of the bit line insulating layer 56. The patterned channel material layer 73p may extend in the X direction between the mold structures MS and may be spaced apart from each other in the Y direction.

[0085] Reference FIG. 15A to FIG. 15D , the sacrificial layer SL may be removed, and a dielectric material layer 76p and a conductive layer 79p may be formed. The dielectric material layer 76p may be conformally formed on the bit line insulating layer 56, the channel material layer 73p, and the mold structure MS. The conductive layer 79p may cover the dielectric material layer 76p.

[0086] Refer again Figures 1A to 1D , the dielectric material layer 76p and the conductive layer 79p may be etched by an anisotropic etching process to form a dielectric structure 76 and a gate electrode 79. In an example embodiment, a portion of the dielectric structure 76 covering the upper surface of the mold structure MS may be retained without being removed, but is not limited thereto. In some embodiments, a portion of the dielectric structure 76 covering the upper surface of the mold structure MS may be removed, and the upper surface of the mold structure MS may be exposed.

[0087] In a plan view, the gate electrode 79 may intersect the bit line 50. For example, the gate electrodes 79 may be disposed on one side of the mold structure MS, extend in the Y direction, and be spaced apart from each other in the X direction.

[0088] In an example embodiment, the channel structure 73 may be formed by etching a portion of the channel material layer 73p between the mold structures MS. The channel structure 73 may include a horizontal portion 73L and a vertical channel portion 73S, the horizontal portion 73L contacts the bit line 50 and extends in the horizontal direction, and the vertical channel portion 73S extends upward from one end of the horizontal portion 73L. In an example embodiment, the vertical channel portion 73S may extend in a direction inclined to the vertical direction (Z direction), but is not limited thereto. In some embodiments, the vertical channel portion 73S may extend in the vertical direction. Portions of the channel material layer 73p may be etched to partially expose the upper surface of the bit line 50 between the mold structures MS. In some embodiments, the channel structure 73 may extend uninterruptedly between adjacent mold structures MS in the X direction.

[0089] An upper insulating structure 81 and an upper cover layer 82 may be formed. The upper insulating structure 81 may be formed by depositing an insulating material to cover the channel structure 73, the dielectric structure 76, and the gate electrode 79, and then planarizing the insulating material. The upper insulating structure 81 may extend in the Y direction and may be spaced apart from each other in the X direction. The upper insulating structure 81 may be alternately arranged with the mold structure MS in the X direction. The upper cover layer 82 may cover the upper surface of the upper insulating structure 81.

[0090] An opening exposing the channel structure 73 may be formed in the upper cover layer 82 by an anisotropic etching process, and a conductive material may be formed in the opening. Thereafter, a bonding pad structure 83 may be formed by patterning the conductive material. The bonding pad structure 83 contacts the channel structure 73 and may be electrically connected to the bit line 50 through the channel structure 73.

[0091] After depositing the insulating material to cover the bonding pad structure 83, the insulating material may be flattened to expose the upper surface of the bonding pad structure 83, thereby forming an insulating pattern 86. The insulating pattern 86 may be disposed at the same level as the bonding pad structure 83, and electrically insulate the bonding pad structures 83 from each other. The mold structure MS, the channel structure 73, the dielectric structure 76, the gate electrode 79, the upper insulating structure 81, the upper cover layer 82, the bonding pad structure 83, and the insulating pattern 86 may form an upper structure US.

[0092] After that, a heating process may be performed. Through the heating process, the channel structure 73 may receive oxygen from the lower mold layer M2 including silicon oxide. Therefore, oxygen vacancies in the channel structure 73 including the oxide semiconductor layer may be reduced, and the cell active leakage current (Ioff) may be reduced and / or prevented. For example, when the cell transistor is not operating, the cell active leakage current is reduced, and when a voltage is applied to the gate electrode 79 and the cell transistor is operating, current may flow in the channel structure 73. The switching characteristics of the semiconductor device 100 may be improved. In addition, according to example embodiments, the vertical channel portion 73S of the channel structure 73 is arranged to overlap with the mold structure MS in the Y direction, and three sides (e.g., side surfaces of the three sides) of the vertical channel portion 73S may contact the mold structure MS. Therefore, without increasing the size of the semiconductor device 100, the contact area between the vertical channel portion 73S and the mold structure MS may be increased. In addition, by increasing the contact area, oxygen vacancies may be more effectively reduced by the heating process, and the cell active leakage current may be further reduced.

[0093] As described above, according to example embodiments, the vertical channel portion of the channel structure contacts the protrusion or recess of the mold structure, and thus the contact area between the channel structure and the mold structure can be increased. Therefore, oxygen vacancies in the channel structure can be more effectively reduced through the heating process, and the cell active leakage current can be reduced and / or prevented.

[0094] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: A bit line extending in a first horizontal direction; molded structure, on the bit line; a channel structure including a horizontal portion contacting an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode, on the channel structure; as well as a bonding pad structure on the vertical channel portion and electrically connected to the channel structure, wherein The vertical channel portion contacts the side surface of the mold structure, At least a portion of the vertical channel portion overlaps the molding structure in a second horizontal direction, and The second horizontal direction intersects the first horizontal direction.

2. The semiconductor device according to claim 1, wherein The molding structure includes: a protrusion protruding from a side surface of the molding structure in a first horizontal direction, and The vertical channel portion overlaps the protrusion in a second horizontal direction.

3. The semiconductor device according to claim 2, wherein: A vertical channel partially surrounds the outer side surface of the protrusion.

4. The semiconductor device according to claim 1, wherein The vertical channel portion includes a first portion and a second portion and is bent, The first portion contacts the molding structure in a first horizontal direction, The second portion extends from the first portion, and The second portion contacts the molding structure in a second horizontal direction.

5. The semiconductor device according to claim 2, wherein: The horizontal width of the protrusion in the second horizontal direction decreases with increasing distance from a central axis of the molding structure extending in the second horizontal direction.

6. The semiconductor device according to claim 2, wherein: In a plan view, the protrusion has a trapezoidal shape.

7. The semiconductor device according to claim 2, wherein: The vertical channel portion includes a first bent portion, a second bent portion, and an extending portion extending in a second horizontal direction, The first curved portion and the second curved portion extend from different sides of the extending portion, respectively, and The first curved portion and the second curved portion each extend in a direction different from the second horizontal direction, respectively.

8. The semiconductor device according to claim 7, wherein: The vertical channel portion further includes: a first end portion and a second end portion extending in a second horizontal direction, The first end portion is connected to the first curved portion, and The second end portion is connected to the second curved portion.

9. The semiconductor device according to claim 1, wherein: The molding structure includes: a recessed portion on a side surface of the molding structure, and At least a portion of the vertical channel portion is within the recess.

10. The semiconductor device according to claim 9, wherein A portion of the vertical channel portion protrudes from a side surface of the molding structure in a first horizontal direction.

11. The semiconductor device according to claim 9, wherein The vertical channel portion completely fills the recess.

12. The semiconductor device according to claim 9, further comprising: A dielectric structure between the channel structure and the gate electrode, wherein A portion of the dielectric structure is within the recess.

13. The semiconductor device according to claim 9, wherein: An end of the vertical channel portion contacts a side surface of the molding structure, and An end portion of the vertical channel portion extends along a side surface of the molding structure in a second horizontal direction.

14. A semiconductor device comprising: A bit line extending in a first horizontal direction; a molded structure on the bit line and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; a channel structure including a horizontal portion contacting an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode, on the channel structure; as well as a bonding pad structure on the vertical channel portion and electrically connected to the channel structure, wherein The molded structure includes first and second parts alternately arranged in a second horizontal direction, The lower surface of the first portion of the molded structure has a first horizontal width in a first horizontal direction, The lower surface of the second portion of the molded structure has a second horizontal width in the first horizontal direction, The second horizontal width is different from the first horizontal width, The vertical channel portions are spaced apart from each other in a second horizontal direction, and The vertical channel portion contacts the side surface of the molding structure.

15. The semiconductor device according to claim 14, wherein: The second horizontal width is greater than the first horizontal width, and The vertical channel portions respectively surround side surfaces of the second portion of the molding structure.

16. The semiconductor device according to claim 15, wherein: The vertical channel portion partially contacts a side surface of the first portion of the contact molding structure.

17. The semiconductor device according to claim 14, wherein: A distance between adjacent vertical channel portions in the second horizontal direction is smaller than a distance between adjacent second portions of the mold structure in the second horizontal direction.

18. The semiconductor device according to claim 14, wherein: The vertical channel portion includes a first side surface, a second side surface and a third side surface, respectively, The second side surface and the third side surface are connected to different sides of the first side surface, and The first side surface, the second side surface, and the third side surface are in contact with the side surface of the molding structure.

19. The semiconductor device according to claim 14, wherein: The second horizontal width is smaller than the first horizontal width, The vertical channel portions contact side surfaces of the second portion of the molding structure, respectively, and The vertical channel portions overlap the first portions of the molding structure in a second horizontal direction, respectively.

20. A semiconductor device comprising: a lower structure including circuit elements; a bit line on the lower structure and extending in a first horizontal direction; a mold structure on the bit line and extending in a second horizontal direction intersecting the first horizontal direction; a channel structure including a horizontal portion contacting an upper surface of the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a gate electrode, on the channel structure; a dielectric structure extending in a second horizontal direction between the channel structure and the gate electrode; an upper insulating structure spaced apart from the mold structure and covering the gate electrode and the bit line; an upper cover layer, covering the molded structure and the upper insulating structure; a bonding pad structure penetrating the upper cover layer and electrically connected to the channel structure; as well as An information storage structure on a bonding pad structure, wherein The vertical channel portion contacts the side surface of the molding structure, and At least a portion of the vertical channel portion overlaps the molding structure in the second horizontal direction.

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