Semiconductor device

Abstract

A semiconductor device includes: a channel pattern on a substrate and extending in a first direction perpendicular to a surface of the substrate; the gate insulating layer is positioned on the side wall of the channel pattern, and the gate insulating layer is provided with an upper surface which is higher than the uppermost surface of the channel pattern; a first gate electrode on the gate insulating layer and having a first work function; a second gate electrode covering a surface of the first gate electrode, the second gate electrode having a second work function greater than the first work function; and a first contact plug on an uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer, in which a lower portion of the first contact plug faces at least a portion of the second gate electrode in a second direction intersecting the first direction.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor device including a vertical channel transistor. Background Art

[0002] For high integration of semiconductor devices, a vertical channel transistor including a channel layer perpendicular to a substrate surface may be used in the semiconductor device. A contact plug may be connected to an end of the channel layer of the vertical channel transistor. In the vertical channel transistor, a portion of the gate insulating layer facing both the contact plug and the gate electrode may have reliability defects.

[0003] The information disclosed in this background technology section is already known to the inventor or derived by the inventor before or during the implementation of the embodiments of the present application, or is technical information obtained in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0004] One or more example embodiments provide a semiconductor device including a vertical channel transistor.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0006] According to an aspect of example embodiments, a semiconductor device may include: a channel pattern, the channel pattern being located on a substrate, the channel pattern including a channel pattern sidewall portion and a channel pattern lower portion, the channel pattern sidewall portion extending in a first direction perpendicular to a surface of the substrate, the channel pattern lower portion connecting lower ends of the channel pattern sidewall portions facing each other in a second direction intersecting the first direction; a gate insulating layer, the gate insulating layer being located on surfaces of the channel pattern sidewall portion and the channel pattern lower portion, the gate insulating layer including a gate insulating layer sidewall portion and a gate insulating layer lower portion, the gate insulating layer sidewall portion extending in the first direction, the gate insulating layer lower portion The gate insulating layer comprises a first gate electrode, the first gate electrode being located on an inner surface of at least one of the sidewall portions of the gate insulating layer, the first gate electrode having a first work function, a second gate electrode, the second gate electrode covering a surface of the first gate electrode, and the second gate electrode having a second work function greater than the first work function, and a first contact plug, the first contact plug being located on the upper surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer, wherein the uppermost surface of the second gate electrode is higher than the uppermost surface of the channel pattern.

[0007] According to an aspect of example embodiments, a semiconductor device may include: a first conductive layer pattern, the first conductive layer pattern being located on a substrate, the first conductive layer pattern extending in a first direction parallel to an upper surface of the substrate; a channel pattern, the channel pattern being located on the first conductive layer pattern, the channel pattern including a channel pattern sidewall portion and a channel pattern lower portion, the channel pattern sidewall portion extending in a second direction intersecting the first direction, the channel pattern lower portion connecting lower ends of the channel pattern sidewall portions facing each other in the first direction, wherein a lower surface of the channel pattern contacts the first conductive layer pattern; and a gate insulating layer, the gate insulating layer being located on surfaces of the channel pattern sidewall portion and the channel pattern lower portion, the gate insulating layer including a gate insulating layer sidewall portion and a gate insulating layer lower portion, the gate insulating layer sidewall portion extending in the second direction, the gate insulating layer a first gate electrode, the first gate electrode being arranged on the inner surface of at least one of the sidewall portions of the gate insulation layer, the first gate electrode extending in the second direction, the first gate electrode having a first work function; a second gate electrode, the second gate electrode covering the surface of the first gate electrode, the second gate electrode extending in the second direction and having a second work function greater than the first work function; and a first contact plug, the first contact plug being located on the upper surface of the channel pattern, the first contact plug contacting the upper portion of the gate insulation layer, wherein a height difference between the uppermost surface of the first gate electrode and the uppermost surface of the channel pattern is less than a height difference between the uppermost surface of the second gate electrode and the uppermost surface of the channel pattern.

[0008] According to an aspect of an example embodiment, a semiconductor device may include: a channel pattern, the channel pattern being located on a substrate, the channel pattern extending in a first direction perpendicular to a surface of the substrate; a gate insulating layer, the gate insulating layer being located on a sidewall of the channel pattern, the upper surface of the gate insulating layer being higher than an uppermost surface of the channel pattern; a first gate electrode, the first gate electrode being located on the gate insulating layer, the first gate electrode having a first work function; a second gate electrode, the second gate electrode covering a surface of the first gate electrode, the second gate electrode having a second work function greater than the first work function; and a first contact plug, the first contact plug being located on an uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer; wherein a lower portion of the first contact plug faces at least a portion of the second gate electrode in a second direction intersecting the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will be more readily understood through the following description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view showing a semiconductor device according to one or more embodiments;

[0011] Figure 2 and Figure 3 is a cross-sectional view showing a semiconductor device according to one or more embodiments;

[0012] Figure 4 is an enlarged cross-sectional view showing a portion of a semiconductor device according to one or more embodiments;

[0013] Figure 5 is an enlarged cross-sectional view showing a portion of a semiconductor device according to one or more embodiments;

[0014] Figures 6 to 38 is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments;

[0015] Fig.39 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments;

[0016] Fig.40 is an enlarged cross-sectional view showing a portion of a semiconductor device according to one or more embodiments; and

[0017] Fig.41 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0018] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same components in the accompanying drawings use the same reference numerals, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms.

[0019] As used herein, expressions such as "at least one of..." when preceding a list of elements modify the entire list of elements rather than modifying the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0020] It will be understood that when an element or layer is referred to as being “on,” “over,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly on, over, above, under, under, under, directly connected to or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to,” there are no intervening elements or layers.

[0021] Figure 1 is a top view illustrating a semiconductor device according to one or more embodiments. Figure 2 and Figure 3 is a cross-sectional view illustrating a semiconductor device according to one or more embodiments. Figure 4 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments. Figure 5 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments. Fig.40 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments. Fig.41 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments.

[0022] The semiconductor device may be a dynamic random access memory (RAM) (DRAM) device. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA' in FIG. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB'. Figure 4 and Figure 5 is with Figure 2 The enlarged cross-sectional view of the portion corresponding to D in FIG. Figure 1 The components formed on the second conductive layer pattern may be omitted.

[0023] Reference Figures 1 to 3 The semiconductor device may include a first conductive layer pattern 106, a mold insulation structure 116, a channel pattern 130a, a gate insulation layer 140, a first gate electrode 150, a second gate electrode 170, a first contact plug 200, a second contact plug 204, a second conductive layer pattern 202, a third conductive layer pattern 206 and a capacitor 226.

[0024] The semiconductor device may further include a first lower insulating layer 102 , a capping insulating pattern 180 , a buried insulating pattern 182 , a first insulating layer 184 , a second insulating pattern 208 , and a first etch stop layer 210 .

[0025] In one or more embodiments, the semiconductor device may include a vertical channel transistor formed on the channel pattern 130 a including an oxide semiconductor.

[0026] A first lower insulating layer 102 may be formed on the substrate 100. The first lower insulating layer 102 may include, for example, silicon oxide. An upper surface of the first lower insulating layer 102 may be substantially flat.

[0027] A plurality of first conductive layer patterns 106 may be disposed on the first lower insulating layer 102, and each of the plurality of first conductive layer patterns 106 may have a line shape extending in a first direction D1 parallel to the upper surface of the substrate 100. The first conductive layer patterns 106 may be arranged in parallel with each other, and may be spaced apart from each other in a second direction D2 parallel to the upper surface of the substrate 100 and perpendicular to the first direction D1. Each first conductive layer pattern 106 may function as a bit line.

[0028] The second lower insulating layer 108 may be disposed on the first lower insulating layer 102 and may at least partially fill the space between the first conductive layer patterns 106. The upper surfaces of the first conductive layer patterns 106 and the second lower insulating layer 108 may be coplanar with each other and may be substantially flat. Thus, the upper surface of the first conductive layer pattern 106 may be exposed by the second lower insulating layer 108.

[0029] In one or more embodiments, the plurality of first conductive layer patterns 106 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first conductive layer patterns 106 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, WSi, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the embodiment is not limited thereto. The plurality of first conductive layer patterns 106 may include a single layer or multiple layers of the above materials. For example, each first conductive layer pattern 106 may have a structure in which a titanium nitride layer, a tungsten layer, a tungsten silicide layer, and a titanium nitride layer are stacked.

[0030] A plurality of molded insulating structures 116 having a line shape extending in the second direction D2 may be disposed on the first conductive layer pattern 106 and the second lower insulating layer 108. The molded insulating structures 116 may be arranged to perpendicularly intersect the first conductive layer pattern 106. A first trench 118 extending in the second direction D2 may be formed between the molded insulating structures 116. A plurality of first trenches 118 may be provided.

[0031] Each of the mold insulation structures 116 may have a structure in which the first mold insulation pattern 112 and the second mold insulation pattern 114 are sequentially stacked in the vertical direction D3 .

[0032] In one or more embodiments, the first mold insulating pattern 112 may include, for example, silicon oxide. The second mold insulating pattern 114 may include, for example, silicon nitride. A vertical thickness of the first mold insulating pattern 112 may be greater than a vertical thickness of the second mold insulating pattern 114.

[0033] The channel pattern 130a may be conformally formed on the sidewalls of the molded insulating structures 116 facing each other and on the upper surface of the first conductive layer pattern 106 between the molded insulating structures 116. The channel pattern 130a may be formed along the contours of the sidewalls of the molded insulating structures 116 facing each other and on the upper surface of the first conductive layer pattern 106 between the molded insulating structures 116. Each molded insulating structure 116 may be disposed on the outer wall of the channel pattern. The channel pattern 130a may include a sidewall portion extending in the vertical direction D3 and a lower portion of two lower ends of the sidewall portion facing each other in the horizontal direction (i.e., the first direction D1). Therefore, in a cross-sectional view cut along the first direction D1, the channel pattern 130a may have a U-shape.

[0034] The uppermost surface (ie, both ends) of the channel pattern 130a may be lower than the upper surface of the mold insulating structure 116. The uppermost surface of the channel pattern 130a may be lower than the upper surface of the second mold insulating pattern 114.

[0035] Hereinafter, in a structure having a U-shape, the inner space of the U-shape may be referred to as an inner portion. In addition, a portion extending in a vertical direction D3 in a structure having a U-shape may be referred to as a side wall portion. A portion connecting the lower end of the side wall portion in a horizontal direction may be referred to as a lower portion. The area outside the U-shape may be referred to as an outer portion or an outer surface.

[0036] The lower surface of the channel pattern 130a may contact the upper surface of the first conductive layer pattern 106. The plurality of channel patterns 130a may be spaced apart from each other in the first direction D1 and the second direction D2. In one or more embodiments, the channel pattern 130a may not be formed on the second lower insulating layer 108. The mold insulating structure 116 may be disposed between the channel patterns 130a along the first direction D1.

[0037] The channel pattern 130a may include an oxide semiconductor material. In one or more embodiments, the channel pattern 130a may include InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, or a combination thereof. For example, the channel pattern 130a may include InxGayZnzO. In one or more embodiments, the channel pattern 130a may be amorphous.

[0038] The gate insulating layer 140 may be disposed along the surface of the inner portion of the sidewall of the channel pattern 130a and the surface of the lower portion of the channel pattern 130a. That is, the gate insulating layer 140 may be conformally formed along the inner portion of the U-shape of the channel pattern 130a. The gate insulating layer 140 may be formed on the inner surface of the channel pattern 130a. In addition, the gate insulating layer 140 may be formed on the molded insulating structure 116. In one or more embodiments, the gate insulating layer 140 may have a U-shape in a cross-sectional view cut along the first direction D1. The gate insulating layer 140 may extend in the second direction D2.

[0039] The gate insulating layer 140 may include a metal oxide having a dielectric constant greater than that of silicon nitride. In one or more embodiments, the gate insulating layer 140 may include aluminum oxide, zirconium oxide, hafnium oxide, or titanium oxide. For example, the gate insulating layer 140 may include aluminum oxide.

[0040] In one or more embodiments, the upper surface of the gate insulating layer 140 may be higher than the uppermost surface of the channel pattern 130a. The uppermost surface (e.g., both ends) of the gate insulating layer 140 on the inner portion of the sidewall of the channel pattern 130a may be coplanar with the upper surface of the mold insulating structure 116. Therefore, a third hole may be formed between the mold insulating structure 116 and the gate insulating layer 140 located at a position higher than the uppermost surface of the channel pattern 130a.

[0041] The first gate electrode 150 may be disposed on an inner portion of the gate insulating layer 140 (e.g., the first gate electrode 150 may be formed on a sidewall of the gate insulating layer 140). The first gate electrode 150 may be disposed inside sidewall portions of the gate insulating layer 140 having a U-shape that face each other. The first gate electrode 150 may not be formed on a lower portion of the gate insulating layer 140 having a U-shape. Each of the first gate electrodes 150 may extend in the second direction D2.

[0042] In one or more embodiments, the uppermost surface of the first gate electrode 150 may be coplanar with the uppermost surface of the channel pattern 130a. Therefore, the first gate electrode 150 may face the sidewall portion of the channel pattern 130a and the sidewall portion of the gate insulating layer 140. In this case, the vertical channel transistor may have target electrical characteristics, and the reliability defects of the gate insulating layer 140 may be reduced. However, according to process variations or circuit design, the uppermost surface of the first gate electrode 150 may be slightly higher or lower than the uppermost surface of the channel pattern 130a. In this case, the height difference between the uppermost surface of the first gate electrode 150 and the uppermost surface of the channel pattern 130a may be less than about 5% of the vertical height of the channel pattern 130a. When the uppermost surface of the first gate electrode 150 is higher than the uppermost surface of the channel pattern 130a by more than 5% of the vertical height of the channel pattern 130a, the effect of reducing the reliability defects of the gate insulating layer 140 may be reduced. When the uppermost surface of the first gate electrode 150 is lower than the uppermost surface of the channel pattern 130 a by more than 5% of the vertical height of the channel pattern 130 a , it may be difficult for the vertical channel transistor to have target electrical characteristics.

[0043] The first gate electrode 150 may include a conductive material having a first work function. The first gate electrode 150 may include a metal having a target work function for a vertical channel transistor having target electrical characteristics (eg, threshold voltage characteristics).

[0044] The first gate electrode 150 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. In one or more embodiments, the gate insulating layer 140 may include a metal oxide, and the first gate electrode 150 may include a metal material. For example, the first gate electrode 150 may include Ti, Ta, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the embodiment is not limited thereto.

[0045] The second gate electrode 170 may cover a surface (eg, an exposed surface) of the first gate electrode 150. In addition, the second gate electrode 170 may cover a portion of the gate insulating layer 140 disposed on the uppermost surface of the first gate electrode 150. The uppermost surface of the second gate electrode 170 may be higher than the uppermost surface of the channel pattern 130a.

[0046] In one or more embodiments, the second gate electrode 170 may cover the sidewall portion and the uppermost surface of the first gate electrode 150. The portion of the second gate electrode 170 disposed higher than the uppermost surface of the first gate electrode 150 may be referred to as an upper portion of the second gate 170, and the upper portion of the second gate electrode 170 may contact the surface of the gate insulating layer 140.

[0047] In one or more embodiments, Figure 4 As shown, the upper portion of the second gate electrode 170 may not include a vertical extension portion extending along a sidewall portion of the gate insulating layer 140 in the vertical direction D3.

[0048] In one or more embodiments, Figure 5 As shown, the upper portion of the second gate electrode 170 may include a vertical extension extending in the vertical direction D3 along the sidewall of the gate insulating layer 140. In this case, the upper portion of the second gate electrode 170 may include a bent portion.

[0049] The stacked structure of the first gate electrode 150 and the second gate electrode 170 may be used as a gate electrode structure 172. The gate electrode structure 172 may be used as a gate electrode of a vertical channel transistor. The gate electrode structure 172 may extend in the second direction D2. The gate electrode structure 172 may be used as a word line of a semiconductor device.

[0050] A surface of a lower portion of the gate insulating layer 140 may be exposed between the gate electrode structures 172 .

[0051] The uppermost surface of the second gate electrode 170 may be higher than the uppermost surface of the channel pattern 130a. Therefore, the upper portion of the second gate electrode 170 may not face the sidewall portion of the channel pattern 130a. However, the upper portion of the second gate electrode 170 may face the upper portion of the sidewall of the gate insulating layer 140.

[0052] The second gate electrode 170 may include a conductive material having a second work function greater than the first work function.

[0053] The second gate electrode 170 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the second gate electrode 170 may include doped polysilicon, Ti, Ta, W, Mo, Pt, Ni, Co, Ru, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof. The material of the second gate electrode 170 may be selected to have a work function greater than that of the first gate electrode 150.

[0054] The capping insulating pattern 180 may be conformally formed on the surfaces of the gate insulating layer 140 and the second gate electrode 170. The buried insulating pattern 182 may be formed on the capping insulating pattern 180. The buried insulating pattern 182 may fill the inner portion of the gate insulating layer 140 having a U-shape. The buried insulating pattern 182 may have a line shape extending in the second direction D2. The buried insulating pattern 182 may face the mold insulating structure 116 in the first direction D1.

[0055] The capping insulating pattern 180 may include, for example, silicon nitride. The buried insulating pattern 182 may include, for example, silicon oxide.

[0056] An upper surface of the buried insulating pattern 182 may be coplanar with an uppermost surface of the gate insulating layer 140 on an upper surface of the mold insulating structure 116 .

[0057] The first insulating layer 184 may be disposed on the uppermost surfaces of the capping insulating pattern 180, the buried insulating pattern 182, and the gate insulating layer 140. The first insulating layer 184 may include, for example, silicon nitride.

[0058] The first contact plug 200 may pass through the first insulating layer 184 , the capping insulating pattern 180 , and the uppermost surface of the gate insulating layer 140 , and may extend downward to contact the uppermost surface of the channel pattern 130 a .

[0059] The first contact plug 200 may include an upper portion passing through the first insulating layer 184, covering the insulating pattern 180 and the uppermost surface of the gate insulating layer 140, and a lower portion disposed below the uppermost surface of the gate insulating layer 40. The upper portion of the first contact plug 200 may have a first width, and the lower portion of the first contact plug 200 may have a second width less than the first width. The lower portion of the first contact plug 200 may face a portion of the gate insulating layer 140 and a portion of the second gate electrode 170 in a horizontal direction (e.g., the first direction D1).

[0060] The bottom of the first contact plug 200 may directly contact the uppermost surface of the channel pattern 130a. The lower sidewall of the first contact plug 200 may contact the mold insulation structure 116 and the upper portion of the gate insulation layer 140. In one or more embodiments, a portion of the first contact plug 200 may contact the outer wall of the gate insulation layer 140.

[0061] In one or more embodiments, the first contact plug 200 may include a conductive material having a third work function equal to or less than the first work function. In one or more embodiments, the first contact plug 200 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the first contact plug 200 may include doped polysilicon, Ti, Ta, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof. The first contact plug 200 may include a material selected as a material having a work function equal to or less than the first gate electrode 150.

[0062] In one or more embodiments, a height difference between an uppermost surface of the first gate electrode 150 and an uppermost surface of the channel pattern 130 a may be smaller than a height difference between an uppermost surface of the second gate electrode 170 and an uppermost surface of the channel pattern 130 a .

[0063] In one or more embodiments, the uppermost surface of the channel pattern 130a may be coplanar with the uppermost surface of the first gate electrode 150. In this case, the first contact plug 200 and the first gate electrode 150 may not face each other in a horizontal direction (e.g., lateral direction D1). Therefore, reliability defects of the gate insulating layer 140 caused by the overlap between the first contact plug 200 and the first gate electrode 150 having a low work function may be reduced.

[0064] Depending on process variations or circuit design, such as Fig.40 As shown, when the uppermost surface of the channel pattern 130a is slightly higher than the uppermost surface of the first gate electrode 150, the first contact plug 200 and the first gate electrode 150 may not face each other in the first direction D1. The first contact plug 200 may face at least a portion of the second gate electrode 170 in the first direction D1. Therefore, the first contact plug 200 may overlap the gate insulating layer 140 and the second gate electrode 170. Therefore, the reliability defect of the gate insulating layer 140 can be reduced.

[0065] Depending on process variations or circuit design, such as Fig.41As shown, when the uppermost surface of the channel pattern 130a is slightly lower than the uppermost surface of the first gate electrode 150, the on-current of the vertical channel transistor may increase. In this case, the first contact plug 200 may face at least a portion of the first gate electrode 150 and the second gate electrode 170 in the first direction D1. The height of the region where the first contact plug 200 and the second gate electrode 170 face each other in the first direction D1 may be greater than the height of the region where the first contact plug 200 and the first gate electrode 150 face each other in the first direction D1. Therefore, the reliability defect of the gate insulating layer 140 can be reduced.

[0066] The first gate electrode 150 may face the channel pattern 130a and the gate insulating layer 140, so that the first gate electrode 150 may be used as a switch gate of the vertical channel transistor. The second gate electrode 170 may face the first contact plug 200 and the gate insulating layer 140, so that the second gate electrode 170 may not be used as a switch gate of the vertical channel transistor. A portion of the gate insulating layer 140 may be interposed between the first contact plug 200 and the second gate electrode 170.

[0067] As described above, the channel pattern 130a, the gate insulating layer 140, and the first gate electrode 150 may be arranged along the first direction D1 so that the channel pattern 130a, the gate insulating layer 140, and the first gate electrode 150 may operate as a vertical channel transistor. The first gate electrode 150 may have a first work function so that the vertical channel transistor may have target electrical characteristics. In addition, the first contact plug 200 contacting the uppermost surface of the channel pattern 130a may overlap the gate insulating layer 140 and the second gate electrode 170, and the second gate electrode 170 may have a work function greater than the work function of the first gate electrode 150. Therefore, the off current generated in the region where the first contact plug 200, the gate insulating layer 140, and the second gate electrode 170 overlap can be reduced. In addition, the reliability defect of the gate insulating layer 140 occurring in the region where the first contact plug 200, the gate insulating layer 140, and the second gate electrode 170 overlap can be reduced.

[0068] Examples of metal used as each of the first gate electrode 150 , the second gate electrode 170 , and the first contact plug 200 may be given in the following table.

[0069] [Table 1]

[0070]

[0071]

[0072] The second conductive layer pattern 202 may be disposed on the first insulating layer 184 and may contact an upper surface of the first contact plug 200. In one or more embodiments, the second conductive layer pattern 202 and the first contact plug 200 may include the same material. In one or more embodiments, the second conductive layer pattern 202 and the first contact plug 200 may be integral, so that an interface between the second conductive layer pattern 202 and the first contact plug 200 may not be formed. The second conductive layer pattern 202 may be used as a pad for connecting the capacitor 226.

[0073] The second contact plug 204 may directly contact an edge portion of the gate electrode structure 172 in the second direction D2. An electrical signal may be applied to the gate electrode structure 172 through the second contact plug 204.

[0074] The second contact plug 204 may pass through the first insulating layer 184, the capping insulating pattern 180, and the buried insulating pattern 182, and may extend down to the surface of the lower portion of the gate insulating layer 140. In one or more embodiments, the second contact plug 204 may contact the uppermost surface and sidewalls of the second gate electrode 170.

[0075] The third conductive layer pattern 206 may be disposed on the first insulating layer 184 and may contact an upper surface of the second contact plug 204. In one or more embodiments, the third conductive layer pattern 206 and the second contact plug 204 may include the same material. In one or more embodiments, the third conductive layer pattern 206 and the second contact plug 204 may be integral so that an interface between the third conductive layer pattern 206 and the second contact plug 204 may not be formed.

[0076] In one or more embodiments, the second conductive layer pattern 202 , the third conductive layer pattern 206 , the first contact plug 200 , and the second contact plug 204 may include the same material.

[0077] The second insulating pattern 208 may be formed on the first insulating layer 184 and may fill the space between the second conductive layer patterns 202 and the space between the third conductive layer patterns 206. The upper surface of the second insulating pattern 208 and the upper surfaces of the second conductive layer patterns 202 and the third conductive layer patterns 206 may be coplanar with each other. The upper surfaces of the second insulating pattern 208 and the second conductive layer patterns 202 and the third conductive layer patterns 206 may be substantially flat. The second insulating pattern 208 may include, for example, silicon oxide.

[0078] A first etch stop layer 210 may be disposed on the second insulating pattern 208 and the second conductive layer pattern 202. The first etch stop layer 210 may include, for example, silicon nitride.

[0079] The capacitor 226 may pass through the first etch stop layer 210 and may be disposed on an upper surface of the second conductive layer pattern 202. The capacitor 226 may include a lower electrode 220, a dielectric layer 222, and an upper electrode 224 stacked sequentially. The lower electrode 220 may directly contact an upper surface of the third conductive layer pattern 206. The lower electrode 220 may have a pillar or cylindrical shape.

[0080] The lower electrode 220 of the capacitor 226 may be electrically connected to the channel pattern 130 a through the second conductive layer pattern 202 and the first contact plug 200 .

[0081] Figures 6 to 38 is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0082] Figure 6 , Figure 8 , Fig.10 , Fig.16 , Fig.19 , Fig.24 , Fig.32 and Fig.37 It is a top view. Figure 7 , Fig. 9 , Fig.11 , Fig.12 , Fig.14 , Fig.17 , Fig.18 , Figure 20 to Figure 23 , Figure 25 to Figure 29 , Fig.31 , Fig.33 , Fig.34 , Fig.35 and Fig.38 It is a cross-sectional view taken along the line AA'.

[0083] Fig.30 and Fig.36 It is a cross-sectional view taken along the line BB'. Fig.13 and Fig.15 It is a cross-sectional view taken along the line CC'.

[0084] Reference Figure 6 and Figure 7 , a first lower insulating layer 102 may be formed on the substrate 100 .

[0085] A first conductive layer pattern 106 having a line shape extending in the first direction D1 may be formed on the first lower insulating layer 102. The first conductive layer patterns 106 may be parallel to each other and may be spaced apart from each other in the second direction D2. A second lower insulating layer 108 may be formed on the first lower insulating layer 102 between the first conductive layer patterns 106. Upper surfaces of the first conductive layer patterns 106 and the second lower insulating layer 108 may be coplanar with each other and may be substantially flat.

[0086] In one or more embodiments, the first lower insulating layer 102 and the second lower insulating layer 108 may include silicon oxide. In one or more embodiments, the first conductive layer pattern 106 may include metal.

[0087] In one or more embodiments, the first conductive layer pattern 106 may be formed by an embossed manner. In this case, a first conductive layer may be formed on the first lower insulating layer 102. The first conductive layer may be patterned by a photolithography process to form the first conductive layer pattern 106. Thereafter, an insulating layer may be formed on the first conductive layer pattern 106. The insulating layer may be planarized until the upper surface of the first conductive layer pattern 106 is exposed to form the second lower insulating layer 108.

[0088] In one or more embodiments, the first conductive layer pattern 106 may be formed by a damascene process. In this case, a second lower insulating layer 108 may be formed on the first lower insulating layer 102. The second lower insulating layer may be patterned by a photolithography process to form a groove. The first conductive layer may be formed on the second lower insulating layer 108 to fill the groove. The first conductive layer may be planarized until the upper surface of the second lower insulating layer 108 is exposed to form the first conductive layer pattern 106. The first conductive layer pattern 106 may be formed in the grooves, respectively.

[0089] Reference Figure 8 and Fig. 9 , a first mold insulating layer and a second mold insulating layer may be sequentially formed on the first conductive layer pattern 106 and the second lower insulating layer 108. The first mold insulating layer and the second mold insulating layer may be patterned to form mold insulating structures 116. Each mold insulating structure 116 may have a structure in which a first mold insulating pattern 112 and a second mold insulating pattern 114 are stacked. The thickness of the second mold insulating pattern 114 may be greater than the thickness of the first mold insulating pattern 112.

[0090] In one or more embodiments, the first mold insulating pattern 112 may include, for example, silicon oxide. The second mold insulating pattern 114 may include, for example, silicon nitride.

[0091] The molded insulating structures 116 may have a line shape extending in the second direction D2. The molded insulating structures 116 may be spaced apart from each other in the first direction D1. A first trench 118 extending in the second direction D2 may be formed between the molded insulating structures 116. The first conductive layer pattern 106 and the second lower insulating layer 108 may be exposed through the bottom of the first trench 118.

[0092] The mold insulation structure 116 may be used as a mold for forming a channel pattern, a gate insulation layer pattern, and a gate electrode structure in subsequent processes.

[0093] Reference Fig.10 and Fig.11 , a channel layer 120 may be conformally formed along the surface of the mold insulation structure 116 and the bottom of the first trench 118. The channel layer 120 may include an oxide semiconductor layer. The oxide semiconductor layer may be used as a channel pattern of a vertical channel transistor through subsequent processes.

[0094] The channel layer 120 may cover the surface of the molded insulating structure 116, the upper surface of the first conductive layer pattern 106, and the upper surface of the second lower insulating layer 108. The channel layer 120 may be formed to have a uniform thickness along the surface profile of the first trench 118. The channel layer 120 may not completely fill the first trench 118. The channel layer 120 may contact the first conductive layer pattern 106.

[0095] In one or more embodiments, the channel layer 120 may be amorphous. In one or more embodiments, the channel layer 120 may include InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, or a combination thereof. For example, the channel layer 120 may include InxGayZnzO.

[0096] In one or more embodiments, the channel layer 120 may be formed by an atomic layer deposition process.

[0097] Reference Fig.12 and Fig.13 , a first sacrificial layer may be formed on the channel layer 120. The first sacrificial layer may fill the first trench 118. An upper surface of the first sacrificial layer may be substantially flat. In one or more embodiments, the first sacrificial layer may include a spin-on hard mask. The spin-on hard mask may include amorphous carbon.

[0098] A first etching mask may be formed on the first sacrificial layer, and the first sacrificial layer may be anisotropically etched using the mask to form a first sacrificial layer pattern 122. Subsequently, the channel layer 120 may be anisotropically etched using the first sacrificial layer pattern 122 as an etching mask to form a first preliminary channel pattern 120a. Thus, the first preliminary channel patterns 120a may be spaced apart from each other in the second direction D2.

[0099] In one or more embodiments, the first etching mask may be a photoresist pattern. The first etching mask may overlap with the upper surface of the first conductive layer pattern 106. Therefore, the first sacrificial layer pattern 122 may cover the upper surface of the first conductive layer pattern 106 and may extend in the first direction D1. A first opening 124 may be formed between the first sacrificial layer pattern 122 and the molded insulating structure 116. The second lower insulating layer 108 may be exposed through the bottom of the first opening 124. The lower surface of the first preliminary channel pattern 120a may contact the first conductive layer pattern 106.

[0100] Reference Fig.14 and Fig.15 A second sacrificial layer 126 may be formed on the second lower insulating layer 108, the mold insulating structure 116, the first sacrificial layer pattern 122, and the first preliminary channel pattern 120a. The second sacrificial layer 126 may fill the first opening 124. An upper surface of the second sacrificial layer 126 may be higher than an uppermost surface of the first preliminary channel pattern 120a.

[0101] In one or more embodiments, the second sacrificial layer 126 may include the same material as that of the first sacrificial layer pattern 122. Thus, the second sacrificial layer 126 and the first sacrificial layer pattern 122 may be merged into one sacrificial layer pattern.

[0102] In one or more embodiments, the second sacrificial layer 126 may include a spin-on hard mask.

[0103] The second sacrificial layer 126, the first sacrificial layer pattern 122, and upper portions of the first preliminary channel pattern 120a may be removed to expose an upper surface of the mold insulation structure 116. Thus, the first preliminary channel pattern 120a may be divided into a plurality of second preliminary channel patterns 130. The planarization process may include an etch-back process.

[0104] Each second preliminary channel pattern 130 may be formed along the sidewall profile of the mold insulation structure 116 and the upper surface of the first conductive layer pattern 106 between the mold insulation structures 116. In a cross-sectional view, each second preliminary channel pattern 130 may have a U-shape. The second preliminary channel patterns 130 may be spaced apart from each other in the first direction D1 and the second direction D2. The second preliminary channel patterns 130 may be repeatedly arranged. The lower surface of each second preliminary channel pattern 130 may contact the first conductive layer pattern 106.

[0105] The mold insulating structure 116 may be disposed between the second preliminary channel patterns 130 in the first direction D1. The mold insulating structure 116 may be arranged in the first direction D1. The second lower insulating layer 108 may be exposed between the second preliminary channel patterns 130 in the second direction D2.

[0106] Reference Fig.16 and Fig.17 , the first sacrificial layer pattern 122 and the second sacrificial layer 126 may be removed. The removal process of the first sacrificial layer pattern 122 and the second sacrificial layer 126 may include an ashing process and a cleaning process. Thus, the upper surface of the second preliminary channel pattern 130 may be exposed.

[0107] The first trench 118 may be formed again between the molded insulation structures 116 .

[0108] Reference Fig.18 , a gate insulating layer 140 may be formed on the second preliminary channel pattern 130, the mold insulating structure 116, and the second lower insulating layer 108. A first gate electrode layer 142 may be formed on the gate insulating layer 140. The gate insulating layer 140 and the first gate electrode layer 142 may be conformally formed on the second preliminary channel pattern 130, the mold insulating structure 116, and the second lower insulating layer 108. The gate insulating layer 140 and the first gate electrode layer 142 may be formed along surface contours of the second preliminary channel pattern 130, the mold insulating structure 116, and the second lower insulating layer 108.

[0109] The gate insulating layer 140 may include a metal oxide having a higher dielectric constant than that of silicon nitride. For example, the gate insulating layer 140 may include aluminum oxide.

[0110] The first gate electrode layer 142 may include a metal having a first work function. The first gate electrode layer 142 may include a material having a target work function for a vertical channel transistor having target electrical characteristics (eg, threshold voltage characteristics).

[0111] In one or more embodiments, the gate insulating layer 140 and the first gate electrode layer 142 may be formed by an atomic layer deposition process.

[0112] Reference Fig.19 and Fig. 20 , the first gate electrode layer 142 may be anisotropically etched, so that the first gate electrode layer 142 on the mold insulating structure and the first gate electrode layer 142 between the mold insulating structures may be removed. Therefore, the first gate electrode layers 142 may be separated from each other to form a first preliminary gate electrode 144. The first preliminary gate electrode 144 may be formed on the gate insulating layer 140 on the sidewall of the mold insulating structure 116. The first preliminary gate electrode 144 may extend in the second direction D2.

[0113] Reference Fig.21, a third sacrificial layer may be formed to cover the first preliminary gate electrode 144 and the gate insulating layer 140. An upper surface of the third sacrificial layer may be higher than the uppermost surface of the gate insulating layer 140. An upper surface of the third sacrificial layer may be substantially flat. In one or more embodiments, the third sacrificial layer may include a spin-on hard mask.

[0114] The third sacrificial layer may be etched back to form a third sacrificial layer pattern 146. An upper surface and upper sidewalls of the first preliminary gate electrode 144 may be exposed by the third sacrificial layer pattern 146. An upper surface of the third sacrificial layer pattern 146 may be coplanar with a target uppermost surface of a first gate electrode to be subsequently formed. The target upper surface of the first gate electrode may be lower than an uppermost surface of the second preliminary channel pattern 130.

[0115] Reference Fig. 22 , the first preliminary gate electrode 144 exposed by the third sacrificial layer pattern 146 may be etched to form a first gate electrode 150. The etching process may include a wet etching process.

[0116] The uppermost surface of the first gate electrode 150 may be lower than the uppermost surface of the first preliminary gate electrode 144. Through the above-mentioned processes, the first gate electrode 150 may have a target uppermost surface.

[0117] In one or more embodiments, the uppermost surface of the first gate electrode 150 may be coplanar with the bottom of a first contact plug formed subsequently. In one or more embodiments, depending on process profile, the uppermost surface of the first gate electrode 150 may be slightly lower than the bottom of the first contact plug.

[0118] The third sacrificial layer pattern 146 is removed through an ashing process and a stripping process.

[0119] Reference Fig.23 , the second gate electrode layer 160 may be conformally formed on the gate insulating layer 140 and the first gate electrode 150 . The second gate electrode layer 160 may be formed along surface profiles of the gate insulating layer 140 and the first gate electrode 150 .

[0120] The second gate electrode layer 160 may include a metal or polysilicon having a work function greater than that of the first gate electrode 150. The second gate electrode layer 160 may be provided to reduce reliability defects of the gate insulating layer 140.

[0121] In one or more embodiments, the second gate electrode layer 160 may be formed by an atomic layer deposition process.

[0122] Reference Fig.24 and Fig.25, the second gate electrode layer 160 may be anisotropically etched, so that the second gate electrode layer 160 formed on the upper surface of the mold insulation structure 116 and between the mold insulation structures 116 may be removed. Therefore, the second gate electrode layers 160 may be separated from each other to form a second preliminary gate electrode 162. The second preliminary gate electrode 162 may cover the upper surface and sidewalls of the first gate electrode 150. The second preliminary gate electrode 162 may extend in the second direction D2.

[0123] Reference Fig.26 , a fourth sacrificial layer may be formed to cover the second preliminary gate electrode 162 and the gate insulating layer 140. An upper surface of the fourth sacrificial layer may be higher than the uppermost surface of the gate insulating layer 140. An upper surface of the fourth sacrificial layer may be substantially flat. In one or more embodiments, the fourth sacrificial layer may include a spin-on hard mask.

[0124] The fourth sacrificial layer may be etched back until the upper surface and upper sidewalls of the second preliminary gate electrode 162 are exposed to form a fourth sacrificial layer pattern 164. An upper surface of the fourth sacrificial layer pattern 164 may be substantially coplanar with a target upper surface of a subsequently formed second gate electrode.

[0125] The second gate electrode may cover the entire exposed surface of the first gate electrode 150. In addition, the uppermost surface of the second gate electrode may be lower than the uppermost surface of the second preliminary channel pattern 130. Therefore, the uppermost surface of the fourth sacrificial layer pattern 164 may be higher than the uppermost surface of the first gate electrode 150. Therefore, the upper surface of the fourth sacrificial layer pattern 164 may be lower than the uppermost surface of the second preliminary channel pattern 130.

[0126] The second preliminary gate electrode 162 may be bent on the uppermost surface of the first gate electrode 150 , and may be formed along a surface profile of the gate insulating layer 140 exposed by the first gate electrode 150 .

[0127] In one or more embodiments, an upper surface of the fourth sacrificial layer pattern 164 may be substantially coplanar with the bent portion of the second preliminary gate electrode 162 , or may be higher than the bent portion of the second preliminary gate electrode 162 .

[0128] Reference Fig. 27 and Fig.28 , the second preliminary gate electrode 162 exposed by the fourth sacrificial layer pattern 164 may be etched to form a second gate electrode 170. The etching process may include a wet etching process.

[0129] The fourth sacrificial layer pattern 164 may be removed through an ashing process and a stripping process.

[0130] The first gate electrode 150 and the second gate electrode 170 may serve as a gate electrode structure 172. The gate electrode structure 172 may serve as a word line in a semiconductor device.

[0131] According to the position of the fourth sacrificial layer pattern, the shape of the second gate electrode 170 may vary.

[0132] In one or more embodiments, the second preliminary gate electrode 162 disposed above the bent portion may be removed in the removal process, thereby forming a gate electrode as shown in FIG. Fig. 27 The second gate electrode 170 shown. The second gate electrode 170 on the surface of the gate insulating layer 140 above the uppermost surface of the first gate electrode 150 may not extend in the vertical direction D3. Fig. 27 The second gate electrode 170 shown in FIG. 1 is used as an example to describe the following process.

[0133] In one or more embodiments, after the removal process, the second preliminary gate electrode 162 disposed above the bent portion may partially remain. Fig.28 As shown, the second gate electrode 170 may be bent on the uppermost surface of the first gate electrode 150. The second gate electrode 170 on the surface of the gate insulating layer 140 above the uppermost surface of the first gate electrode 150 may extend in the vertical direction D3, so that the second gate electrode 170 may include a portion extending in the vertical direction D3.

[0134] Reference Fig.29 A capping insulating layer may be conformally formed on the second gate electrode 170 , the gate insulating layer 140 , and the mold insulating structure 116 . A buried insulating layer may be formed on the capping insulating layer to completely fill the first trench 118 .

[0135] The capping insulating layer may include, for example, silicon nitride. The buried insulating layer may include, for example, silicon oxide.

[0136] Thereafter, the buried insulating layer and the capping insulating layer may be planarized until the uppermost surface of the gate insulating layer 140 is exposed to form a capping insulating pattern 180 and a buried insulating pattern 182. The capping insulating pattern 180 and the buried insulating pattern 182 may be formed on surfaces of the gate insulating layer 140 and the second gate electrode 170 in the first trench 118. The capping insulating pattern 180 and the buried insulating pattern 182 may fill the first trench 118.

[0137] In one or more embodiments, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0138] Thereafter, a first insulating layer 184 may be formed on the gate insulating layer 140, the capping insulating pattern 180, and the buried insulating pattern 182. In example embodiments, the first insulating layer 184 may include silicon nitride.

[0139] Reference Fig.30 , a second etching mask 186 may be formed on the first insulating layer 184. The second etching mask 186 may be a photoresist pattern. The second etching mask 186 may include a hole exposing an edge portion of the gate electrode structure 172 in the second direction D2. The hole may overlap at least the upper surface and the sidewall of the edge portion of the gate electrode structure 172 in the second direction D2.

[0140] The first insulating layer 184, the capping insulating pattern 180, and the buried insulating pattern 182 may be etched using the second etching mask 186 to form a first hole 188. An upper surface and a sidewall of an edge of the second gate electrode 170 in the second direction D2 may be exposed through the first hole 188.

[0141] Thereafter, the second etch mask 186 may be removed.

[0142] Reference Fig.31 , a third etch mask 190 may be formed on the first insulating layer 184. The third etch mask 190 may be a photoresist pattern.

[0143] The third etch mask 190 may include holes facing the uppermost surface (i.e., both ends) of the second preliminary channel pattern 130. Each hole included in the third etch mask 190 may face the uppermost surface of the second preliminary channel pattern 130 and a portion of the mold insulation structure 116 adjacent to the second preliminary channel pattern 130. In addition, the third etch mask 190 may cover the entire region or most of the upper surface facing the buried insulation pattern 182.

[0144] The first insulating layer 184, the gate insulating layer 140, and the capping insulating pattern 180 may be etched using the third etching mask 190 to form a second hole 192. The second preliminary channel pattern 130, the gate insulating layer 140, and the capping insulating pattern 180 may be exposed through the bottom of the second hole 192.

[0145] The etching process of the first insulating layer 184 may include, for example, a dry etching process. The etching process of the gate insulating layer 140 may include, for example, a wet etching process.

[0146] Reference Fig.32 and Fig.33, the second preliminary channel pattern 130 exposed by the bottom of the second hole 192 may be selectively etched to form a third hole 194. The third hole 194 may communicate with the second hole 192, and may have an inner width smaller than the inner width of the second hole 92. With the formation of the third hole 194, the height of the uppermost surface of the second preliminary channel pattern 130 may be reduced to form a channel pattern 130a.

[0147] The uppermost surface of the channel pattern 130a may be exposed through the bottom of the third hole 194. At least the upper sidewall of the gate insulating layer 140 and the sidewall of the second mold insulating pattern 114 may be exposed by the sidewall of the third hole 194. In one or more embodiments, the upper sidewall of the first mold insulating pattern 112 may be exposed by the sidewall of the third hole 194.

[0148] The bottom of the third hole 194 may be coplanar with the uppermost surface of the first gate electrode 150. In one or more embodiments, according to process variations, the bottom of the third hole 194 may be slightly higher than the uppermost surface of the first gate electrode 150. Therefore, the sidewall of the third hole 194 may not face the first gate electrode 150. The sidewall of the third hole 194 may face the second gate electrode 170.

[0149] Thereafter, the third etch mask 190 may be removed.

[0150] Reference Fig.34 , a second conductive layer 196 may be formed on the first insulating layer 184 to fill the first hole 188 , the second hole 192 , and the third hole 194 .

[0151] The second conductive layer 196 may include a metal. The second conductive layer 196 may include a metal having a work function equal to or less than the first work function.

[0152] A fourth etch mask 198 may be formed on the second conductive layer 196. The fourth etch mask 198 may include, for example, a photoresist pattern.

[0153] The fourth etch mask 198 may have an isolation shape covering a region facing each of the first hole 188 and the second hole 192 .

[0154] Reference Fig.35 and Fig.36 , the second conductive layer 196 may be etched using a fourth etching mask 198 to form a first contact plug 200. The first contact plug 200 may be formed in the second hole 192 and the third hole 194. In addition, a second conductive layer pattern 202 may be formed on the first contact plug 200. A second contact plug 204 may be formed in the first hole 188. In addition, a third conductive layer pattern 206 may be formed on the second contact plug 204.

[0155] The first contact plug 200 may directly contact the uppermost surface of the channel pattern 130a. Therefore, an electrical signal may be input and output to the channel pattern 130a through the first contact plug 200. The second conductive layer pattern 202 may function as a pad for connecting a capacitor.

[0156] The first contact plug 200 may include an upper portion having a first width and a lower portion having a width less than the first width. The upper portion of the first contact plug 200 may correspond to an inner portion of the second hole 192 , and the lower portion of the first contact plug 200 may correspond to an inner portion of the third hole 194 .

[0157] A sidewall of the first contact plug 200 may face a portion of the gate insulating layer 140 and a portion of the second gate electrode 170. That is, a portion of the gate insulating layer 140 may be interposed between the first contact plug 200 and the second gate electrode 170.

[0158] The second contact plug 204 may directly contact the gate electrode structure 172. Therefore, an electrical signal may be applied to the gate electrode structure 172 through the second contact plug 204.

[0159] In order to operate the vertical channel transistor, a voltage may be repeatedly supplied to the first contact plug 200 and the gate electrode structure 172. Therefore, the gate insulating layer 140 disposed between the first contact plug 200 and the gate electrode structure 172 may be broken down and / or damaged due to repeated voltage supply. That is, a reliability defect of the gate insulating layer 140 may occur. For example, a time-dependent dielectric breakdown (TDDB) defect of the gate insulating layer 140 may occur.

[0160] However, in one or more embodiments, the gate insulating layer 140 may be disposed between the first contact plug 200 and the second gate electrode 170, and the second gate electrode 170 may have a work function greater than a work function of the first gate electrode 150. Therefore, an off-current generated in a region where the first contact plug 200, the gate insulating layer 140, and the second gate electrode 170 overlap may be reduced. In addition, reliability defects of the gate insulating layer in a region where the first contact plug 200, the gate insulating layer 140, and the second gate electrode 170 overlap may be reduced.

[0161] Reference Fig.37 and Fig.38 A second insulating layer may be formed on the first insulating layer 184 and the second and third conductive layer patterns 202 and 206. The second insulating layer may fill gaps between the second conductive layer patterns 202. The second insulating layer may include, for example, silicon nitride or silicon oxide.

[0162] The second insulating layer may be planarized until upper surfaces of the second conductive layer patterns 202 and the third conductive layer patterns 206 are exposed to form second insulating patterns 208. The second insulating patterns 208 may be formed in gaps between the second conductive layer patterns 202.

[0163] A first etch stop layer 210 may be formed on the second insulating pattern 208. A capacitor 226 may pass through the first etch stop layer 210 and may contact an upper surface of the second conductive layer pattern 202. The capacitor 226 may include a lower electrode 220, a dielectric layer 222, and an upper electrode 224 stacked in sequence. The lower electrode 220 may directly contact an upper surface of the second conductive layer pattern 202. The lower electrode 220 may have a column shape. A semiconductor device may be manufactured by the above process.

[0164] In one or more embodiments, the gate electrode structure 172 may be formed by stacking the first gate electrode 150 and the second gate electrode 170 along the first direction D1. The second gate electrode 170 may include a conductive material having a work function greater than that of the first gate electrode 150. A portion of the gate insulating layer 140 may be interposed between the first contact plug 200 and the second gate electrode 170. Therefore, in a vertical channel transistor, reliability defects of the gate insulating layer occurring in a region where the first contact plug 200, the gate insulating layer 140, and the second gate electrode 170 overlap may be reduced.

[0165] Fig.39 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0166] The method for manufacturing a semiconductor device may be the same as that of reference 1 except for some processes for forming the second gate electrode. Figures 6 to 38 The method described is the same.

[0167] First, you can perform a reference Figures 6 to 19 The processes described above. In these processes, a conductive material whose work function can be increased by performing a surface treatment process can be deposited to form the first gate electrode layer 142. In one or more embodiments, the first gate electrode layer 142 may include a metal having a work function that can be increased by performing a nitridation process. For example, the first gate electrode layer 142 may include titanium. In this case, the first gate electrode 150 may include titanium.

[0168] Afterwards, you can perform a reference Figure 20 to Figure 22 The process is described to form the first gate electrode 150 on the gate insulating layer 140.

[0169] Reference Fig.39, a surface treatment process of the first gate electrode 150 may be performed to form the second gate electrode 170 on the surface of the first gate electrode 250. The work function of the second gate electrode 170 may be greater than the work function of the first gate electrode 150.

[0170] The surface treatment may include, for example, a nitridation treatment. When the first gate electrode 150 includes titanium, the second gate electrode 170 may include titanium nitride.

[0171] Thus, a gate electrode structure 172 including the first gate electrode 150 and the second gate electrode 170 may be formed.

[0172] After that, you can execute and refer to Figures 29 to 38 The same process as described is used to manufacture Figure 1 and Figure 2 The semiconductor device shown.

[0173] The vertical channel transistor included in the semiconductor device of one or more embodiments may be used as a selection transistor of various memory devices. The semiconductor device of one or more embodiments may be used as a memory included in electronic products such as mobile devices, memory cards, and computers.

[0174] In a semiconductor device according to one or more embodiments, a vertical channel transistor may include a first gate electrode having a first work function and a second gate electrode having a second work function greater than the first work function. Since the first gate electrode is provided, the vertical channel transistor may have target electrical characteristics. Since the second gate electrode is provided, the breakdown and damage of the gate insulating layer between the first contact plug and the second gate electrode may be reduced. Therefore, the reliability defects of the gate insulating layer may be reduced. Therefore, the characteristics of the vertical channel transistor in the semiconductor device may be improved.

[0175] Each embodiment provided in the above description is not exclusive of being associated with one or more features of another example, nor is it exclusive of being associated with another embodiment provided or not provided herein but consistent with the present disclosure.

[0176] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a channel pattern located on a substrate, the channel pattern comprising a channel pattern sidewall portion extending in a first direction perpendicular to a surface of the substrate and a channel pattern lower portion connecting lower ends of the channel pattern sidewall portions facing each other in a second direction intersecting the first direction; a gate insulating layer, the gate insulating layer being located on a surface of the sidewall portion of the channel pattern and a surface of a lower portion of the channel pattern, the gate insulating layer comprising a gate insulating layer sidewall portion and a gate insulating layer lower portion, the gate insulating layer sidewall portion extending in the first direction, and the gate insulating layer lower portion connecting lower ends of the gate insulating layer sidewall portions facing each other in the second direction, and an upper surface of the gate insulating layer being higher than an uppermost surface of the channel pattern; a first gate electrode, the first gate electrode being located on an inner surface of at least one sidewall portion of the gate insulating layer, the first gate electrode having a first work function; a second gate electrode, the second gate electrode covering a surface of the first gate electrode, and the second gate electrode having a second work function greater than the first work function; as well as a first contact plug, the first contact plug being located on an uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer, Wherein, the uppermost surface of the second gate electrode is higher than the uppermost surface of the channel pattern.

2. The semiconductor device according to claim 1, wherein The channel pattern includes an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein A height difference between an uppermost surface of the first gate electrode and an uppermost surface of the channel pattern is smaller than a height difference between an uppermost surface of the second gate electrode and an uppermost surface of the channel pattern.

4. The semiconductor device according to claim 3, wherein: An uppermost surface of the first gate electrode is coplanar with an uppermost surface of the channel pattern.

5. The semiconductor device according to claim 1, wherein A height difference between an uppermost surface of the first gate electrode and an uppermost surface of the channel pattern is less than 5% of a vertical height of the channel pattern.

6. The semiconductor device according to claim 1, wherein The first contact plug has a third work function equal to or smaller than the first work function.

7. The semiconductor device according to claim 1, wherein The first contact plug includes an upper portion having a first width and a lower portion having a second width smaller than the first width.

8. The semiconductor device according to claim 7, wherein: The lower portion of the first contact plug faces the gate insulating layer and the second gate electrode in the second direction.

9. The semiconductor device according to claim 1, wherein: The gate insulating layer includes a metal oxide having a dielectric constant greater than that of silicon nitride, and Wherein, the first gate electrode comprises metal.

10. The semiconductor device according to claim 1, wherein The first gate electrode comprises titanium or titanium nitride, and Wherein, the second gate electrode includes Ni or Ru.

11. The semiconductor device according to claim 1, further comprising a capacitor located on the first contact plug, in, The capacitor is connected to the first contact plug.

12. The semiconductor device according to claim 1, further comprising a mold insulation structure on an outer surface of the channel pattern, in, An upper surface of the mold insulation structure is higher than an uppermost surface of the channel pattern.

13. A semiconductor device, comprising: a first conductive layer pattern, the first conductive layer pattern being located on the substrate and extending along a first direction parallel to an upper surface of the substrate; a channel pattern, the channel pattern being located on the first conductive layer pattern, the channel pattern comprising a channel pattern sidewall portion and a channel pattern lower portion, the channel pattern sidewall portion extending in a second direction intersecting the first direction, the channel pattern lower portion connecting lower ends of the channel pattern sidewall portions facing each other in the first direction, wherein a lower surface of the channel pattern contacts the first conductive layer pattern; a gate insulating layer, the gate insulating layer being located on the surface of the sidewall portion of the channel pattern and the surface of the lower portion of the channel pattern, the gate insulating layer comprising a gate insulating layer sidewall portion and a gate insulating layer lower portion, the gate insulating layer sidewall portion extending in the second direction, the gate insulating layer lower portion connecting lower ends of the gate insulating layer sidewall portions facing each other in the first direction, and an upper surface of the gate insulating layer being higher than an uppermost surface of the channel pattern; a first gate electrode, the first gate electrode being disposed on an inner surface of at least one sidewall portion of the gate insulating layer, the first gate electrode extending in a third direction intersecting the first direction and parallel to an upper surface of the substrate, the first gate electrode having a first work function; a second gate electrode, the second gate electrode covering a surface of the first gate electrode, the second gate electrode extending in the third direction and having a second work function greater than the first work function; and a first contact plug, the first contact plug being located on an uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer, A height difference between an uppermost surface of the first gate electrode and an uppermost surface of the channel pattern is smaller than a height difference between an uppermost surface of the second gate electrode and an uppermost surface of the channel pattern.

14. The semiconductor device according to claim 13, wherein: An uppermost surface of the second gate electrode is higher than an uppermost surface of the channel pattern.

15. The semiconductor device according to claim 13, wherein: An uppermost surface of the first gate electrode is coplanar with an uppermost surface of the channel pattern.

16. The semiconductor device according to claim 13, wherein: The second gate electrode faces the first contact plug in the first direction.

17. The semiconductor device according to claim 13, wherein: The first contact plug has a third work function equal to or smaller than the first work function.

18. A semiconductor device, comprising: A channel pattern, the channel pattern being located on a substrate and extending in a first direction perpendicular to a surface of the substrate; a gate insulating layer, the gate insulating layer being located on the sidewalls of the channel pattern, and the upper surface of the gate insulating layer being higher than the uppermost surface of the channel pattern; a first gate electrode, the first gate electrode being located on the gate insulating layer, and the first gate electrode having a first work function; a second gate electrode, the second gate electrode covering a surface of the first gate electrode, the second gate electrode having a second work function greater than the first work function; and a first contact plug located on an uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulating layer; Wherein, a lower portion of the first contact plug faces at least a portion of the second gate electrode in a second direction intersecting with the first direction.

19. The semiconductor device according to claim 18, wherein: An uppermost surface of the first gate electrode is coplanar with an uppermost surface of the channel pattern.

20. The semiconductor device according to claim 18, wherein The first contact plug has a third work function equal to or smaller than the first work function.

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