Solar cell and manufacturing method thereof

Abstract

The invention provides a solar cell and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The solar cell comprises a silicon substrate, a semiconductor layer and a transparent conductive layer, the semiconductor layer is formed on the silicon substrate, and the semiconductor layer is of a porous structure; and the transparent conductive layer is positioned on the surface, far away from the silicon substrate, of the semiconductor layer and is in contact with the porous structure. The semiconductor layer has the porous structure, so that the contact area between the semiconductor layer and the transparent conductive layer can be increased, the current transmission characteristic is improved, the energy consumption in the current collection process is reduced, and the cell efficiency is improved.

Description

[0001] This application claims the priority of the Chinese patent application with the application number 202410961507.7 and filed on July 16, 2024. Technical Field

[0002] This application relates to the technical field of semiconductor devices. Specifically, this application relates to a solar cell and a manufacturing method thereof. Background Art

[0003] Heterojunction cells have advantages such as high conversion efficiency and simple process structure. A conventional heterojunction cell deposits an intrinsic amorphous silicon layer on both sides of a silicon substrate, then deposits doped amorphous silicon film layers with different doping types, subsequently prepares a transparent conductive film layer on the doped amorphous silicon film layer, and finally metallizes the surface of the transparent conductive film layer to obtain metal electrodes.

[0004] The current transport resistance has a great influence on the performance of heterojunction cells. In order to reduce the current transport resistance and improve the output performance of the cells, the contact structure between the metal electrode and the transparent conductive film layer can be improved. For example, a seed layer is formed on the surfaces of the metal electrode and the transparent conductive film layer to improve the adhesion, or a new material such as an alloy is used as the metal electrode material. However, there is still a need to further reduce the current transport resistance. Summary of the Invention

[0005] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, this application provides a solar cell and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of this application is as follows:

[0007] According to an embodiment of one aspect of this application, a solar cell is provided, including: a silicon substrate; a semiconductor layer located on the silicon substrate, the semiconductor layer having a porous structure; and a transparent conductive layer located on the surface of the semiconductor layer away from the silicon substrate and in contact with the porous structure.

[0008] According to an embodiment of another aspect of this application, a manufacturing method of a solar cell is provided, including: forming a semiconductor layer on a silicon substrate; performing laser treatment on the semiconductor layer to make the semiconductor layer form a porous structure, the semiconductor layer including at least one of an amorphous silicon layer, nanocrystalline silicon, and microcrystalline silicon; and forming a transparent conductive layer on the surface of the laser-treated semiconductor layer away from the silicon substrate.

[0009] According to the embodiment of this application, the solar cell provided by this application can increase the contact area with the transparent conductive layer due to the porous structure of the semiconductor layer, thereby improving the current transport characteristics, reducing the energy consumption during the current collection process, and improving the cell efficiency.

[0010] According to an embodiment of the present application, the porous structure of the semiconductor layer of the present application is formed by laser treatment of the semiconductor layer. Only an operation of applying laser to the semiconductor layer needs to be added on the basis of the original battery process, which has the advantage of simple operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features and advantages of the present application will become clearer. In the drawings:

[0012] Figure 1 It is a partial structural schematic diagram of the solar cell according to the embodiment of the present application;

[0013] Figure 2A It is a surface scanning electron microscope (SEM) image of the doped amorphous silicon layer according to the embodiment of the present application after the first laser treatment under laser condition 1;

[0014] Figure 2B and Figure 2C are respectively Figure 2A microscopic SEM images of the doped amorphous silicon layer in

[0015] Figures 2D to 2F It is a surface scanning electron microscope (SEM) image of the doped amorphous silicon layer according to the present application after the first laser treatment under laser conditions 2 to 4 respectively;

[0016] Figure 3 It is a contact resistance test result diagram of the doped polycrystalline silicon layer 103 under the action of the first laser according to the embodiment of the present application;

[0017] Figure 4A It is a cross-sectional transmission electron microscope (TEM) image of the doped amorphous silicon layer according to the embodiment of the present application after the first laser treatment under laser condition 1;

[0018] Figure 4B and Figure 4C are respectively Figure 4A locally enlarged TEM images at different positions of

[0019] Figure 4D and Figure 4E are respectively Figure 4A locally enlarged TEM images of different grain parts in

[0020] Figure 5 It is a side view of the overall structure of the solar cell according to the embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of the positional relationship between the edge part and the main part of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer according to the embodiment of the present invention;

[0022] Figure 7Side view of the overall structure of a solar cell according to another embodiment of the present application;

[0023] Figure 8 Schematic diagram of the manufacturing process of a solar cell according to an embodiment of the present application;

[0024] Figures 9A to 9E Schematic diagrams of the preparation process of a solar cell according to still another embodiment of the present application, respectively. Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the following further describes the present application in detail with reference to specific embodiments and the accompanying drawings.

[0026] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0027] Regarding the relative position between two components (such as a film layer or a region) mentioned in the present application, such as "above", "on" or "over", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. Similarly, regarding the relative position between two components mentioned in the present application, such as "below", "under" or "beneath", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. For example, when one component (such as a film layer or a region) is referred to as "on another component", it may be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there are no components between the two. Additionally, when one component is referred to as "on another component", there is an up-and-down relationship between the two in the top-down direction, and this component may be above or below the other component. Therefore, this up-and-down relationship depends on the orientation of the device.

[0028] For a solar cell, in order to reduce the contact resistance and thus improve the cell performance, the contact structure between, for example, a metal electrode and a transparent conductive film layer is usually improved, while less thought is given to improving the contact structure between the transparent conductive film layer and the semiconductor layer. In the process of implementing the concept of this application, it is found that by laser treating an amorphous silicon layer, a porous structure can be formed in the amorphous silicon layer, and further experimental verification shows that after the amorphous silicon layer is laser treated to form a porous structure, the current transmission characteristics between the amorphous silicon layer and the transparent conductive layer can be effectively reduced, thereby improving the cell performance.

[0029] Accordingly, a solar cell based on a semiconductor layer and a transparent conductive layer with an improved structure is proposed. The solar cell of the embodiment of this application mainly includes a silicon substrate, a semiconductor layer, and a transparent conductive layer, where: the semiconductor layer is located on the silicon substrate, and the semiconductor layer has a porous structure; the transparent conductive layer is located on the surface of the semiconductor layer away from the silicon substrate and is in contact with the porous structure. Here, the "semiconductor layer" may be a silicon semiconductor layer, and its material may include at least one of amorphous silicon, microcrystalline silicon, or nanocrystalline silicon, preferably including amorphous silicon. For ease of understanding, the following will take the semiconductor layer as an amorphous silicon layer as an example for illustration, which may include amorphous silicon, and may further include microcrystalline silicon and / or nanocrystalline silicon, etc.

[0030] Specifically, according to an embodiment of one aspect of this application, a solar cell is provided. Figure 1 It is a partial structural schematic diagram of the solar cell of the embodiment of this application. As Figure 1 shown, the solar cell of the embodiment of this application mainly includes a silicon substrate 101, an amorphous silicon layer 102, and a transparent conductive layer 103, where: the amorphous silicon layer 102 is located on the silicon substrate 101, the amorphous silicon layer 102 has a porous structure, and the transparent conductive layer is located on the surface of the amorphous silicon layer 102 away from the silicon substrate 101 and is in contact with the porous structure.

[0031] According to the embodiment of this application, the silicon substrate 101 may be an N-type or P-type crystalline silicon substrate. For example, it may be a semiconductor material such as single-crystalline silicon, polycrystalline silicon, or microcrystalline silicon, preferably an N-type or P-type single-crystalline silicon substrate. The conversion efficiency of the cell based on a single-crystalline silicon substrate is relatively high compared to other types such as polycrystalline silicon cells. By introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) and other elements into these semiconductor materials, an N-type crystalline silicon substrate is obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) and other elements into these semiconductor materials, a P-type crystalline silicon substrate is obtained.

[0032] According to an embodiment of the present application, the amorphous silicon layer 102 may be at least partially doped or undoped. In the case of doping, the doping type may be N-type or P-type, which can be specifically determined according to the battery type and the doping type of the silicon substrate. Similar to the silicon substrate 101, different doping types are obtained by introducing donor impurities or acceptor impurities into the main material of the amorphous silicon layer 102.

[0033] According to an embodiment of the present application, there is no special limitation on the material of the transparent conductive layer 103. For example, a transparent conductive oxide (Transparent Conductive Oxide, abbreviated as TCO) can be used. Specifically, for example, indium tin oxide (ITO), tin oxide doped with tungsten (VTTO), indium oxide doped with tungsten (IWO), indium oxide doped with molybdenum (IMO), or tin fluoride oxide (TOF), etc. are not limited thereto. The transparent conductive layer 103 is conformally formed on the amorphous silicon layer 102 and covers the porous structure of the amorphous silicon layer 102 to form a relatively tight contact with the amorphous silicon layer 102.

[0034] According to an embodiment of the present application, the solar cell type of the present application is mainly applicable to the heterojunction battery type, which may be a double-sided heterojunction (Heterojunction with Intrinsic Thin-layer, abbreviated as HJT) battery, a back-contact heterojunction (Heterojunction Back Contac, abbreviated as HBC) battery, a hybrid HBC battery, such as a hybrid battery combined with TBC (TopCon-BackContact)-HJT, etc. As long as it is a battery using an amorphous silicon layer and a transparent conductive layer, it should be applicable.

[0035] According to an embodiment of the present application, the applicant found through experiments that a porous structure can be formed in the amorphous silicon layer by laser treatment of the amorphous silicon layer. It is speculated that after the laser energy is absorbed by the film layer, the temperature of the film layer rises, resulting in a molten state and causing hydrogen to escape from the film layer, thereby generating a porous structure. Therefore, it is proposed to use laser treatment on the amorphous silicon layer 103 to form a porous structure in the amorphous silicon layer 102. Since the amorphous silicon layer 102 has a porous structure, the contact area with the transparent conductive layer can be increased, thereby reducing the current transmission resistance between the transparent conductive layer 104, reducing the energy loss during current collection, and improving the battery efficiency.

[0036] According to an embodiment of the present application, the amorphous silicon layer 102 may include a second structural layer 102b and a first structural layer 102a sequentially arranged in a direction away from the silicon substrate 101; wherein, the first structural layer 102a is configured to have a first porous structure, and the first porous structure has a plurality of first pores penetrating therethrough, and the plurality of first pores are used to expose the second structural layer.

[0037] For ease of explanation, by way of example, the surface morphology of the amorphous silicon layer 102 is observed by scanning electron microscopy. Figure 2A FIG. is a scanning electron microscopy (SEM) image of the surface of the amorphous silicon layer of the embodiment of the present application after the first laser treatment under laser condition 1; Figure 2B and Figure 2C are respectively Figure 2A the microscopic SEM images of the amorphous silicon layer in FIG. sequentially magnified locally. As Figures 2A to 2C shown, the dark region is the second structural layer 102b, and the light region is the first structural layer 102a, and an obvious porous structure can be seen.

[0038] According to the embodiment of the present application, the through-hole morphology of the first structural layer 102a of the amorphous silicon layer 102 enables the transparent conductive layer 104 to be in contact with the first structural layer 102a and the second structural layer 102b respectively. While increasing the contact area with the transparent conductive layer 104, it is ensured that the process of forming the porous morphology of the first structural layer 102a will not have an adverse impact on the layer structure located below the second structural layer 102b.

[0039] According to the embodiment of the present application, the second structural layer 102b can be non-porous or porous in morphology. Preferably, as Figure 2C shown, the second structural layer 102b is configured to have a second porous structure, and the pore diameter of the second porous structure is smaller than the pore diameter of the first porous structure. Further preferably, as Figure 2C encircled by the circular frame in FIG., the second structural layer 102b has a plurality of second pores, and the plurality of second pores expose from the plurality of first pores, thereby forming a hierarchical nested porous structure between the first structural layer 102a and the second structural layer 102b.

[0040] According to the embodiment of the present application, the second structural layer 102b is configured to have a second porous structure and form a hierarchical nested porous structure with the first structural layer 102a, which can further increase the contact area with the transparent conductive layer 104, thereby helping to reduce the current transmission resistance and achieve an improvement in battery efficiency.

[0041] According to the embodiment of the present application, further optionally, the pore diameter of the first porous structure is less than or equal to 1 μm, for example, it can be a pore diameter of less than 1 μm, less than 0.8 μm, less than 0.5 μm, less than 0.3 μm, less than 0.1 μm, and preferably a pore diameter of less than or equal to 0.3 μm.

[0042] According to the embodiment of the present application, further optionally, the pore diameter of the second porous structure is less than or equal to 300 nm, for example, it can be a pore diameter of less than 0.3 μm, less than 0.1 μm, less than 0.08 μm, less than 0.06 μm, less than 0.04 μm, and preferably a pore diameter of less than or equal to 0.3 μm.

[0043] It should be noted that the "pore diameter" of the first porous structure or the second porous structure refers to the pore diameter range of the main pores of the porous structure. For a single pore, the pore diameter can be the diameter after the shape of the pore along the surface direction is equivalent to a circle. The main pores can be pores that account for more than 50% of all pores, preferably more than 80%, and more preferably more than 90%.

[0044] According to the embodiments of the present application, by controlling the pore diameter of the amorphous silicon layer 102 within the above range, it is more conducive to improving the contact resistance and enhancing the battery efficiency.

[0045] According to the embodiments of the present application, the first structural layer 102a has an island structure formed by being separated by a plurality of first pores. Further optionally, the first pores of the first porous structure are formed in the island structure. It is found through experiments that when the first structural layer 102a has an island structure, it has a lower contact resistance with the transparent conductive layer 103. Preferably, the size of the island structure is less than or equal to 2 μm, which can ensure fewer defects while increasing the current collection efficiency.

[0046] According to the embodiments of the present application, further optionally, the material of the first structural layer 102a may include amorphous silicon, and further may include nanocrystalline silicon, but the possibility of including microcrystalline silicon is less, or so little that it is considered that there is no microcrystalline silicon; the material of the second structural layer 102b may include amorphous silicon.

[0047] According to the embodiments of the present application, for another example Figure 1 As shown, the amorphous silicon layer 102 of the present application may include an intrinsic amorphous silicon layer 1021 and a doped amorphous silicon layer 1022. The intrinsic amorphous silicon layer 1021 is located between the silicon substrate 101 and the doped amorphous silicon layer 1022. When the doping type of the doped amorphous silicon layer 1022 is the same as that of the silicon substrate 101, this film layer structure can be used to form a back surface field. When the doping type of the doped amorphous silicon layer 1022 is different from that of the silicon substrate 101, it can be used to form a P-N junction.

[0048] It can be understood that when the amorphous silicon layer 102 includes the intrinsic amorphous silicon layer 1021, the porous structure of the amorphous silicon layer 102 does not penetrate deep into the intrinsic amorphous silicon layer 1021, but is mainly located in the doped amorphous silicon layer 1022. Thus, it will not have an adverse effect on the passivation effect of the intrinsic amorphous silicon layer 1021.

[0049] According to an embodiment of the present application, further optionally, the thickness of the intrinsic amorphous silicon layer 1021 can be 5 to 30 nm, for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc., and the thickness of the doped amorphous silicon layer 1022 is 10 to 45 nm, for example, it can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc. It should be noted that unless otherwise specified, the "thickness" generally refers to the dimension in the direction perpendicular to the surface of the silicon substrate.

[0050] According to an embodiment of the present application, the thickness of the intrinsic amorphous silicon layer 1021 has a great influence on the contact resistance and the passivation effect. Specifically, on the one hand, the thicker the intrinsic amorphous silicon layer 1021, the higher the contact resistance, the greater the current collection loss, and the lower the battery efficiency; on the other hand, within a suitable thickness range, the thicker the intrinsic amorphous silicon layer 1021, the better the passivation effect, the less carrier recombination, and the higher the battery efficiency. And because the doped amorphous silicon layer 1022 of the present application adopts a porous structure, the contact resistance is reduced, thereby releasing space for thickening the intrinsic amorphous silicon layer 1021 and improving the passivation effect.

[0051] And when the thickness of the doped amorphous silicon layer 1022 is within the above range, on the one hand, since the light intensity absorbed by the film layer decreases exponentially with depth, if the film layer is thicker, when the surface film layer reaches the same high temperature, the interface temperature between the silicon substrate and the intrinsic amorphous silicon layer is lower, and the passivation damage is weaker. Thus, it can be avoided that when the thickness is too thin, the temperature of the silicon substrate 101 and the intrinsic amorphous silicon layer 1021 is too high during laser treatment, resulting in a deterioration of the passivation effect. On the other hand, as the film layer thickens, it helps to slow down heat dissipation and is more conducive to achieving a high temperature on the surface of the film layer.

[0052] According to an embodiment of the present application, the surface of the silicon substrate 101 has a polished area with a pyramid base structure, which can be obtained through texturing and polishing; among them, the amorphous silicon layer 102 is located above the polished area of the silicon substrate 101. Through experiments, it is found that when the surface of the silicon substrate 101 is a polished surface with a pyramid base structure, it is beneficial to the generation of a porous structure, while when the surface is a textured surface, it is difficult to observe the generation of a porous structure. Of course, it is not limited to this, and the surface of the silicon substrate 101 can also be a surface that has not been textured and polished.

[0053] According to an embodiment of the present application, the solar cell of the present application may further include an electrode 104, which is located on the surface of the transparent conductive layer 103. The electrode 104 can be made of materials such as silver, copper, silver-coated copper, aluminum, etc., and is fabricated by patterning through processes such as vacuum evaporation, electroplating, screen printing, etc.

[0054] In some exemplary embodiments, to more clearly illustrate the various film layers of the solar cell of the present application, a single-crystalline silicon wafer is used as the silicon substrate 101, and one surface of the silicon substrate 101 is a polished surface with a pyramid base structure; an intrinsic amorphous silicon layer 1021 and a P-type doped amorphous silicon layer are sequentially deposited on the polished surface of the silicon substrate 101; then, the P-type doped amorphous silicon layer with a thickness of 10 - 40 nm is processed by the first laser under laser condition 1 to form a P-type doped amorphous silicon layer with a porous structure, obtaining a silicon wafer suitable for detection by a scanning electron microscope (SEM), and the detection results are as Figures 2A to 2C shown. Further, an SiN layer and a Pt layer are sequentially deposited on the surface of the doped amorphous silicon layer 1022, obtaining a silicon wafer suitable for detection by a transmission electron microscope (TEM).

[0055] In some other exemplary embodiments, laser condition 1 of the laser used can be adjusted to laser condition 2 to laser condition 4 respectively, and the specific parameters of laser condition 1 to laser condition 4 are shown in Table 1 below, so as to form the corresponding amorphous silicon layer 102 on the silicon substrate 101.

[0056] Table 1

[0057]

[0058] The surface microtopography of the amorphous silicon layer 102 after the action of laser condition 1 to laser condition 4 is observed by a scanning electron microscope. Figures 2D to 2F They are respectively the surface scanning electron microscope (SEM) images of the amorphous silicon layer 102 of the present application after being processed by the first laser under laser condition 2 - 4. As Figures 2A to 2F shown, an obvious layered porous structure is observed in the amorphous silicon layer 102 under different laser conditions. This is because after the laser is absorbed by the film layer, the temperature of the film layer rises, causing hydrogen in the film layer to escape, resulting in a porous structure. Moreover, the porous morphologies under different laser conditions are different.

[0059] Furthermore, as Figures 2A to 2C it can be observed that the porous morphology at the base structure is different from that at other positions. This is because the porous morphology is affected by the laser energy density and the film layer temperature, and the steps at the base edge of the polished surface of the silicon substrate 101 will affect the light path, and thus affect the laser energy density and the film layer temperature. However, the base structure does not affect the overall porous morphology distribution in a larger range.

[0060] As Figures 2C to 2FAs shown, a hierarchical nested morphology of the amorphous silicon layer 102 was observed under laser conditions 1, 3, and 4, that is, there are pores with smaller pore diameters in the second structural layer 102b under the first structural layer 102a. It is difficult to observe the porous structure of the second structural layer 102b in the doped polysilicon layer 103 under laser condition 2, and its pore diameter is much smaller than 0.1 μm, which can be a pore-free morphology.

[0061] The contact resistance of the amorphous silicon layer 102 without laser action and after the first laser action under laser conditions 1 to 4 was tested by current-voltage testing. Specifically, a double-sided symmetric P-type doped amorphous silicon / intrinsic amorphous silicon / P-type doped amorphous silicon / TCO layer / electrode structure was tested, and it was found that the contact resistance of the amorphous silicon layer 102 after the first laser treatment under different laser conditions showed a significant decrease. Figure 3 This is a contact resistance test result diagram of the amorphous silicon layer 102 of the embodiment of the present application after covering the TCO layer and forming a metal electrode under the action of the first laser, showing the contact resistance of the amorphous silicon 102 after the action of the more preferred laser condition 1; the results are as Figure 3 shown. Compared with no laser treatment, the contact resistance of the amorphous silicon layer 102 after the first laser treatment under laser condition 1 showed a significant decrease. And from Figures 2C to 2F the comparison, it can be seen that the amorphous silicon layer 102 after the first laser action under laser condition 1 has the following obvious different structural features compared with other laser conditions, which is beneficial to the reduction of contact resistance, that is: the first structural layer 102a has an island structure formed by being separated by the first pores. Further, some of the first pores are formed in the island structure.

[0062] The cross-sectional micro-morphology of the amorphous silicon 102 after the action of laser conditions 1 to 4 was observed by transmission electron microscopy. Figure 4A This is a cross-sectional transmission electron microscopy (TEM) diagram of the doped amorphous silicon layer of the embodiment of the present application after the first laser treatment under laser condition 1. Figure 4B and Figure 4C are Figure 4A local enlarged TEM diagrams at different positions of Figure 4D and Figure 4E are local enlarged TEM diagrams of different grain parts in Figure 4A respectively, where SiN is the protective layer used during the test. As Figures 4A to 4E shown, although the porous morphology at the cross-section is not obvious, it can still be observed that the morphology of the amorphous silicon layer 102 has changed after the first laser treatment, and a hierarchical structure has occurred in the P-type doped amorphous silicon layer, that is, the first structural layer 102a and the second structural layer 102b, as Figure 4BThe rectangular frame shown outlines the intrinsic amorphous silicon layer 1021 (i.e., i-a-Si) and the second structural layer 102b (i.e., p-a-Si). Above the rectangular frame is the first structural layer 102a (i.e., p-a-Si). As Figure 4B and Figure 4C shown, circular grain portions can be observed in the first structural layer 102a. As Figure 4D and 4E shown, an ordered lattice structure can be observed in the grain portions, indicating that partial crystallization has occurred in the amorphous silicon of the first structural layer 102a, and this ordered lattice structure is nanocrystalline silicon. It can be seen that the material of the first structural layer 102a can include, in addition to the remaining amorphous silicon, crystallized nanocrystalline silicon. This is where laser treatment of the amorphous silicon layer is superior to treating the nanocrystalline silicon layer and the microcrystalline silicon layer. In this way, partial crystallization of the amorphous silicon layer can be achieved to obtain a current collection effect similar to that of the nanocrystalline silicon layer and the microcrystalline silicon layer, while also taking into account the advantages of the fast deposition rate and low cost of the amorphous silicon layer.

[0063] According to an embodiment of the present application, taking a double-sided heterojunction battery as an example, the solar cell of the present application will be further explained. Figure 5 is a side view of the overall structure of the solar cell according to an embodiment of the present application. As Figure 5 shown, the silicon substrate 101 includes opposite first surface 101a and second surface 101b. The amorphous silicon layer 102 includes a first-type doped amorphous silicon layer 1022a located on the first surface 101a of the silicon substrate 101. The solar cell further includes a second-type doped amorphous silicon layer 1022b located on the second surface 101b of the silicon substrate 101. Here, the doping types of the first type and the second type are opposite. For example, the first-type doped amorphous silicon layer 1022a can be an N-type doped amorphous silicon layer, then the second-type doped amorphous silicon layer 1022b can be a P-type doped amorphous silicon layer, or the polarities of the two can be interchanged. Preferably, the silicon substrate 101 is an N-type substrate, and the first-type doped amorphous silicon layer 1022a is a P-type.

[0064] Figure 6 is a schematic diagram of the positional relationship between the edge portion and the main body portion of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer according to an embodiment of the present invention. As Figure 6 shown, the first-type doped amorphous silicon layer 1022a and / or the second-type doped amorphous silicon layer 1022b respectively include a main body portion A and an edge portion B surrounding the periphery of the main body portion. The main body portion A has a porous structure, and the edge portion B has a non-porous structure. Since the edge portion B is thinner and has more defects, and the electron-hole recombination rate is relatively large, by setting the edge portion B to have a non-porous structure, on the one hand, the damage caused by, for example, laser treatment to the thinner edge portion can be reduced to ensure the passivation effect, and on the other hand, the defects of the edge portion can be further isolated to inhibit the recombination of carriers.

[0065] According to an embodiment of the present application, further preferably, the first surface 101a of the silicon substrate 101 is a polished surface with a pyramid base structure, which can be used as a backlight surface. The first-type doped amorphous silicon layer 1022a has a porous structure, that is, the main part A has a porous structure and the edge part B has a non-porous structure; the second surface 101b of the silicon substrate 101 is a textured surface with a pyramid structure, which can be used as a light-receiving surface, and the second-type doped amorphous silicon layer 1022b has a non-porous structure. Thus, a higher light utilization rate can be achieved on the light-receiving surface. At the same time, the contact resistance can be reduced on the backlight surface, thereby improving the battery efficiency.

[0066] According to an embodiment of the present application, further, the solar cell of the present application may further include a first transparent conductive layer 103a and a second transparent conductive layer 103b. The first transparent conductive layer 103a is located away from the first surface 101a of the silicon substrate 101 in the first-type doped amorphous silicon layer 1022a and is in contact with the porous structure of the main part A in the first-type doped amorphous silicon layer 1022a; the second transparent conductive layer 103b is located away from the second surface 101b of the silicon substrate 101 in the second-type doped amorphous silicon layer 1022b.

[0067] According to an embodiment of the present application, further, the solar cell of the present application may further include a first intrinsic amorphous silicon layer 1021a, a second intrinsic amorphous silicon layer 1021b, a first electrode 104a and a second electrode 104b. The first intrinsic amorphous silicon layer 1021a is located between the silicon substrate 101 and the first-type doped amorphous silicon layer 1022a and forms an amorphous silicon layer 102 with the first-type doped amorphous silicon layer 1022a. The second intrinsic amorphous silicon layer 1021b is located between the silicon substrate 101 and the second-type doped amorphous silicon layer 1022b and forms another amorphous silicon layer 102' with the second-type doped amorphous silicon layer 1022b; the first electrode 104a is located on the first transparent conductive layer 103a, and the second electrode 104b is located on the second transparent conductive layer 103b.

[0068] According to an embodiment of the present application, taking the hybrid back contact heterojunction battery as an example, the solar cell of the present application is further explained. Figure 7 It is a side view of the overall structure of the solar cell according to another embodiment of the present application, as Figure 7 shown, the silicon substrate 101 includes opposite first surface 101a and second surface 101b. The first surface includes a first region 101a' and a second region 101a'' which are arranged at intervals; the amorphous silicon layer 102 includes a first-type doped amorphous silicon layer 1022a, which is located in the first region 101a' of the silicon substrate 101; the solar cell further includes a second-type doped polycrystalline silicon layer 1023, which is located in the second region 101a'' of the silicon substrate 101.

[0069] Among them, the first-type doped amorphous silicon layer 1022a extends over the second-type doped polysilicon layer 1023 to form an overlap with the second-type doped polysilicon layer 1023, and the overlapping portion between the first-type doped amorphous silicon layer 1022a and the second-type doped polysilicon layer 1023 has a pore-free structure. The position corresponding to the overlapping portion here is the position circled by the rectangular frame. It can be understood that other portions of the first-type doped amorphous silicon layer 1022a except the overlapping portion have a porous structure. By setting the first-type doped amorphous silicon layer 1022a at the overlapping portion to have a pore-free structure, it helps to improve the leakage current between the first-type doped amorphous silicon layer 1022a and the second-type doped polysilicon layer 1023.

[0070] According to an embodiment of the present application, further, the solar cell of the present application includes a transparent conductive layer 103, which is located on the surface of the first region 101a' of the first-type doped amorphous silicon layer 1022a facing away from the silicon substrate 101 and the surface of the second region 101a" of the second-type doped polysilicon layer 1023 facing away from the silicon substrate 101, and is in contact with the porous structure in the first-type doped amorphous silicon layer 1022a. It can be understood that the transparent conductive layer 103 here is a patterned layer structure.

[0071] According to an embodiment of the present application, the solar cell of the present application further includes an intrinsic amorphous silicon layer 1021, a tunneling oxide layer 105, and an electrode 104. Among them, the intrinsic amorphous silicon layer 1021 is located between the silicon substrate 101 and the first-type doped amorphous silicon layer 1022a, the tunneling oxide layer 105 is located between the silicon substrate 101 and the second-type doped polysilicon layer 1023, and the electrode 104 is located on the transparent conductive layer 103. A heterojunction can be formed by the intrinsic amorphous silicon layer 1021, the first-type doped amorphous silicon layer 1022a, and the silicon substrate 101, and a tunneling oxide passivation structure can be formed by the tunneling oxide layer 105 and the second-type doped polysilicon layer 1023.

[0072] According to an embodiment of the present application, the intrinsic amorphous silicon layer 1021 extends over the second-type doped polysilicon layer 1023 to form an overlap with the second-type doped polysilicon layer 1023. At this time, the intrinsic amorphous silicon layer 1021 located between the first-type doped amorphous silicon layer 1022a and the second-type doped polysilicon layer 1023 is used to play an insulating role. If the thickness of the intrinsic amorphous silicon layer 1021 is thinner, the lateral wall thickness of the intrinsic amorphous silicon layer 1021 is thinner, resulting in a worse insulating effect, and thus a larger leakage current, reducing the battery efficiency. Among them, "lateral" is the direction from the side wall of the first-type doped amorphous silicon layer 1022a to the side wall of the second-type doped polysilicon layer 1023.

[0073] On this basis, since the porous structure of the first-type doped amorphous silicon layer 1022a helps to reduce the contact resistance, thus releasing space for thickening the intrinsic amorphous silicon layer 1021, both the passivation effect and the leakage situation are improved. As a result, the contact resistance, the passivation effect and the suppression of leakage are taken into account, and the battery efficiency reaches a remarkable effect of being relatively excellent.

[0074] According to an embodiment of the present application, in the solar cell as Figure 7 shown, the tunneling oxide layer 105 can be replaced by the intrinsic amorphous silicon layer 1021, and the second-type doped polysilicon layer 1023 can be replaced by the second-type doped amorphous silicon layer 1022b. The solar cell formed thereby is of the HBC cell type.

[0075] According to an embodiment of the present application, the solar cell of the present application further includes a passivation and antireflection layer, which is formed on the second surface 101b of the silicon substrate 101 for surface passivation and at the same time improving the light utilization rate. As Figure 7 shown, the passivation and antireflection layer may sequentially include, for example, a third intrinsic amorphous silicon layer 106 and a silicon nitride layer 107, but is not limited thereto. For example, it may also include silicon nitride (SiNx) or an alumina / SiNx stacked film, etc.

[0076] According to some embodiments of the present application, a manufacturing method of a solar cell is further provided. Figure 8 is a schematic diagram of the manufacturing process of the solar cell according to the embodiment of the present application. As Figure 8 shown, the manufacturing method of the solar cell according to the embodiment of the present application mainly includes operations S801 to S803.

[0077] In operation S801, a semiconductor layer is formed on the silicon substrate.

[0078] In operation S802, the semiconductor layer is processed by a first laser to form a porous structure.

[0079] In operation S803, a transparent conductive layer is formed on the surface of the semiconductor layer that has been laser-processed and is away from the silicon substrate. The meaning of "semiconductor layer" is the same as described above, and the following further illustrates with the semiconductor layer being an amorphous silicon layer as an example.

[0080] According to an embodiment of the present application, the present application uses a laser to process the amorphous silicon layer, so that the amorphous silicon layer forms a porous structure. Only an operation of applying a laser to the amorphous silicon layer needs to be added on the basis of the original battery process, which has the advantage of simple operation.

[0081] According to an embodiment of the present application, the wavelength of the laser is 325 - 532 nm, for example, it can be 325 nm, 350 nm, 400 nm, 450 nm, 500 nm, 532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200 - 6000 mJ / cm 2 , for example, it can be 200 mJ / cm 2 , 500 mJ / cm 2 , 1000 mJ / cm 2 , 2000 mJ / cm 2 , 3000 mJ / cm 2 , 4000 mJ / cm 2 , 5000 mJ / cm 2 , 6000 mJ / cm 2 etc., and the laser overlap rate is 60% - 95%, for example, it can be 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%.

[0082] According to an embodiment of the present application, in order to further understand the overall manufacturing process of the solar cell of the present application, taking the specific method of preparing a hybrid back - contact heterojunction cell as shown in Figure 7 as an example for illustration. Figures 9A to 9E are respectively schematic diagrams of the manufacturing process of the solar cell according to another embodiment of the present application. As shown in Figures 9A to 9E , the manufacturing method of the solar cell according to the embodiment of the present application includes operations S901 - S905.

[0083] In operation S901, a tunneling oxide layer 905 and a p - type doped polysilicon layer 9023 are formed on the first surface 901a of the silicon substrate 901.

[0084] In operation S902, the tunneling oxide layer 905 and the p - type doped polysilicon layer 9023 are patterned, and the tunneling oxide layer 905 and the p - type doped polysilicon layer 9023 remaining on the second region 901a” of the first surface 901a are retained.

[0085] In operation S903, the other regions of the first surface 901a except the second region 901a” are textured and polished to obtain a polished surface with a pyramid base structure.

[0086] In operation S904, an intrinsic amorphous silicon layer 9021 and a first-type doped amorphous silicon layer 9022a are sequentially formed on the polishing surface, and the first-type doped amorphous silicon layer 9022a is processed using a first laser; preferably, the boundary of the processing does not reach the boundary of the adjacent second-type doped polysilicon layer 9023, and there is a certain distance between the boundary of the first laser processing the first-type doped amorphous silicon 9022a and the boundary of the second-type doped polysilicon 9023, for example, it can be 50 - 200 microns.

[0087] In operation S905, a patterned transparent conductive layer 903 and an electrode 904 are fabricated on the surfaces of the first-type doped amorphous silicon layer 903a and the second-type doped polysilicon layer 9023 that have been laser processed.

[0088] According to an embodiment of the present application, as Figure 9A shown, in operation S901, it may specifically include: (1) Polishing: Double-sided polishing is performed on the silicon substrate 901 to make its surface flat and smooth. (2) First chemical vapor deposition (CVD1): A tunneling oxide layer 905 and a polysilicon or amorphous silicon layer 9031 are sequentially deposited on the first surface 901a of the silicon substrate 901 that has been double-sided polished using a chemical vapor deposition method. The deposition conditions are not the key of the present application and will not be elaborated here. (3) Doping: A diffusion process is used to transform the polysilicon or amorphous silicon layer 9031 into a second-type doped polysilicon layer 9023. The diffusion conditions are not the key of the present application and will not be elaborated here.

[0089] It can be understood that different doping types and diffusion processes will form different doping sources 9032 on the surface of the second-type doped polysilicon layer 9023. For example, a phosphorus diffusion process will form phosphosilicate glass on the surface of the second-type doped polysilicon layer 9023, and a boron diffusion process will form borosilicate glass on the surface of the second-type doped polysilicon layer 9023.

[0090] According to an embodiment of the present application, as Figure 9B shown, in operation S902, it may specifically include:

[0091] (1) First wet treatment (Wet 1): The doping source 9032 is removed by wet method, for example, phosphosilicate glass or borosilicate glass can be removed through an acid pickling process.

[0092] (2) Second chemical vapor deposition (CVD2): A mask layer 908 is deposited on the surface of the second-type doped polysilicon layer 9023 that is far from the silicon substrate 101 using a chemical vapor deposition method. For example, a silicon nitride layer can be deposited. The deposition conditions are not the key of the present application and will not be elaborated here.

[0093] (3)Second laser treatment (laser2): Use a second laser to perform laser film opening on the tunneling oxide layer 905, the second-type doped polysilicon layer 9023, and the mask layer 908, and remove the tunneling oxide layer 905 and the second-type doped polysilicon layer 9023 on the remaining regions other than the second region 901a” on the first surface 901a. The laser film opening conditions are not the key of this application and will not be elaborated here.

[0094] According to an embodiment of the present application, as Figure 9C shown, in operation S903, it may specifically include:

[0095] (1)Second wet treatment (wet process 2): Adopt a double-sided texturing method to perform wet texturing on the other regions of the first surface 901a except the second region 901a” and the second surface 901b of the silicon substrate. For example, wet texturing can be performed using an alkali tank device.

[0096] (2)Second chemical vapor deposition (CVD2-2): Use chemical vapor deposition method to deposit a passivation and antireflection layer on the second surface 901b of the silicon substrate 901 that has been wet textured. For example, deposit a third intrinsic amorphous silicon layer 906 and a silicon nitride layer 907 in sequence.

[0097] (3)Second wet treatment (wet process 2-2): Use a chain device to perform alkali polishing on the other regions of the first surface 901a except the second region 901a” to obtain a polished surface, and use a chain device to acid wash and remove the mask layer on the surface of the second-type doped polysilicon layer 9023.

[0098] According to an embodiment of the present application, as Figure 9D shown, in operation S904, it may specifically include:

[0099] (1)Third chemical vapor deposition (CVD3): Use chemical vapor deposition method to deposit an intrinsic amorphous silicon layer 9021 and a first-type doped amorphous silicon layer 9022a on the polished surface of the silicon substrate 901 and the surface of the second-type doped polysilicon layer 9023 in sequence. Through the intrinsic amorphous silicon layer 9021, an isolation region can be formed between the first-type doped amorphous silicon layer 9022a and the second-type doped polysilicon layer 9023, playing an insulating role.

[0100] (2) Laser and third wet treatment: First, use the third laser to remove part of the intrinsic amorphous silicon layer 9021 and the first-type doped amorphous silicon layer 9022a on the surface of the second-type doped polysilicon layer 9023. Among them, an overlap is formed between the remaining first-type doped amorphous silicon layer 9022a and the second-type doped polysilicon layer 9023, and this overlapping part can reduce the damage to the second-type doped polysilicon layer 9023 when the transparent conductive layer of the isolation region is opened in the subsequent process. Secondly, use the first laser to process the remaining part of the first-type doped amorphous silicon layer 9022a except for the overlapping part, so that the first-type doped amorphous silicon layer 9022a forms a porous structure. Thirdly, use pickling to remove the silicon oxide formed on the film surface after the action of the third laser and the first laser.

[0101] According to an embodiment of the present application, as Figure 9E shown, in operation S905, it specifically includes: Physical Vapor Deposition (PVD): Use physical vapor deposition to deposit the transparent conductive layer 903 on the exposed surface of the second-type doped polysilicon layer 9023 and the exposed surface of the first-type doped amorphous silicon layer 9022a processed by the first laser. The deposition conditions are not the key of this application and will not be elaborated here.

[0102] According to an embodiment of the present application, continue as Figure 9E shown, after operation S905, it may further include:

[0103] (1) Insulation treatment (TCO insulation): Remove the transparent conductive layer 903 at the isolation position between the first-type doped amorphous silicon layer 9022a and the second-type doped polysilicon layer 9023. For example, it can be removed by laser film opening.

[0104] (2) Screen printing: Use screen printing to make the electrode 904 on the transparent conductive layer 903, and obtain a solar cell with the structure as Figure 7 shown.

[0105] According to an embodiment of the present application, the solar cell obtained by the above manufacturing method is based on the porous structure of the first-type doped amorphous silicon, reducing the contact resistance with the transparent conductive layer, thereby releasing space for thickening the intrinsic amorphous silicon layer. Thus, the effects of contact resistance, passivation effect, and leakage current can be taken into account, optimizing the cell efficiency.

[0106] The specific embodiments described above further elaborate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application and are not used to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that: The solar cell comprises: Silicon substrate; a semiconductor layer, located on the silicon substrate, the semiconductor layer having a porous structure, and comprising at least one of an amorphous silicon layer, nanocrystalline silicon and microcrystalline silicon; and The transparent conductive layer is located on the surface of the semiconductor layer away from the silicon substrate and is in contact with the porous structure.

2. The solar cell according to claim 1, characterized in that The semiconductor layer comprises a second structure layer and a first structure layer which are sequentially arranged in a direction away from the silicon substrate; The first structural layer is configured to have a first porous structure having a plurality of first pores arranged therethrough, and the plurality of first pores are used to expose at least a portion of the second structural layer.

3. The solar cell according to claim 2, characterized in that: The second structural layer is configured to have a second porous structure, and a pore size of the second porous structure is smaller than a pore size of the first porous structure.

4. The solar cell according to claim 3, characterized in that: The second porous structure includes a plurality of second pores, and the plurality of second pores are exposed from the plurality of first pores.

5. The solar cell according to claim 2, characterized in that: The first structure layer has an island structure separated by the plurality of first pores.

6. The solar cell according to claim 5, characterized in that: Part of the first pores is formed in the isolated island structure, and / or the size of the isolated island structure is less than or equal to 2 μm.

7. The solar cell according to claim 3, characterized in that: The pore size of the first porous structure is less than or equal to 1 μm, and the pore size of the second porous structure is less than or equal to 300 nm.

8. The solar cell according to any one of claims 2 to 7, characterized in that The material of the first structure layer includes amorphous silicon and nanocrystalline silicon, and the material of the second structure layer includes amorphous silicon.

9. The solar cell according to claim 1, characterized in that: The surface of the silicon substrate has a polishing area containing a pyramid base structure; Wherein, the semiconductor layer is located on the polishing area of ​​the silicon substrate.

10. The solar cell according to claim 1, characterized in that: The semiconductor layer comprises: An intrinsic amorphous silicon layer and a doped amorphous silicon layer, wherein the intrinsic amorphous silicon layer is located between the silicon substrate and the doped amorphous silicon layer; Wherein, the thickness of the intrinsic amorphous silicon layer is 5-30 nm, and the thickness of the doped amorphous silicon layer is 10-45 nm.

11. The solar cell according to any one of claims 1 to 7, 9 to 10, characterized in that: The solar cell is a double-sided heterojunction cell or a back-contact heterojunction cell.

12. The solar cell according to claim 11, characterized in that: The silicon substrate comprises a first surface and a second surface opposite to each other; The semiconductor layer includes a first-type doped amorphous silicon layer located on the first surface of the silicon substrate; The solar cell further comprises a second type doped amorphous silicon layer located on the second surface of the silicon substrate; The first-type doped amorphous silicon layer and / or the second-type doped amorphous silicon layer respectively include a main body portion and an edge portion surrounding the main body portion, the main body portion has a porous structure, and the edge portion has a non-porous structure.

13. The solar cell according to claim 11, characterized in that: The silicon substrate comprises a first surface and a second surface opposite to each other, wherein the first surface comprises a first region and a second region spaced apart from each other; The semiconductor layer includes a first-type doped amorphous silicon layer located in the first region of the silicon substrate; The solar cell further comprises a second type doped polysilicon or amorphous silicon layer located in the second region of the silicon substrate; Among them, the first type doped amorphous silicon layer extends onto the second type doped polysilicon or amorphous silicon layer to overlap with the second type doped polysilicon or amorphous silicon layer, and the first type doped amorphous silicon in the overlapping part between the first type doped amorphous silicon layer and the second type doped polysilicon or amorphous silicon layer is a non-porous structure.

14. A method for manufacturing a solar cell, characterized in that: The manufacturing method comprises: forming a semiconductor layer on a silicon substrate; Using a first laser to process the semiconductor layer, so that the semiconductor layer forms a porous structure; A transparent conductive layer is formed on the surface of the semiconductor layer processed by laser away from the silicon substrate.

15. The manufacturing method according to claim 14, characterized in that: The wavelength of the laser is 325-532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200-6000 mJ / cm 2 .

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