Solar cell and manufacturing method thereof

Abstract

The invention provides a solar cell and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The solar cell comprises a silicon substrate and a semiconductor layer, the silicon substrate comprises a first surface and a second surface which are opposite, the semiconductor layer is located on the first surface, the first semiconductor layer comprises a second structural region and a first structural region, and the crystallization degree of the first structural region is larger than that of the second structural region; wherein the second structural region is closer to the first surface than the first structural region, and the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon. The semiconductor layer has a crystallization structure, and the contact resistance between the semiconductor layer and the conductive material layer can be reduced, so that the current transmission characteristic is improved, the energy consumption in the current collection process is reduced, and the cell efficiency is improved.

Description

[0001] This application claims priority to a Chinese patent application with application number 202410961507.7 filed on July 16, 2024, a Chinese patent application with application number 202411131776.7 filed on August 16, 2024, and a Chinese patent application with application number 202411132114.1 filed on August 16, 2024, respectively. Technical Field

[0002] This application relates to the technical field of semiconductor devices. Specifically, this application relates to a solar cell and a manufacturing method thereof. Background Art

[0003] Heterojunction cells have advantages such as high conversion efficiency and simple process structure. A conventional heterojunction cell deposits an intrinsic amorphous silicon layer on both sides of a silicon substrate, then deposits doped amorphous silicon film layers with different doping types, subsequently prepares a transparent conductive film layer on the doped amorphous silicon film layer, and finally metallizes the surface of the transparent conductive film layer to obtain metal electrodes.

[0004] The current transport resistance has a great influence on the performance of heterojunction cells. In order to reduce the current transport resistance and improve the output performance of the cells, the contact structure between the metal electrodes and the transparent conductive film layer can be improved. For example, a seed layer is formed on the surfaces of the metal electrodes and the transparent conductive film layer to improve the adhesion, or a new material such as an alloy is used as the metal electrode material. However, there is still a need to further reduce the current transport resistance. Summary of the Invention

[0005] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, this application provides a solar cell and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of this application is as follows:

[0007] According to an embodiment of one aspect of this application, a solar cell is provided, including: a silicon substrate including opposite first and second surfaces; a first semiconductor layer located on the first surface of the silicon substrate, the first semiconductor layer including a second structure region and a first structure region, the crystallization degree of the first structure region being greater than that of the second structure region; wherein, the second structure region is closer to the first surface than the first structure region, and the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon.

[0008] According to an embodiment of another aspect of the present application, a method for manufacturing a solar cell is provided, including: forming a semiconductor layer on a silicon substrate, wherein the material of the semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon; processing the semiconductor layer with a first laser so that the crystallization degree of at least a part of the semiconductor layer becomes larger to form a crystallized region; wherein, the semiconductor layer located in the crystallized region includes a second structure region and a first structure region, and the crystallization degree of the first structure region is greater than that of the second structure region; wherein, the second structure region is closer to the first surface than the first structure region.

[0009] According to the embodiment of the present application, for the solar cell provided by the present application, since partial crystallization occurs in the semiconductor layer, it can help reduce the contact resistance, release space for thickening the intrinsic silicon layer, so that while the energy loss during the current collection process is reduced, the passivation effect provided by the intrinsic silicon layer is improved, thereby improving the cell efficiency.

[0010] According to the embodiment of the present application, the crystallized structure of the semiconductor layer of the present application is formed by processing the semiconductor layer with a laser, and only an operation of applying a laser to the semiconductor layer needs to be added on the basis of the original process of the cell, which has the advantage of simple operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0012] Figure 1 is a partial structural schematic diagram of the solar cell according to the embodiment of the present application;

[0013] Figure 2 is a partial structural schematic diagram of the solar cell according to another embodiment of the present application

[0014] Figure 3A is a cross-sectional transmission electron microscope (TEM) image of the doped amorphous silicon layer according to the embodiment of the present application after being processed by the first laser under laser condition 1;

[0015] Figure 3B and Figure 3C are respectively Figure 4A local enlarged TEM images at different positions of

[0016] Figure 3D and Figure 3E are respectively Figure 4A local enlarged TEM images of different grain parts in

[0017] Figure 4A is a surface scanning electron microscope (SEM) image of the doped amorphous silicon layer according to the embodiment of the present application after being processed by the first laser under laser condition 1;

[0018] Figure 4B and Figure 4C are respectively Figure 4A the sequentially locally enlarged microscopic SEM images of the doped amorphous silicon layer in

[0019] Figures 4D to 4F the surface scanning electron microscope (SEM) images of the doped amorphous silicon layer of this application after the first laser treatment under laser conditions 2 to 4;

[0020] Figure 5A is the cross-sectional transmission electron microscope (TEM) image of the amorphous silicon layer of another embodiment of this application after the first laser treatment under laser condition 1;

[0021] Figure 5B is Figure 4A the locally enlarged TEM image of the grain part on the tip of the tower in

[0022] Figure 5C is Figure 5A the top-view TEM image of the amorphous silicon layer of

[0023] Figure 6A is the surface SEM image of the amorphous silicon layer of yet another embodiment of this application after the first laser treatment under laser condition 1;

[0024] Figure 6B is the cross-sectional TEM image of the amorphous precious layer of yet another embodiment of this application after the first laser treatment under laser condition 1;

[0025] Figure 7 is the side view of the overall structure of the solar cell of yet another embodiment of this application;

[0026] Figure 8 is the top-view schematic diagram of the positional relationship between the edge part and the main part of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer of yet another embodiment of this application;

[0027] Figure 9 is the side view of the overall structure of the solar cell of yet another embodiment of this application;

[0028] Figure 10 is the top-view schematic diagram of the positional relationship between the first-type doped amorphous silicon layer and the second-type doped polycrystalline silicon layer of yet another embodiment of this application;

[0029] Figure 11A is the schematic diagram of the manufacturing process of the solar cell of the embodiment of this application;

[0030] Figure 11B is the test result diagram of the contact resistance of the doped polycrystalline silicon layer 103 under the action of the first laser of the embodiment of this application;

[0031] Figures 12A to 12ESchematic diagram of the preparation process of a solar cell according to another embodiment of the present application. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0033] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0034] Regarding the relative positions between two components (such as film layers or regions) mentioned in the present application, such as "above", "on", or "over", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. Similarly, regarding the relative positions between two components mentioned in the present application, such as "below", "under", or "beneath", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. For example, when one component (such as a film layer or region) is referred to as "on another component", it may be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there are no components between the two. Additionally, when one component is referred to as "on another component", there is an up-down relationship between the two in the top-down view direction, and this component may be above or below the other component, so this up-down relationship depends on the orientation of the device.

[0035] For a solar cell, in order to reduce the contact resistance and thus improve the cell performance, usually the contact structure between, for example, a metal electrode and a transparent conductive film layer is improved, and less thought is given to improving the contact structure of the semiconductor layer. During the process of implementing the concept of the present application, it is found that by performing laser treatment on the semiconductor layer on a silicon substrate, crystallization modification of the semiconductor layer can be achieved, such that the semiconductor layer exhibits a specific crystallization morphology in the direction away from the surface of the silicon substrate. Through further experimental verification, after performing laser treatment on the semiconductor layer to form a specific crystallization morphology, the current transmission characteristics between the semiconductor layer and a conductive material layer, such as a transparent conductive layer or a metal electrode layer, can be effectively improved, thereby improving the cell performance.

[0036] Specifically, according to an embodiment of an aspect of the present application, a solar cell is provided. Figure 1 It is a partial structural schematic diagram of the solar cell according to the embodiment of the present application. Figure 2 It is a partial structural schematic diagram of the solar cell according to another embodiment of the present application. As Figure 1 and Figure 2 shown, the solar cell according to the embodiment of the present application mainly includes a silicon substrate 101 and a first semiconductor layer 102. The silicon substrate includes an opposite first surface 101a and a second surface. The first semiconductor layer 102 is located on the first surface 101a. The first semiconductor layer 102 includes a second structural region 102b and a first structural region 102a. The crystallization degree of the first structural region 102a is greater than that of the second structural region 102b. Among them, the second structural region 102b is closer to the first surface 101a than the first structural region 102a. The first semiconductor layer 102 includes at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon.

[0037] It should be noted that the "crystallization degree" is used to characterize the crystallization rate, grain size and grain number. Generally speaking, the greater the crystallization degree, the greater its crystallization rate, grain size and / or grain number. For example, when the first semiconductor layer is a nanocrystalline silicon layer (the nanocrystalline silicon layer generally still contains a part of amorphous silicon inside, which is inevitable and the content of the amorphous silicon part is small, which is well known in the art), the first structural region 102a with a greater crystallization degree has a greater crystallization rate and / or grain size than the second structural region 102b. When the first semiconductor layer is an amorphous silicon layer (the amorphous silicon inside may contain a small amount of nanocrystalline silicon part, but the content of the nanocrystalline silicon part is very small, for example, less than 5%, which is well known in the art), grains with ordered lattices will be generated inside the first structural region 102a with a greater crystallization degree, and its crystallization degree increases, while the second structural region 102b with a smaller crystallization degree is still an amorphous silicon material and has no grains generated after being treated by laser or the like. For the sampling of the crystallization degree, since the sampling in the region with a greater crystallization degree is also local, rather than in the entire laser treatment region, the sampling area should be a square region with an area greater than or equal to 5μm * 5μm, and the crystallization degree within such an area region is compared.

[0038] Preferably, the crystallization rate of the second structural region 102b is greater than or equal to 10%, and / or the difference between the crystallization rate of the second structural region and the crystallization rate of the first structural region is less than or equal to 10%. A greater crystallization rate of the second structural region 102b can ensure a smaller contact resistance, and the difference between the crystallization rate of the second structural region and the crystallization rate of the first structural region can achieve the transmission continuity of the first semiconductor layer and increase the current collection efficiency.

[0039] According to an embodiment of the present application, the first structural region 102a and / or the second structural region 102b may be located on at least a part of the first surface of the silicon substrate 101, that is, may cover the first surface 101a of the silicon substrate 101, as Figure 1 shown, or located on a partial region of the first surface 101a of the silicon substrate 101, for example, on the tip of at least one pyramid structure of the silicon substrate 101 circled by a dashed line, as Figure 2 shown.

[0040] Furthermore, the first structural region 102a and the second structural region 102b may be determined according to the obvious stratification of the crystallization degree of the first semiconductor layer 102. For example, the first structural region 102a contains nanocrystalline silicon, while the second structural region 102b may not contain or not significantly contain nanocrystalline silicon. For example, it can be defined that when the crystallization rate is lower than 5%, preferably lower than 1%, it is not significantly containing nanocrystalline silicon. Of course, the first structural region 102a and the second structural region 102b may also be determined according to the material stratification of the first semiconductor layer 102. For example, when the first semiconductor layer 102 is an amorphous silicon layer, it can be stratified by intrinsic silicon and doped silicon.

[0041] According to an embodiment of the present application, the silicon substrate 101 may be an N-type or P-type crystalline silicon substrate. For example, it may be a semiconductor material such as single-crystalline silicon, polycrystalline silicon, or microcrystalline silicon. Preferably, it is an N-type or P-type single-crystalline silicon substrate. The conversion efficiency of the battery based on the single-crystalline silicon substrate is relatively high compared to other types such as polycrystalline silicon batteries. By introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) and other elements into these semiconductor materials, an N-type crystalline silicon substrate is obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) and other elements into these semiconductor materials, a P-type crystalline silicon substrate is obtained.

[0042] According to an embodiment of the present application, the first semiconductor layer 102 may be at least partially doped or undoped, and in the case of doping, the doping type may be N-type or P-type, which can be specifically determined according to the battery type and the doping type of the silicon substrate. Similar to the silicon substrate 101, different doping types are obtained by introducing donor impurities or acceptor impurities into the main material of the first semiconductor layer 102.

[0043] According to embodiments of the present application, the type of solar cell of the present application is mainly applicable to heterojunction cell types, which may be double-sided heterojunction (Heterojunction with Intrinsic Thin-layer, abbreviated as HJT) cells, back-contact heterojunction (Heterojunction Back Contac, abbreviated as HBC) cells, hybrid HBC cells, such as hybrid cells combined with TBC (TopCon-BackContact)-HJT, etc. As long as it is a cell that needs to improve the contact performance between the first semiconductor layer and the conductive material layer, it should be applicable.

[0044] According to embodiments of the present application, the applicant found through experiments that by laser-treating the first semiconductor layer, the degree of crystallization of some regions of the first semiconductor layer away from the silicon substrate can be increased, which is beneficial to reducing the contact resistance of the first semiconductor layer. And the first semiconductor layer with a smaller degree of crystallization can ensure the passivation effect of the first semiconductor layer, that is, the balance between contact resistance and passivation effect is taken into account.

[0045] According to embodiments of the present application, the second structural region preferably includes a first intrinsic silicon layer with a thickness of 5 to 30 nm, such as 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, 18 nm, 20 nm, 25 nm, 28 nm, 30 nm, etc., and preferably a first intrinsic silicon layer with a thickness of 8 to 20 nm. Due to the reduction of the contact resistance of the first semiconductor layer 102, space is provided for releasing the thickness of the first intrinsic silicon layer, which helps to improve the passivation effect of the first intrinsic silicon layer, thereby improving the cell efficiency.

[0046] According to embodiments of the present application, there are multiple grains in the first semiconductor layer 102, and the maximum size of the multiple grains is less than the thickness of the first semiconductor layer 102.

[0047] In terms of grain size, the first part of the first semiconductor layer 102 contains grains, and the maximum size of the grains can be equal to the thickness of the first part. At this time, the first part of the first semiconductor layer 102 has high conductivity, which can further reduce the transmission loss of the carriers collected in the first semiconductor layer 102 to the conductive material. In the actual manufacturing process, the larger the grain size in the first part of the first semiconductor layer 102, the higher the temperature during the crystallization treatment of the first part of the first semiconductor layer 102, which in turn leads to a larger amount of hydrogen overflow in the first semiconductor 102, reducing the passivation effect of the second structural region 102b on the silicon substrate. Therefore, when the grain size in the first part of the first semiconductor layer 102 is smaller than the thickness of the first part, the crystallization temperature corresponding to the first semiconductor layer 102 is lower, so that the part of the first semiconductor layer 102 where no grains grow has the effect of passivating the semiconductor substrate, which is conducive to balancing the passivation effect and transmission loss corresponding to the first semiconductor layer 102 and further improving the working performance of the solar cell.

[0048] According to an embodiment of the present application, the material of the second structural region 102b includes intrinsic amorphous silicon, and the material of the first structural region 102a includes amorphous silicon and nanocrystalline silicon, but the possibility of including microcrystalline silicon is less, or so little that it is considered that there is no microcrystalline silicon. Thus, the crystallization rate of the first structural region 102a is greater than that of the second structural region 102b, so as to balance the improvement of the passivation effect and the contact resistance. Further optionally, the material of the first structural region 102a includes amorphous silicon and nanocrystalline silicon with a grain size of 5 to 25 nm (for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, etc.).

[0049] According to an embodiment of the present application, the first surface 101a of the silicon substrate 101 can be a polished area with a pyramid base structure or a textured area with a pyramid structure, and the morphology of the first semiconductor layer 102 formed on different areas is different, specifically manifested in differences in the crystallization structure and porous morphology.

[0050] Specifically, as Figure 1 shown, taking the first surface 101a of the silicon substrate 101 having a polished area with a pyramid base structure as an example, when the first semiconductor layer 102 is formed on the polished area, the crystallization structure is mainly located in the part of the first semiconductor layer 102 away from the first surface 101a. At this time, the first structural region 102a and the second structural region 102b can be determined according to the morphology and / or material of the first semiconductor layer 102. The morphological division basis can be, for example, the crystallized and non-crystallized structures, and the material can be, for example, intrinsic silicon and doped silicon, etc.

[0051] Further optionally, the first structural region 102a and the second structural region 102b may be determined according to the obvious stratification of the crystallization degree of the first semiconductor layer 102. At this time, the second structural layer 102b may include an intrinsic silicon layer, and further may include a part of a doped silicon layer, and the first structural layer 102a may include at least a part of the doped silicon layer.

[0052] Of course, the first structural region 102a and the second structural region 102b may also be stratified according to intrinsic silicon and doped silicon. Since for the polished region, the crystallized structure of the amorphous silicon layer 102 is mainly located in the doped silicon layer, it is also considered that the crystallization degree of the first structural region 102a is greater than that of the second structural region 102b.

[0053] Exemplarily, taking the first semiconductor layer 102 as an amorphous silicon layer as an example, the cross-sectional microscopic morphology of the first semiconductor layer 102 after the action of the first laser is observed by using a transmission electron microscope. Specifically, first, a first intrinsic amorphous silicon layer (abbreviated as i-a-Si) and a P-type doped amorphous silicon layer (abbreviated as p-a-Si) are sequentially deposited on the polished surface of the silicon substrate 101; then, the P-type doped amorphous silicon layer with a thickness of 10-40 nm is processed by the first laser under laser condition 1 to form a P-type doped amorphous silicon layer with a porous structure. Then, SiN and Pt layers are sequentially deposited on the surface of the P-type doped amorphous silicon layer to obtain a silicon wafer suitable for detection by a transmission electron microscope (TEM). Figure 3A It is a cross-sectional transmission electron microscope (TEM) image of the amorphous silicon layer of the embodiment of the present application after being processed by the first laser under laser condition 1. Figure 3B and Figure 3C is Figure 3A a local enlarged TEM image at different positions of Figure 3D and Figure 3E is respectively Figure 3A a local enlarged TEM image of different grain parts in , where SiN is the protective layer used during testing.

[0054] As Figures 3A to 3E shown, it can be observed that the first semiconductor layer 102 has undergone partial crystallization after the first laser treatment and a layered structure has been generated, that is, the first structural region 102a and the second structural region 102b. As Figure 3B shown, the rectangular frame circles the second structural region 102b (i.e., i, p-a-Si), and above the rectangular frame is the first structural region 102a (i.e., p-a-Si). As Figure 3B and Figure 3C shown, circular grain parts can be observed in the first structural region 102a. As Figure 3D and 3EThe ordered lattice structure can be observed in the shown grain part, indicating that partial crystallization has occurred in the amorphous silicon of the first structural region 102a, and this ordered lattice structure is nanocrystalline silicon. It can be seen that the material of the first structural region 102a can include, in addition to the remaining amorphous silicon, the crystallized nanocrystalline silicon. This is where laser treatment of the amorphous silicon layer is superior to treating the nanocrystalline silicon layer and the microcrystalline silicon layer. In this way, partial crystallization of the amorphous silicon layer can be achieved to realize a current collection effect similar to that of the nanocrystalline silicon layer and the microcrystalline silicon layer, while taking into account the advantages of the fast deposition rate and low cost of the amorphous silicon layer.

[0055] Preferably, the crystallization degree of the first structural region 102a and the second structural region 102b is gradually changed, that is, along the first surface of the first semiconductor layer 102 away from the silicon substrate, the crystallization degree gradually increases, and the grain size also gradually increases.

[0056] According to an embodiment of the present application, the first semiconductor layer 102 located on the polishing region can form a porous structure while undergoing crystallization, that is, the first semiconductor layer 102 located on the polishing region can further have a porous structure, thereby increasing the contact area between the first semiconductor layer 102 and the conductive material layer, which helps to further improve the current transmission characteristics of the first semiconductor layer 102. Further optionally, the first structural region 101a has a porous structure, and the second structural region 102b has a porous structure or is a non-porous structure, which is beneficial to the contact with the conductive material layer.

[0057] Further optionally, for another example Figure 1 As shown, the solar cell of the present application may further include a transparent conductive layer 103, as the aforementioned conductive material layer, located on the surface of the first semiconductor layer 102 away from the silicon substrate 101. The transparent conductive layer 103 can be in contact with the porous structure of the first semiconductor layer 102. Specifically, it can be in contact with the porous structure of the first structural region 101a to increase the contact area and improve the current transmission performance between the first semiconductor layer 102 and the transparent conductive layer 103. The transparent conductive layer 103 completely covers the first structural region 102a, so that the region with a larger crystallization degree completely coincides with the transparent conductive layer 103, resulting in a smaller contact resistance.

[0058] According to an embodiment of the present application, through appropriate laser processing conditions, a porous structure can be formed in a partial region of the first semiconductor layer 101. It is speculated that after the laser energy is absorbed by the film layer, the temperature of the film layer increases, resulting in a molten state and causing hydrogen in the film layer to escape, thereby generating a porous structure. Therefore, it is proposed to use laser to process the first semiconductor layer 102, so as to form a porous structure in the first semiconductor layer 102. Since the first semiconductor layer 102 has a porous structure, the contact area with the transparent conductive layer 103 can be increased, thereby reducing the current transmission resistance between the first semiconductor layer 102 and the transparent conductive layer 103, reducing the energy loss during current collection, and improving the battery efficiency.

[0059] According to an embodiment of the present application, the first structural region 102a has a first porous structure, and the second structural region 102b has a second porous structure. The pore size of the second porous structure is smaller than that of the first porous structure. Since the pore structure will weaken the passivation effect and reduce the current collection efficiency of the solar cell, by setting the pore size of the second porous structure to be smaller than that of the first porous structure, while improving the contact performance of the first semiconductor layer 102, the passivation effect of the first semiconductor layer 102 can be ensured.

[0060] Further optionally, the first porous structure has a plurality of first pores arranged therethrough, and the second porous structure includes a plurality of second pores, and the plurality of second pores are exposed from the plurality of first pores. The through-hole morphology of the first structural region 102a enables the transparent conductive layer 103 to be in contact with the first structural region 102a and the second structural region 102b respectively. While increasing the contact area with the transparent conductive layer 104, it is ensured that the process of forming the porous morphology of the first structural region 102a will not have an adverse effect on the layer structure under the second structural region 102b. Such a setting is more conducive to taking into account the improvement of contact performance and passivation effect.

[0061] For ease of explanation, taking the first semiconductor layer 102 as an amorphous silicon layer as an example, the surface morphology of the first semiconductor layer 102 is observed by scanning electron microscopy. Figure 4A FIG. is a surface scanning electron microscope (SEM) image of the amorphous silicon layer of the embodiment of the present application after the first laser treatment under laser condition 1; Figure 4B and Figure 4C are respectively Figure 4A successively partial enlarged microscopic SEM images of the amorphous silicon layer in Figures 4A to 4C . As shown in

[0062] According to an embodiment of the present application, the second structural region 102b may be non-porous or porous in morphology. Preferably, as shown in Figure 4CAs shown, the second structural region 102b is configured to have a second porous structure, and the pore size of the second porous structure is smaller than that of the first porous structure. Further preferably, as shown by the circular frame in Figure 4C the second structural region 102b has a plurality of second pores that are exposed from the plurality of first pores, thereby forming a hierarchical nested porous structure between the first structural region 102a and the second structural region 102b.

[0063] According to an embodiment of the present application, the second structural region 102b is configured to have a second porous structure and form a hierarchical nested porous structure with the first structural region 102a, which can further increase the contact area with the transparent conductive layer 103, thereby helping to reduce the current transmission resistance and achieve an improvement in battery efficiency.

[0064] According to an embodiment of the present application, further optionally, the pore size of the first porous structure is less than or equal to 1 μm, for example, it can be a pore size of less than 1 μm, less than 0.8 μm, less than 0.5 μm, less than 0.3 μm, or less than 0.1 μm, and preferably less than or equal to 0.3 μm.

[0065] According to an embodiment of the present application, further optionally, the pore size of the second porous structure is less than or equal to 300 nm, for example, it can be a pore size of less than 0.3 μm, less than 0.1 μm, less than 0.08 μm, less than 0.06 μm, or less than 0.04 μm, and preferably less than or equal to 0.3 μm.

[0066] It should be noted that the "pore size" of the first porous structure or the second porous structure refers to the pore size range of the main pores of the porous structure. For a single pore, the pore size can be the diameter after the shape of the pore along the surface direction is equivalent to a circle. The main pores can be pores that account for more than 50% of all pore numbers, preferably more than 80%, and more preferably more than 90%.

[0067] According to an embodiment of the present application, by controlling the pore size of the first semiconductor layer 102 within the above range, it is more beneficial to improve the contact resistance and enhance the battery efficiency.

[0068] According to an embodiment of the present application, the first surface 101a of the silicon substrate 101 can be a matte region having a plurality of pyramid structures, as shown in Figure 2 The first structural region 102a and the second structural region 102b are located on a partial region of the first surface 101a, and further, it can be determined according to material stratification. For example, the first structural region 102a is an intrinsic silicon layer, and the second structural region 102b is a doped silicon layer, and the crystallization degree of the doped silicon layer is greater than that of the intrinsic silicon layer.

[0069] Further, along the direction away from the first surface 101a, the pyramid structure includes a tower base portion 1011 and a tower tip portion 1012; wherein both the first structure region 102a and the second structure region 102b are located on the tower tip portion 1012, and the crystallization degree of the second structure region 102b located on the tower tip portion 1012 is greater than the crystallization degree of the first semiconductor layer 102 located on the tower base portion 1011.

[0070] Exemplarily, taking the first semiconductor layer 102 as an amorphous silicon layer as an example, a transmission electron microscope is used to observe the cross-sectional microscopic morphology of the first semiconductor layer 102 after the action of the first laser. Specifically, a first intrinsic amorphous silicon layer (abbreviated as i-a-Si) and a P-type doped amorphous silicon layer (abbreviated as p-a-Si) are sequentially deposited on the textured surface of the silicon substrate 101; then the P-type doped amorphous silicon layer with a thickness of 10-40 nm is processed by the first laser under laser condition 1 to form a P-type doped amorphous silicon layer with a crystallized structure. Then, SiN and Pt layers are sequentially deposited on the surface of the P-type doped amorphous silicon layer to obtain a silicon wafer suitable for detection by a transmission electron microscope (TEM). Figure 5A The cross-sectional transmission electron microscope (TEM) image of the amorphous silicon layer of another embodiment of the present application after being processed by the first laser under laser condition 1, Figure 5B is Figure 5A the partial enlarged TEM image of the grain part on the tower tip portion in Figure 5C is Figure 5A the top-down TEM image of the amorphous silicon layer of

[0071] As Figure 5A and Figure 5B shown, it can be observed that the first semiconductor layer 102 has undergone partial crystallization after the first laser treatment, and a crystallization structure different from that shown in Figures 3A to 3B is generated, that is, the crystallization degree mainly increases in the first semiconductor layer 102 on the tower tip portion 1012, further including nanocrystalline silicon, and it can still be observed that the crystallization degree (i.e., crystallization rate, grain number, and grain size) of the first structure region 102a is greater than the crystallization degree of the second structure region 102b. As Figure 5A encircles the first semiconductor layer 102 located on the tower tip portion 1012, and circular grain parts can be observed. As Figure 5BThe grain part of the first semiconductor layer 102 located at the tip of the tower can observe an ordered lattice structure, indicating that partial crystallization has occurred in the amorphous silicon located on the tip 1012, and this ordered lattice structure is nanocrystalline silicon. Similarly, it is also found that the partial crystallization of the first semiconductor layer 102 can help improve the current collection effect. Among them, the thickness of the first structural region 102a can be more than 25 nm, that is, it can be more than 25 nm away from the surface of the silicon substrate pyramid in the thickness direction of the first semiconductor layer 102, and it only contains a doped silicon layer; the thickness of the second structural region 102b can be 15 nm or less, that is, it can be 15 nm or less close to the surface of the silicon substrate pyramid in the thickness direction of the first semiconductor layer 102. Preferably, there is no obvious interface between the first structural region 102a and the second structural region 102b in the pyramid structure (the same is true for the tip having a hole structure), such as Figure 5A , along the surface of the pyramid away from the silicon substrate, the degree of crystallization of the first semiconductor layer 102 gradually increases, and the grain size also gradually increases.

[0072] According to the embodiments of the present application, through experiments, it is found that when the surface of the silicon substrate 101 is a polished surface with a pyramid base structure, it is beneficial to the generation of the porous structure of the first semiconductor layer 102 thereon, while when the surface is a matte surface, it is difficult to observe the generation of the porous structure. However, by selecting appropriate laser processing conditions, it is still possible to control the formation of a porous structure in a specific region of the first semiconductor layer 102 on the first surface when it is a matte surface.

[0073] Further optionally, the first semiconductor layer 102 located on the tip 1012 can form a porous structure or a non-porous structure while undergoing crystallization. The first semiconductor layer 102 with a non-porous structure is more easily obtained through laser processing, such as Figure 5C shown, no obvious porous structure is observed in the first semiconductor layer 102 located at the tip.

[0074] Further optionally, as Figure 5C shown, the first semiconductor layer 102 located on the pyramid structure has a side surface extending from the top to the bottom; among them, in the extending direction of the side surface, the ratio between the maximum extending length L1 of the first semiconductor layer located on the tip on the side surface and the length L2 of the side surface is less than or equal to 0.3, for example, it can be 0.05, 0.1, 0.15, 0.2, 0.25 or 0.3, etc. By setting it like this, while the first semiconductor layer located at the base of the tower mainly plays a passivation effect, the first semiconductor layer located at the tip can be used to optimize the contact performance.

[0075] In other embodiments, by selecting appropriate laser processing conditions, a porous structure 102c can be formed in the first semiconductor layer 102 located on the tip portion 1012. The first semiconductor layer 102 having the porous structure 102c is more conducive to further increasing the contact area between the first semiconductor layer 102 and the transparent conductive layer, which helps to further improve the current transmission characteristics of the first semiconductor layer 102.

[0076] According to the embodiments of the present application, in order to further illustrate the porous structure of the first semiconductor layer 102 of the present application, Figure 6A FIG. is a surface SEM image of the doped amorphous silicon layer according to another embodiment of the present application after the first laser treatment under laser condition 1; Figure 6B FIG. is a cross-sectional TEM image of the doped amorphous silicon layer according to still another embodiment of the present application after the first laser treatment under laser condition 1.

[0077] As Figure 6A and Figure 6B shown, at least one hole included in the porous structure is a blind hole that does not penetrate the first semiconductor layer 102. Since a part of the first semiconductor layer 102 corresponding to the blind hole still retains a part of the thickness, it is possible to passivate a part of the surface of the silicon substrate 101, and the improvement of both the current transmission performance and the passivation effect can be taken into account. Further optionally, the aperture of at least one hole included in the porous structure 102c is less than 100 nm, for example, it can be less than or equal to 80 nm, less than or equal to 60 nm, less than or equal to 50 nm, etc. Again, as Figure 6A shown, the first semiconductor layer located on the pyramid structure has a side surface extending from the tip portion to the bottom portion of the tower; wherein, along the extending direction of the side surface, the ratio of the distribution length L1 of the porous structure 102c on the side surface to the length L2 of the side surface is less than or equal to 0.5. For example, it can be 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, etc. By setting it like this, while the first semiconductor layer located at the tower base mainly plays a passivation effect, the first semiconductor layer located at the tip portion can be used to optimize the contact performance.

[0078] Again, as Figure 6B shown, the thickness of the part of the first semiconductor layer 102 where the porous structure 102c is not provided is greater than or equal to 10 nm; and / or, the thickness of the part of the first semiconductor layer 102 where the porous structure is not provided is less than or equal to 45 nm. For example, the thickness of the first semiconductor layer can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc.

[0079] On the one hand, since the light intensity absorbed by the film layer decreases exponentially with depth, if the film layer is thicker, when the surface film layer reaches the same high temperature, the interface temperature between the silicon substrate and the first semiconductor layer 102 is lower, and the passivation damage is weaker. Therefore, it is possible to avoid the deterioration of the passivation effect caused by the excessive temperature of the silicon substrate 101 and the first semiconductor layer 102 when using laser treatment when the thickness is too thin. On the other hand, as the film layer thickens, it helps to slow down heat dissipation and is more conducive to achieving high temperature on the surface of the film layer.

[0080] According to an embodiment of the present application, for another example Figure 1 and Figure 2 As shown, the solar cell may further include an electrode 104, and the electrode 104 is located on the surface of the transparent conductive layer 103. The electrode 104 may be made of, for example, silver, copper, silver-coated copper, aluminum, etc., and is formed by patterning through processes such as vacuum evaporation, electroplating, screen printing, etc.

[0081] According to an embodiment of the present application, along the direction parallel to the first surface 101a, the first semiconductor layer 102 includes a main body portion and an edge portion adjacent to the periphery of the main body portion, and the crystallization degree of the main body portion is greater than that of the edge portion. Here, "adjacent" means that the main body portion and the edge portion are in contact, so as to form the first semiconductor layer 102 as a whole.

[0082] Exemplarily, taking the main body portion as a strip or rectangle extending along the first direction as an example, the edge portion may be distributed on both side edges of the main body portion along the first direction, or may be distributed on both side edges of the main body portion in the second direction perpendicular to the first direction, or may surround the periphery of the main body portion to form an annular shape.

[0083] With such a setting, on the one hand, it is possible to reduce the damage caused by, for example, laser treatment to the thinner edge portion to ensure the passivation effect, and on the other hand, it is possible to further isolate the defects of the edge portion and suppress the recombination of carriers.

[0084] According to an embodiment of the present application, taking a double-sided heterojunction battery as an example, the solar cell of the present application is further explained. Figure 7 The side view of the overall structure of the solar cell according to another embodiment of the present application is as shown in Figure 1 and Figure 7 As shown, the silicon substrate 101 includes opposite first surface 101a and second surface 101b. Among them, the first surface 101a of the silicon substrate 101 is a polished surface with a pyramid base structure and can be used as the backlight surface. At this time, the first structural region 102a includes a first-type doped amorphous silicon layer 1021a, which is located on the first surface 101a of the silicon substrate 101, and the second structural region 102b includes a first intrinsic amorphous silicon layer 1021b, which forms an amorphous silicon layer with the first-type doped amorphous silicon layer 1021a, and the amorphous silicon layer serves as the first semiconductor layer 102.

[0085] According to an embodiment of the present application, the thickness of the first-type doped amorphous silicon layer 1021a is 10 to 45 nm, and for example, it can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc.

[0086] Among them, when the thickness of the first-type doped amorphous silicon layer 1021a is within the above range, on the one hand, since the light intensity absorbed by the film layer decreases exponentially with depth, if the film layer is thicker, when the surface film layer reaches the same high temperature, the interface temperature between the silicon substrate and the first intrinsic amorphous silicon layer is lower, and the passivation damage is weaker. Thus, it can avoid the deterioration of the passivation effect caused by the excessive temperature of the silicon substrate 101 and the first intrinsic amorphous silicon layer 1021b when using laser treatment when the thickness is too thin. On the other hand, as the film layer thickens, it helps to slow down heat dissipation and is more conducive to achieving a high temperature on the film surface.

[0087] According to an embodiment of the present application, the solar cell further includes a second intrinsic amorphous silicon layer 1022b and a second-type doped amorphous silicon layer 1022a sequentially disposed on the second surface 101b, and the two form another amorphous silicon layer, that is, as the second semiconductor layer 102'. The second semiconductor layer 102' may or may not adopt a crystallization structure similar to that of the first semiconductor layer 102. Here, the doping types of the first type and the second type are opposite. For example, if the first-type doped amorphous silicon layer 1021a is an N-type doped amorphous silicon layer, then the second-type doped amorphous silicon layer 1022a can be a P-type doped amorphous silicon layer, or the polarities of the two can be interchanged.

[0088] Since the nanocrystalline silicon is mainly located in the doped silicon layer, the crystallization structure of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer is further described. Figure 8 It is a top view schematic diagram of the positional relationship between the edge part and the main part of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer according to another embodiment of the present application. As Figure 8As shown, the first semiconductor layer 102 entirely covers the first surface 101a, or the second semiconductor layer 102' entirely covers the second surface 101b. From a top-down perspective, it can be observed that the corresponding first-type doped amorphous silicon layer 1021a and / or the second-type doped amorphous silicon layer 1022a each include a main body portion A and an edge portion B surrounding the periphery of the main body portion. The edge portion B is in an annular shape. Further optionally, the main body portion A contains nanocrystalline silicon, and the edge portion B does not contain nanocrystalline silicon, so that the degree of crystallization of the main body portion A is greater than that of the edge portion B. Since the edge portion B is thinner and has more defects, and the electron-hole recombination rate is relatively high, by setting the edge portion B to not contain nanocrystalline silicon, on the one hand, it is possible to reduce the damage caused by, for example, laser treatment to the thinner edge portion B to ensure the passivation effect, and on the other hand, it is possible to further isolate the defects in the edge portion and suppress the recombination of carriers.

[0089] Further optionally, the main body portion A is mainly located in the electrode contact region of the solar cell, while the edge portion B is mainly located in the non-electrode contact region of the solar cell, so that the degree of crystallization of the electrode contact region is greater than that of the non-electrode contact region, which is more conducive to improving the current transmission characteristics of the doped amorphous silicon layer. Here, the "electrode contact region" refers to the region where the electrode can contact the doped amorphous silicon layer.

[0090] According to an embodiment of the present application, when the first surface 101a of the silicon substrate 101 is a textured surface with pyramid structures, the above-described structural settings of the edge portion and the main body portion are equally applicable and will not be elaborated here.

[0091] According to an embodiment of the present application, further preferably, the second surface 101b of the silicon substrate 101 is a textured surface with pyramid structures and can serve as the light-receiving surface. The second-type doped amorphous silicon layer 1022b may or may not contain nanocrystalline silicon. Among them, when the second-type doped amorphous silicon layer 1022b contains nanocrystalline silicon, a crystallization structure similar to that shown in Figure 2 、 Figure 5A and Figure 5B is obtained. Thus, a higher light utilization rate can be achieved on the light-receiving surface, and at the same time, the contact resistance can be reduced on the backlight surface, thereby improving the battery efficiency.

[0092] According to an embodiment of the present application, further, the solar cell of the present application may further include a first transparent conductive layer 103a and a second transparent conductive layer 103b. The first transparent conductive layer 103a is located on the surface of the first-type doped amorphous silicon layer 1021a away from the silicon substrate 101; the second transparent conductive layer 103b is located on the surface of the second-type doped amorphous silicon layer 1022a away from the silicon substrate 101.

[0093] According to an embodiment of the present application, further, the solar cell of the present application may further include a first electrode 104a and a second electrode 104b. The first electrode 104a is located on the first transparent conductive layer 103a, and the second electrode 104b is located on the second transparent conductive layer 103b.

[0094] According to an embodiment of the present application, taking the hybrid back contact heterojunction cell as an example, the solar cell of the present application will be further explained. Figure 9 It is a side view of the overall structure of the solar cell according to another embodiment of the present application. Figure 10 It is a top view schematic diagram of the positional relationship between the first-type doped amorphous silicon layer and the second-type doped polycrystalline silicon layer according to another embodiment of the present application. As Figure 9 and Figure 10 shown, the silicon substrate 101 includes opposite first surface 101a and second surface 101b, and includes first region 101a' and second region 101a'' which are spaced apart. The first region 101a' is a polished region with a pyramid base structure; the first semiconductor layer 102 is located in the first region 101a' of the silicon substrate 101; the solar cell further includes a second semiconductor layer 102', which is located in the second region 101a'' of the silicon substrate 101, and the second semiconductor layer 102' has a different conductivity type from the first semiconductor layer 102.

[0095] Wherein, the first semiconductor layer 102 extends above the second semiconductor layer 102' to overlap with the second semiconductor layer 102' to form an overlapping portion C. The first semiconductor layer 102 of the overlapping portion C belongs to the edge portion B. The position corresponding to the overlapping portion C here is the position circled by the rectangular frame. By setting the first semiconductor layer 102 at the overlapping portion to have a lower crystallization degree than the main body portion, it helps to improve the leakage between the first semiconductor layer 102 and the second semiconductor layer 102', and at the same time can also increase the reverse conduction voltage, providing a larger reverse voltage for preventing hot spots.

[0096] According to an embodiment of the present application, as Figure 10 shown, the first semiconductor layer 102 and the second semiconductor layer 102' are respectively strip-shaped portions extending in the first direction, and are alternately distributed in the second direction perpendicular to the first direction. The first semiconductor layer 102 may further include edge portions B distributed along the two side edges of the first semiconductor 102 in the first direction, which together with the overlapping portion C form an annular shape surrounding the periphery of the main body portion A.

[0097] According to an embodiment of the present application, in the direction from the main body portion A to the edge portion B, the width of the edge portion is less than or equal to 500 μm. With such a setting, by reducing the width of the edge portion as much as possible, the area of the main body portion is increased, the contact resistance is reduced, and the current collection ability is improved. And preferably, the width of the edge portion is greater than or equal to 100 μm to ensure that the laser does not affect the performance of other layers due to precision problems, for example, it will irradiate the boundary position of the second semiconductor layer.

[0098] According to an embodiment of the present application, when the first region 101a' of the silicon substrate 101 is a matte region with a pyramid structure, the above-described structure of the overlapping portion is equally applicable and will not be elaborated here.

[0099] According to an embodiment of the present application, the solar cell of the present application may further include a transparent conductive layer 103, which is located on the surface of the first-type doped amorphous silicon layer 1021a facing away from the first region 101a' of the silicon substrate 101 and on the surface of the second-type doped polycrystalline silicon layer 1023 facing away from the second region 101a" of the silicon substrate 101. It can be understood that the transparent conductive layer 103 here is a patterned layer structure.

[0100] According to an embodiment of the present application, by way of example, as Figure 9 and Figure 10 shown, taking the first structural region 102a of the first semiconductor layer 102 including the first-type doped amorphous silicon layer 1021a and the second semiconductor layer 102' including the second-type doped polycrystalline silicon layer 1023 as an example, the solar cell of the present application further includes a first intrinsic amorphous silicon layer 1021b, a tunneling oxide layer 105, and an electrode 104, where the first intrinsic amorphous silicon layer 1021b is located between the silicon substrate 101 and the first-type doped polycrystalline silicon layer 1021a, the tunneling oxide layer 105 is located between the silicon substrate 101 and the second-type doped polycrystalline silicon layer 1023, and the electrode 104 is located on the transparent conductive layer 103. A heterojunction can be formed by the first intrinsic amorphous silicon layer 1021b, the first-type doped amorphous silicon layer 1021a, and the silicon substrate 101, and a tunneling oxide passivation structure can be formed by the tunneling oxide layer 105 and the second-type doped polycrystalline silicon layer 1023.

[0101] According to an embodiment of the present application, there is no special limitation on the material of the transparent conductive layer 103. For example, a transparent conductive oxide (Transparent Conductive Oxide, abbreviated as TCO) can be used. Specifically, for example, it can be indium tin oxide (ITO), tungsten-doped tin oxide (VTTO), indium tungsten oxide (IWO), indium molybdenum oxide (IMO), or tin fluoride oxide (TOF), etc., and is not limited thereto. The transparent conductive layer 103 is conformally formed on the first semiconductor layer 102 and covers the porous structure of the first semiconductor layer 102 to form a relatively tight contact with the first semiconductor layer 102.

[0102] According to an embodiment of the present application, the first intrinsic amorphous silicon layer 1021b extends over the second-type doped polysilicon layer 1023. At this time, the first intrinsic amorphous silicon layer 1021b located between the first-type doped amorphous silicon layer 1021a and the second-type doped polysilicon layer 1023 is used to play an insulating role. If the thickness of the first intrinsic amorphous silicon layer 1021b is thinner, the lateral wall thickness of the first intrinsic amorphous silicon layer 1021b is thinner, resulting in a worse insulating effect, and thus a larger leakage current, reducing the battery efficiency. The "lateral direction" is the direction from the side wall of the first-type doped amorphous silicon layer 1021a to the side wall of the second-type doped polysilicon layer 1023.

[0103] According to some embodiments of the present application, a method for manufacturing a solar cell is further provided. Figure 11A It is a schematic flowchart of the manufacturing process of the solar cell according to the embodiment of the present application, as Figure 11A shown, the method for manufacturing the solar cell according to the embodiment of the present application mainly includes operations S1101 to S1103.

[0104] In operation S1101, a semiconductor layer is formed on the first surface of the silicon substrate. The meaning of the "semiconductor layer" is the same as described above, and hereinafter, the semiconductor layer is taken as an amorphous silicon layer as an example for further illustration.

[0105] In operation S1102, the semiconductor layer is processed by a first laser to increase the crystallization degree of at least a part to form a crystallized region.

[0106] Among them, the semiconductor layer located in the crystallized region includes a second structure region and a first structure region, and the crystallization degree of the first structure region is greater than that of the second structure region; among them, the second structure region is closer to the first surface than the first structure region.

[0107] According to an embodiment of the present application, the present application uses a laser to process the amorphous silicon layer, so that part of the amorphous silicon layer forms a porous structure or crystallizes. Only an operation of applying a laser to the amorphous silicon layer needs to be added on the basis of the original battery process, which has the advantage of simple operation.

[0108] According to an embodiment of the present application, by using the crystallization of the semiconductor layer, the intrinsic silicon layer in the semiconductor layer is thickened to a thickness of 8 to 20 nm, for example, it can be 8 nm, 10 nm, 13 nm, 15 nm, 18 nm, 20 nm.

[0109] According to an embodiment of the present application, the wavelength of the first laser is 325 to 532 nm, for example, it can be 325 nm, 350 nm, 400 nm, 450 nm, 500 nm, 532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200 to 6000 mJ / cm2 , for example, it can be 200 mJ / cm 2 , 500 mJ / cm 2 , 1000 mJ / cm 2 , 2000 mJ / cm 2 , 3000 mJ / cm 2 , 4000 mJ / cm 2 , 5000 mJ / cm 2 , 6000 mJ / cm 2 etc. The laser overlap rate is 60% - 95%, for example, it can be 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%.

[0110] In some exemplary embodiments, the laser conditions of the lasers used can be adjusted to laser condition 1 to laser condition 4 respectively, and the specific parameters of laser condition 1 to laser condition 4 are shown in Table 1 below.

[0111] Table 1

[0112]

[0113] The contact resistance of the amorphous silicon layer without laser action and after the first laser action under laser condition 1 to laser condition 4 respectively is tested by current - voltage test. Specifically, for the double - sided symmetric P - type doped amorphous silicon / intrinsic amorphous silicon / P - type doped amorphous silicon / TCO layer / electrode structure, it is found that the contact resistance of the amorphous silicon layer after the first laser treatment under different laser conditions all shows a relatively obvious decrease. Figure 11B This is the contact resistance test result diagram of the amorphous silicon layer covered with a TCO layer and formed with a metal electrode after the first laser action in the embodiment of the present application, showing the contact resistance of the amorphous silicon layer after the action of the more preferred laser condition 1; the result is as Figure 11B shown. Compared with no laser treatment, the contact resistance of the amorphous silicon layer after the first laser treatment under laser condition 1 shows a relatively obvious decrease. This is because the generation of a crystallized structure is observed in the amorphous silicon layer after the first laser treatment.

[0114] According to the embodiment of the present application, along the direction parallel to the first surface, the semiconductor layer includes a main body part and an edge part adjacent to the periphery of the main body part; operation S1102 specifically includes: irradiating the main body part of the semiconductor layer with a first laser, so that the crystallization degree of the main body part is greater than that of the edge part, and the crystallization degree of the first structure region in the main body part is greater than that of the second structure region.

[0115] According to an embodiment of the present application, the semiconductor layer is amorphous silicon. Operation S1102 specifically includes: processing the semiconductor layer with a first laser to crystallize a part of the amorphous silicon in the semiconductor layer, so as to form nanocrystalline silicon in the crystallized region of the semiconductor layer.

[0116] According to an embodiment of the present application, the preparation method of the present application further includes operation S1103 of forming a transparent conductive layer on the surface of the semiconductor layer far from the silicon substrate after laser treatment.

[0117] According to an embodiment of the present application, in order to further understand the overall manufacturing process of the solar cell of the present application, a specific method for preparing a hybrid back-contact heterojunction cell as Figure 9 shown is taken as an example for illustration. Figures 12A to 12E FIGS. are respectively schematic diagrams of the preparation process of the solar cell according to another embodiment of the present application. As Figures 12A to 12E shown, the manufacturing method of the solar cell according to the embodiment of the present application includes operations S1201 to S1205.

[0118] In operation S1201, a tunneling oxide layer 1205 and a second-type doped polysilicon layer 12023 are formed on the first surface 1201a of the silicon substrate 1201.

[0119] In operation S1202, the tunneling oxide layer 1205 and the second-type doped polysilicon layer 12023 are patterned, and the tunneling oxide layer 1205 and the second-type doped polysilicon layer 12023 remaining on the second region 1201a'' of the first surface 1201a are retained.

[0120] In operation S1203, the other regions of the first surface 1201a except the second region 1201a'' are subjected to texturing and polishing treatments to obtain a polished surface with a pyramid base structure.

[0121] In operation S1204, an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 are sequentially formed on the polished surface, and the first-type doped amorphous silicon layer 12022 is processed with a first laser; preferably, the boundary of the processing does not reach the boundary of the adjacent second-type doped polysilicon layer 12023, and there is a certain distance between the boundary of the first laser processing the first-type doped amorphous silicon 12022 and the boundary of the second-type doped polysilicon 12023, for example, it can be 50-200 microns.

[0122] In operation S1205, a patterned transparent conductive layer 1203 and an electrode 1204 are fabricated on the surfaces of the first-type doped amorphous silicon layer 1203a and the second-type doped polysilicon layer 12023 after laser treatment.

[0123] According to an embodiment of the present application, as Figure 12AAs shown, in operation S1201, it may specifically include: (1) Polishing: Double-sided polishing the silicon substrate 1201 to make its surface flat and smooth. (2) First Chemical Vapor Deposition (CVD1): Using chemical vapor deposition method to sequentially deposit a tunneling oxide layer 1205 and a polysilicon or amorphous silicon layer 12031 on the first surface 1201a of the double-sided polished silicon substrate 1201. The deposition conditions are not the key of this application and will not be elaborated here. (3) Doping: Using a diffusion process to transform the polysilicon or amorphous silicon layer 12031 into a second-type doped polysilicon layer 12023. The diffusion conditions are not the key of this application and will not be elaborated here.

[0124] It can be understood that different doping types and diffusion processes will form different doping sources 12032 on the surface of the second-type doped polysilicon layer 12023. For example, a phosphorus diffusion process will form phosphosilicate glass on the surface of the second-type doped polysilicon layer 12023, and a boron diffusion process will form borosilicate glass on the surface of the second-type doped polysilicon layer 12023.

[0125] According to an embodiment of the present application, as Figure 12B shown, in operation S1202, it may specifically include:

[0126] (1) First wet treatment (wet method 1): Wet removal of the doping source 12032. For example, phosphosilicate glass or borosilicate glass can be removed by pickling process.

[0127] (2) Second Chemical Vapor Deposition (CVD2): Using chemical vapor deposition method to deposit a mask layer 1208 on the surface of the second-type doped polysilicon layer 12023 away from the silicon substrate 101. For example, a silicon nitride layer can be deposited. The deposition conditions are not the key of this application and will not be elaborated here.

[0128] (3) Second laser treatment (laser2): Using a second laser to perform laser opening on the tunneling oxide layer 1205, the second-type doped polysilicon layer 12023 and the mask layer 1208, and removing the tunneling oxide layer 1205 and the second-type doped polysilicon layer 12023 on the remaining regions except the second region 1201a” on the first surface 1201a. The laser opening conditions are not the key of this application and will not be elaborated here.

[0129] According to an embodiment of the present application, as Figure 12C shown, in operation S1203, it may specifically include:

[0130] (1) Second wet treatment (wet method 2): Using a double-sided texturing method to perform wet texturing on the other regions of the first surface 1201a except the second region 1201a” and the second surface 1201b of the silicon substrate. For example, wet texturing can be performed using an alkali tank device.

[0131] (2) Second Chemical Vapor Deposition (CVD2-2): Using the chemical vapor deposition method, a passivation and antireflection layer is deposited on the second surface 1201b of the silicon substrate 1201 that has been wet-etched to form a textured surface. For example, a third intrinsic amorphous silicon layer 1206 and a silicon nitride layer 1207 are deposited sequentially.

[0132] (3) Second Wet Processing (Wet Process 2-2): Using a chain equipment, the other regions of the first surface 1201a except the second region 1201a” are subjected to alkaline polishing to obtain a polished surface, and the mask layer on the surface of the second-type doped polysilicon layer 12023 is removed by pickling using the chain equipment.

[0133] According to an embodiment of the present application, in other embodiments, the polishing process in operation S1203 can also be omitted, thereby obtaining a textured surface with a pyramid structure. Then, an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 are sequentially formed on the textured surface.

[0134] According to an embodiment of the present application, as Figure 12D shown, in operation S1204, it may specifically include:

[0135] (1) Third Chemical Vapor Deposition (CVD3): Using the chemical vapor deposition method, an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 are sequentially deposited on the polished surface of the silicon substrate 1201 and the surface of the second-type doped polysilicon layer 12023. The intrinsic amorphous silicon layer 12021 can form an isolation region between the first-type doped amorphous silicon layer 12022 and the second-type doped polysilicon layer 12023, thereby playing an insulating role.

[0136] (2) Laser and Third Wet Processing: First, a third laser is used to remove a part of the intrinsic amorphous silicon layer 12021 and the first-type doped amorphous silicon layer 12022 on the surface of the second-type doped polysilicon layer 12023. Among them, an overlap is formed between the remaining first-type doped amorphous silicon layer 12022 and the second-type doped polysilicon layer 12023, and this overlapping part can reduce the damage to the second-type doped polysilicon layer 12023 when the transparent conductive layer of the isolation region is opened in the subsequent process. Second, a first laser is used to process the remaining part of the first-type doped amorphous silicon layer 12022 except the overlapping part, so that the first-type doped amorphous silicon layer 12022 forms a crystallized region. Third, pickling is used to remove the silicon oxide formed on the film surface after the action of the third laser and the first laser.

[0137] According to an embodiment of the present application, as Figure 12EAs shown, in operation S1205, it specifically includes: Physical Vapor Deposition (PVD): The transparent conductive layer 1203 is deposited on the exposed surface of the second-type doped polysilicon layer 12023 and the exposed surface of the first-type doped amorphous silicon layer 12022 that has undergone the first laser treatment by physical vapor deposition. The deposition conditions are not the key of this application and will not be elaborated here.

[0138] According to the embodiments of the present application, continue as Figure 12E shown. After operation S1205, it may further include:

[0139] (1) Insulation treatment (TCO insulation): The transparent conductive layer 1203 at the isolation position between the first-type doped amorphous silicon layer 12022 and the second-type doped polysilicon layer 12023 is removed. For example, it can be removed by laser film opening.

[0140] (2) Screen printing: Electrodes 1204 are fabricated on the transparent conductive layer 1203 by screen printing, obtaining a solar cell with the structure as Figure 9 shown.

[0141] According to the embodiments of the present application, the solar cell obtained by the above manufacturing method, based on the porous structure and / or crystallized structure of the first-type doped amorphous silicon, reduces the contact resistance with the transparent conductive layer, thereby releasing space for thickening the intrinsic amorphous silicon layer. Thus, the effects of contact resistance, passivation effect, and leakage current can be taken into account, optimizing the cell efficiency.

[0142] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A solar cell, characterized in that: The solar cell comprises: a silicon substrate including a first surface and a second surface opposite to each other; and A first semiconductor layer is located on the first surface; the first semiconductor layer includes a second structure region and a first structure region, the degree of crystallization of the first structure region is greater than the degree of crystallization of the second structure region; wherein the second structure region is closer to the first surface than the first structure region, and the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon.

2. The solar cell according to claim 1, characterized in that The second structure region includes a first intrinsic silicon layer with a thickness of 5 to 30 nm, preferably 8 to 20 nm.

3. The solar cell according to claim 1, characterized in that The material of the second structure region includes intrinsic amorphous silicon, and the material of the first structure region includes amorphous silicon and nanocrystalline silicon.

4. The solar cell according to claim 1, characterized in that The material of the first structural area includes amorphous silicon and nanocrystalline silicon with a grain size of 5-25 nm.

5. The solar cell according to claim 1, characterized in that: The first semiconductor layer has a plurality of crystal grains therein, and the maximum size of the plurality of crystal grains is smaller than the thickness of the first semiconductor layer.

6. The solar cell according to claim 1, characterized in that The solar cell further includes a transparent conductive layer located on a surface of the first semiconductor layer away from the silicon substrate, and the first structure region is covered by the transparent conductive layer.

7. The solar cell according to claim 1, characterized in that Along a direction parallel to the first surface, the first semiconductor layer includes a main body portion and an edge portion adjacent to a periphery of the main body portion, and a crystallization degree of the main body portion is greater than a crystallization degree of the edge portion.

8. The solar cell according to claim 7, characterized in that: The first semiconductor layer entirely covers the first surface, and the edge portion is in a ring shape surrounding the main body portion.

9. The solar cell according to claim 7, characterized in that: The first surface of the silicon substrate comprises a first region and a second region which are spaced apart from each other, and the first semiconductor layer is located on the first region; The solar cell further comprises a second semiconductor layer located on the second region, wherein the second semiconductor layer has a conductivity type different from that of the first semiconductor layer; The first semiconductor layer is located on the first region and extends onto the second semiconductor layer to overlap with the second semiconductor layer to form an overlapping portion, and the first semiconductor layer in the overlapping portion belongs to the edge portion.

10. The solar cell according to any one of claims 7 to 9, characterized in that: In a direction from the main body portion to the edge portion, a width of the edge portion is less than or equal to 500 μm.

11. The solar cell according to any one of claims 1 to 6, characterized in that: The first surface of the silicon substrate has a polishing area having a pyramid base structure, Wherein, the first semiconductor layer is located on the polishing area, and the first semiconductor layer has a porous structure.

12. The solar cell according to claim 11, characterized in that: The first structural region has a first porous structure, and the second structural region has a second porous structure, wherein the pore size of the second porous structure is smaller than the pore size of the first porous structure.

13. The solar cell according to claim 12, characterized in that: The first porous structure has a plurality of first pores disposed therethrough, and the second porous structure includes a plurality of second pores, wherein the plurality of second pores are exposed from the plurality of first pores.

14. The solar cell according to claim 12, characterized in that: The pore size of the first porous structure is less than or equal to 1 μm, and the pore size of the second porous structure is less than or equal to 300 nm.

15. The solar cell according to claim 11, characterized in that The first structural region has a porous structure, and the second structural region has a non-porous structure.

16. The solar cell according to any one of claims 1 to 6, characterized in that The first surface of the silicon substrate has a velvet area containing a plurality of pyramid structures, and along a direction away from the first surface, the pyramid structures include a base and a top; The first structure region and the second structure region are both located on the top of the tower, and the degree of crystallization of the second structure region is greater than the degree of crystallization of the first semiconductor layer located on the base of the tower.

17. The solar cell according to claim 16, characterized in that: The first semiconductor layer located on the pyramid structure is a non-porous structure and has a side surface extending from the top to the bottom; Wherein, in the extension direction of the side surface, a ratio between a maximum extension length of the first semiconductor layer located on the tower tip on the side surface and a length of the side surface is less than or equal to 0.

3.

18. The solar cell according to claim 16, characterized in that: The portion of the first semiconductor layer located on the tower tip has a porous structure.

19. The solar cell according to claim 18, characterized in that At least one hole included in the porous structure is a blind hole that does not penetrate the first semiconductor layer, and / or at least one hole included in the porous structure has a pore size less than 100 nm.

20. The solar cell according to claim 18, characterized in that The first semiconductor layer located on the pyramid structure has a side surface extending from the top of the pyramid to the bottom of the pyramid; Wherein, along the extension direction of the side surface, the ratio between the distribution length of the porous structure on the side surface and the length of the side surface is less than or equal to 0.

5.

21. The solar cell according to claim 18, characterized in that The thickness of a portion of the first semiconductor layer where the hole structure is not provided is greater than or equal to 10 nm; and / or the thickness of a portion of the first semiconductor layer where the hole structure is not provided is less than or equal to 45 nm.

22. The solar cell according to claim 1, characterized in that The crystallization rate of the second structure region is greater than or equal to 10%, and / or the difference between the crystallization rate of the second structure region and the crystallization rate of the first structure region is less than or equal to 10%.

23. A method for manufacturing a solar cell, characterized in that: The manufacturing method comprises: forming a semiconductor layer on the first surface of the silicon substrate, wherein the material of the semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon; The semiconductor layer is processed by a first laser so that at least a portion of the semiconductor layer is crystallized to a greater degree to form a crystallized region; The semiconductor layer located in the crystallized region includes a second structure region and a first structure region, the crystallization degree of the first structure region is greater than that of the second structure region; and the second structure region is closer to the first surface than the first structure region.

24. The manufacturing method according to claim 23, characterized in that: The wavelength of the first laser is 325-532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200-6000 mJ / cm 2 .

25. The manufacturing method according to claim 23, characterized in that: In a direction parallel to the first surface, the semiconductor layer includes a main body portion and an edge portion adjacent to a periphery of the main body portion; The step of processing the semiconductor layer with the first laser so that at least a portion of the semiconductor layer is crystallized to a greater degree to form a crystallized region comprises: The main body of the semiconductor layer is irradiated with the first laser so that the main body has a higher degree of crystallization than the edge portion and the first structure region of the main body has a higher degree of crystallization than the second structure region.

26. The manufacturing method according to claim 23, characterized in that: The semiconductor layer is amorphous silicon, and the processing of the semiconductor layer with a first laser to increase the degree of crystallization of at least a portion of the semiconductor layer to form a crystallized region includes: The semiconductor layer is processed by using a first laser to crystallize a portion of amorphous silicon in the semiconductor layer, so as to form nanocrystalline silicon in the crystallized region of the semiconductor layer.

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