Three-dimensional dynamic random access memory array structure and semiconductor device including same

Abstract

The invention provides a three-dimensional DRAM array structure and a semiconductor device including the same. The three-dimensional DRAM array structure comprises L layers, M rows and N columns of DRAM unit structures, each DRAM unit structure comprises a first gate transistor and a second gate transistor which are provided with tubular channels, are sequentially arranged in the vertical direction and are electrically connected in parallel, and a storage capacitor which is provided with a tubular structure, is arranged between the first gate transistor and the second gate transistor in the vertical direction and is electrically connected in parallel with the first gate transistor and the second gate transistor. The inner electrodes are connected to the first source / drain electrodes of the first and second gate-all-around transistors, and the outer electrodes are connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional dynamic random access memory (DRAM) array structure and a semiconductor device including the same. Background Art

[0002] Since the invention of dynamic random access memory (DRAM) by Intel Corporation in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit generally consists of a select transistor for selection and a storage capacitor for storing charge (1T1C structure). In a DRAM cell structure using a conventional horizontal transistor based on a planar structure, such as a metal oxide semiconductor field effect transistor (MOSFET), the source, gate, and drain of the transistor are arranged in a horizontal direction parallel to the substrate surface. Since the source, gate, and drain of the transistor each occupy an independent area in the horizontal direction, the miniaturization of the DRAM cell circuit structure is limited by the gate length and contact size, and cannot meet the continuous miniaturization requirements of DRAM devices, thereby restricting the further increase in the integration density and bandwidth of DRAM devices.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate, and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without additional area occupation, which is beneficial to the size miniaturization of the DRAM array structure. In addition, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, the memory integration density can be further improved.

[0005] DRAM manufacturing is a highly competitive industry. The industry continuously needs to reduce the size of individual cells and increase the memory cell density, so that a single memory chip can accommodate more memory.

[0006] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus may include information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel three-dimensional dynamic random access memory (DRAM) array structure and a semiconductor device including the same.

[0008] According to one aspect of the present disclosure, a three-dimensional DRAM array structure is provided, which includes: a plurality of DRAM cell structures arranged in L layers, M rows, and N columns, where L, M, and N are natural numbers greater than 1. Each of the plurality of DRAM cell structures includes: a first gate transistor and a second gate transistor, both having a channel with a tubular structure, arranged in sequence in the vertical direction and electrically connected in parallel, and a storage capacitor having a tubular structure, arranged in the vertical direction between the first gate transistor and the second gate transistor, whose inner electrode is connected to the first source / drain of the first gate transistor and the second gate transistor, and whose outer electrode is connected to the source line; M×N bit lines extending respectively inside the tubular structures formed jointly by the first gate transistor, the second gate transistor, and the storage capacitor in M rows and N columns of DRAM cell structures in the vertical direction, and respectively connected to the second source / drain of the first gate transistor and the second gate transistor in M rows and N columns of DRAM cell structures; L×M first word lines extending in the first horizontal direction and respectively connected to the gates of the first gate transistors in L layers and M rows of DRAM cell structures; and L×M second word lines extending in the first horizontal direction and respectively connected to the gates of the second gate transistors in L layers and M rows of DRAM cell structures.

[0009] According to another aspect of the present disclosure, a semiconductor device is provided, which includes: the three-dimensional DRAM array structure according to the above aspect of the present disclosure; and a circuit board including a plurality of circuits, and the three-dimensional DRAM array structure is arranged on the circuit board.

[0010] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two gate transistors and a storage capacitor that are mirror-symmetrically arranged in the vertical direction, where the inner electrode of the storage capacitor, the source / drain, and the channel regions of the two gate transistors are formed of the same semiconductor material layer, so it has advantages such as simple structure and good switching performance.

[0011] In addition, the DRAM array structure according to the present disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby improving the integration density. In addition, the DRAM array structure according to the present disclosure can be stacked on a circuit board including a plurality of circuits, so system-level three-dimensional vertical integration can be achieved, thereby greatly reducing the area overhead of the circuit system.

[0012] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. Description of the Drawings

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure, and the drawings incorporated in and constituting a part of this specification illustrate exemplary embodiments of the present disclosure and, together with the specification, are used to explain the inventive concept.

[0014] Figure 1 is an equivalent circuit diagram showing a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0015] Figure 2 is a perspective view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 3 is a top view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0017] Figure 4 is showing along Figure 3 a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line AA' in

[0018] Figure 5 is showing along Figure 5 a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line BB' in

[0019] Figure 6 is showing along Figure 4 a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line CC' in

[0020] Figure 7 is showing along Figure 4 a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line DD' in

[0021] Figure 8 is showing a DRAM array structure formed by the DRAM cell structure shown in Figure 1 according to an embodiment of the present disclosure, and is an equivalent circuit diagram.

[0022] Figure 9 is showing Figure 8 an equivalent circuit diagram of the DRAM cell structure of the first row of the DRAM array structure according to an embodiment of the present disclosure shown in

[0023] Figure 10 is showing Figure 8 a schematic perspective view of the DRAM cell structure of the first row of the first layer of the DRAM array structure according to an embodiment of the present disclosure shown in

[0024] Figure 11 is showing Figure 8A top view of a partial DRAM array structure of a DRAM array structure according to an embodiment of the present disclosure.

[0025] Figure 12 It is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line AA' in Figure 11 .

[0026] Figure 13 It is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line BB' in Figure 11 .

[0027] Figure 14 It is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line CC' in Figure 12 .

[0028] Figure 15 It is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line DD' in Figure 12 .

[0029] Figure 16 It is an equivalent circuit diagram of a DRAM array structure having an alternative configuration of word lines according to an embodiment of the present disclosure.

[0030] Figure 17 It is an equivalent circuit diagram of a DRAM array structure having an alternative configuration of bit lines according to an embodiment of the present disclosure.

[0031] Figure 18 It is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 19 It is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Embodiments

[0033] In the following description, for the purpose of illustration, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, "embodiment" is a non-limiting example of a device or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent configurations. In addition, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0034] Unless otherwise specified, the described exemplary embodiments should be understood to provide exemplary features of some variations of details that can implement the inventive concept in practice. Therefore, unless otherwise specified, features, components, modules, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of each embodiment can be combined, separated, interchanged, and / or reconfigured otherwise without departing from the inventive concept.

[0035] For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0037] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. Further, when used in this specification, the terms "comprises" and / or "comprising" mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to account for the inherent deviations in measurements, calculations, and / or provided values recognized by those of ordinary skill in the art.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be construed to have a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0039] Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like reference numerals throughout the figures denote like elements. Further, in the drawings, for clarity of illustration, the components are not necessarily drawn to scale, and the proportions and dimensions of the components may be enlarged.

[0040] A dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0042] As Figure 1 shown, the DRAM cell structure 100 according to an embodiment of the present disclosure may adopt a cell structure of 2T1C (i.e., two select transistors and one storage capacitor). Specifically, the DRAM cell structure 100 may include two gate-all-around (GAA) transistors arranged in sequence in the vertical direction (z-direction) and electrically connected in parallel, i.e., a first GAA transistor T1 and a second GAA transistor T2. Both the first and second GAA transistors T1 and T2 may have a channel with a tubular structure (as described below with reference to Figures 2 to 17 ), and serve as select transistors of the DRAM cell structure 100.

[0043] According to an embodiment of the present disclosure, a first source / drain S / D11 of the first GAA transistor T1 and a first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (inner electrode) of the memory capacitor C, and a second source / drain S / D12 of the first GAA transistor T1 and a second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of the present disclosure, the bit line BL may extend in the vertical direction (z-direction). In addition, according to an embodiment of the present disclosure, a gate G1 of the first GAA transistor T1 may be connected to a first word line WLA, and a gate G2 of the second GAA transistor T2 may be connected to a second word line WLB. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may be shorted together. Alternatively, according to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may also not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 separately.

[0044] In addition, according to an embodiment of the present disclosure, another electrode plate (outer electrode) of the storage capacitor C may be connected to the source line SL. Those skilled in the art should recognize that in the DRAM array structure composed of the DRAM cell structure 100 according to the present disclosure, the source lines SL of all the DRAM cell structures may be connected together either commonly or in groups, and thus the source line SL may also be referred to as a "common electrode" herein.

[0045] Figure 2 A perspective view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 4 As shown along Figure 3 a cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along line AA' in Figure 5 As shown along Figure 3 a cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along line BB' in Figure 6 As shown along Figure 4 a cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along line CC' in Figure 7 As shown along Figure 4 a cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along line DD' in

[0046] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include bit line holes extending in the vertical direction (z direction) (such as Figure 3 , Figure 6 and Figure 7 the holes located at the center and having a circular cross-section, for example, as shown), and common electrode grooves extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) (such as Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 the grooves located on both sides of the bit line hole at the center, as shown).

[0047] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a conductor line 109 disposed in the bit line hole, the conductor line 109 extending in the vertical direction (z direction) and may be used as such as Figure 1The bit line BL of the DRAM cell structure 100 shown. According to an embodiment of the present disclosure, the material for forming the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In particular, according to an embodiment of the present disclosure, the conductor line 109 may have the shape of a cylinder extending in the vertical direction (z direction). For example, as Figure 3 , Figure 6 and Figure 7 shown, the conductor line 109 may be a cylinder having a first diameter d1.

[0048] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 having a tubular structure surrounding the conductor line 109 and a first isolation material layer 111 disposed in the bit line hole. Specifically, as Figure 4 and Figure 5 more clearly shown, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first isolation material layer 111. In other words, according to an embodiment of the present disclosure, both the semiconductor material layer 107 and the first isolation material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 the tubular structure has a circular cross-section, the present disclosure is not limited thereto, and those skilled in the art should recognize that the tubular structure may also have a cross-section of any other shape, such as an elliptical, square, or rectangular cross-section, and the cross-sectional shape of the conductor line 109 may be adjusted accordingly at this time.

[0049] According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphosilicate glass, or a combination thereof. According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may also be a low-K material. The low-K material may have a dielectric constant lower than that of silicon oxide. Silicon oxide may have a dielectric constant of about 3.9, and the first isolation material layer 111 may include a low-K material having a dielectric constant of about 3.9 or lower. According to an embodiment of the present disclosure, the low-K material may include porous silicon oxide (SiO 2) Polymers such as silicone, fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxycarbide (SiCOH), or parylene, polyimide (PI). According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may also be a combination of the above dielectric materials and the above low-K materials.

[0050] According to an embodiment of the present disclosure, the material for forming the semiconductor material layer 107 may be a semiconductor thin film material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to an embodiment of the present disclosure, the material for forming the semiconductor material layer 107 may be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO) with different ratios, indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO). In particular, according to an embodiment of the present disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

[0051] In addition, according to an embodiment of the present disclosure, as described in more detail below, the semiconductor material layer 107 may form the source / drain regions and channel regions of the first GAA transistor T1 and the second GAA transistor T2 as shown in Figure 1 wherein the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first GAA transistor T1 and the first source / drain S / D21 and the second source / drain S / D22 of the second GAA transistor T2. It should be noted here that the source / drain regions described from a structural perspective are equivalent to the source / drain described from a circuit perspective. In addition, according to an embodiment of the present disclosure, the semiconductor material layer 107 may also form the inner electrode of the storage capacitor C as shown in Figure 1 Therefore, according to an embodiment of the present disclosure, the storage capacitor C may also have a tubular structure.

[0052] As shown in Figures 2 to 7 According to an embodiment of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in the bit line holes and respectively surrounding the upper and lower ends of the semiconductor material layer 107. According to an embodiment of the present disclosure, the two first dielectric layers 106 may respectively form the gate dielectrics of the first GAA transistor T1 and the second GAA transistor T2 as shown in Figure 1 As shown in Figure 4 and Figure 5 According to an embodiment of the present disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, as shown in Figures 2 to 5As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion farther from the end of the conductor line 109 relative to the first portion, and the first portion and the second portion may be connected by a connecting portion in the horizontal direction. According to an embodiment of the present disclosure, the material for forming the first dielectric layer 106 may include, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ) or a combination thereof.

[0053] Therefore, according to an embodiment of the present disclosure, both the first GAA transistor T1 and the second GAA transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0054] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a first gate layer 104 below and a second gate layer 105 above that are respectively disposed around the thicker second portions of the first dielectric layer 106 below and above. As Figure 2 and Figure 6 shown, according to an embodiment of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a slat shape with a hole formed in the middle. According to an embodiment of the present disclosure, the first gate layer 104 may correspond to the gate G1 of the first GAA transistor T1 as Figure 1 shown, and the second gate layer 105 may correspond to the gate G2 of the second GAA transistor T2 as Figure 1 shown. In addition, as Figure 2 , Figure 3 and Figure 5 shown, according to an embodiment of the present disclosure, the first gate layer 104 may extend in the first horizontal direction (y-direction) to further correspond to the first word line WLA connected to the first gate G1 of the first GAA transistor T1 as Figure 1 shown. Accordingly, according to an embodiment of the present disclosure, the second gate layer 105 may extend in the first horizontal direction (y-direction) to further correspond to the second word line WLB connected to the gate G2 of the second GAA transistor T2 as Figure 1 shown. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may be led out from the distal end in the first horizontal direction (y-direction).

[0055] Thus, according to an embodiment of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in a first horizontal direction (y-direction). According to an embodiment of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically inside a tubular structure formed by a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C. In addition, according to an embodiment of the present disclosure, a first gate layer 104 and a second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0056] In addition, according to an embodiment of the present disclosure, the materials for forming the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

[0057] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include two second isolation material layers 103 disposed to respectively surround thinner first portions of a first dielectric layer 106 above and below. As Figure 2 and Figure 3 shown, according to an embodiment of the present disclosure, the second isolation material layer 103 may have a strip shape with a hole formed in the middle. According to an embodiment of the present disclosure, the materials for forming the second isolation material layer 103 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon oxide (SiCOH), or aluminum oxide (Al 2 O 3 ). According to an embodiment of the present disclosure, the first isolation material layer 111 and the second isolation material layer 103 may be formed of the same or different isolation materials.

[0058] As Figure 4 and Figure 5 shown, according to an embodiment of the present disclosure, as described above, the semiconductor material layer 107 may include, in the vertical direction (z-direction), a first portion 1071 of the channel regions of the first and second GAA transistors T1 and T2 indicated by shading, and between the first portions 1071, forming Figure 1 shown, Figure 1The first source / drain region of the first GAA transistor T1 shown (corresponding to the first source / drain S / D11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D21 of the second GAA transistor T2), and the second part 1072 of the inner electrode of the memory capacitor C. Thus, according to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are connected together with the inner electrode of the memory capacitor C. According to an embodiment of the present disclosure, the first part 1071 and the second part 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by the first isolation material layer 111 surrounding the conductor line 109.

[0059] According to an embodiment of the present disclosure, the doping type, doping concentration, and / or atomic composition ratio of the second part 1072 of the semiconductor material layer 107 can be changed by material modification processes such as doping and etching, so that it has better conductivity as the inner electrode of the memory capacitor C. That is, according to an embodiment of the present disclosure, the first part 1071 and the second part 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to an embodiment of the present disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second part 1072 can be removed by, for example, an etching process to improve its conductivity, or part of the oxygen (O) atoms in the second part 1072 can be removed by, for example, an etching process to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0060] In addition, as Figure 4 and Figure 5 shown, according to an embodiment of the present disclosure, as described above, the semiconductor material layer 107 can further include, in the vertical direction (z - direction), a third part 1073 that contacts both ends of the conductor line 109 and serves as Figure 1 shown, the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D22 of the second GAA transistor T2), and a first horizontal connection part 1074 connecting the first part 1071 and the third part 1073. Thus, according to an embodiment of the present disclosure, the third part 1073 of the semiconductor material layer 107 contacts the conductor line 109, so that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third part 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0061] As Figure 3 shown, according to an embodiment of the present disclosure, a third portion 1073 of the semiconductor material layer 107 of the tubular structure may have a second diameter d2, which is greater than a first diameter d1 of the conductor line 109. In addition, as Figures 3 to 7 shown, according to an embodiment of the present disclosure, a first portion 1071 and a second portion 1072 of the semiconductor material layer 107 of the tubular structure may have a third diameter d3, which is greater than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0062] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 serving as a capacitive dielectric of the storage capacitor C disposed in the common electrode trench. According to an embodiment of the present disclosure, the second dielectric layer 108 may be conformally formed along the trench wall of the common electrode trench. As Figure 2 and Figure 4 shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact two second isolation material layers 103, the first gate layer 104, the second gate layer 105, and the second portion of the semiconductor material layer 107 in a second horizontal direction (x direction). In addition, as Figure 2 and Figure 5 shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact the second portion of the semiconductor material layer 107 in a first horizontal direction (y direction). The first horizontal direction, i.e., the y direction, may be perpendicular to the second horizontal direction, i.e., the x direction.

[0063] In addition, according to an embodiment of the present disclosure, the material for forming the second dielectric layer 108 may be a high-k material. The high-k material may have a dielectric constant higher than that of silicon oxide. Silicon oxide may have a dielectric constant of about 3.9, and the second dielectric layer 108 may include a high-k material having a dielectric constant of about 4 or greater. According to an embodiment of the present disclosure, the high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), strontium titanate (SrTiO 3 ) or a combination thereof.

[0064] As Figures 2 to 7As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 that extends along the surface of the second dielectric layer 108 and fills the common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to Figure 1 the outer electrode of the storage capacitor C shown, that is, the common electrode of the storage capacitor C, and the source line SL. As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the electrode layer 110 corresponding to the outer electrode of the storage capacitor C and the source line SL may extend in a first horizontal direction (y direction) and penetrate the DRAM cell structure 100 in a vertical direction (z direction). According to an embodiment of the present disclosure, the material for forming the electrode layer 110 may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof. Therefore, according to an embodiment of the present disclosure, the storage capacitor C of the DRAM cell structure 100 may be formed as a columnar capacitor.

[0065] In addition, although not shown in the figure, according to an embodiment of the present disclosure, a third isolation material layer may also be provided between the first gate layer 104 and the second gate layer 105 and the second dielectric layer 108 to reduce the parasitic capacitance and leakage current between the outer electrode (source line SL) of the storage capacitor and the gates G1 and G2 (i.e., the first and second word lines WLA and WLB) of the first and second GAA transistors T1 and T2.

[0066] Figure 8 is an equivalent circuit diagram of a DRAM array structure 200 formed by the Figure 1 shown DRAM cell structure according to an embodiment of the present disclosure. As Figure 8 shown, according to an embodiment of the present disclosure, the DRAM array structure 200 formed by the Figure 1 shown DRAM cell structure may be a three-dimensional DRAM array structure stacked in a vertical direction (z direction).

[0067] As Figure 8 shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may include as Figure 1A plurality of DRAM cell structures 100 are shown. For clarity, some reference numerals inside each DRAM cell structure are omitted. According to an embodiment of the present disclosure, the plurality of DRAM cell structures are arranged in an L-layer M-row N-column L-layer, where L, M, and N are all natural numbers greater than 1. Herein, each of the plurality of DRAM cell structures included in the DRAM array structure 200 can be represented as Clmn, that is, the DRAM cell structure located in the m-th row, n-th column, and l-th layer of the DRAM array structure 200, where m, n, and l are natural numbers, and 1 ≤ m ≤ M, 1 ≤ n ≤ N, and 1 ≤ l ≤ L. In addition, herein, M represents the number of rows of DRAM cell structures in the DRAM array structure 200 along the first horizontal direction (y direction), N represents the number of columns of DRAM cell structures in the DRAM array structure 200 along the second horizontal direction (x direction), and L represents the number of layers of DRAM cell structures in the DRAM array structure 200 along the vertical direction (z direction).

[0068] According to an embodiment of the present disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM, and M×N bit lines BL11 to BLMN.

[0069] Therefore, as Figure 8 shown, according to an embodiment of the present disclosure, in the DRAM array structure 200, each of the L layers of DRAM cell structures includes a total of M×N DRAM cell structures in M rows and N columns, each of the M rows of DRAM cell structures includes a total of L×N DRAM cell structures in L layers and N columns, and each of the N columns of DRAM cell structures includes a total of L×M DRAM cell structures in L layers and M rows.

[0070] As described above with reference to Figures 1 to 7 each of the plurality of DRAM cell structures included in the DRAM array structure 200 can include: a first GAA transistor and a second GAA transistor, both having a channel with a tubular structure, arranged in sequence in the vertical direction and electrically connected in parallel; and a storage capacitor, having a tubular structure, arranged in the vertical direction between the first GAA transistor and the second GAA transistor, and its inner electrode is connected to the first source / drain of the first GAA transistor and the second GAA transistor.

[0071] In addition, as Figure 8As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend inside the tubular structures formed by L first GAA transistors, L second GAA transistors, and L storage capacitors in the M-row N-column DRAM cell structures in the vertical direction, and are respectively connected to the second source / drain electrodes of the L first GAA transistors and L second GAA transistors in the M-row N-column DRAM cell structures.

[0072] In addition, although not shown, according to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, L first word lines WLA1m to WLALm may be respectively connected to L second word lines WLB1m to WLBLm. For example, as Figure 8 shown, in the first row of the DRAM array structure, the first word line WLA11 may be connected to the second word line WLB11, the first word line WLA21 may be connected to the second word line WLB21, and so on, until the first word line WLAL1 may be connected to the second word line WLBL1. According to an embodiment of the present disclosure, the corresponding connection of the L first word lines and the L second word lines in each row of the M-row DRAM array structure may be achieved externally from the distal end of the array. Here, since the paired first word line WLAlm and second word line WLBlm extending in the first horizontal direction (y direction) may be connected together, they may be commonly referred to as the word line WL and assigned the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this time, according to an embodiment of the present disclosure, the cell selection operation of the multiple DRAM cell structures included in the DRAM array structure 200 may be performed by L×M word lines WL11 to WLLM and M×N bit lines BL11 to BLMN.

[0073] In addition, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L layers of DRAM cell structures, which extend in the first horizontal direction (y direction) and are respectively connected to the outer electrodes of the storage capacitors in the L layers of DRAM cell structures. In addition, as Figure 8 shown, according to an embodiment of the present disclosure, the L source lines SL may be connected together through a common electrode groove that is disposed between the bit lines and penetrates the entire DRAM array structure 200 in the vertical direction (z direction). At this time, the source lines SL also extend in the vertical direction (z direction). Although not shown, according to an alternative embodiment of the present disclosure, the L source lines SL may also be connected together only externally to the DRAM array structure 200, either commonly or in groups, omitting the common electrode groove.

[0074] Figure 9 is shown Figure 8The equivalent circuit diagram of the DRAM cell structures C111 to CL1N in the first row of the DRAM array structure 200 according to an embodiment of the present disclosure. As Figure 9 shown, at the intersection of the first bit line BL11 in the first column extending in the vertical direction (z direction) and the first layer word lines (the first word line WLA11 and the second word line WLB11) extending in the first horizontal direction (y direction), the first layer first column DRAM cell structure C111 is provided. And so on, Figure 9 the first row of the DRAM array structure 200 shown includes N×L DRAM cell structures C111 to CL1N.

[0075] As described above with reference to Figure 1 According to an embodiment of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example, Figure 9 the DRAM cell structure C111 shown, includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C.

[0076] Figure 10 is a schematic perspective view showing Figure 8 the first layer first row DRAM cell structure of the DRAM array structure 200 according to an embodiment of the present disclosure. As Figure 10 shown, in the first layer first row DRAM cell structure of the DRAM array structure, the first layer first row word lines WL11 (the first word line WLA11 and the second word line WLB11) can extend in the first horizontal direction (y direction), and the first row bit lines (only BL11 to BL13 are shown) can extend in the vertical direction (z direction). According to an embodiment of the present disclosure, the source line SL of the first layer DRAM cell structure can extend in the first horizontal direction (y direction). In addition, as Figure 10 shown, the source line SL can also be connected to the source line SL in other layers together in a common electrode groove extending in the vertical direction (z direction).

[0077] In addition, as Figures 8 to 10 shown, according to an embodiment of the present disclosure, the m-th row and n-th column bit line BLmn can be commonly connected to the second source / drains of L first GAA transistors and L second GAA transistors in the m-th row and n-th column DRAM cell structure of the DRAM array structure 200 for performing a cell selection operation on the m-th row and n-th column DRAM cell structure.

[0078] Figure 11 is a top view showing Figure 8 the partial DRAM array structure 201 of the DRAM array structure 200 according to an embodiment of the present disclosure. Figure 12 is a view showing alongFigure 11 A cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure taken along line AA' in Figure 13 is a view showing along Figure 11 A cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure taken along line BB' in Figure 14 is a view showing along Figure 12 A cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure taken along line CC' in Figure 15 is a view showing along Figure 12 A cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure taken along line DD' in

[0079] It should be noted that Figures 11 to 15 is exemplarily shown as Figure 8 a partial DRAM array structure 201 that is part of the DRAM array structure 200 shown in , which includes DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222 from the first row and first column of the first layer to the second row and second column of the second layer, and these eight DRAM cell structures are arranged in two rows, two columns, and two layers.

[0080] According to an embodiment of the present disclosure, the M rows and N columns of bit lines BL11 to BLMN of the DRAM array structure 200 can extend in the vertical direction (z direction) and be arranged in a matrix form of M×N in the first horizontal direction (y direction) and the second horizontal direction (x direction). In addition, according to an embodiment of the present disclosure, the L-layer DRAM cell structures of the DRAM array structure 200 are stacked in sequence in the vertical direction, and each layer of DRAM cell structures includes M×N DRAM cell structures.

[0081] Specifically, as Figures 11 to 15 shown, a total of four bit lines BL11, BL12, BL21, and BL22 in two rows and two columns can extend in the vertical direction (z direction) and be arranged in a matrix form of 2×2 in the first horizontal direction (y direction) and the second horizontal direction (x direction). In addition, as Figure 12 and Figure 13 shown, the first-layer DRAM cell structures C111, C112, C121, and C122 are stacked above the second-layer DRAM cell structures C211, C212, C121, and C222.

[0082] As Figure 11 and Figure 12As shown, the first word line WLA11 in the first row of the first layer is connected to the gates of the first GAA transistors in the DRAM cell structures C111 and C112 in the first row of the first layer, and the second word line WLB11 in the first row of the first layer is connected to the gates of the second GAA transistors in the DRAM cell structures C111 and C112 in the first row of the first layer. Similarly, the first word line WLA12 in the second row of the first layer is connected to the gates of the first GAA transistors in the DRAM cell structures C121 and C122 in the second row of the first layer, and the second word line WLB12 in the second row of the first layer is connected to the gates of the second GAA transistors in the DRAM cell structures C121 and C122 in the second row of the first layer. Similarly, the first word line WLA21 in the first row of the second layer is connected to the gates of the first GAA transistors in the DRAM cell structures C211 and C212 in the first row of the second layer, and the second word line WLB21 in the first row of the second layer is connected to the gates of the second GAA transistors in the DRAM cell structures C211 and C212 in the first row of the second layer. Similarly, the first word line WLA22 in the second row of the second layer is connected to the gates of the first GAA transistors in the DRAM cell structures C221 and C222 in the second row of the second layer, and the second word line WLB22 in the second row of the second layer is connected to the gates of the second GAA transistors in the DRAM cell structures C221 and C222 in the second row of the second layer.

[0083] As Figures 11 to 15As shown, four bit lines BL11, BL12, BL21, and BL22 are respectively formed in four bit line holes extending through the DRAM array structure in the vertical direction (z direction). Specifically, the bit line BL11 in the first row and first column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the DRAM cell structures C111 and C211 in the first row and first column, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the DRAM cell structures C111 and C211 in the first row and first column. Similarly, the bit line BL12 in the first row and second column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the DRAM cell structures C112 and C212 in the first row and second column, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the DRAM cell structures C112 and C212 in the first row and second column. Similarly, the bit line BL21 in the second row and first column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the DRAM cell structures C121 and C221 in the second row and first column, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the DRAM cell structures C121 and C221 in the second row and first column. Similarly, the bit line BL22 in the second row and second column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the DRAM cell structures C122 and C222 in the second row and second column, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the DRAM cell structures C122 and C222 in the second row and second column.

[0084] According to an embodiment of the present disclosure, in each of the DRAM cell structures in M rows × N columns, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor are formed of the same semiconductor material layer. That is, according to an embodiment of the present disclosure, in each of the M × N bit line holes extending through L layers of DRAM cell structures in the vertical direction (z direction), the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the L layers of DRAM cell structures are formed of the same semiconductor material layer having a tubular structure. That is, the semiconductor material layer having the tubular structure extends through the entire DRAM array structure 200 in the vertical direction (z direction).

[0085] Specifically, as Figures 11 to 15As shown, the first source / drain and second source / drain, channel regions, and inner electrodes of the storage capacitors of the first GAA transistors and second GAA transistors in the first-layer DRAM cell structure C111 and the second-layer DRAM cell structure C211 connected to the bit line BL11 in the first row and first column are formed of the same semiconductor material layer. Similarly, the first source / drain and second source / drain, channel regions, and inner electrodes of the storage capacitors of the first GAA transistors and second GAA transistors in the first-layer DRAM cell structure C112 and the second-layer DRAM cell structure C212 connected to the bit line BL12 in the first row and second column are formed of the same semiconductor material layer. Similarly, the first source / drain and second source / drain, channel regions, and inner electrodes of the storage capacitors of the first GAA transistors and second GAA transistors in the first-layer DRAM cell structure C121 and the second-layer DRAM cell structure C221 connected to the bit line BL21 in the second row and first column are formed of the same semiconductor material layer. Similarly, the first source / drain and second source / drain, channel regions, and inner electrodes of the storage capacitors of the first GAA transistors and second GAA transistors in the first-layer DRAM cell structure C122 and the second-layer DRAM cell structure C222 connected to the bit line BL22 in the second row and second column are formed of the same semiconductor material layer.

[0086] According to an embodiment of the present disclosure, the common electrode trench may extend in the first horizontal direction (y direction) and penetrate through the L-layer DRAM array structure in the vertical direction (z direction), and at this time, the L source lines SL corresponding to the L-layer DRAM cell structures may be connected together in the vertical direction (z direction). In addition, according to an embodiment of the present disclosure, the DRAM cell structures in adjacent rows in the second horizontal direction (x direction) may share the common electrode trench. In addition, as described above, the capacitance medium and the outer electrode of the storage capacitor in each DRAM cell structure of the DRAM array structure 200 may be disposed in the common electrode trench.

[0087] Alternatively, according to an embodiment of the present disclosure, in the DRAM array structure 200, the common electrode trench may also be omitted, and at this time, the source line SL may only extend in the first horizontal direction (y direction) and be connected together outside the DRAM array structure 200 either commonly or in groups.

[0088] Figure 16 is an equivalent circuit diagram showing a DRAM array structure 200' having an alternative configuration of word lines according to an embodiment of the present disclosure. In Figure 16 , components identical to Figure 8 are denoted by the same reference numerals, and their repeated descriptions will be omitted.

[0089] Combined with Figure 8 Referring to Figure 16 , Figure 16The DRAM array structure 200' shown is different from Figure 8 the DRAM array structure 200 shown in that, in each layer of the L-layer DRAM cell structure, M first word lines WLAl1 to WLAlM can be connected together to form a common first word line WLAl of the l-th layer, and M second word lines WLBl1 to WLBlM can be connected together to form a common second word line WLBl of the l-th layer. Specifically, as Figure 16 shown, the first word lines WLA11 to WLA1M of the first-layer DRAM cell structure are connected together to form a common first word line WLA1 of the first layer, and the second word lines WLB11 to WLB1M of the first-layer DRAM cell structure are connected together to form a common second word line WLB1 of the first layer. Similarly, the first word lines WLA21 to WLA2M of the second-layer DRAM cell structure are connected together to form a common first word line WLA2 of the second layer, and the second word lines WLB21 to WLB2M of the second-layer DRAM cell structure are connected together to form a common second word line WLB2 of the first layer. And so on, until the first word lines WLAL1 to WLALM of the L-th layer DRAM cell structure are connected together to form a common first word line WLAL of the L-th layer, and the second word lines WLBL1 to WLBLM of the L-th layer DRAM cell structure are connected together to form a common second word line WLBL of the L-th layer.

[0090] At this time, according to an embodiment of the present disclosure, the DRAM array structure 200' has L first word lines WLA1 to WLAL, L second word lines WLB1 to WLBL, and M×N bit lines BL11 to BLMN. According to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the first word line WLAl, the second word line WLBl, and the bit line BLmn.

[0091] In addition, according to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, when the L first word lines WLA1m to WLALm are respectively connected to the L second word lines WLB1m to WLBLm, Figure 16 the DRAM array structure 200' shown can be further simplified to L word lines WL1 to WLL. At this time, according to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the word line WLl and the bit line BLmn.

[0092] Therefore, Figure 16 the DRAM array structure 200' shown, compared with Figure 8 the DRAM array structure 200 shown, can simplify the word line configuration.

[0093] Figure 17 is an equivalent circuit diagram showing an alternative configuration of bit lines in a DRAM array structure 200 according to an embodiment of the present disclosure. In Figure 17 , components identical to Figure 8 are denoted by the same reference numerals, and their repeated descriptions will be omitted.

[0094] Combined with Figure 8 referring to Figure 17 , Figure 17 the DRAM array structure 200" shown is different from Figure 8 the DRAM array structure 200 shown in that, in each of the N columns of DRAM cell structures, M bit lines BL1n to BLMn can be connected together to form a common bit line BLn of the nth column. Specifically, as Figure 17 shown, the bit lines BL11 to BLM1 of the first column DRAM cell structure are connected together to form the common bit line BL1 of the first column. Similarly, the bit lines BL12 to BLM2 of the second column DRAM cell structure are connected together to form the common bit line BL2 of the first column. And so on, the bit lines BL1N to BLMN of the Nth column DRAM cell structure are connected together to form the common bit line BLN of the Nth column.

[0095] At this time, according to an embodiment of the present disclosure, the DRAM array structure 200" has L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, and N bit lines BL1 to BLN. According to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be achieved by the first word line WLAlm, the second word line WLBlm, and the bit line BLn.

[0096] In addition, according to an embodiment of the present disclosure, in each of the M rows of the DRAM array structure, when L first word lines WLA1m to WLALm are respectively connected to L second word lines WLB1m to WLBLm, Figure 17 the DRAM array structure 200" shown can be further simplified to L×M word lines WL11 to WLLM. At this time, according to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be achieved by the word line WLlm and the bit line BLn.

[0097] Therefore, Figure 17 the DRAM array structure 200" shown, compared with Figure 8 the DRAM array structure 200 shown, can simplify the bit line configuration.

[0098] According to an embodiment of the present disclosure, since the DRAM array structure 200 is a three-dimensional vertically integrated DRAM array structure, it can be stacked on a circuit substrate including various circuits, thereby realizing a vertically integrated semiconductor device.

[0099] Figure 18 FIG. 4 is a schematic cross-sectional view showing a semiconductor device 400 according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the semiconductor device 400 may include a circuit substrate 300 and a DRAM array structure 200 disposed on the circuit substrate 300. Although Figure 18 only a partial DRAM array structure of the DRAM array structure 200 shown in Figure 8 is shown, that is, the DRAM cell structures CLmn, C(L-1)nm, CL(m+1)n, and C(L-1)(m+1)n are stacked on the circuit substrate 300, those skilled in the art should recognize that the entire DRAM array structure 200 can be stacked on the circuit substrate 300.

[0100] As Figure 18 shown, according to an embodiment of the present disclosure, the circuit substrate 300 may be a semiconductor substrate, on which multiple circuits can be fabricated through a semiconductor manufacturing process such as a standard CMOS process. According to an embodiment of the present disclosure, the L-layer DRAM cell structures of the DRAM array structure 200 can be stacked on the circuit substrate 300 in the vertical direction (z direction), thereby realizing system-level three-dimensional vertical integration.

[0101] According to an embodiment of the present disclosure, the multiple circuits on the circuit substrate 300 can be connected to the DRAM array structure 200 through, for example, wires and vias extending in the vertical direction (z direction).

[0102] Figure 19 FIG. 20 is a schematic block diagram showing a semiconductor device 400 according to an embodiment of the present disclosure.

[0103] As Figure 19 shown, according to an embodiment of the present disclosure, the multiple circuits included in the circuit substrate 300 may be a memory controller circuit 302, a word line circuit 303, and a bit line circuit 304.

[0104] According to an embodiment of the present disclosure, the memory controller circuit 302 may be the main management circuit of the DRAM array structure 200, which is used to process all instructions related to the read and write operations of the DRAM array structure 200. In addition, the memory controller circuit 302 is also used to refresh the DRAM cell structure because the data stored in the DRAM cell structure gradually disappears over time, so it needs to be refreshed regularly to maintain the integrity of the data.

[0105] According to an embodiment of the present disclosure, the word line circuit 303 is used to select a group of DRAM cell structures connected to a specified word line in the DRAM array structure 200. For example, when data needs to be read from or written to the DRAM array structure, the word line circuit 303 is activated to select a group of DRAM cell structures connected to the specified word line. In addition, the bit line circuit 304 is used to select a specific DRAM cell structure among a group of DRAM cell structures connected to the specified word line. When the word line circuit 303 selects a group of DRAM cell structures, the bit line circuit 304 can select a bit line connected to one DRAM cell structure in the group of DRAM cell structures, thereby determining the exact location of the data. In addition, the bit line circuit 304 is also used to transfer data during read and write operations.

[0106] According to an embodiment of the present disclosure, the word line circuit 303 can be connected to the word line WL of the DRAM array structure 200, and the bit line circuit 304 can be connected to the bit line BL of the DRAM array structure 200.

[0107] According to an embodiment of the present disclosure, when Figure 8 the illustrated DRAM array structure 200 is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L×M word lines WL11 to WLLM (L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM), and the bit line circuit 304 can be connected to M×N bit lines BL11 to BLMN. In addition, according to an embodiment of the present disclosure, when Figure 16 the illustrated DRAM array structure 200' is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L word lines WL1 to WLL (L first word lines WLA1 to WLAL and L second word lines WLB1 to WLBL), and the bit line circuit 304 can be connected to M×N bit lines BL11 to BLMN. In addition, according to an embodiment of the present disclosure, when Figure 17 the illustrated DRAM array structure 200" is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L×M word lines WL11 to WLLM (L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM), and the bit line circuit 304 can be connected to N bit lines BL1 to BLN.

[0108] According to an embodiment of the present disclosure, in the three-dimensional DRAM array structures (200, 200', and 200") according to the embodiments of the present disclosure, since the word lines WL extend in the first horizontal direction (y direction), the word line circuit 303 can be connected to the word lines WL of the three-dimensional DRAM array structure through wires and vias extending in the vertical direction (z direction). In addition, according to an embodiment of the present disclosure, in the three-dimensional DRAM array structures (200, 200', and 200") according to the embodiments of the present disclosure, since the bit lines BL extend in the vertical direction (z direction), the bit line circuit 304 can be directly connected to the bit lines BL.

[0109] In addition, according to an embodiment of the present disclosure, the plurality of circuits included in the circuit substrate 300 may further include a circuit 301, which may be a processor circuit or a memory interface circuit. According to an embodiment of the present disclosure, the circuit 301 can be connected to the memory controller circuit 302 to send information such as addresses, instructions, and / or data thereto, and can be connected to the bit line circuit 304 to transfer or receive data therefrom.

[0110] According to an embodiment of the present disclosure, when the circuit 301 is a processor circuit, the semiconductor device 400 can be a computing system, and when the circuit 301 is a memory interface circuit, the semiconductor device 400 can be a memory system.

[0111] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two surrounding gate transistors and a storage capacitor that are mirror-symmetrically arranged in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two surrounding gate transistors are formed of the same semiconductor material layer, so it has advantages such as simple structure and good switching performance.

[0112] In particular, this cell structure solves the connection problem between the source / drain of the transistor and the inner electrode of the storage capacitor by using a vertical structure, is suitable for application to three-dimensional vertical integration of multi-level cells, and the vertical structure is suitable for one-time processing and formation of multi-level cells without multiple epitaxial processes and processing processes, and the manufacturing cost is low.

[0113] In addition, the DRAM array structure according to the present disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby improving the integration density. In addition, the DRAM array structure according to the present disclosure can be stacked in a circuit substrate including a plurality of circuits, so system-level three-dimensional vertical integration can be achieved, thereby greatly reducing the area overhead of the circuit system.

[0114] Although this document contains many details, these details should not be construed as limitations on the present disclosure or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although a feature may be described above as acting in certain combinations and even initially so claimed, in some cases, one or more features of the combination may be deleted from the claimed combination, and the claimed combination may cover a sub-combination or a variation of the sub-combination.

Claims

1. A three-dimensional dynamic random access memory DRAM array structure, comprising: A plurality of DRAM cell structures are arranged into L layers, M rows and N columns, wherein L, M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures comprises: A first gate-all-around transistor and a second gate-all-around transistor, both having a channel of a tubular structure, are arranged in sequence in a vertical direction and electrically connected in parallel, and a storage capacitor having a tubular structure, disposed between the first gate-all-around transistor and the second gate-all-around transistor in a vertical direction, having an inner electrode connected to first sources / drains of the first gate-all-around transistor and the second gate-all-around transistor, and having an outer electrode connected to a source line; M×N bit lines extend vertically inside a tubular structure formed by a first all-around gate transistor and a second all-around gate transistor and a storage capacitor in an M-row and N-column DRAM cell structure, and are respectively connected to second sources / drains of the first all-around gate transistor and the second all-around gate transistor in the M-row and N-column DRAM cell structure; L×M first word lines extending along a first horizontal direction and respectively connected to gates of first all-around gate transistors in L layers and M rows of DRAM cell structures; and L×M second word lines extend along the first horizontal direction and are respectively connected to gates of second all-around gate transistors in the L layers and M rows of DRAM cell structures.

2. The three-dimensional DRAM array structure according to claim 1, further comprising: M×N bit line holes extend through the DRAM array structure in the vertical direction, and the M×N bit lines are respectively arranged in the M×N bit line holes.

3. The three-dimensional DRAM array structure according to claim 1, wherein: L layers of DRAM cell structures are stacked in sequence in the vertical direction, and In the M-row DRAM cell structure, L first word lines and L second word lines are alternately stacked in sequence in the vertical direction.

4. The three-dimensional DRAM array structure according to claim 1, wherein: In each of the M rows of DRAM cell structures, L first word lines are connected to L second word lines, respectively.

5. The three-dimensional DRAM array structure according to claim 1, wherein: In each layer of the L-layer DRAM cell structure, M first word lines are connected together, and M second word lines are connected together.

6. The three-dimensional DRAM array structure according to claim 1, wherein: In each column of N columns of DRAM cell structures, M bit lines are connected together.

7. The three-dimensional DRAM array structure according to claim 1, further comprising: L source lines, respectively corresponding to the L-layer DRAM cell structures, extend along the first horizontal direction and are respectively connected to external electrodes of storage capacitors in the L-layer DRAM cell structures.

8. The three-dimensional DRAM array structure according to claim 7, further comprising: A common electrode groove extends in the first horizontal direction and penetrates the DRAM array structure in the vertical direction, and is arranged between adjacent rows of DRAM unit structures. The L source lines are connected together through the common electrode groove.

9. The three-dimensional DRAM array structure according to claim 7, wherein: The L source lines are connected together in common or in groups outside the DRAM array structure.

10. The three-dimensional DRAM array structure according to claim 1, wherein: The first and second sources / drains, the channel regions, and the inner electrodes of the storage capacitors of the first and second gate-all-around transistors in the L-layer DRAM cell structures of each of the M rows and N columns are formed from the same semiconductor material layer.

11. The three-dimensional DRAM array structure according to claim 10, wherein: The semiconductor material layer includes a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

12. The three-dimensional DRAM array structure according to claim 10, wherein: The semiconductor material layer includes single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene or a combination thereof.

13. A semiconductor device comprising: The three-dimensional DRAM array structure according to any one of claims 1 to 12; as well as The circuit substrate comprises a plurality of circuits, and the three-dimensional DRAM array structure is arranged on the circuit substrate.

14. The semiconductor device according to claim 13, in, The plurality of circuits include a memory interface circuit, a memory controller circuit, a word line circuit, and a bit line circuit, wherein the bit line circuit is connected to the bit line of the three-dimensional DRAM array structure, wherein the word line circuit is connected to the word line of the three-dimensional DRAM array structure, and Wherein, the memory interface circuit is connected to the memory controller circuit and the bit line circuit.

15. The semiconductor device according to claim 13, in, The plurality of circuits include processor circuits, memory controller circuits, word line circuits, and bit line circuits, wherein the bit line circuit is connected to the bit line of the three-dimensional DRAM array structure, wherein the word line circuit is connected to the word line of the three-dimensional DRAM array structure, and Wherein, the processor circuit is connected to the memory controller circuit and the bit line circuit.

16. The semiconductor device according to claim 14 or 15, in, The word line circuit is connected to the word lines of the three-dimensional DRAM array structure through conductive lines and vias extending in the vertical direction.

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