Vertical short-channel transistor and preparation method thereof

Abstract

The invention relates to a vertical short channel transistor and a preparation method thereof, the vertical short channel transistor comprises a Si substrate and a SiO2 layer located on the Si substrate, the SiO2 layer has a first thickness and a second thickness and forms an L-shaped step, a first electrode is arranged on a SiO2 layer area corresponding to the first thickness, a second electrode is arranged on a SiO2 layer area corresponding to the second thickness, and a third electrode is arranged on a SiO2 layer area corresponding to the second thickness. The single-crystal two-dimensional material thin layer MoS2 or WSe2 is arranged on the L-shaped step, the high-dielectric-constant material layer is arranged on the single-crystal two-dimensional material thin layer, one end of the single-crystal two-dimensional material thin layer is in contact with the source electrode, the other end of the single-crystal two-dimensional material thin layer is in contact with the drain electrode, and a third electrode is arranged on the high-dielectric-constant material layer; the transistor shows excellent electrical properties, including low sub-threshold swing, high switch ratio and high driving current; the method is compatible with an existing CMOS technology, the preparation process is simple, cost is low, and the method is suitable for large-scale production.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices for high-density integrated circuits and digital logic applications, and particularly to a vertical short-channel transistor and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology, traditional silicon-based transistors are gradually approaching their physical limits, and short-channel effects (SCEs) have become the main problem restricting device performance. When the device size is reduced to the nanometer level, problems such as increased leakage current and deteriorated subthreshold swing significantly affect the performance of transistors. Two-dimensional materials are considered important candidate materials for next-generation microelectronic devices due to their atomic-scale thickness and excellent electrical properties. Among them, MoS 2 and WSe 2 and other transition metal sulfides have shown great application potential in short-channel transistors due to their high mobility, high on / off ratio, and low leakage current.

[0003] However, the existing manufacturing processes for two-dimensional material transistors still face the following problems: First, traditional two-dimensional transistors are mostly planar structures, and it is difficult to effectively suppress short-channel effects in the short-channel state; second, the processing and transfer processes of two-dimensional materials are complex, and it is difficult to achieve performance consistency for large-area devices; finally, there are still technical difficulties in the selection and integration of device insulating layers. Therefore, how to design a vertical short-channel structure and optimize the manufacturing process to improve device performance and consistency is the current research focus. Summary of the Invention

[0004] The primary objective of the present invention is to provide a vertical short-channel two-dimensional transistor and a method for manufacturing the same, aiming to solve the problems of poor short-channel effect suppression ability, complex manufacturing process, and insufficient performance consistency in existing two-dimensional material transistors. The present invention prepares an Au-SiO 2 -Au vertical mesa through ultraviolet lithography, wet etching technology, and evaporation deposition process. The two-dimensional material (such as MoS 2 or WSe 2 ) is transferred to this vertical mesa by mechanical exfoliation, and further combined with atomic deposition of HfO 2 or Al 2 O 3 or transferred h-BN to act as the gate dielectric layer, and a metal gate electrode (such as Cr / Au) is deposited through an electron beam evaporation deposition process, finally realizing the preparation of a high-performance vertical short-channel two-dimensional transistor.

[0005] On the one hand, the present invention provides a vertical short-channel transistor, including an Si substrate, an SiO 2 layer located on the Si substrate, and the SiO 2The layer has a first thickness and a second thickness, forming an L-shaped step. The first electrode is disposed on the SiO corresponding to the first thickness. 2 layer region, and the second electrode is disposed on the SiO corresponding to the second thickness. 2 layer region. A single-crystal two-dimensional material thin layer of MoS 2 or WSe 2 is disposed on the L-shaped step. A high-k dielectric constant material layer is disposed on the single-crystal two-dimensional material thin layer. One end of the single-crystal two-dimensional material thin layer is in contact with the source electrode, and the other end thereof is in contact with the drain electrode. A third electrode is disposed on the high-k dielectric constant material layer.

[0006] On the one hand, the present invention provides a method for manufacturing a vertical short-channel transistor, including the following steps:

[0007] Clean the SiO 2 / Si substrate, and the SiO on this substrate 2 layer has a first thickness;

[0008] Spin-coat a photoresist layer on the SiO 2 / Si substrate, then use an ultraviolet laser lithography process to etch and form a first electrode pattern. Then, deposit a metal layer, and subsequently remove the photoresist layer to form the first electrode;

[0009] Subsequently, use a wet etching process to etch the SiO outside the first electrode 2 layer to form a SiO layer region with a second thickness. An L-shaped vertical step is formed between the SiO layer region with the first thickness 2 and the SiO layer region with the second thickness. Then, deposit a metal layer to form a second electrode on the SiO layer region with the second thickness 2 2 ; 2 2 layer region;

[0010] Use a mechanical exfoliation method to dispose a single-crystal two-dimensional material thin layer of MoS 2 or WSe 2 on the L-shaped vertical step;

[0011] Use a transfer method or an atomic layer deposition process to dispose a high-k dielectric constant material layer on the single-crystal two-dimensional material thin layer;

[0012] Dispose a gate metal on the high-k dielectric constant material layer;

[0013] Anneal at a high temperature in an inert gas to obtain the vertical short-channel transistor.

[0014] Furthermore, the high-k dielectric constant material layer is h-BN or a high-k dielectric constant oxide.

[0015] Furthermore, the high-k dielectric constant oxide is HfO 2 or Al2 O 3 。

[0016] Further, the first electrode is a drain electrode, the second electrode is a source electrode, and the third electrode is a gate electrode.

[0017] Further, the thickness of the high-k dielectric material layer is 20 - 30 nm.

[0018] Further, the thickness of the single-crystalline two-dimensional material thin layer is 5 nm - 20 nm.

[0019] Further, the source electrode and the drain electrode are Au layers, and the thickness of the Au layer is 30 - 50 nm;

[0020] The gate electrode is a Cr / Au layer, the thickness of the Cr layer is 8 - 12 nm, and the thickness of the Au layer is 40 - 50 nm.

[0021] Further, the annealing temperature is 100 - 150 °C, and the annealing time is 1 - 2 hours.

[0022] Further, the high-k dielectric oxide HfO 2 or Al 2 O 3 is deposited by atomic layer deposition process. In the atomic layer deposition process, the deposition temperature is controlled at 150 - 250 °C, and the deposition thickness is 30 nm.

[0023] Further, the metal layer is evaporated by electron beam evaporation process, and the deposition rate of the metal is 0.01 nm / s.

[0024] Compared with the prior art, the present invention has at least the following beneficial effects:

[0025] The present invention adopts mature evaporation coating, wet etching and mechanical exfoliation technologies, combined with ultraviolet lithography and atomic layer deposition process, to achieve efficient transfer of two-dimensional materials and precise manufacturing of vertical channel transistors. Compared with the complex processing methods in the prior art, the process flow of the present invention is simple, the equipment is easy to obtain, the manufacturing cost is reduced, and the consistency and repeatability of the device are improved. By precisely transferring single-crystalline two-dimensional materials (such as MoS 2 or WSe 2 ) by mechanical exfoliation technology, and combining with the Au-SiO 2 -Au mesa structure, a high-quality heterojunction structure is achieved, and the channel length can be controlled within 150 nm. This method is compatible with a variety of materials (such as h-BN or high-k dielectric oxide layer), providing a technical basis for multi-material heterogeneous integration.

[0026] In addition, in the preparation method provided by the present invention, it is not only applicable to two-dimensional semiconductor materials (such as MoS 2and WSe 2 ) can also be extended to other two-dimensional materials or new dielectric materials (such as h-BN or HfO 2 ), with good versatility and adaptability, providing more choices for device functional design and performance optimization.

[0027] The transistors prepared by the present invention have high-performance electrical characteristics. In one embodiment, the vertical short-channel transistor exhibits excellent electrical performance, including a low subthreshold swing (MoS 2 channel is 162 mV / dec, WSe 2 channel is 82 mV / dec), a high on / off ratio (>10 8 ) and a high drive current (70 μA / μm). The device exhibits low-power operation characteristics and is very suitable for applications in low-power logic circuits and large-scale integrated circuits. In addition, the transistor can be switched between "always-on" and "always-off" modes and is further integrated into a CMOS inverter, showing a voltage gain of up to 21 and a noise margin of 80.5%. The method of the present invention is compatible with existing CMOS processes, with a simple and low-cost preparation process and is suitable for large-scale production. Through this method, multi-device integration can also be achieved, such as the construction of a 2×4 array transistor and digital logic circuits (such as NAND and NOR gates) based on two-dimensional materials, demonstrating the application potential in the fields of high-density digital circuits and next-generation integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the device structure of the vertical short-channel transistor according to an embodiment of the present invention.

[0029] Figure 2 Optical microscope image of the vertical short-channel transistor prepared according to an embodiment of the present invention.

[0030] Figure 3 Transfer characteristic curve of the vertical short-channel transistor prepared according to an embodiment of the present invention.

[0031] Figure 4 SS curve of the vertical short-channel transistor prepared according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present invention. In the following embodiments, the experimental methods are conventional methods unless otherwise specified; the reagents and materials can be obtained from public commercial channels unless otherwise specified.

[0033] In this specification, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those different from the orientations shown in the figures.

[0034] In addition, terms such as "first", "second", etc. are used to describe each element, layer, region, section, etc., and are not intended to be limiting. The terms "having", "containing", "including", etc. are open-ended terms, indicating the presence of the stated element or feature, but do not exclude additional elements or features, unless the context clearly dictates otherwise.

[0035] As Figure 1 shown is a MoS 2 vertical short-channel transistor according to an embodiment of the present invention, which includes a Si substrate, on which a first SiO 2 layer region and a second SiO 2 layer region with different thicknesses are provided. An L-shaped vertical step is formed between the SiO 2 layer region with the first thickness and the SiO 2 layer region with the second thickness. The source electrode is disposed on the SiO 2 layer region with the first thickness, and the drain electrode is disposed on the SiO 2 layer region with the second thickness. In one embodiment, the source electrode and the drain electrode are made of a Cr / Au layer, the thickness of the Cr layer is 8 - 10 nm, and the thickness of the Au layer is 30 - 50 nm, forming an Au-SiO 2 -Au vertical mesa. A single-crystalline two-dimensional material thin layer of MoS 2 is disposed on this Au-SiO 2 -Au vertical mesa, and the thickness of the single-crystalline two-dimensional material thin layer is 5 nm - 20 nm. In this embodiment, the single-crystalline two-dimensional material thin layer of MoS 2 is disposed on the L-shaped vertical mesa, a high-k dielectric material layer is disposed on the single-crystalline two-dimensional material thin layer, one end of the single-crystalline two-dimensional material thin layer is in contact with the source electrode, and the other end thereof is in contact with the drain electrode. The high-k dielectric material layer is h-BN or a high-k dielectric oxide, and the high-k dielectric oxide is HfO 2 or Al2 O 3 ; The thickness of the high-k dielectric material layer is 20 - 30 nm. In this preferred embodiment, the high-k dielectric material layer is h-BN as the insulating layer. Due to its high dielectric strength and low leakage characteristics, h-BN can effectively improve the gate control performance. A top gate electrode is provided on the high-k dielectric material layer. The top gate electrode is selected as a Cr / Au layer, where the thickness of the Cr layer is 8 - 10 nm and the thickness of the Au layer is 30 - 40 nm.

[0036] In another embodiment of the present invention, the single-crystal two-dimensional material thin layer WSe 2 is disposed on the Au-SiO 2 -Au vertical tabletop, and the rest is the same as the above embodiment.

[0037] To make the vertical short-channel transistor of the present invention clearer, the following embodiments will detail the manufacturing method of this transistor.

[0038] First, the SiO 2 / Si growth substrate is successively immersed in acetone solution, isopropyl alcohol solution, and deionized water for cleaning. Each time during cleaning, the substrate is completely immersed in the solution, and an ultrasonic treatment device is used to ultrasonically clean for 5 minutes to remove organic contaminants, particulate impurities, and oxide residues on the surface.

[0039] Next, an ultraviolet laser lithography process is used to etch the electrode tabletop. The substrate is placed on the chuck of a spin coater, the spin coating rate is set at 4000 revolutions per second, the spin coating duration is set to 1 minute, and then the substrate is placed on a heating table and cured at 100 °C for 4 minutes to form the first electrode pattern using ultraviolet laser lithography.

[0040] Next, a 30 - 50 nm Au layer is deposited using an electron beam evaporation process at a deposition rate of 0.01 nm / s. After the deposition is completed, the substrate is immersed in acetone for ten minutes to dissolve the photoresist, thereby removing the excess Au layer to form the first electrode, which is the drain in this embodiment.

[0041] Next, a wet etching process (such as KIO and BOE solutions) is used to etch the SiO 2 layer outside the first electrode region and remove part of the SiO 2 to form a SiO 2 layer region with a second thickness; then the above-mentioned electron beam evaporation process is used to deposit a 30 - 50 nm Au layer to form the second electrode, which is the source in this embodiment, to form an Au-SiO 2-Au mesa structure. After evaporation, it is placed in acetone for ten minutes to dissolve the photoresist, thus removing the excess Au layer. This structure can provide good electrode contact and conductivity for the subsequent transfer of two-dimensional materials, and at the same time form clear channel boundaries in the vertical direction.

[0042] Then, the mechanical exfoliation method is used to transfer MoS 2 and h-BN thin layers in sequence. First, tape is used to paste on the MoS 2 single crystal. The single crystal MoS 2 is exfoliated onto the flexible PDMS substrate. Using a microscope for precise alignment, the MoS 2 (with a thickness of about 6 - 20 nm) thin layer is transferred onto the Au-SiO 2 -Au mesa, covering the vertical channel area and ensuring good contact between the two-dimensional material and the bottom electrode. Next, the thin layer of h-BN is obtained from the bulk single crystal h-BN by the same exfoliation method and transferred onto the MoS 2 thin layer as the insulating layer. Due to its high dielectric strength and low leakage current characteristics, h-BN can effectively improve the gate control performance.

[0043] A 10 nm Cr layer and a 50 nm Au layer are evaporated on h-BN by electron beam evaporation and thermal evaporation processes at an evaporation rate of 0.01 nm / s. Subsequently, it is placed in acetone for ten minutes to remove the photoresist. As the photoresist is dissolved by acetone, the excess gold film will also fall off due to the dissolution of acetone. It is then placed in deionized water for cleaning, and then the moisture on the substrate surface is blown dry with a nitrogen gun. Finally, the substrate is placed in a glove box and annealed at 150 °C in argon for 1 - 2 hours to increase the contact degree between different materials and improve the stability of the device, thereby obtaining the final self-aligned vertical short-channel transistor device.

[0044] Figure 2 The optical microscope image of the MoS 2 vertical short channel obtained by the above preparation method is shown. The source and drain are respectively set at the upper and lower ends of the L-shaped vertical step, and the gate is set above the thin layer of h-BN dielectric layer. Figure 3 For the MoS 2 vertical short-channel transistor obtained by the above preparation, in the scanning range of the gate voltage from -6V to 6V, the transfer characteristic curve with the bias voltage in the range of 0.5V to 3V shows that the transistor has good electrical behavior, extremely low off-state current and extremely high on-state current (70 μA / μm), and has a high on-off ratio (up to 10 8) excellent characteristics. The transfer characteristic curve shows the variation of the drain current of the two-dimensional material vertical short-channel transistor under different gate voltages, clearly indicating the excellent electrical performance of the device. The curve intuitively demonstrates the switching process of the device from the off state to the on state and the current regulation ability. In addition, the drive current shown in the transfer characteristic curve is as high as 70 μA / μm, further verifying the high carrier mobility advantage of the two-dimensional material in the vertical short-channel structure. The linear part of the curve shows that the drain current reaches a saturation value at high gate voltages, indicating that the electron transport process of the device has good stability. This transistor is further integrated into a CMOS inverter, showing a voltage gain as high as 21 and a noise margin of 80.5%.

[0045] Figure 4 The vertical short-channel transistor prepared by the above-mentioned embodiments is shown. When the gate voltage gradually increases, the drain current shows an exponential growth, reflecting the excellent performance of the device in the subthreshold region. The subthreshold swing (SS) is a key parameter, and its subthreshold swing is 162 mV / dec, indicating that the device has strong gate control ability and low leakage current. In another embodiment of the present invention, a single-crystalline two-dimensional material thin layer WSe 2 is used as the channel material, and the subthreshold swing of this device is 82 mV / dec, indicating that the device has strong gate control ability and low leakage current.

[0046] Generally speaking, the transfer characteristic curve fully verifies the excellent performance of the vertical short-channel transistor structure proposed in this study under electric field regulation. It shows significant advantages in suppressing short-channel effects, high switching ratio, low leakage current, and high drive current, providing important theoretical basis and practical support for the application of two-dimensional material transistors in low-power logic circuits and large-scale integrated circuits.

[0047] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A vertical short channel transistor, characterized in that: It includes a Si substrate, a SiO2 layer located on the Si substrate, the SiO2 layer has a first thickness and a second thickness to form an L-shaped step, a first electrode is arranged on a region of the SiO2 layer corresponding to the first thickness, a second electrode is arranged on a region of the SiO2 layer corresponding to the second thickness, a single crystal two-dimensional material thin layer MoS2 or WSe2 is arranged on the L-shaped step, a high dielectric constant material layer is arranged on the single crystal two-dimensional material thin layer, one end of the single crystal two-dimensional material thin layer is in contact with a source electrode, and the other end thereof is in contact with a drain electrode, and a third electrode is arranged on the high dielectric constant material layer.

2. A method for preparing a vertical short channel transistor, characterized in that: The following steps are involved: Cleaning a SiO2 / Si substrate, wherein the SiO2 layer on the substrate has a first thickness; A photoresist layer is spin-coated on a SiO2 / Si substrate, and then a first electrode pattern is formed by etching using an ultraviolet laser photolithography process, followed by evaporation of a metal layer, and then removal of the photoresist layer to form a first electrode; Then, the SiO2 layer outside the first electrode is etched by a wet etching process to form a SiO2 layer region with a second thickness, an L-shaped vertical step is formed between the SiO2 layer region with the first thickness and the SiO2 layer region with the second thickness, and then a metal layer is evaporated to form a second electrode on the SiO2 layer region with the second thickness; A single-crystalline two-dimensional material thin layer of MoS2 or WSe2 is placed on an L-shaped vertical step using a mechanical exfoliation method; A high dielectric constant material layer is provided on a single crystal two-dimensional material thin layer by using a transfer method or an atomic layer deposition process; Depositing a metal layer on the high dielectric constant material layer to form a third electrode; The vertical short channel transistor is obtained by high temperature annealing in an inert gas.

3. The vertical short channel transistor according to claim 1, or the method for preparing the vertical short channel transistor according to claim 2, characterized in that: The high dielectric constant material layer is h-BN or a high dielectric constant oxide.

4. The vertical short channel transistor or the preparation method according to claim 3, characterized in that: The high dielectric constant oxide is HfO2 or Al2O3.

5. The vertical short channel transistor or the preparation method according to claim 3, characterized in that: The first electrode is a drain electrode, the second electrode is a source electrode, and the third electrode is a gate electrode.

6. The vertical short channel transistor or the preparation method according to claim 4 or 5, characterized in that: The thickness of the high dielectric constant material layer is 20-30 nm.

7. The vertical short channel transistor or the preparation method according to claim 6, characterized in that: The thickness of the single crystal two-dimensional material thin layer is 5nm to 20nm.

8. The vertical short channel transistor or the preparation method according to claim 6, characterized in that: The source electrode and the drain electrode are Au layers, and the thickness of the Au layers is 30 to 50 nm; The gate is a Cr / Au layer, the thickness of the Cr layer is 8-12nm, and the thickness of the Au layer is 40-50nm.

9. The preparation method according to claim 2 or 3, characterized in that: The annealing temperature is 100-150° C., and the annealing time is 1-2 hours.

10. The preparation method according to claim 2, characterized in that: The high dielectric constant oxide HfO2 or Al2O3 is deposited by an atomic layer deposition process, wherein the deposition temperature is controlled at 150-250° C. and the deposition thickness is 30 nm; The metal layer is deposited by electron beam evaporation process, and the metal deposition rate is 0.01nm / s.

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