Display device and method of providing display device

Abstract

The invention discloses a display device and a method of providing the same. The display device includes: a substrate; a via insulating layer on the substrate; and a pixel electrode of the light-emitting element on the through-hole insulating layer, the pixel electrode including a first pixel electrode layer, a second pixel electrode layer, and a third pixel electrode layer in order from the through-hole insulating layer, the second pixel electrode layer having a flat upper surface.

Description

Technical Field

[0001] Embodiments relate to a display device and a method of manufacturing (or providing) the display device. Background Art

[0002] Various display devices such as an organic light emitting display device or a quantum dot display device include a plurality of layers such as an insulating layer or a metal layer stacked on a substrate. One or more of the plurality of layers may have surface unevenness. Summary of the invention

[0003] Since the surface non-uniformity of one or more layers in the stack of layers of the display device may be transferred to an adjacent layer and affect the adjacent layer, the surface non-uniformity removal may be performed on the stack of layers. For example, during the process of manufacturing (or providing) the display device, a polishing process such as chemical mechanical polishing (CMP) may be used to flatten the surfaces of the multiple layers or remove the step differences between the multiple layers.

[0004] The embodiment provides a display device with improved display quality.

[0005] The embodiment provides a method of manufacturing (or providing) a display device.

[0006] A display device according to an embodiment of the present disclosure includes: a substrate; a through-hole insulating layer on the substrate; a first pixel electrode on the through-hole insulating layer; a second pixel electrode on the first pixel electrode and having a flat upper surface; and a third pixel electrode on the second pixel electrode.

[0007] In an embodiment, the thickness of the second pixel electrode may not be constant.

[0008] In embodiments, an upper surface of the second pixel electrode may be polished to be flat (eg, a polished surface).

[0009] In embodiments, an upper surface of the via insulating layer may be polished to be flat (eg, a polished surface).

[0010] In an embodiment, the thickness of the via insulating layer may not be constant.

[0011] In an embodiment, the display device may further include: a light emitting layer on the third pixel electrode and including quantum dots.

[0012] In an embodiment, the display device may further include: a first active pattern on the substrate; and a second active pattern on the substrate, spaced apart from the first active pattern and including a material different from that of the first active pattern.

[0013] According to an embodiment of the present disclosure, a method for manufacturing (or providing) a display device includes: forming (or providing) a through-hole insulating layer on a substrate; forming a first pixel electrode layer on the through-hole insulating layer; forming a second pixel electrode layer having a flat upper surface on the first pixel electrode layer; and forming a third pixel electrode layer on the second pixel electrode layer.

[0014] In an embodiment, forming the second pixel electrode layer may include: forming a preliminary second pixel electrode layer having an upper surface whose level is not constant on the first pixel electrode layer; and polishing the upper surface of the preliminary second pixel electrode layer to form the second pixel electrode layer.

[0015] In an embodiment, the formation of the second pixel electrode layer may be performed by a chemical mechanical polishing process.

[0016] In an embodiment, the formation of the second pixel electrode layer may be performed using a zirconium oxide slurry.

[0017] In an embodiment, in the forming of the second pixel electrode layer, an upper surface of the preliminary second pixel electrode layer may be polished by a difference between a minimum level of the upper surface of the preliminary second pixel electrode layer and a maximum level of the upper surface of the preliminary second pixel electrode layer.

[0018] In an embodiment, the difference may be about 100 angstroms. To about

[0019] In an embodiment, the second pixel electrode layer may be formed to have a non-constant thickness.

[0020] In an embodiment, after the formation of the third pixel electrode layer, the method may further include: forming a pixel electrode by patterning the first pixel electrode layer, the second pixel electrode layer, and the third pixel electrode layer; and forming a light emitting layer on the pixel electrode.

[0021] In an embodiment, the light emitting layer may be formed by an inkjet process.

[0022] In an embodiment, the light emitting layer may include quantum dots.

[0023] In an embodiment, the forming of the via insulating layer may include: forming a preliminary via insulating layer having an upper surface whose level is not constant on the substrate; and polishing the upper surface of the preliminary via insulating layer to form the via insulating layer having a flat upper surface.

[0024] In embodiments, the via insulating layer may be formed to have a non-constant thickness.

[0025] In an embodiment, the method may further include: forming a first active pattern on the substrate; and forming a second active pattern on the substrate that is spaced apart from the first active pattern and includes a material different from that of the first active pattern.

[0026] In a display device according to an embodiment of the present disclosure, the display device may include a pixel electrode, the pixel electrode includes a first pixel electrode, a second pixel electrode and a third pixel electrode, and the upper surface of the second pixel electrode is polished to be substantially flat. Since the thickness of the light-emitting layer on the pixel electrode can be substantially uniform without a step difference, the luminous efficiency and brightness uniformity of the light-emitting element can be improved. In addition, since the upper surface of the second pixel electrode can be polished to provide a polished surface, the roughness of the second pixel electrode can be reduced, and thus the reflectivity of the light-emitting element can be improved. Accordingly, the display quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0029] Figure 3 yes Figure 2 An enlarged cross-sectional view of area A.

[0030] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 The diagram is manufactured (or provided) Figure 2 A cross-sectional view of a method for displaying a device.

[0031] Fig.13 is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0032] Fig.14 yes Fig.13 An enlarged cross-sectional view of region E.

[0033] Fig.15 , Fig.16 and Fig.17 Is manufactured (or provided) Fig.13 A cross-sectional view of a method for displaying a device. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0035] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals refer to the same elements from beginning to end. For example, in the drawings and text of the present disclosure, the reference numerals indicating the singular form of an element may also be used to refer to a plurality of singular elements.

[0036] It will be understood that when an element is referred to as being associated with another element (e.g., "on" another element), it can be directly on the other element or intervening elements may be present therebetween. Conversely, when an element is referred to as being associated with another element (e.g., "directly on" another element), there are no intervening elements present.

[0037] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0038] The terms used herein are only for the purpose of describing a particular embodiment, and are not intended to be limited. As used herein, unless the context clearly indicates otherwise, "one", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the reference to "one" element in the claim (followed by the reference to "the" element) includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as a restrictive "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the related listed items. It will be further understood that when the term "includes" or "comprising" is used in this specification, it is indicated that the existence of the stated features, regions, entireties, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or its groups.

[0039] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the accompanying drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0040] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0042] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Therefore, variations in the shapes of the illustrations, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0043] Figure 1 is a plan view illustrating a display device 10 according to an embodiment of the present disclosure.

[0044] refer to Figure 1 , the display device 10 may include a display area DA and a non-display area NDA.

[0045] The pixel PX may be provided in the display area DA, and the pixel PX may be provided in plurality to define a plurality of pixels PX. The plurality of pixels PX may be arranged in a first direction D1 (or along the first direction D1) and in a second direction D2 (or along the second direction D2) intersecting the first direction D1. For example, the first direction D1 may be perpendicular to the second direction D2. Each of the plurality of pixels PX may emit light. Since each of the plurality of pixels PX may emit light, the display area DA may display an image using the emitted light.

[0046] Lines (eg, signal lines, conductive lines, etc.) connected to the plurality of pixels PX may be further provided in the display area DA. For example, the lines may include data signal lines, gate signal lines, power lines, and the like.

[0047] The non-display area NDA may be an area where an image is not displayed. The non-display area NDA may be disposed adjacent to the display area DA, for example, around the display area DA. For example, the non-display area NDA may surround the display area DA. The display area DA and the non-display area NDA may have a plane area defined along a plane defined by a first direction D1 and a second direction D2 intersecting each other.

[0048] A driver for driving the plurality of pixels PX may be disposed in the non-display area NDA. For example, the driver may include a data driver, a gate driver, a power voltage generator, a timing controller, etc. The plurality of pixels PX may emit light based on a signal received from the driver.

[0049] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'. Figure 3 yes Figure 2 An enlarged cross-sectional view of region A of FIG. Figure 3 may be an enlarged cross-sectional view of the pixel electrode PE included in the display device 10 .

[0050] refer to Figure 1 , Figure 2 and Figure 3 The display device 10 may include a substrate SUB, a buffer layer BFR, a plurality of insulating layers, a first active pattern AP1, a first gate layer, a second gate layer, a second active pattern AP2, a third gate layer, a first conductive layer, a second conductive layer, a light emitting element LE, a pixel defining layer PDL, and an encapsulation layer TFE.

[0051] The substrate SUB may include a transparent material or an opaque material. For example, the substrate SUB may include a rigid glass substrate, a plastic substrate, a flexible film, or a metal substrate, etc. These may be used alone or in combination with each other.

[0052] The buffer layer BFR may be disposed on the substrate SUB. The buffer layer BFR may prevent metal atoms or impurities from diffusing from the substrate SUB and diffusing into other layers within the stacked structure on the substrate SUB. In addition, when the surface of the substrate SUB is uneven, the buffer layer BFR may improve the flatness of the surface of the substrate SUB on which other layers are provided. The buffer layer BFR may include a silicon oxide (SiO x ), Silicon Nitride (SiN x ), Silicon Carbide (SiC x ), silicon oxynitride (SiO x N y ) or silicon oxycarbide (SiO x C y ) etc. These may be used alone or in combination with each other.

[0053] The first active pattern AP1 may be disposed on the buffer layer BFR. The first active pattern AP1 may include a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the first active pattern AP1 may include a silicon semiconductor material. Examples of silicon semiconductor materials may include amorphous silicon or polycrystalline silicon, etc. These may be used alone or in combination with each other.

[0054] The first gate insulating layer GI1 may be disposed on the buffer layer BFR and the first active pattern AP1. The first gate insulating layer GI1 may cover the first active pattern AP1. The first gate insulating layer GI1 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0055] The first gate layer may be disposed on the first gate insulating layer GI1. The first gate layer may include a first gate electrode GE1. In a plan view, the first gate electrode GE1 may overlap with a channel region of the first active pattern AP1. The first gate layer may include a metal, an alloy, a conductive metal oxide, or a conductive metal nitride, etc. Examples of the metal may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc), etc. Examples of the conductive metal oxide may include indium tin oxide or indium zinc oxide, etc. Examples of the conductive metal nitride may include aluminum nitride (AlN x ), tungsten nitride (WN x ) or chromium nitride (CrN x ) etc. These may be used alone or in combination with each other.

[0056] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and the first gate layer. The second gate insulating layer GI2 may cover the first gate layer. The second gate insulating layer GI2 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0057] The second gate layer may be disposed on the second gate insulating layer GI2. The second gate layer may include a capacitor electrode CAE and a second gate electrode GE2. In a plan view, the capacitor electrode CAE may overlap with the first gate electrode GE1. For example, the capacitor electrode CAE and the first gate electrode GE1 may together define a storage capacitor. The second gate electrode GE2 may be spaced apart from the capacitor electrode CAE. The second gate layer may include a metal, an alloy, a conductive metal oxide or a conductive metal nitride, etc. These may be used alone or in combination with each other.

[0058] The capacitor electrode CAE and the second gate electrode GE2 may be in the same layer as each other. Since they are in the same layer, multiple elements may be formed in the same process and / or include the same material as each other, multiple elements may be parts of the same material layer, and multiple elements may be in the same layer by forming an interface with the same lower layer or the same upper layer, etc., but are not limited thereto.

[0059] The first interlayer insulating layer ILD1 may be disposed on the second gate insulating layer GI2 and the second gate layer. The first interlayer insulating layer ILD1 may cover the second gate layer. The first interlayer insulating layer ILD1 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0060] The second active pattern AP2 may be disposed on the first interlayer insulating layer ILD1. The second active pattern AP2 may include a source region, a drain region, and a channel region between the source region and the drain region. The second active pattern AP2 may be spaced apart from the first active pattern AP1, and may include a material different from that of the first active pattern AP1. However, the present disclosure is not limited thereto, and the second active pattern AP2 may include the same material as that of the first active pattern AP1. In an embodiment, the second active pattern AP2 may include an oxide semiconductor material. Examples of oxide semiconductor materials may include indium gallium zinc oxide or indium tin zinc oxide, etc. These may be used alone or in combination with each other.

[0061] The third gate insulating layer GI3 may be disposed on the first interlayer insulating layer ILD1 and the second active pattern AP2. The third gate insulating layer GI3 may cover the second active pattern AP2. The third gate insulating layer GI3 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0062] The third gate layer may be disposed on the third gate insulating layer GI3. The third gate layer may include a third gate electrode GE3. In a plan view, the third gate electrode GE3 may overlap with the channel region of the second active pattern AP2. In addition, in a plan view, the third gate electrode GE3 may overlap with the second gate electrode GE2. The third gate layer may include a metal, an alloy, a conductive metal oxide or a conductive metal nitride, etc. These may be used alone or in combination with each other.

[0063] The second interlayer insulating layer ILD2 may be disposed on the third gate insulating layer GI3 and the third gate layer. The second interlayer insulating layer ILD2 may cover the third gate layer. The second interlayer insulating layer ILD2 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0064] The first conductive layer may be disposed on the second interlayer insulating layer ILD2. The first conductive layer may include a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2. The first conductive layer may include a metal, an alloy, a conductive metal oxide, or a conductive metal nitride, etc. These may be used alone or in combination with each other.

[0065] The first source electrode SE1 and the first drain electrode DE1 may be connected to the first active pattern AP1. For example, the first source electrode SE1 may be in contact with the source region of the first active pattern AP1, and the first drain electrode DE1 may be in contact with the drain region of the first active pattern AP1. In addition, the second source electrode SE2 and the second drain electrode DE2 may be connected to the second active pattern AP2. For example, the second source electrode SE2 may be in contact with the source region of the second active pattern AP2, and the second drain electrode DE2 may be in contact with the drain region of the second active pattern AP2. When in contact, the elements may be in physical contact, such as forming an interface between the elements, but is not limited thereto. Within a pixel circuit layer, such as within a switching element or a transistor, a corresponding source electrode and a corresponding drain electrode may be connected (e.g., electrically connected) to a corresponding active pattern.

[0066] The first through-hole insulating layer VIA1 may be disposed on the second interlayer insulating layer ILD2 and the first conductive layer. The first through-hole insulating layer VIA1 may cover the first conductive layer. The upper surface of the first through-hole insulating layer VIA1 may not be substantially flat due to a cross-sectional structure or profile defined by a lower component (e.g., a layer thereunder). That is, the upper surface of the first through-hole insulating layer VIA1 may have a step difference, and the horizontal height of the upper surface of the first through-hole insulating layer VIA1 may not be substantially constant. That is, the distance or horizontal height of the upper surface of the first through-hole insulating layer VIA1 relative to a reference such as the upper surface of the substrate SUB may be non-constant. The first through-hole insulating layer VIA1 may include an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. These may be used alone or in combination with each other.

[0067] The second conductive layer may be disposed on the first through-hole insulating layer VIA1. The second conductive layer may include a connection electrode CNE. The connection electrode CNE may be connected to the first drain electrode DE1 or the first source electrode SE1. For example, the connection electrode CNE may contact the first drain electrode DE1 or the first source electrode SE1. The second conductive layer may include a metal, an alloy, a conductive metal oxide, or a conductive metal nitride, etc. These may be used alone or in combination with each other.

[0068] The second through-hole insulating layer VIA2 may be disposed on the first through-hole insulating layer VIA1 and the second conductive layer. The second through-hole insulating layer VIA2 may cover the second conductive layer. The second through-hole insulating layer VIA2 may have a single-layer structure or a multi-layer structure. Due to the lower components, the upper surface of the second through-hole insulating layer VIA2 may not be substantially flat. That is, the upper surface of the second through-hole insulating layer VIA2 may have a step difference, and the horizontal height of the upper surface of the second through-hole insulating layer VIA2 may not be substantially constant. The second through-hole insulating layer VIA2 may include an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. These may be used alone or in combination with each other.

[0069] The light emitting element LE may be disposed on the second through hole insulating layer VIA2. The light emitting element LE may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE. In an embodiment, the light emitting element LE of the image display layer may be connected to a pixel circuit layer that provides an electrical signal (e.g., a drive signal, a control signal, etc.) to the pixel PX. The pixel circuit layer may include a switching element, a transistor, a capacitor, etc.

[0070] The pixel electrode PE may be disposed on the second through-hole insulating layer VIA2. The pixel electrode PE may be connected to the connection electrode CNE. For example, the pixel electrode PE may be in contact with the connection electrode CNE. In an embodiment, the upper surface of the pixel electrode PE may be substantially flat. That is, the upper surface of the pixel electrode PE may not have a step difference, and the upper surface of the pixel electrode PE may be substantially constant from the horizontal height of the reference. The pixel electrode PE may include a first pixel electrode PE1 as a first pixel electrode layer, a second pixel electrode PE2 as a second pixel electrode layer, and a third pixel electrode PE3 as a third pixel electrode layer.

[0071] The first pixel electrode PE1 may be disposed on the second through-hole insulating layer VIA2. The first pixel electrode PE1 may be disposed along the profile of the second through-hole insulating layer VIA2. That is, the upper surface of the first pixel electrode PE1 may not be substantially flat, and may have a cross-sectional profile corresponding to the cross-sectional profile of the upper surface of the first pixel electrode layer. The first pixel electrode PE1 may include a conductive metal oxide. For example, the first pixel electrode PE1 may include indium tin oxide (ITO), but the present disclosure is not limited thereto.

[0072] The second pixel electrode PE2 may be disposed on the first pixel electrode PE1. In an embodiment, an upper surface S1 of the second pixel electrode PE2 may be substantially flat. That is, the upper surface S1 of the second pixel electrode PE2, which is the surface farthest from the substrate SUB, may not have a step difference, and the horizontal height of the upper surface S1 of the second pixel electrode PE2 may be substantially constant. The second pixel electrode layer flattens the upper surface of the first pixel electrode layer. For example, the material layer of the second pixel electrode layer having an uneven upper surface may be polished to define a substantially flat upper surface S1 of the second pixel electrode PE2.

[0073] The lower surface S2 of the second pixel electrode PE2, which is the surface closest to the substrate SUB, may be arranged along the contour of the first pixel electrode PE1 to have a shape corresponding thereto. Accordingly, the lower surface S2 of the second pixel electrode PE2 may not be substantially flat. That is, the lower surface S2 of the second pixel electrode PE2 may have a step difference, and the horizontal height of the lower surface S2 of the second pixel electrode PE2 may not be substantially constant.

[0074] In an embodiment, the thickness of the second pixel electrode PE2 may not be constant. Here, the thickness of the second pixel electrode PE2 may be the length (or size) of the second pixel electrode PE2 in a third direction D3 that intersects with each of the first direction D1 and the second direction D2 to define the thickness direction. For example, the third direction D3 may be perpendicular to each of the first direction D1 and the second direction D2. Since the lower surface S2 of the second pixel electrode PE2 may not be substantially flat, and the upper surface S1 of the second pixel electrode PE2 may be substantially flat, the thickness of the second pixel electrode PE2 may be uneven in the direction along the second through-hole insulating layer VIA2. Here, in the pixel electrode PE, the first pixel electrode layer (e.g., the first pixel electrode PE1) has an uneven upper surface in the direction along the first pixel electrode layer, and the thickness of the second pixel electrode layer (e.g., the second pixel electrode PE2) is not constant in the direction along the first pixel electrode layer.

[0075] The second pixel electrode PE2 may include a metal that is a material different from that of the first pixel electrode PE1. For example, the second pixel electrode PE2 may include silver, but the present disclosure is not limited thereto. In an embodiment, the roughness (e.g., image surface roughness) of the upper surface S1 of the second pixel electrode PE2 may be less than or equal to about 1.4 nanometers (nm). Accordingly, the reflectivity of the second pixel electrode PE2 may be improved by having a surface roughness disclosed herein.

[0076] The third pixel electrode PE3 may be disposed on the second pixel electrode PE2. The third pixel electrode PE3 may be disposed along the contour of the upper surface S1 of the second pixel electrode PE2. That is, except for the lower surface of the third pixel electrode PE3, the upper surface of the third pixel electrode PE3 may also be substantially flat. The third pixel electrode PE3 may include a conductive metal oxide as a material different from that of the second pixel electrode PE2. For example, the third pixel electrode PE3 may include indium tin oxide, but the present disclosure is not limited thereto.

[0077] The pixel defining layer PDL may be disposed on the second through hole insulating layer VIA2 and the pixel electrode PE. The pixel defining layer PDL may include a pixel opening defined therein. The pixel opening defined in the pixel defining layer PDL may expose at least a portion of the pixel electrode PE to the outside of the pixel defining layer PDL. For example, the pixel defining layer PDL may cover the side surface of the pixel electrode PE. The pixel defining layer PDL may include an organic material or an inorganic material.

[0078] The light emitting layer EL may be disposed on the pixel electrode PE. The light emitting layer EL may be disposed on the upper surface of the pixel electrode PE that is exposed to the outside of the pixel defining layer PDL through the pixel opening defined in the pixel defining layer PDL. Since the upper surface of the pixel electrode PE is substantially flat, the thickness of the light emitting layer EL may be substantially constant. Here, the thickness of the light emitting layer EL may be the length of the light emitting layer EL in the third direction D3.

[0079] In an embodiment, the light emitting layer EL may include quantum dots. The quantum dots may emit light by excitation caused by light, and may improve color purity and color reproducibility. For example, the light emitting element LE may be a quantum dot light emitting element. The quantum dots may have a single structure with homogeneous components and composition or may have a composite structure such as a core-shell structure or a gradient structure. For example, the quantum dots may include II-VI semiconductor compounds, III-VI semiconductor compounds, III-V semiconductor compounds, IV-VI semiconductor compounds, IV group elements or compounds, or I-III-VI semiconductor compounds. These may be used alone or in combination. However, the present disclosure is not limited thereto, and the light emitting layer EL may include an organic light emitting material and the light emitting element LE may be an organic light emitting element.

[0080] A functional layer such as a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer may be provided on or under the light emitting layer EL.

[0081] The common electrode CE may be disposed on the pixel defining layer PDL and the light emitting layer EL. The common electrode CE may include metal, alloy, conductive metal oxide, conductive metal nitride or transparent conductive material, etc. These may be used alone or in combination with each other. The common electrode CE may extend continuously throughout a plurality of pixels PX.

[0082] Accordingly, a light emitting element LE including a pixel electrode PE, a light emitting layer EL, and a common electrode CE may be disposed on the substrate SUB. The light emitting element LE may emit light in a third direction D3.

[0083] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may protect the light emitting element LE from external oxygen and moisture. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer.

[0084] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 The diagram is manufactured (or provided) Figure 2 A cross-sectional view of a method of displaying the device 10. For example, Figure 7 Can be Figure 6 An enlarged cross-sectional view of region B, Fig. 9 Can be Figure 8 An enlarged cross-sectional view of region C, and Fig.11 Can be Fig.10 An enlarged cross-sectional view of region D.

[0085] refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 The method of manufacturing (or providing) the display device 10 described may be a method of manufacturing a reference Figure 1 , Figure 2 and Figure 3 Accordingly, redundant descriptions will be omitted or simplified.

[0086] refer to Figure 4 A buffer layer BFR, a first active pattern AP1, a first gate insulating layer GI1, a first gate layer, a second gate insulating layer GI2, a second gate layer, a first interlayer insulating layer ILD1, a second active pattern AP2, a third gate insulating layer GI3, a third gate layer, a second interlayer insulating layer ILD2, a first conductive layer, a first through hole insulating layer VIA1, a second conductive layer, and a second through hole insulating layer VIA2 can be sequentially formed on the substrate SUB.

[0087] The upper surface of the second via insulating layer VIA2 may not be substantially flat. A contact hole exposing at least a portion of the connection electrode CNE to the outside of the second via insulating layer VIA2 may be formed (or provided) in the second via insulating layer VIA2 at a position corresponding to the switching element (or transistor).

[0088] refer to Figure 5 , a first pixel electrode layer PEL1 may be formed on the second through hole insulating layer VIA2. A material layer for forming the first pixel electrode layer PEL1 may be formed along the contour of the second through hole insulating layer VIA2. That is, the upper surface of the first pixel electrode layer PEL1 provided by the material layer may not be substantially flat. The first pixel electrode layer PEL1 may contact the connection electrode CNE through a contact hole formed in the second through hole insulating layer VIA2 (or in the contact hole). The first pixel electrode layer PEL1 may include a conductive material such as a conductive metal oxide. For example, the first pixel electrode layer PEL1 may include indium tin oxide, but the present disclosure is not limited thereto.

[0089] refer to Figure 6 and Figure 7 , a preliminary second pixel electrode layer P_PEL2 may be formed on the first pixel electrode layer PEL1. A material layer for preliminary forming the preliminary second pixel electrode layer P_PEL2 may be formed along the contour of the first pixel electrode layer PEL1. That is, the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 may not be substantially flat. The preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 may have a step difference, and the level of the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 relative to the lower layer of the image substrate SUB may not be substantially constant.

[0090] The prepared upper surface P_S1 of the prepared second pixel electrode layer P_PEL2 may include a minimum horizontal height LL where the prepared upper surface P_S1 is closest to the substrate SUB among the positions along the substrate SUB and a maximum horizontal height HL where the prepared upper surface P_S1 is farthest from the substrate SUB among the positions along the substrate SUB. The minimum horizontal height LL ( Figure 7 The dotted line in the figure) may be defined at a plane that is substantially common to the entire material layer. The lower thickness portion of the preliminary second pixel electrode layer P_PEL2 may be defined below the plane defined at the minimum horizontal height LL, and the upper thickness portion may be defined above the plane. The lower thickness portion and the upper thickness portion may intersect at the plane.

[0091] For example, when forming the preliminary second pixel electrode layer P_PEL2, the upper thickness portion of the preliminary second pixel electrode layer P_PEL2 may be formed by a difference ST between the minimum horizontal height LL of the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 and the maximum horizontal height HL of the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2. For example, when the thickness of the existing preliminary second pixel electrode layer P_PEL2 is about 800 angstroms, And the difference ST is approximately When That is, the total thickness may be determined by the maximum horizontal height HL and the lower surface S2 (reference Figure 3 Here, each thickness of the preliminary second pixel electrode layer P_PEL2 may be the length (or height) of the preliminary second pixel electrode layer P_PEL2 in the third direction D3.

[0092] In an embodiment, a difference ST between a minimum horizontal height LL of the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 and a maximum horizontal height HL of the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 may be approximately To about However, the present disclosure is not limited thereto.

[0093] refer to Figure 7 , Figure 8 and Fig. 9 , the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 may be polished to form a second pixel electrode layer PEL2 having a flat upper surface. In an embodiment, the preliminary second pixel electrode layer P_PEL2 may be polished with a difference ST. That is, the total thickness of the preliminary second pixel electrode layer P_PEL2 is reduced to define a flat upper surface, wherein the reduced thickness corresponds to the difference ST. Here, in providing the second pixel electrode layer PEL2, the uneven upper surface of the preliminary second pixel electrode layer P_PEL2 is polished to remove a thickness portion of the preliminary second pixel electrode layer P_PEL2 corresponding to the difference ST.

[0094] Since the preliminary second pixel electrode layer P_PEL2 may be polished at its preliminary upper surface P_S1, the planarized upper surface L_S1 (or the polished upper surface) of the second pixel electrode layer PEL2 may be substantially flat. That is, the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may not have a step difference, and the level of the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may be substantially constant relative to a reference surface or a reference plane.

[0095] For example, the preliminary upper surface P_S1 of the preliminary second pixel electrode layer P_PEL2 may be polished by a chemical mechanical polishing (CMP) process. In addition, the polishing process may be performed using zirconium oxide slurry, but the present disclosure is not limited thereto.

[0096] In an embodiment, the thickness of the second pixel electrode layer PEL2 at a position along the first pixel electrode layer PEL1 may not be constant. Here, at a corresponding position along the first pixel electrode layer PEL1, the thickness of the second pixel electrode layer PEL2 may be the length of the second pixel electrode layer PEL2 in the third direction D3. That is, since the lower surface L_S2 of the second pixel electrode layer PEL2 may be formed along the contour of the first pixel electrode layer PEL1, and the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may be formed to be substantially flat by a polishing process, the thickness of the second pixel electrode layer PEL2 along the first pixel electrode layer PEL1 may be uneven.

[0097] The second pixel electrode layer PEL2 may include a conductive material such as a metal. For example, the second pixel electrode layer PEL2 may include silver, but the present disclosure is not limited thereto. Since the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may be formed by a polishing process, the surface roughness of the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may be reduced. For example, the surface roughness of the planarized upper surface L_S1 of the second pixel electrode layer PEL2 may be less than or equal to about 1.4 nm. Accordingly, the reflectivity of the second pixel electrode layer PEL2 may be improved.

[0098] refer to Fig.10 and Fig.11 , a third pixel electrode layer PEL3 may be formed on the second pixel electrode layer PEL2.

[0099] The third pixel electrode layer PEL3 may be disposed along a contour of the planarized upper surface L_S1 of the second pixel electrode layer PEL2. That is, the upper surface of the third pixel electrode layer PEL3 may be substantially flat. The third pixel electrode layer PEL3 may include a conductive metal oxide. For example, the third pixel electrode layer PEL3 may include indium tin oxide, but the present disclosure is not limited thereto. In an embodiment, due to the planarized upper surface L_S1 of the second pixel electrode layer PEL2 along which a material layer for forming the third pixel electrode layer PEL3 is provided, the upper surface of the third pixel electrode layer PEL3 may be substantially flat.

[0100] Accordingly, a pixel electrode layer PEL including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2, and a third pixel electrode layer PEL3 may be formed on the second through hole insulating layer VIA2. The upper surface of the pixel electrode layer PEL may be substantially flat. The upper surface of the pixel electrode layer PEL may be substantially flat. The minimum horizontal height LL (reference Figure 7 ) are coplanar or parallel.

[0101] refer to Fig.10 and Fig.12 , the pixel electrode layer PEL as a preliminary pixel electrode may be patterned to form a pixel electrode PE including a patterned portion of each of the first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the third pixel electrode layer PEL3. That is, the first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the third pixel electrode layer PEL3 may be patterned to form the pixel electrode PE. The upper surface of the pixel electrode PE may be substantially flat.

[0102] Return to reference Figure 2 , a pixel defining layer PDL, a light emitting layer EL, a common electrode CE and an encapsulation layer TFE may be sequentially formed on the pixel electrode PE.

[0103] In an embodiment, the light emitting layer EL may be formed by an inkjet process. In this case, since the upper surface of the pixel electrode PE may be substantially flat, the thickness of the light emitting layer EL may be substantially uniform. In an embodiment, since the upper surface of the pixel electrode PE along which the material layer for forming the light emitting layer EL is provided, the thickness of the light emitting layer EL may be substantially uniform.

[0104] The display device 10 according to an embodiment of the present disclosure may include a second pixel electrode PE2 whose upper surface S1 is flattened to be substantially flat, for example, by polishing. Since the thickness of the light emitting layer EL disposed on the second pixel electrode PE2 may be substantially uniform without a step difference due to the flat upper surface of the pixel electrode PE, the luminous efficiency and brightness uniformity of the light emitting element LE may be improved. In addition, since the upper surface S1 of the second pixel electrode PE2 may be polished, the roughness of the second pixel electrode PE2 may be reduced, and thus the reflectivity of the light emitting element LE may be improved. Accordingly, the display quality of the display device 10 may be improved.

[0105] Fig.13 is a cross-sectional view illustrating a display device 20 according to an embodiment of the present disclosure. Fig.14 yes Fig.13 An enlarged cross-sectional view of region E of FIG. For example, Fig.13 Can be with Figure 2 The cross-sectional view corresponds to the cross-sectional view of .

[0106] In the following, the references will be omitted or simplified. Figure 1 , Figure 2 and Figure 3 The description of the display device 10 is repeated.

[0107] refer to Fig.13 The display device 20 may include a substrate SUB, a buffer layer BFR, a plurality of insulating layers, a first active pattern AP1, a first gate layer, a second gate layer, a second active pattern AP2, a third gate layer, a first conductive layer, a second conductive layer, a light emitting element LE, a pixel defining layer PDL, and an encapsulation layer TFE.

[0108] A buffer layer BFR, a first active pattern AP1, a first gate insulation layer GI1, a first gate layer, a second gate insulation layer GI2, a second gate layer, a first interlayer insulation layer ILD1, a second active pattern AP2, a third gate insulation layer GI3, a third gate layer, a second interlayer insulation layer ILD2, a first conductive layer, a first through hole insulation layer VIA1, and a second conductive layer may be sequentially disposed on a substrate SUB.

[0109] The upper surface of the first via insulating layer VIA1 may not be substantially flat due to lower components. That is, the upper surface of the first via insulating layer VIA1 may have a step difference, and the level of the upper surface of the first via insulating layer VIA1 may not be substantially constant.

[0110] The second through-hole insulating layer VIA2 may be disposed on the first through-hole insulating layer VIA1 and the second conductive layer. The second through-hole insulating layer VIA2 may cover the second conductive layer. The second through-hole insulating layer VIA2 may have a single-layer structure or a multi-layer structure. In an embodiment, the upper surface SF of the second through-hole insulating layer VIA2 may be substantially flat. That is, the upper surface SF of the second through-hole insulating layer VIA2 may not have a step difference, and the horizontal height of the upper surface SF of the second through-hole insulating layer VIA2 may be substantially constant. For example, the upper surface SF of the second through-hole insulating layer VIA2 may be polished to be substantially flat.

[0111] The lower surface of the second through-hole insulating layer VIA2 may be arranged along the uneven contour of the first through-hole insulating layer VIA1. Accordingly, the lower surface of the second through-hole insulating layer VIA2 may not be substantially flat. That is, the lower surface of the second through-hole insulating layer VIA2 may have a step difference, and the horizontal height of the lower surface of the second through-hole insulating layer VIA2 may not be substantially constant. Here, at a position overlapping with the pixel electrode PE, the through-hole insulating layer includes: a first through-hole insulating layer VIA1, defining an uneven upper surface; and a second through-hole insulating layer VIA2, between the substrate SUB and the first pixel electrode layer, closer to the pixel electrode PE than the first through-hole insulating layer VIA1, and having a flat upper surface, and the thickness of the second through-hole insulating layer VIA2 is not constant in the direction along the pixel electrode PE.

[0112] In an embodiment, the thickness of the second through-hole insulation layer VIA2 may not be constant at a position along the first through-hole insulation layer VIA1. Here, the thickness of the second through-hole insulation layer VIA2 may be the length of the second through-hole insulation layer VIA2 in the third direction D3. Since the lower surface of the second through-hole insulation layer VIA2 may not be substantially flat, and the upper surface SF of the second through-hole insulation layer VIA2 may be substantially flat, the thickness of the second through-hole insulation layer VIA2 may not be uniform.

[0113] The light emitting element LE may be disposed on a portion of the second via insulating layer VIA2. The light emitting element LE may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0114] The pixel electrode PE may be disposed on the second through hole insulating layer VIA2 and may include, in sequence along a thickness direction, a first pixel electrode PE1 disposed on the second through hole insulating layer VIA2, a second pixel electrode PE2 disposed on the first pixel electrode PE1, and a third pixel electrode PE3 disposed on the second pixel electrode PE2.

[0115] The pixel electrode PE may be disposed along the contour of the upper surface SF of the second through-hole insulating layer VIA2. That is, the upper surface of the pixel electrode PE may be substantially flat. The upper surface of the pixel electrode PE may not have a step difference, and the level of the upper surface of the pixel electrode PE may be substantially constant.

[0116] The pixel defining layer PDL may be disposed on the second via hole insulating layer VIA2 and the pixel electrode PE, and may expose at least a portion of the pixel electrode PE to the outside of the pixel defining layer PDL.

[0117] The light emitting layer EL may be disposed on the pixel electrode PE exposed by the pixel defining layer PDL. Since the upper surface SF of the second through hole insulating layer VIA2 and the upper surface of the pixel electrode PE may be substantially flat, the thickness of the light emitting layer EL may be substantially constant. Here, the thickness of the light emitting layer EL may be the length of the light emitting layer EL in the third direction D3. In an embodiment, the light emitting layer EL may include quantum dots.

[0118] The common electrode CE may be disposed on the pixel defining layer PDL and the light emitting layer EL, and the encapsulation layer TFE may be disposed on the common electrode CE.

[0119] Fig.15 , Fig.16 and Fig.17 It is a graphic manufacturing Fig.13 A cross-sectional view of a method of displaying a device 20 is provided.

[0120] refer to Fig.15 , Fig.16 and Fig.17 The method of manufacturing the display device 20 described may be a method of manufacturing a display device 20 as described in reference Fig.13 and Fig.14 Accordingly, redundant descriptions will be omitted or simplified.

[0121] refer to Fig.15 A buffer layer BFR, a first active pattern AP1, a first gate insulating layer GI1, a first gate layer, a second gate insulating layer GI2, a second gate layer, a first interlayer insulating layer ILD1, a second active pattern AP2, a third gate insulating layer GI3, a third gate layer, a second interlayer insulating layer ILD2, a first conductive layer, a first through hole insulating layer VIA1 and a second conductive layer may be sequentially formed on the substrate SUB.

[0122] A preliminary second through-hole insulation layer P_VIA2 may be formed on the first through-hole insulation layer VIA1 and the second conductive layer. The preliminary second through-hole insulation layer P_VIA2 may cover the second conductive layer. The preliminary second through-hole insulation layer P_VIA2 may be formed along the contour of the first through-hole insulation layer VIA1. That is, the preliminary upper surface P_SF of the preliminary second through-hole insulation layer P_VIA2 may not be substantially flat. The preliminary upper surface P_SF of the preliminary second through-hole insulation layer P_VIA2 may have a step difference, and the level of the preliminary upper surface P_SF of the preliminary second through-hole insulation layer P_VIA2 may not be substantially constant.

[0123] refer to Fig.15 and Fig.16 , the prepared upper surface P_SF of the prepared second through hole insulation layer P_VIA2 may be planarized, for example, by polishing, to form the second through hole insulation layer VIA2.

[0124] Since the prepared upper surface P_SF of the prepared second through hole insulation layer P_VIA2 may be polished, the planarized upper surface SF of the second through hole insulation layer VIA2 may be substantially flat. That is, the planarized upper surface SF of the second through hole insulation layer VIA2 may not have a step difference, and the level of the planarized upper surface SF of the second through hole insulation layer VIA2 may be substantially constant.

[0125] For example, the preliminary upper surface P_SF of the preliminary second via insulating layer P_VIA2 may be polished by a chemical mechanical polishing process. In addition, the polishing process may be performed using zirconium oxide slurry, but the present disclosure is not limited thereto.

[0126] In an embodiment, the thickness of the second through-hole insulation layer VIA2 may not be constant at a position along the first through-hole insulation layer VIA1. That is, since the lower surface of the second through-hole insulation layer VIA2 may be formed along the contour of the first through-hole insulation layer VIA1, and the planarized upper surface SF of the second through-hole insulation layer VIA2 may be formed to be substantially flat through a polishing process, the thickness of the second through-hole insulation layer VIA2 may not be uniform.

[0127] refer to Fig.16 and Fig.17 , the pixel electrode PE may be formed on the second through hole insulating layer VIA2. The pixel electrode PE may be disposed along the contour of the planarized upper surface SF of the second through hole insulating layer VIA2. That is, due to the planarized upper surface SF of the second through hole insulating layer VIA2 along which the material layer for forming the pixel electrode PE is provided, the upper surface of the pixel electrode PE may be substantially flat.

[0128] Return to reference Fig.13 , a pixel defining layer PDL, a light emitting layer EL, a common electrode CE and an encapsulation layer TFE may be sequentially formed on the pixel electrode PE.

[0129] In an embodiment, the light emitting layer EL may be formed by an inkjet process. In this case, since the planarized upper surface SF of the second via insulating layer VIA2 and the upper surface of the pixel electrode PE may be substantially flat, the thickness of the light emitting layer EL may be substantially constant.

[0130] The display device 20 according to an embodiment of the present disclosure may include a second through-hole insulating layer VIA2 whose planarized upper surface SF is polished to be substantially flat. Since the thickness of the light-emitting layer EL disposed on the second through-hole insulating layer VIA2 may be substantially uniform without a step difference, the light-emitting efficiency and brightness uniformity of the light-emitting element LE may be improved. Accordingly, the display quality of the display device 20 may be improved.

[0131] The present disclosure can be applied to various display devices. For example, the present disclosure is applicable to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0132] The foregoing is an illustration of the embodiments and should not be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications of the disclosed embodiments and other embodiments are intended to be included within the scope of the claims.

Claims

1. A display device, comprising: substrate; a through-hole insulating layer on the substrate; A pixel electrode of the light-emitting element is on the through-hole insulating layer, and the pixel electrode includes, starting from the through-hole insulating layer, in order: a first pixel electrode layer; a second pixel electrode layer having a flat upper surface; and A third pixel electrode layer.

2. The display device according to claim 1, wherein: In the pixel electrode, The first pixel electrode layer has an uneven upper surface in a direction along the first pixel electrode layer, The thickness of the second pixel electrode layer is not constant in the direction along the first pixel electrode layer, and The flat upper surface of the second pixel electrode layer is a polished surface.

3. The display device according to claim 1, wherein: The upper surface of the through hole insulating layer is a flat polished surface, At a position overlapping with the pixel electrode, the through hole insulating layer comprises: a first through hole insulating layer defining an uneven upper surface; and The second through-hole insulating layer is between the substrate and the first pixel electrode layer, is closer to the pixel electrode than the first through-hole insulating layer, and has a flat upper surface, and A thickness of the second via hole insulating layer is not constant in a direction along the pixel electrode.

4. The display device according to any one of claims 1 to 3, further comprising: The quantum dot light-emitting layer of the light-emitting element is on the third pixel electrode layer; as well as A pixel circuit layer connected to the light emitting element and comprising: a first active pattern on the substrate; and A second active pattern is spaced apart from the first active pattern on the substrate and includes a material different from that of the first active pattern.

5. A method for providing a display device, the method comprising: providing a through-hole insulating layer on the substrate; as well as Providing a pixel electrode of a light emitting element on the through hole insulating layer, wherein the providing of the pixel electrode comprises: providing a first pixel electrode layer on the through hole insulating layer; providing a second pixel electrode layer having a flat upper surface on the first pixel electrode layer; and A third pixel electrode layer is provided on the second pixel electrode layer.

6. The method according to claim 5, wherein: The providing of the second pixel electrode layer comprises: providing a preliminary second pixel electrode layer having an uneven upper surface on the first pixel electrode layer; and The uneven upper surface of the preliminary second pixel electrode layer is polished to provide a flat upper surface of the second pixel electrode layer.

7. The method according to claim 6, wherein: In the uneven upper surface: The maximum level of the uneven upper surface is farthest from the substrate; and The minimum horizontal height of the uneven upper surface is closest to the substrate and is spaced apart from the maximum horizontal height by a difference along the thickness direction of the pixel electrode; and In the providing of the second pixel electrode layer, the uneven upper surface of the preliminary second pixel electrode layer is polished to remove a thickness portion of the preliminary second pixel electrode layer corresponding to the difference.

8. The method according to claim 5, wherein: By the provision of the second pixel electrode layer on the first pixel electrode layer and having the flat upper surface, the thickness of the second pixel electrode layer is not constant in a direction along the first pixel electrode layer.

9. The method according to claim 5, wherein: The providing of the through hole insulating layer comprises: providing a preliminary through-hole insulating layer having an uneven upper surface on the substrate; and The uneven upper surface of the preliminary via hole insulating layer is polished to provide the via hole insulating layer having a flat upper surface.

10. The method according to claim 9, wherein: The providing of the through hole insulating layer further comprises: providing a first through hole insulating layer defining an uneven upper surface on the substrate; providing a second through hole insulating layer having an uneven upper surface corresponding to the uneven upper surface of the first through hole insulating layer; and The uneven upper surface of the second through hole insulating layer is polished to provide the second through hole insulating layer having a non-constant thickness and the through hole insulating layer having the flat upper surface.

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