Display panel and display device

Abstract

A display panel includes a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines. At least one multiplexing circuit is connected to the plurality of multiplexing control lines, at least two of the plurality of data lines, and at least one of the plurality of multiplexing data lines. The at least one multiplexing circuit comprises a plurality of multiplexing control transistors, the at least one multiplexing control transistor comprises a first grid electrode, a second grid electrode and an active layer, the first grid electrode is located on the side, away from the substrate, of the active layer, and the second grid electrode is located on the side, close to the substrate, of the active layer; the second grid electrode is configured to receive the voltage stabilizing signal or is connected with the first grid electrode.

Description

Technical Field

[0001] This document relates to, but is not limited to, the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present application provide a display panel and a display device.

[0005] On the one hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines. The plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits, the plurality of multiplexing control lines, and the plurality of multiplexing data lines are located on one side of the plurality of sub-pixels. At least one multiplexing circuit among the plurality of multiplexing circuits is connected to at least two data lines among the plurality of data lines, at least one multiplexing control line among the plurality of multiplexing control lines, and at least one multiplexing data line among the plurality of multiplexing data lines; the at least one multiplexing circuit includes: a plurality of multiplexing control transistors, and at least one multiplexing control transistor among the plurality of multiplexing control transistors includes: a first gate, a second gate, and an active layer. The first gate is located on a side of the active layer away from the substrate, and the second gate is located on a side of the active layer close to the substrate; the second gate is configured to receive a regulated voltage signal or be connected to the first gate.

[0006] In some exemplary embodiments, the at least one multiplexing circuit is configured to, under the control of the plurality of multiplexing control lines, time-division multiplex the signal transmitted by the at least one multiplexing data line and transmit it to the at least two data lines.

[0007] In some exemplary embodiments, the second gates of the plurality of multiplexing control transistors of the at least one multiplexing circuit are of an integrated structure and are configured to receive a regulated voltage signal; the orthographic projection of the integrated structure on the substrate includes the orthographic projection of the active layers of the plurality of multiplexing control transistors on the substrate.

[0008] In some exemplary embodiments, the display panel further includes: a first shielding structure, a positive projection of the first shielding structure on the substrate at least partially overlaps with a positive projection of the plurality of sub-pixels on the substrate, and the first shielding structure is connected to second gates of the plurality of multiplexing control transistors.

[0009] In some exemplary embodiments, at least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit includes a driving transistor, and a positive projection of the first shielding structure on the substrate includes a channel region of the active layer of the driving transistor of the pixel circuit in the positive projection on the substrate.

[0010] In some exemplary embodiments, the pixel circuit is connected to a first power supply line, the light-emitting element is connected to a second power supply line, a first power signal provided by the first power supply line is greater than a second power signal provided by the second power supply line; the voltage stabilizing signal includes: the first power signal.

[0011] In some exemplary embodiments, the at least one multiplexing circuit includes: multiple groups of multiplexing units, each group of multiplexing units includes a plurality of multiplexing control transistors; first gates and second gates of the plurality of multiplexing control transistors in one group of multiplexing units are connected to the same multiplexing control line, and the second gates of the plurality of multiplexing control transistors in one group of multiplexing units are an integral structure.

[0012] In some exemplary embodiments, the display panel further includes at least one of the following: a first shielding structure, a second shielding structure. The first shielding structure includes: a plurality of shielding bars; the at least one multiplexing circuit includes: multiple groups of multiplexing units, and at least one group of multiplexing units in the multiple groups of multiplexing units includes at least one multiplexing control transistor; at least one of the plurality of shielding bars is located between positive projections of active layers of multiplexing control transistors in adjacent two groups of multiplexing units in the positive projection on the substrate. The second shielding structure is located on a side of the plurality of multiplexing circuits away from the substrate, and a positive projection of the second shielding structure on the substrate at least partially overlaps with a positive projection of the plurality of multiplexing circuits on the substrate.

[0013] In some exemplary embodiments, the second shielding structure is located on a side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollow portions.

[0014] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate, and the first shielding structure is located in the second source-drain metal layer.

[0015] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode sequentially arranged along a direction away from the substrate, and the second shielding structure is disposed on the same layer as the first electrode of the light-emitting element.

[0016] In some exemplary embodiments, the substrate includes a display area and a first border area located on one side of the display area, and the plurality of sub-pixels are located in the display area; the first border area includes: a first sub-area, a bending area, and a second sub-area sequentially arranged along a direction away from the display area, and the plurality of multiplexing circuits are located in the first sub-area or the second sub-area.

[0017] On the other hand, this embodiment provides a display device including the display panel as described above.

[0018] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, and a plurality of multiplexing circuits. The substrate includes a display area and a first border area located on one side of the display area; the plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits are located in the first border area and are connected to the plurality of data lines. The display panel further includes at least one of the following: a first shielding structure, a second shielding structure. The first shielding structure is located in the first border area and includes a plurality of shielding bars, at least one multiplexing circuit includes a plurality of sets of multiplexing units, at least one set of multiplexing units includes at least one multiplexing control transistor, and the orthographic projection of the shielding bar on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of adjacent two sets of multiplexing units on the substrate. The second shielding structure is located in the first border area and on a side of the plurality of multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of multiplexing circuits on the substrate.

[0019] In some exemplary embodiments, the second shielding structure is located on a side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollow portions.

[0020] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate, and the first shielding structure is located in the second source-drain metal layer.

[0021] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode sequentially arranged along a direction away from the substrate, and the second shielding structure is disposed on the same layer as the first electrode of the light-emitting element.

[0022] In some exemplary embodiments, the first border region includes: a first sub-region, a bending region, and a second sub-region sequentially arranged along a direction away from the display region, and the plurality of multiplexing circuits are located in the second sub-region.

[0023] Other features and advantages of the present application will be described in the subsequent description, and, in part, will become apparent from the description, or will be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the description and the drawings. Description of the Drawings

[0024] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the description, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0025] Figure 1A Schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0026] Figure 1B Another schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0027] Figure 2 Equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 3 Partial cross-sectional schematic diagram of a display region according to at least one embodiment of the present disclosure;

[0029] Figure 4 An equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0030] Figure 5 Partial plan schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0031] Figure 6A For Figure 5 Schematic diagram of the bottom shielding metal layer in

[0032] Figure 6B For Figure 5 Schematic diagram of the semiconductor layer, the first conductive layer, and the second conductive layer in

[0033] Figure 6C For Figure 5Schematic diagram of the bottom shielding metal layer, semiconductor layer, first conductive layer, and second conductive layer therein;

[0034] Figure 7 Another equivalent circuit diagram of the multiplexing circuit according to at least one embodiment of the present disclosure;

[0035] Figure 8 Another partial plan view of the display panel according to at least one embodiment of the present disclosure;

[0036] Figure 9A is Figure 8 Schematic diagram of the bottom shielding metal layer therein;

[0037] Figure 9B is Figure 8 Schematic diagram of the bottom shielding metal layer and semiconductor layer therein;

[0038] Figure 9C is Figure 8 Schematic diagram of the semiconductor layer and first conductive layer therein;

[0039] Figure 10 Another equivalent circuit diagram of the multiplexing circuit according to at least one embodiment of the present disclosure;

[0040] Figure 11 Another partial plan view of the display panel according to at least one embodiment of the present disclosure;

[0041] Figure 12A is Figure 11 Schematic diagram of the bottom shielding metal layer therein;

[0042] Figure 12B is Figure 11 Schematic diagram of the semiconductor layer, first conductive layer, second conductive layer, and third conductive layer therein;

[0043] Figure 13 Another partial plan view of the display panel according to at least one embodiment of the present disclosure;

[0044] Figure 14 Another partial plan view of the display panel according to at least one embodiment of the present disclosure;

[0045] Figure 15 is Figure 14 Schematic diagram of the second shielding structure therein;

[0046] Figure 16 Another partial plan view of the display panel according to at least one embodiment of the present disclosure;

[0047] Figure 17 Another schematic diagram of the first border region of the display panel according to at least one embodiment of the present disclosure;

[0048] Figure 18 Schematic diagram of the bending of the display panel according to at least one embodiment of the present disclosure;

[0049] Figure 19 Schematic diagram of the display device according to at least one embodiment of the present disclosure. Detailed implementation manners

[0050] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0051] In the accompanying drawings, sometimes, for the sake of clarity, the sizes, thicknesses of layers, or regions of one or more constituent elements are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of one or more components in the drawings do not reflect the true proportions. In addition, the accompanying drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings.

[0052] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of constituent elements, rather than to limit in terms of quantity. "Multiple" in the present disclosure means two or more quantities.

[0053] In this specification, for convenience, words and phrases indicating orientation or positional relationships such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationships of the constituent elements are appropriately changed according to the directions of the described constituent elements. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0054] In this specification, unless otherwise clearly defined or limited, the terms "installed", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" can include "electrical connection". "Electrical connection" includes the case where constituent elements are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0055] In this specification, a transistor refers to an element having at least three terminals including a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region where current mainly flows.

[0056] In this specification, the first pole can be the drain and the second pole can be the source, or the first pole can be the source and the second pole can be the drain. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" sometimes switch with each other. Therefore, in this specification, the "source" and "drain" can be switched with each other. In addition, the gate can also be referred to as the control pole.

[0057] In this specification, "parallel" means a state where the angle formed by two straight lines is 10° or less and -10° or more, and thus also includes a state where the angle is 5° or less and -5° or more. In addition, "perpendicular" means a state where the angle formed by two straight lines is 100° or less and 80° or more, and thus also includes an angle state of 95° or less and 85° or more.

[0058] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not in a strict sense and can be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons, or approximate hexagons, etc. There can be some small deformations caused by tolerances, such as chamfers, arc edges, and deformations.

[0059] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0060] "About" and "substantially" in this disclosure mean not strictly defining the boundary and allowing for cases within the process and measurement error range. In this disclosure, "the same" may include cases where the numerical values differ by within 10%.

[0061] In this disclosure, A extending along the B direction means that A may include a main body part and a secondary part connected to the main body part. The main body part is in the shape of a line, a line segment, or a strip, the main body part extends along the B direction, and the length of the main body part extending along the B direction is greater than the length of the secondary part extending along other directions. When it is said that "A extends along the B direction" in this disclosure, it always means that "the main body part of A extends along the B direction".

[0062] When it is said that "A and B are disposed on the same layer" in this disclosure, it means that A and B are formed simultaneously through the same patterning process, or the distances from the surfaces of A and B close to the substrate side to the substrate are substantially the same, or the surfaces of A and B close to the substrate side are in direct contact with the same film layer. "The orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. When it is said that "the shape of A" in this disclosure, it refers to the shape of the orthographic projection of A on the substrate.

[0063] As display technology develops towards high integration and low cost, the trend of OLED display products expanding from small-sized mobile phones, watches, etc. to the medium-sized field has become increasingly obvious. The demand for medium-sized products such as tablets and in-vehicle products has grown rapidly, and the demand for low cost has also received increasing market attention. A demultiplexer can effectively reduce the number of data channels, thereby reducing the number of integrated circuits (ICs), or can support integrated circuits with low cost and low channel numbers. However, due to process manufacturing deviations or high and low temperature scenarios that occur during actual use, the threshold voltage of transistors will drift, which easily affects the output stability of the demultiplexer circuit, thereby affecting the display quality of the display panel. For example, the demultiplexer circuit uses low-temperature polysilicon thin-film transistors, and the threshold voltage of low-temperature polysilicon thin-film transistors is unstable and has poor uniformity. After a long-term reliability test, the threshold voltage is likely to shift beyond the working range of the demultiplexer circuit, resulting in abnormal display.

[0064] This embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines. The plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits, the plurality of multiplexing control lines, and the plurality of multiplexing data lines are located on one side of the plurality of sub-pixels. At least one multiplexing circuit among the plurality of multiplexing circuits is connected to at least two data lines among the plurality of data lines, at least one multiplexing control line, and at least one multiplexing data line among the plurality of multiplexing data lines. At least one multiplexing circuit includes a plurality of multiplexing control transistors, and at least one multiplexing control transistor among the plurality of multiplexing control transistors includes: a first gate, a second gate, and an active layer. The first gate is located on a side of the active layer away from the substrate, and the second gate is located on a side of the active layer close to the substrate. The second gate is configured to receive a regulated voltage signal or be connected to the first gate.

[0065] In the display panel provided in this embodiment, the multiplexing control transistor of the multiplexing circuit includes a first gate and a second gate, and the second gate can receive a regulated voltage signal or be connected to the first gate, which can effectively improve the characteristic stability of the multiplexing control transistor, ensure the output stability of the multiplexing circuit, and thus ensure the display quality of the display panel. Moreover, by improving the characteristic stability of the multiplexing circuit itself, it is beneficial to improve the anti-interference ability of the multiplexing circuit to external signals.

[0066] In some exemplary embodiments, at least one multiplexing circuit can be configured to, under the control of a plurality of multiplexing control lines, time-division multiplex the signal transmitted by at least one multiplexing data line and transmit it to at least two data lines. For example, the multiplexing circuit can be connected to two multiplexing control lines, and under the control of the two multiplexing control lines, time-division multiplex the signal transmitted by one multiplexing data line and transmit it to two data lines.

[0067] In some exemplary embodiments, the second gates of the plurality of multiplexing control transistors of at least one multiplexing circuit are of an integral structure and are configured to receive a regulated voltage signal; the orthographic projection of the integral structure on the substrate may include the orthographic projections of the active layers of the plurality of multiplexing control transistors on the substrate. In this example, the characteristic stability of the multiplexing control transistor is improved by setting the second gates of the plurality of multiplexing control transistors to receive a regulated voltage signal.

[0068] In some exemplary embodiments, at least one multiplexing circuit may include: multiple groups of multiplexing units, each group of multiplexing units including a plurality of multiplexing control transistors; the first gates and the second gates of the plurality of multiplexing control transistors in one group of multiplexing units are connected to the same multiplexing control line, and the second gates of the plurality of multiplexing control transistors in one group of multiplexing units are of an integral structure. In this example, the characteristic stability of the multiplexing control transistor is improved by setting the second gates of the plurality of multiplexing control transistors to be connected to the first gate.

[0069] In some exemplary embodiments, the display panel may further include at least one of the following: a first shielding structure, a second shielding structure. The first shielding structure may include: a plurality of shielding bars; the at least one multiplexing circuit includes: multiple groups of multiplexing units, and at least one group of multiplexing units includes at least one multiplexing control transistor; the orthographic projection of the shielding bar on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of adjacent two groups of multiplexing units on the substrate. The second shielding structure may be located on a side of the multiple multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the multiple multiplexing circuits on the substrate. In this example, by providing the first shielding structure, signal shielding can be performed between adjacent multiplexing units to prevent mutual crosstalk; by providing the second shielding structure, interference of other signals (such as touch signals, antenna signals, etc.) on the multiplexing circuit can be prevented.

[0070] The following uses some examples to illustrate the solution of this embodiment.

[0071] Figure 1A Schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1B Another schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1A Shown is a schematic diagram of a small-sized display panel; Figure 1B Shown is a schematic diagram of a medium-sized display panel.

[0072] In some examples, as Figure 1A and Figure 1B shown, the display panel may be a closed polygon including linear sides. The display panel may include: a display area AA and a border area BB located around the display area AA. The border area BB may include: a first border area B1 and a second border area B2 located on both sides of the display area AA along a first direction D1, and a third border area B3 and a fourth border area B4 located on both sides of the display area AA along a second direction D2. The first border area B1 may be connected to the third border area B3 and the fourth border area B4, the second border area B2 may be connected to the third border area B3 and the fourth border area B4, and after the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 are connected, they may surround the display area AA. For example, the first border area B1 may also be referred to as the lower border area of the display panel, the second border area B2 may also be referred to as the upper border area of the display panel, the third border area B3 may also be referred to as the left border area of the display panel, and the fourth border area B4 may also be referred to as the right border area of the display panel. However, this embodiment is not limited thereto.

[0073] In some examples, the display area AA may include: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signal may include a scan signal, or may include a scan signal and a light emission control signal, or may include a scan signal, a reset control signal, and a light emission control signal.

[0074] In some examples, the second direction D2 may be the extension direction of the gate line GL in the display area AA (e.g., the row direction); the first direction D1 may be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 may intersect with each other, for example, may be perpendicular to each other.

[0075] In some examples, one pixel unit of the display area AA may include a plurality of sub-pixels. For example, one pixel unit may include four sub-pixels, and the four sub-pixels may be a first sub-pixel that emits a first color light (e.g., red light), a second sub-pixel that emits a second color light (e.g., blue light), and two third sub-pixels that emit a third color light (e.g., green light). In other examples, one pixel unit may include three sub-pixels, and the three sub-pixels may be a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third sub-pixel that emits a third color light.

[0076] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Among them, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number in front of T represents the number of thin-film transistors in the circuit, and the number in front of C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0077] In some examples, the shape of the light-emitting element of the sub-pixel can be rectangular, rhombic, pentagonal, or hexagonal. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged in a horizontal side-by-side, vertical side-by-side, or square manner. However, this embodiment is not limited thereto. In other examples, when a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pattern.

[0078] In some examples, the light-emitting element can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element can include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0079] In some examples, as Figure 1A shown, the first border region B1 can include: a first sub-region B11, a bending region B12, and a second sub-region B13 that are sequentially arranged on one side away from the display region AA in the first direction D1. The first sub-region B11 can be connected to the display region AA, the third border region B3, and the fourth border region B4. The bending region B12 can be connected between the first sub-region B11 and the second sub-region B13. The bending region B12 can be configured to bend the second sub-region B13 to the back of the display region AA.

[0080] In some examples, as Figure 1A shown, the first sub-region B11 can include a first routing area FA1, and a plurality of multiplexing circuits 30 can be located on the side of the first routing area FA1 close to the display region AA. The first routing area FA1 can include a plurality of multiplexed data lines connected to the plurality of multiplexing circuits 30. The plurality of multiplexing circuits 30 can be located at the boundary position of the first sub-region B11 close to the display region AA. In other examples, a part of the plurality of multiplexing circuits can be located in the display region AA, and another part can be located in the first sub-region B11. In other examples, the plurality of multiplexing circuits can be arranged in the display region AA to reduce the size of the first sub-region B11 in the first direction D1 and achieve a narrow border design.

[0081] In some examples, as Figure 1A shown, the second sub-region B13 may include: a second routing area FA2, a first signal access area B131, and a second signal access area B132, which are sequentially arranged in a direction away from the bending area B12 along the first direction D1. The second routing area FA2 may include a plurality of data lead-out routing lines for transmitting data signals. The plurality of data lead-out routing lines in the second routing area FA2 may extend to the first signal access area B131. The first signal access area B131 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect an integrated circuit (IC). Some of the plurality of first contact pads may be configured to provide data signals through the plurality of data lead-out routing lines. The second signal access area B132 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to be bonded and connected to an external flexible printed circuit (FPC). At least one first contact pad in the first signal access area B131 and at least one second contact pad in the second signal access area B132 may be connected through an inner lead bonding (ILB).

[0082] In some examples, as Figure 1B shown, the first border area B1 may include: two first signal access areas B131a and B131b, and two second signal access areas B132a and B132b. The two second signal access areas B132a and B132b may be located on a side of the two first signal access areas B131a and B131b away from the display area AA. A plurality of multiplexing circuits 30 may be located in the first sub-region B11 of the first border area B1, and two routing areas FAa and FAb may be located in the second sub-region B13. The two routing areas FAa and FAb may include a plurality of multiplexed data lines connected to the plurality of multiplexing circuits 30. The two first signal access areas B131a and B131b may be arranged along the second direction D2, and the two second signal access areas B132a and B132b may be arranged along the second direction D2.

[0083] In some examples, as Figure 1B shown, the third border area B3 may be provided with a first gate driving circuit 191, and the fourth border area B4 may be provided with a second gate driving circuit 192. The first gate driving circuit 191 and the second gate driving circuit 192 may be connected to a plurality of gate lines GL of the display area AA, and are configured to provide pixel control signals to pixel circuits of a plurality of sub-pixels PX in the display area AA.

[0084] In some examples, as Figure 1BAs shown, the border region BB may be provided with a first border power supply line VLD and a second border power supply line VLS. The first border power supply line VLD may be located on a side of the second border power supply line VLS closer to the display region AA. The second border power supply line VLS may be located on a side of the first gate driving circuit 191 and the second gate driving circuit 192 away from the display region AA, and the first border power supply line VLD may be located on a side of the first gate driving circuit 191 and the second gate driving circuit 192 closer to the display region AA. One end of the first border power supply line VLD may be connected to a second contact pad within the second signal access region B132a, and the other end may be connected to a second contact pad within the second signal access region B132b. One end of the second border power supply line VLS may be connected to a second contact pad within the second signal access region B132a, and the other end may be connected to a second contact pad within the second signal access region B132b. The first border power supply line VLD may be configured to provide a first power signal to the pixel circuits of a plurality of sub-pixels PX, and the second border power supply line VLS may be configured to provide a second power signal to the light-emitting elements of the plurality of sub-pixels PX, and the first power signal may be greater than the second power signal.

[0085] In some examples, as Figure 1B shown, the first sub-region B11 of the first border region B1 may further include: a first power connection line 81, a second power connection line 82, and a plurality of third power connection lines 83. The first power connection line 81 and the second power connection line 82 may extend along the second direction D2. The first power connection line 81 may be located on a side of the plurality of multiplexing circuits 30 closer to the display region AA, and the second power connection line 82 may be located on a side of the plurality of multiplexing circuits 30 away from the display region AA. The plurality of third power connection lines 83 may extend along the first direction D1 and connect the first power connection line 81 and the second power connection line 82. The orthographic projection of the third power connection line 83 on the substrate and the orthographic projection of the plurality of multiplexing circuits 30 on the substrate may overlap.

[0086] Figure 2 is an equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of the present exemplary embodiment is described by taking the 7T1C structure as an example. In some examples, as Figure 2As shown, the pixel circuit of this example may include a first transistor (which may also be referred to as a first reset transistor) T1, a second transistor (which may also be referred to as a threshold compensation transistor) T2, a third transistor (which may also be referred to as a driving transistor) T3, a fourth transistor (which may also be referred to as a data writing transistor) T4, a fifth transistor (which may also be referred to as a first light-emitting control transistor) T5, a sixth transistor (which may also be referred to as a second light-emitting control transistor) T6, a seventh transistor (which may also be referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting functional layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element EL may be an anode, and the second electrode of the light-emitting element EL may be a cathode.

[0087] In some examples, as Figure 2 shown, the display panel may include: a scan line GAL, a data line DL, a first power supply line PL1, a second power supply line PL2, a light-emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. Among them, the first power supply line PL1 may be configured to provide a constant first power signal to the pixel circuit, the second power supply line PL2 may be configured to provide a constant second power signal to the cathode of the light-emitting element EL, and the first power signal is greater than the second power signal. The first power supply line PL1 may be connected to the first frame power supply line VLD, and the second power supply line PL2 may be connected to the second frame power supply line VLS. The scan line GAL may be configured to provide a scan signal to the pixel circuit, the data line DL may be configured to provide a data signal to the pixel circuit, the light-emitting control line EML may be configured to provide a light-emitting control signal to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal to the pixel circuit. In some examples, the second reset control line RST2 connected to the pixel circuit of the j-th row and the first reset control line RST1 connected to the pixel circuit of the (j + 1)-th row may be an integral structure. Where j is an integer greater than 0. In this way, the signal lines of the display panel can be reduced, and a narrow border design of the display panel can be achieved.

[0088] In some examples, the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be, for example, between the first power signal and the second power signal, but are not limited thereto. In some other examples, the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.

[0089] In some examples, as Figure 2 shown, the third transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as a scan signal, a data signal, a first power supply signal, and a second power supply signal. The gate of the fourth transistor T4 is electrically connected to the scan line GAL, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the first pole of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GAL, the second pole of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first pole of the second transistor T2 is electrically connected to the second pole of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second pole of the fifth transistor T5 is electrically connected to the first pole of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the second pole of the third transistor T3, and the second pole of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0090] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2. The second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3. The third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0091] Figure 3 It is a schematic cross-sectional view of a part of the display area of at least one embodiment of the present disclosure. Figure 3 The structure of a sub-pixel in the display area is used as an example for illustration. Figure 3Taking one transistor 16 and one capacitor 17 included in the pixel circuit of each sub-pixel as an example for illustration. Among them, the transistor 16 can be a low-temperature polysilicon thin-film transistor. For example, the transistor 16 can be Figure 2 the sixth transistor T6 or the seventh transistor T7 of the pixel circuit shown, and the capacitor 17 can be Figure 2 the storage capacitor Cst of the pixel circuit shown.

[0092] In some examples, as Figure 3 shown, in the direction perpendicular to the display panel, the display panel can include: a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and a packaging structure layer 140 sequentially disposed on the substrate 100. Among them, the circuit structure layer 120 in the display area can include: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel can include multiple transistors and at least one capacitor. The light-emitting structure layer 130 in the display area can include: light-emitting elements of multiple sub-pixels. In some other examples, a touch control structure layer can be disposed on the side of the packaging structure layer 140 away from the substrate 100 to integrate the touch control function.

[0093] In some examples, the circuit structure layer 120 of the display panel may include: a bottom shielding metal (BSM) layer 200 disposed on the substrate 100, a semiconductor layer, a first conductive layer (which may also be referred to as a first gate metal layer), a second conductive layer (which may also be referred to as a second gate metal layer), a third conductive layer (which may also be referred to as a first source-drain metal layer), and a fourth conductive layer (which may also be referred to as a second source-drain metal layer). A first insulating layer (which may also be referred to as a buffer layer) 101 may be disposed between the bottom shielding metal layer 200 and the semiconductor layer; a second insulating layer (which may also be referred to as a first gate insulating layer) 102 may be disposed between the semiconductor layer and the first conductive layer; a third insulating layer (which may also be referred to as a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (which may also be referred to as an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (which may also be referred to as a passivation layer) 105 and a sixth insulating layer (which may also be referred to as a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 may be located on a side of the fifth insulating layer 105 away from the substrate 100; a seventh insulating layer (which may also be referred to as a second planarization layer) 107 may be disposed on a side of the fourth conductive layer away from the substrate 100. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 may be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 may be organic insulating layers. However, this embodiment is not limited thereto. In other examples, the fifth insulating layer may be omitted between the third conductive layer and the fourth conductive layer, and only the sixth insulating layer may be disposed between the third conductive layer and the fourth conductive layer.

[0094] In some examples, the substrate 100 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., for improving the water and oxygen resistance of the substrate.

[0095] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. Among them, the material of the semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and has semiconductor characteristics. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and thus have conductivity. The impurities may vary according to the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source electrode or the drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors. This embodiment does not limit this.

[0096] In some examples, as Figure 3 shown, the semiconductor layer of the display region may include: the active layer 160 of the transistor 16 of the pixel circuit. The active layer 160 of the transistor 16 may include: a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first conductive layer may include: the gate 163 of the transistor 16 and the first electrode plate 171 of the capacitor 17. The orthographic projection of the gate 163 of the transistor 16 on the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 on the substrate 100. The second conductive layer may include: the second electrode 172 of the capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of the capacitor 17 on the substrate 100 may at least partially overlap. For example, the two may coincide.

[0097] In some examples, as Figure 3 shown, the third conductive layer of the display region may include: the source electrode 161 and the drain electrode 162 of the transistor 16. The source electrode 161 of the transistor 16 may be electrically connected to the first region 1601 of the active layer 160, and the drain electrode 162 may be electrically connected to the second region 1602 of the first active layer 160. The fourth conductive layer may include: the anode transfer electrode 181. The anode transfer electrode 181 may be electrically connected to the drain electrode 162 of the transistor 16 of the pixel circuit through a via formed in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the anode transfer electrode 181.

[0098] In some examples, as Figure 3As shown, the light-emitting structure layer 130 may include: a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 131, a light-emitting functional layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the seventh insulating layer 107 and electrically connected to the anode transfer electrode 181 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107. The pixel definition layer 134 may be provided with a plurality of pixel openings, and at least a part of the surface of a corresponding first electrode 131 may be exposed through one pixel opening. At least a part of the light-emitting functional layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the light-emitting functional layer 132 and connected to the light-emitting functional layer 132. The light-emitting functional layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0099] In some examples, the light-emitting functional layer 132 of the light-emitting element may include at least one light-emitting layer (EML, Emitting Layer), and include at least one of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, light may be emitted according to the required gray level by using the light-emitting characteristics of the organic material.

[0100] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), and isolation may be achieved by means of the surface step difference of the formed film layer or surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the light-emitting functional layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or may be formed by an inkjet process.

[0101] In some examples, as Figure 3 shown, the encapsulation structure layer 140 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may adopt inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may adopt an organic material. For example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or may be a polymer resin, etc. to planarize the surface of the display panel, and can relieve the stress between the first encapsulation layer 141 and the third encapsulation layer 143, and may also include a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that invade the interior. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0102] Figure 4 This is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 The multiplexing circuit designed in a 1:2 ratio is taken as an example for illustration. The multiplexing circuit of this example can provide the data signals provided by three multiplexed data lines to six data lines. In some examples, as Figure 4As shown, a multiplexing circuit can be electrically connected to two multiplexing control lines (e.g., including a first multiplexing control line ML1 and a second multiplexing control line ML2), three multiplexing data lines (e.g., including a first multiplexing data line SL1, a second multiplexing data line SL2, and a third multiplexing data line SL3), and multiple data lines (e.g., including a first data line DL1 to a sixth data line DL6).

[0103] In some examples, the multiplexing circuit can include six multiplexing control transistors (i.e., a first multiplexing control transistor M1 to a sixth multiplexing control transistor M6). The first gates of the first reset control transistor M1, the second multiplexing control transistor M2, and the third multiplexing control transistor M3 can be connected to the first multiplexing control line ML1, and the first gates of the fourth multiplexing control transistor M4, the fifth multiplexing control transistor M5, and the sixth multiplexing control transistor M6 can be connected to the second multiplexing control line ML2.

[0104] In some examples, the second gates of the first multiplexing control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, the fourth multiplexing control transistor M4, the fifth multiplexing control transistor M5, and the sixth multiplexing control transistor M6 can be electrically connected to a voltage stabilizing line VL, configured to receive a voltage stabilizing signal. For example, the voltage stabilizing signal can include a first power signal. The second gates of the six multiplexing control transistors of the multiplexing circuit in this example receive the voltage stabilizing signal, which can improve the characteristic stability of the multiplexing control transistors. For example, the threshold voltage of the multiplexing control transistor can be reduced by 0.5V to 1.5V. For instance, the threshold voltage of the multiplexing control transistor can be reduced from 2.7V to about 1.2V.

[0105] In some examples, the first poles of the first multiplexing control transistor M1 and the fourth multiplexing control transistor M4 can be connected to the first multiplexing data line SL1, the first poles of the second multiplexing control transistor M2 and the fifth multiplexing control transistor M5 can be connected to the second multiplexing data line SL2, and the first poles of the third multiplexing control transistor M3 and the sixth multiplexing control transistor M6 can be connected to the third multiplexing data line SL3. The second pole of the first multiplexing control transistor M1 is connected to the first data line DL1, the second pole of the second multiplexing control transistor M2 is connected to the second data line DL2, the second pole of the third multiplexing control transistor M3 is connected to the third data line DL3, the second pole of the fourth multiplexing control transistor M4 is connected to the fourth data line DL4, the second pole of the fifth multiplexing control transistor M5 is connected to the fifth data line DL5, and the second pole of the sixth multiplexing control transistor M6 is connected to the sixth data line DL6.

[0106] In some examples, each data line may be connected to at least one column of pixel circuits within the display area AA. One column of pixel circuits may include a plurality of pixel circuits arranged along the first direction D1. For example, the first data line DL1 may be connected to the pixel circuits of a first sub-pixel that emits a first color light (e.g., red light R), the second data line DL2 may be connected to the pixel circuits of a third sub-pixel that emits a third color light (e.g., green light G), the third data line DL3 may be connected to the pixel circuits of a second sub-pixel that emits a second color light (e.g., blue light B), the fourth data line DL4 may be connected to the pixel circuits of a first sub-pixel that emits a first color light (e.g., red light R), the fifth data line DL5 may be connected to the pixel circuits of a third sub-pixel that emits a third color light (e.g., green light G), and the sixth data line DL6 may be connected to the pixel circuits of a second sub-pixel that emits a second color light (e.g., blue light B).

[0107] In some examples, under the control of the first multiplexing control line ML1, the multiplexing circuit may provide data signals to the first data line DL1, the second data line DL2, and the third data line DL3. Under the control of the second multiplexing control line ML2, the multiplexing circuit may provide data signals to the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6.

[0108] Figure 5 It is a partial plan schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 6A is Figure 5 a schematic diagram of the bottom shielding metal layer in; Figure 6B is Figure 5 a schematic diagram of the semiconductor layer, the first conductive layer, and the second conductive layer in; Figure 6C is Figure 5 a schematic diagram of the bottom shielding metal layer, the semiconductor layer, the first conductive layer, and the second conductive layer in. Figure 5 In, two multiplexing circuits 30 in the first border area are taken as examples for illustration. The film layer structure of the display panel in this example may be as Figure 3 shown.

[0109] In some examples, as Figures 5 to 6CAs shown, the bottom shielding metal layer may include: a first shielding structure 201 located in the display area AA, a first connection structure 211 located in the first sub-region B11 of the first border region, a second connection structure 212, and a plurality of first shielding blocks 220. The first shielding structure 201, the first connection structure 211, the second connection structure 212, and the plurality of first shielding blocks may be an integral structure. The first shielding structure 201 and the first connection structure 211 may be directly connected. The first connection structure 211 may extend along the second direction D2 and be connected to the plurality of second connection structures 212. The plurality of second connection structures 212 may extend along the first direction D1 and be arranged in sequence along the second direction D2. The plurality of first shielding blocks 220 may extend along the first direction D1 and be arranged in sequence along the second direction D2. A single first shielding block 220 may be connected to three second connection structures 212. The orthographic projection of a single first shielding block 220 on the substrate may be a rectangle.

[0110] In some examples, as Figures 5 to 6C shown, the semiconductor layer of the first sub-region B11 may include: active layers of a plurality of multiplexing control transistors (such as the active layers M10a, M10b, M10c, and M10d of the first multiplexing control transistor M1, the active layers M20a, M20b, M20c, and M20d of the second multiplexing control transistor M2, and the active layers M30a, M30b, M30c, and M30d of the third multiplexing control transistor M3). The active layers M10a, M10b, M10c, and M10d of the first multiplexing control transistor M1 may be arranged in alignment along the first direction D1, and the active layer M10a of the first multiplexing control transistor M1, the active layer M20a of the second multiplexing control transistor M2, and the M30a of the third multiplexing control transistor M3 may be arranged in alignment along the second direction D2. The orthographic projection of a single active layer of a single multiplexing control transistor on the substrate may be substantially a rectangle. The orthographic projection of a single first shielding block 220 on the substrate may include the orthographic projections of the active layers of three multiplexing control transistors on the substrate. A single first shielding block 220 may be multiplexed as the second gate of three multiplexing control transistors. For example, the second gates of the first multiplexing control transistor M1, the second gate of the second multiplexing control transistor M2, and the second gate of the third multiplexing control transistor M3 may be an integral structure, and this integral structure may be a first shielding block 220. In this example, the second gates of three multiplexing control transistors connected to the same multiplexing control line in the multiplexing circuit may be an integral structure.

[0111] In some examples, the first conductive layer of the first sub-region B11 may include: the first gates of a plurality of multiplexing control transistors (such as the first gate M13 of the first multiplexing control transistor M1, the first gate M23 of the second multiplexing control transistor M2, the first gate M33 of the third multiplexing control transistor M3, the first gate M43 of the fourth multiplexing control transistor M4, the first gate M53 of the fifth multiplexing control transistor M5, the first gate M63 of the sixth multiplexing control transistor M6), a plurality of first connection blocks (such as first connection blocks 411, 412, 413, 414, 415, and 416), a plurality of second connection blocks (such as second connection blocks 421, 422, 423, 424, 425, and 426), and a plurality of multiplexing data lines (such as the second multiplexing data line SL2). The second conductive layer of the first sub-region B11 may include a plurality of multiplexing data lines (such as the first multiplexing data line SL1 and the second multiplexing data line SL2).

[0112] In some examples, a plurality of the first connection blocks may be located on a side of the first gates of the plurality of multiplexing control transistors close to the display area AA, and a plurality of the second connection blocks and a plurality of the multiplexing data lines may be located on a side of the first gates of the plurality of multiplexing control transistors away from the display area AA.

[0113] In some examples, as Figure 5 shown, the third conductive layer of the first sub-region B11 may include: a first peripheral trace 41, a first multiplexing control line ML1, a second multiplexing control line ML2, a plurality of third connection blocks (such as third connection blocks 431, 432, and 433), and the first and second poles of a plurality of multiplexing control transistors (such as the first pole M11 and the second pole M12 of the first multiplexing control transistor M1, the first pole M21 and the second pole M22 of the second multiplexing control transistor M2, the first pole M31 and the second pole M32 of the third multiplexing control transistor M3, the first pole M41 and the second pole M42 of the fourth multiplexing control transistor M4, the first pole M51 and the second pole M52 of the fifth multiplexing control transistor M5, the first pole M61 and the second pole M62 of the sixth multiplexing control transistor M6). The first multiplexing control line ML1 and the second multiplexing control line ML2 may extend at least along the second direction D2 and be located on a side of the plurality of multiplexing control transistors away from the display area AA along the first direction D1.

[0114] In some examples, the orthographic projection of the first peripheral trace 41 on the substrate and the orthographic projection of the first connection structure 211 on the substrate may at least partially overlap. The first peripheral trace 41 may be connected to the first connection structure 211. For example, the first peripheral trace 41 is Figure 1BAs shown by the first power connection line 81, the first peripheral trace 41 can be configured to transmit a first power signal, such that the entire bottom shielding metal layer can transmit the first power signal, and the second gates of the plurality of multiplexing control transistors receive the first power signal. In some other examples, the first peripheral trace 41 can be configured to transmit other regulated signals.

[0115] In some examples, the first pole M11 of the first multiplexing control transistor M1 can be connected to the first region of the active layers M10a, M10b, M10c, and M10d of the first multiplexing control transistor M1, and can also be connected to the second connection block 421. The first pole M41 of the fourth multiplexing control transistor M4 can be connected to the first region of the active layer of the fourth multiplexing control transistor M4, and can also be connected to the second connection block 424. The second connection blocks 421 and 424 can be connected to the third connection block 431 located in the third conductive layer, and the third connection block 431 can be connected to a first multiplexed data line SL1 located in the second conductive layer.

[0116] In some examples, the first pole M21 of the second multiplexing control transistor M2 can be connected to the first region of the active layers M20a, M20b, M20c, and M20d of the second multiplexing control transistor M2, and can also be connected to the second connection block 422. The first pole M51 of the fifth multiplexing control transistor M5 can be connected to the first region of the active layer of the fifth multiplexing control transistor M5, and can also be connected to the second connection block 425. The second connection blocks 422 and 425 can be connected to the third connection block 432 located in the third conductive layer, and the third connection block 432 can be connected to a second multiplexed data line SL2 located in the first conductive layer.

[0117] In some examples, the first pole M31 of the third multiplexing control transistor M3 can be connected to the first region of the active layers M30a, M30b, M30c, and M30d of the third multiplexing control transistor M3, and can also be connected to the second connection block 423. The first pole M61 of the sixth multiplexing control transistor M6 can be connected to the first region of the active layer of the sixth multiplexing control transistor M6, and can also be connected to the second connection block 426. The second connection blocks 423 and 426 can be connected to the third connection block 433 located in the third conductive layer, and the third connection block 433 can be connected to a third multiplexed data line SL3 located in the second conductive layer. The multiple multiplexed data lines in this example can be alternately arranged in the first conductive layer and the second conductive layer.

[0118] In some examples, the second pole M12 of the first multiplexing control transistor M1 can be connected to the second region of the active layers M10a, M10b, M10c, and M10d of the first multiplexing control transistor M1, and can also be connected to the first connection block 411. The first connection block 411 or the second pole M12 of the first multiplexing control transistor M1 can be connected to a data line. The second pole M22 of the second multiplexing control transistor M2 can be connected to the second region of the active layers M20a, M20b, M20c, and M20d of the second multiplexing control transistor M2, and can also be connected to the first connection block 412. The first connection block 412 or the second pole M22 of the second multiplexing control transistor M2 can be connected to a data line. The second pole M32 of the third multiplexing control transistor M3 can be connected to the second region of the active layers M30a, M30b, M30c, and M30d of the third multiplexing control transistor M3, and can also be connected to the first connection block 413. The first connection block 413 or the second pole M32 of the third multiplexing control transistor M3 can be connected to a data line.

[0119] In some examples, the second pole M42 of the fourth multiplexing control transistor M4 can be connected to the second region of the active layer of the fourth multiplexing control transistor M4, and can also be connected to the first connection block 414. The second pole M52 of the fifth multiplexing control transistor M5 can be connected to the second region of the active layer of the fifth multiplexing control transistor M5, and can also be connected to the first connection block 415. The second pole M62 of the sixth multiplexing control transistor M6 can be connected to the second region of the active layer of the sixth multiplexing control transistor M6, and can also be connected to the first connection block 416.

[0120] In some examples, the first gate M13 of the first multiplexing control transistor M1, the first gate M23 of the second multiplexing control transistor M2, and the first gate M33 of the third multiplexing control transistor M3 can be connected to the first multiplexing control line ML1. The first gate M43 of the fourth multiplexing control transistor M4, the first gate M53 of the fifth multiplexing control transistor M5, and the first gate M63 of the sixth multiplexing control transistor M6 can be connected to the second multiplexing control line ML2.

[0121] By connecting the second gates of multiple multiplexing control transistors connected to the same multiplexing control line in the multiplexing circuit into an integrated structure, and this integrated structure can be configured to receive the first power signal, the display panel of this example can improve the characteristic stability of the multiplexing control transistors, thereby improving the reliability of the multiplexing circuit.

[0122] Figure 7 It is another equivalent circuit diagram of the multiplexing circuit of at least one embodiment of the present disclosure. Figure 7 The multiplexing circuit with a 1:2 design is taken as an example for illustration. Figure 7Schematically shows two multiplexing circuits. The multiplexing circuit of this example can provide the data signals provided by a multiplexed data line to two data lines in a time-division manner. As Figure 7 shown, a multiplexing circuit 30 can be connected to two multiplexed control lines (for example, including a first multiplexed control line ML1 and a second multiplexed control line ML2), a multiplexed data line SL, and multiple data lines (for example, a first data line DL1 and a second data line DL2).

[0123] In some examples, the multiplexing circuit 30 can include two multiplexed control transistors (for example, a seventh multiplexed control transistor M7 and an eighth multiplexed control transistor M8). The first gate of the seventh multiplexed control transistor M7 can be connected to the first multiplexed control line ML1, and the first gate of the eighth multiplexed control transistor M8 can be connected to the second multiplexed control line ML2. The second gates of the seventh multiplexed control transistor M7 and the eighth multiplexed control transistor M8 can be electrically connected to a voltage stabilization line VL, configured to receive a voltage stabilization signal, such as a first power signal.

[0124] In some examples, the first poles of the seventh multiplexed control transistor M7 and the eighth multiplexed control transistor M8 can be connected to the same multiplexed data line SL. The second pole of the seventh multiplexed control transistor M7 can be connected to the first data line DL1, and the second pole of the eighth multiplexed control transistor M8 can be connected to the second data line DL2. A column of sub-pixels connected to the first data line DL1 can include a first sub-pixel that emits red light R and a third sub-pixel that emits green light G, and a column of sub-pixels connected to the second data line DL2 can include a second sub-pixel that emits blue light.

[0125] In some examples, under the control of the first multiplexed control line ML1, the multiplexing circuit can provide a data signal to the first data line DL1, and under the control of the second multiplexed control line ML2, the multiplexing circuit can provide a data signal to the second data line DL2.

[0126] Figure 8 Another partial plan view of a display panel according to at least one embodiment of the present disclosure. Figure 9A is Figure 8 a schematic diagram of the bottom shielding metal layer in Figure 9B is Figure 8 a schematic diagram of the bottom shielding metal layer and the semiconductor layer in Figure 9C is Figure 8 a schematic diagram of the semiconductor layer and the first conductive layer in Figure 8 illustrates by taking four multiplexing circuits 30 in the first border region as an example. The film layer structure of the display panel of this example can be as Figure 3 shown. Figure 8It mainly shows the bottom shielding metal layer, semiconductor layer, first conductive layer and third conductive layer, and the remaining film layers are omitted from the illustration.

[0127] In some examples, such as Figures 8 to 9C As shown, the bottom shielding metal layer may include: a first shielding structure 201 located in the display area AA and a second shielding block 221 located in the first sub-region B11 of the first border region. The first shielding structure 201 and the second shielding block 221 are directly connected and may be an integral structure. The first shielding structure 201 may be generally a mesh structure in the display area AA.

[0128] In some examples, the semiconductor layer of the display panel may include: the active layers of transistors of multiple pixel circuits located in the display area AA (for example, including the active layer T20 of the second transistor T2, the active layer T30 of the third transistor T3, the active layer T40 of the fourth transistor T4, the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, and the active layer T70 of the seventh transistor T7), and the active layers of multiple multiplexing control transistors located in the first sub-region B11 (for example, including the active layers M70a and M70b of the seventh multiplexing control transistor M7, and the active layers M80a and M80b of the eighth multiplexing control transistor M8). The active layers of the seven transistors of a single pixel circuit may be an integral structure. The active layer M70a of the seventh multiplexing control transistor M7 and the active layer M80a of the eighth multiplexing control transistor M8 of the multiplexing circuit may be an integral structure, and the active layer M70b of the seventh multiplexing control transistor M7 and the active layer M80b of the eighth multiplexing control transistor M8 may be an integral structure.

[0129] In some examples, the orthographic projection of the second shielding block 221 on the substrate may cover the orthographic projection of the active layers of multiple multiplexing control transistors on the substrate. The second shielding block 221 may be multiplexed as an integral structure of the second gates of multiple multiplexing control transistors, and the orthographic projection of this integral structure on the substrate may include the orthographic projection of the active layers of multiple multiplexing control transistors on the substrate. The orthographic projection of the first shielding structure 201 on the substrate may include the channel region of the active layer T30 of the third transistor T3 in the orthographic projection on the substrate, ensuring the performance of the third transistor T3.

[0130] In some examples, the first conductive layer may include: scan lines GAL located in the display area AA, emission control lines EML, second reset control lines RST2, and gates of third transistors T3 of multiple pixel circuits, as well as first gates of multiple multiplexing control transistors located in the first sub-region B11 (for example, including the first gate M73 of the seventh multiplexing control transistor M7 and the first gate M83 of the eighth multiplexing control transistor M8). The gate of the third transistor T3 can be multiplexed as the first electrode of the storage capacitor Cst. The overlapping portion of the scan line GAL with the active layer T40 of the fourth transistor T4 can be multiplexed as the gate of the fourth transistor T4, and the overlapping portion of the scan line GAL with the active layer T20 of the second transistor T2 can be multiplexed as the gate of the second transistor T2. The overlapping portion of the emission control line EML with the active layer T50 of the fifth transistor T5 can be multiplexed as the gate of the fifth transistor T5, and the overlapping portion of the emission control line EML with the active layer T60 of the sixth transistor T6 can be multiplexed as the gate of the sixth transistor T6. The overlapping portion of the second reset control line RST2 with the active layer T70 of the seventh transistor T7 can be multiplexed as the gate of the seventh transistor T7. The orthographic projection of the first gate M73 of the seventh multiplexing control transistor M7 and the first gate M83 of the eighth multiplexing control transistor M8 on the substrate may be strip-shaped extending along the first direction D1.

[0131] In some examples, the third conductive layer may include: multiple connection electrodes located in the display area AA, first and second poles of multiple multiplexing control transistors located in the first sub-region B11 (such as including the first pole M71 and the second pole M72 of the seventh multiplexing control transistor M7, the first pole M81 and the second pole M82 of the eighth multiplexing control transistor M8), as well as a first multiplexing control line ML1 and a second multiplexing control line ML2. The first multiplexing control line ML1 and the second multiplexing control line ML2 may be located on a side of the multiple multiplexing control transistors away from the display area AA. The first pole M71 of the seventh multiplexing control transistor M7 and the first pole M81 of the eighth multiplexing control transistor M8 may be an integral structure. For example, the first poles of the seventh multiplexing control transistor M7 and the eighth multiplexing control transistor M8 of two adjacent multiplexing circuits 30 may be an integral structure and connected to the same multiplexing data line. The second pole M72 of the seventh multiplexing control transistor M7 may be connected to a data line, and the second pole M82 of the eighth multiplexing control transistor M8 may be connected to another data line. The first gate M73 of the seventh multiplexing control transistor M7 may be connected to the first multiplexing control line ML1, and the first gate M83 of the eighth multiplexing control transistor M8 may be connected to the second multiplexing control line ML2.

[0132] In some examples, the second shielding block 221 and the first shielding structure 201 of the display area AA may be an integral structure. The first shielding structure 201 may extend to the second border area, the third border area, and the fourth border area, and be connected to the first border power line VLD, so as to receive the first power signal. In other examples, the second shielding block 221 may be connected to the trace located in the first border area and transmitting the first power signal, so as to receive the first power signal. For the remaining descriptions of this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0133] Figure 10 Another equivalent circuit diagram of the multiplexing circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 10 shown, a multiplexing circuit may include six multiplexing control transistors (i.e., the first multiplexing control transistor M1 to the sixth multiplexing control transistor M6). The first gate and the second gate of the first multiplexing control transistor M1, the first gate and the second gate of the second multiplexing control transistor M2, and the first gate and the second gate of the third multiplexing control transistor M3 may be connected to the first multiplexing control line ML1. The first gate and the second gate of the fourth multiplexing control transistor M4, the first gate and the second gate of the fifth multiplexing control transistor M5, and the first gate and the second gate of the sixth multiplexing control transistor M6 may be connected to the second multiplexing control line ML2. For the remaining descriptions of the circuit structure of the multiplexing circuit in this example, reference may be made to Figure 4 the descriptions of the embodiments shown, and thus will not be elaborated herein.

[0134] Figure 11 Another partial plan view of the display panel according to at least one embodiment of the present disclosure. Figure 12A is Figure 11 a schematic diagram of the bottom shielding metal layer in Figure 12B is Figure 11 a schematic diagram of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figures 11 to 12B shown, the bottom shielding metal layer may include: a plurality of first shielding blocks 220a and 220b located in the first border area. The first shielding blocks 220a and 220b may be arranged at intervals along the second direction D2. The first shielding block 220a may be an integral structure of the second gates of the first multiplexing control transistor M1, the second gate of the second multiplexing control transistor M2, and the second gate of the third multiplexing control transistor M3. The orthographic projection of the first shielding block 220a on the substrate may include the orthographic projections of the active layers of the first multiplexing control transistor M1, the second multiplexing control transistor M2, and the third multiplexing control transistor M3 on the substrate. The first shielding block 220a may be connected to the first multiplexing control line ML1.

[0135] In some examples, the first shielding block 220b may be an integrated structure of the second gates of the fourth multiplexing control transistor M4, the fifth multiplexing control transistor M5, and the sixth multiplexing control transistor M6. The orthographic projection of the first shielding block 220b on the substrate may include the orthographic projections of the active layers of the fourth multiplexing control transistor M4, the fifth multiplexing control transistor M5, and the sixth multiplexing control transistor M6 on the substrate. The first shielding block 220b may be connected to the second multiplexing control line ML2.

[0136] In this example, by connecting the second gate of the multiplexing control transistor to the first gate, the characteristic stability of the multiplexing control transistor can be improved. For the remaining descriptions of the display panel in this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0137] Figure 13 FIG. is another partial plan view schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as Figure 13 shown, the multiplexing circuit 30 may include: two multiplexing units (such as multiplexing units 30-1 and 30-2). A single multiplexing unit may include a plurality of multiplexing control transistors connected to the same multiplexing control line. For example, the multiplexing unit 30-1 may include: a first multiplexing control transistor, a second multiplexing control transistor, and a third multiplexing control transistor connected to the first multiplexing control line ML1; the multiplexing unit 30-2 may include: a fourth multiplexing control transistor, a fifth multiplexing control transistor, and a sixth multiplexing control transistor connected to the second multiplexing control line ML2.

[0138] In some examples, as Figure 13 shown, the display panel may further include: a first shielding structure 51. The first shielding structure 51 may be located on the side of the multiplexing circuit 30 away from the substrate. The first shielding structure 51 may be located, for example, in the fourth conductive layer. The first shielding structure 51 may include: a plurality of shielding bars 511 and at least one connecting bar 512. The plurality of shielding bars 511 and the connecting bar 512 may be directly connected. The connecting bar 512 may be located on the same side of the plurality of shielding bars 511, such as on the side of the plurality of shielding bars 511 close to the display area. The shielding bars 511 may extend along the first direction D1, and the connecting bar 512 may extend at least along the second direction D2. The first shielding structure 51 may be configured to receive a regulated signal, for example, a first power signal or a second power signal.

[0139] In some examples, as Figure 13 shown, the orthographic projection of the shielding bar 511 on the substrate may be located between the orthographic projections of two adjacent multiplexing units (such as multiplexing unit 30-1 and multiplexing unit 30-2) on the substrate. The orthographic projection of the shielding bar 511 on the substrate and the orthographic projections of the active layers of the plurality of multiplexing control transistors on the substrate may have no overlap.

[0140] In this example, by setting the first shielding structure, signal shielding can be performed between adjacent multiplexing units, which can prevent mutual crosstalk between adjacent multiplexing units. For the remaining structures of the display panel in this example, reference can be made to the description of the foregoing embodiments, and thus will not be elaborated herein.

[0141] Figure 14 It is another partial plan view of a display panel according to at least one embodiment of the present disclosure; Figure 15 is Figure 14 a schematic diagram of the second shielding structure in. In some examples, as Figure 14 and Figure 15 shown, the display panel may include: a first shielding structure 51 and a second shielding structure 52. The second shielding structure 52 may be located on a side of the first shielding structure 51 away from the substrate. For example, the first shielding structure 51 may be located in the fourth conductive layer, and the second shielding structure 52 may be provided on the same layer as the first electrode of the light-emitting element.

[0142] In some examples, the second shielding structure 52 may include a plurality of hollow portions 520. The plurality of hollow portions 520 may be arranged in an array along a first direction D1 and a second direction D2, wherein multiple rows of hollow portions are offset in the first direction D1. Since the second shielding structure 52 is provided on the same layer as the first electrode of the light-emitting element, a planarization layer (such as Figure 3 the seventh insulating layer shown) is provided on a side of the second shielding structure 52 close to the substrate. By providing a plurality of hollow portions 520 in the second shielding structure 52, an exhaust channel can be provided for the planarization layer, which is beneficial to ensuring the uniformity and stability of the film layer.

[0143] In this example, by setting the first shielding structure, signal shielding can be performed between adjacent multiplexing units, which can prevent mutual crosstalk between adjacent multiplexing units; by setting the second shielding structure, the influence of other signals (such as touch signals or antenna signals) on the multiplexing circuit can be shielded. By performing a hollow design on the second shielding structure, the capacitance of the multiplexing circuit can be reduced, and the power consumption of the multiplexing circuit can be lowered. For the remaining descriptions of this example, reference can be made to the description of the foregoing embodiments, and thus will not be elaborated herein.

[0144] Figure 16 It is another partial plan view of a display panel according to at least one embodiment of the present disclosure. In some examples, as Figure 15 shown, the display panel may include a second shielding structure 52. The second shielding structure 52 may be provided on the same layer as the first electrode of the light-emitting element, or the second shielding structure 52 may be located in the fourth conductive layer. The second shielding structure 52 may include a plurality of hollow portions 520. In other examples, the second shielding structure 52 may be a solid structure.

[0145] In this example, by setting the second shielding structure, the influence of other signals (such as touch signals or antenna signals) on the multiplexing circuit can be shielded. By performing a hollow design on the second shielding structure, the capacitance of the multiplexing circuit can be reduced, and the power consumption of the multiplexing circuit can be lowered. For the remaining descriptions of this example, reference can be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0146] Figure 17 Another schematic diagram of the first border area of the display panel according to at least one embodiment of the present disclosure. Figure 18 A bending schematic diagram of the display panel according to at least one embodiment of the present disclosure. In some examples, as Figure 17 shown, the first border area B1 may include: a first sub-area B11, a bending area B12, and a second sub-area B13 that are sequentially arranged along the direction away from the display area AA. The first sub-area B11 may include a first wiring area FA1; the second sub-area B13 may include a second wiring area FA2, a third wiring area FA3, a first signal access area B131, and a second signal access area B132 that are sequentially arranged along the direction away from the bending area B12. A plurality of multiplexing circuits 30 may be located in the second sub-area B13 and between the second wiring area FA2 and the third wiring area FA3.

[0147] In some examples, Figure 18 shown is a cross-sectional schematic diagram of the display panel 70 after bending. The third direction D3 may be perpendicular to the plane where the display panel 70 is located. The integrated circuit 61 may be bound and connected to the first contact pad of the first signal access area, and the flexible circuit board 62 may be bound and connected to the second contact pad of the second signal access area. The cover plate 71 may cover the display surface of the display panel 70, and the heat dissipation structure 72 and the antenna structure 73 may be provided on the non-display surface of the display panel 70. The non-display surface of the display panel 70 may be the back surface of the display panel. When the multiplexing circuit 30 is provided in the second sub-area B13, after the display panel 70 is bent, the multiplexing circuit 30 will be close to the lower edge position of the antenna structure 73, and there will be interference between the antenna structure 73 and the multiplexing circuit 30. Figure 18 In the area 701 in, there is no interference, and in the area 700, there is interference. The electromagnetic interference between the multiplexing circuit 30 and the antenna structure 73 generates harmonics from the fundamental wave doubling, which interferes with the radio frequency antenna, thereby affecting the display of the display panel. In this example, by introducing a second gate into the multiplexing control transistor of the multiplexing circuit 30, and the second gate is connected to a regulated voltage signal or connected to the first gate, the stability of the multiplexing control transistor can be improved, and the anti-interference ability can be enhanced. In other examples, by providing a second shielding structure on the side of the multiplexing circuit 30 away from the substrate, it is beneficial to shield the antenna signal interference. For the structural description of the multiplexing circuit in this example, reference can be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0148] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, and a plurality of multiplexing circuits. The substrate includes a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels; the plurality of multiplexing circuits are located in the first border area and are connected to the plurality of data lines. The display panel further includes at least one of the following: a first shielding structure, a second shielding structure. The first shielding structure is located in the first border area and includes a plurality of shielding bars. At least one multiplexing circuit includes multiple groups of multiplexing units, and at least one group of multiplexing units includes at least one multiplexing control transistor. The orthographic projection of the shielding bar on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of adjacent two groups of multiplexing units on the substrate. The second shielding structure is located in the first border area and on the side of the plurality of multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of multiplexing circuits on the substrate.

[0149] The display panel provided in this embodiment can perform signal shielding between adjacent multiplexing units by setting the first shielding structure, and can prevent mutual crosstalk between adjacent multiplexing units; by setting the second shielding structure, the influence of other signals (such as touch signals or antenna signals) on the multiplexing circuits can be shielded.

[0150] For the remaining descriptions of the display panel of this example, reference can be made to the descriptions of the foregoing embodiments, so they will not be repeated here.

[0151] Figure 19 It is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As Figure 19 shown, this embodiment provides a display device 91 that may include: a display panel 910. The display panel 910 may be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel. The display device 91 may be a product having an image (including a static image or a dynamic image, where the dynamic image may be a video) display function. For example, the display device may be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device in departments such as e-government, banks, hospitals, and power), a monitor, etc. Any one of the products. Again, the display device may also be a microdisplay, any one of the VR devices or AR devices including the microdisplay, etc.

[0152] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example" or "some examples" mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0153] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of sub-pixels and a plurality of data lines are disposed on the substrate, and the plurality of data lines are connected to the plurality of sub-pixels; A plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines are disposed on the substrate and located on one side of the plurality of sub-pixels, wherein at least one of the plurality of multiplexing circuits is connected to the plurality of multiplexing control lines, at least two of the plurality of data lines, and at least one of the plurality of multiplexing data lines; The at least one multiplexing circuit includes: a plurality of multiplexing control transistors, at least one of the plurality of multiplexing control transistors includes: a first gate, a second gate and an active layer, the first gate is located on a side of the active layer away from the substrate, the second gate is located on a side of the active layer close to the substrate; the second gate is configured to receive a regulated voltage signal, or is connected to the first gate.

2. The display panel according to claim 1, characterized in that: The at least one multiplexing circuit is configured to, under the control of the plurality of multiplexing control lines, time-divisionally transmit the signal transmitted by the at least one multiplexing data line to the at least two data lines.

3. The display panel according to claim 1, characterized in that: The second gates of the multiple multiplexing control transistors of the at least one multiplexing circuit are an integrated structure and are configured to receive a regulated voltage signal; the orthographic projection of the integrated structure on the substrate includes the orthographic projection of the active layers of the multiple multiplexing control transistors on the substrate.

4. The display panel according to claim 3, characterized in that: The display panel further includes a first shielding structure, the orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of sub-pixels on the substrate, and the first shielding structure is connected to the second gates of the plurality of multiplexing control transistors.

5. The display panel according to claim 4, characterized in that: At least one of the multiple sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit includes a driving transistor, and the first shielding structure includes a channel region of an active layer of the driving transistor of the pixel circuit on the substrate in an orthographic projection on the substrate.

6. The display panel according to claim 5, characterized in that: The pixel circuit is connected to a first power line, the light emitting element is connected to a second power line, and a first power signal provided by the first power line is greater than a second power signal provided by the second power line; The voltage stabilization signal includes: the first power supply signal.

7. The display panel according to claim 1, characterized in that: The at least one multiplexing circuit includes: multiple groups of multiplexing units, each group of multiplexing units includes multiple multiplexing control transistors; the first gate and the second gate of the multiple multiplexing control transistors of a group of multiplexing units are connected to the same multiplexing control line, and the second gate of the multiple multiplexing control transistors of the group of multiplexing units is an integrated structure.

8. The display panel according to claim 1, characterized in that: The display panel further includes at least one of the following: A first shielding structure, wherein the first shielding structure comprises: a plurality of shielding bars; the at least one multiplexing circuit comprises: a plurality of multiplexing units, at least one of the plurality of multiplexing units comprises at least one multiplexing control transistor; an orthographic projection of at least one of the plurality of shielding bars on the substrate is located between the orthographic projections of active layers of multiplexing control transistors of two adjacent groups of multiplexing units on the substrate; A second shielding structure is located at a side of the multiplex circuits away from the substrate, and an orthographic projection of the second shielding structure on the substrate at least partially overlaps with an orthographic projection of the multiplex circuits on the substrate.

9. The display panel according to claim 8, characterized in that: The second shielding structure is located on a side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollow portions.

10. The display panel according to claim 8, characterized in that: In a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate, and the first shielding structure is located in the second source-drain metal layer.

11. The display panel according to claim 8, characterized in that: At least one of the multiple sub-pixels includes a light-emitting element, which includes a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

12. The display panel according to claim 1, characterized in that: The substrate includes a display area and a first frame area located on one side of the display area, and the multiple sub-pixels are located in the display area; the first frame area includes: a first sub-area, a bending area, and a second sub-area arranged in sequence along a direction away from the display area, and the multiple multiplexing circuits are located in the first sub-area or the second sub-area.

13. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 12.

14. A display panel, characterized in that: include: A substrate, comprising a display area and a first frame area located on one side of the display area; A plurality of sub-pixels and a plurality of data lines are arranged on the substrate and located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels; A plurality of multiplexing circuits, located in the first frame area and connected to the plurality of data lines; The display panel further includes at least one of the following: A first shielding structure is located in the first frame area and includes a plurality of shielding strips, at least one of the plurality of multiplexing circuits includes a plurality of multiplexing units, at least one of the plurality of multiplexing units includes at least one multiplexing control transistor, and an orthographic projection of at least one of the plurality of shielding strips on the substrate is located between the orthographic projections of active layers of multiplexing control transistors of two adjacent groups of multiplexing units on the substrate; The second shielding structure is located in the first frame area and on a side of the multiplex circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the multiplex circuits on the substrate.

15. The display panel according to claim 14, characterized in that: The second shielding structure is located on a side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollow portions.

16. The display panel according to claim 14, characterized in that: In a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate, and the first shielding structure is located in the second source-drain metal layer.

17. The display panel according to claim 14, characterized in that: At least one of the multiple sub-pixels includes a light-emitting element, which includes a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

18. The display panel according to claim 14, characterized in that: The first frame area includes: a first sub-area, a bending area, and a second sub-area which are sequentially arranged in a direction away from the display area, and the multiplex circuits are located in the second sub-area.

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