Wiring substrate, light-emitting substrate and display device

Abstract

The invention discloses a wiring substrate. The wiring substrate comprises functional units (31) which are distributed in an array; each functional unit (31) comprises: a plurality of first pad groups (311) arranged along a first direction; the second bonding pad group (312) is located on one side of the first bonding pad groups (311) in the second direction, the second bonding pad group (312) comprises a plurality of channel bonding pads and at least two functional bonding pads, the number of the bonding pads is an even number, and the bonding pads are distributed in an array mode in the mode of 2 * N; the plurality of channel bonding pads are sequentially arranged into a first row along the same direction and are respectively connected with the plurality of first bonding pad groups (311) with the same number in a one-to-one correspondence manner; one of the at least two functional bonding pads is located in the first row, and the functional bonding pad is only adjacent to one of the plurality of channel bonding pads; and the other functional pads in the at least two functional channel pads are arranged at intervals in the same direction to form a second row. The wiring substrate can simplify the technological process, improve the product yield and reduce the manufacturing cost. A light emitting substrate including the wiring substrate and a display device including the light emitting substrate are also provided.

Description

Wiring substrate, light-emitting substrate and display device Technical Field

[0001] The present disclosure relates to the technical field of display equipment, and in particular to a wiring substrate, a light-emitting substrate, and a display device. Background Art

[0002] Glass-based Mini-LED display technology is nearing maturity, and more and more panel manufacturers are transitioning to Mini-LED display panel production. As the technology matures and costs decrease, competition is intensifying. For the back plane light board (BP light board) used in glass-based Mini-LED direct display devices, the current mainstream process is still a double-layer copper, six-mask process, which uses two layers of metal routing. This double-layer copper process is complex, has low yields, and is costly.

[0003] Summary of the Invention

[0004] The present disclosure provides a wiring substrate, a light-emitting substrate and a display device. The wiring substrate can greatly simplify the manufacturing process, thereby improving product yield and significantly reducing manufacturing costs.

[0005] To achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A wiring substrate comprises: a plurality of functional units distributed in an array; each of the functional units comprises:

[0007] A plurality of first pad groups, wherein the plurality of first pad groups are arranged at intervals along a first direction, and each of the first pad groups includes a first sub-pad and a second sub-pad arranged at intervals along a second direction;

[0008] A second pad group, the second pad group being located on one side of the plurality of first pad groups along a second direction, the second pad group comprising a plurality of channel pads and at least two functional pads, the number of pads in the second pad group being an even number and being distributed in a 2*N array;

[0009] Among them, the multiple channel pads are arranged in sequence along the same direction to form a first row, and are respectively connected one-to-one with the same number of multiple first pad groups; one of the at least two functional pads is located in the first row, and the functional pad is only adjacent to one of the multiple channel pads; the remaining functional pads of the at least two functional pads are arranged in the second row along the same direction.

[0010] Optionally, it further comprises a plurality of routing groups arranged along the second direction, the number of the plurality of routing groups is the same as the number of columns of the functional units, and each group of the routing groups is correspondingly connected to a column of functional units;

[0011] Each of the routing groups includes a plurality of connecting lines, a first type of routing lines, and a second type of routing lines, wherein the plurality of connecting lines are used to connect the channel pads in a column of functional units to the second sub-pads in a one-to-one correspondence, the first type of routing lines are connected to the functional pads in a column of functional units, and the second type of routing lines are connected to the first sub-pads in a column of functional units;

[0012] Among them, the first type of routing and the second type of routing are arranged along the second direction and extend along the first direction, at least one routing of the first type of routing passes through the gap between the first row and the second row of the second pad group in a column of functional units, and at least one routing of the second type of routing passes through the gap between the first sub-pad and the second sub-pad in a column of functional units, so that each routing in the multiple routing groups is arranged on the same layer.

[0013] Optionally, in each of the functional units, the plurality of channel pads are arranged adjacent to the second sub-pads in the plurality of first pad groups along the second direction, and an arrangement order of the channel pads matches an arrangement order of the corresponding first pad groups.

[0014] Optionally, in each of the functional units, the at least two functional pads include a signal pad, an address input pad, an address output pad, and at least one ground pad;

[0015] Any one of the signal pad, the address input pad and the address output pad is located in the first row of the second pad group, and at least one of the address input pad and the address output pad is adjacent to only one of the other pads in the same row.

[0016] Optionally, the first type of routing includes:

[0017] A signal line connected to all signal pads in a corresponding column of functional units;

[0018] A ground line connected to the ground pad in a corresponding column of functional units;

[0019] A plurality of cascade lines, wherein the plurality of cascade lines are used to cascade every two adjacent functional units in a column of functional units, one end of the cascade line being connected to the address output pad of the preceding functional unit and the other end being connected to the address input pad of the succeeding functional unit;

[0020] An address line is connected to an address input pad of a first functional unit in a corresponding column of functional units.

[0021] Optionally, in each of the functional units, the extension directions of the first row and the second row of the second pad group are both the first direction.

[0022] Optionally, in each of the functional units, the signal pads are located in the first row of the second pad group;

[0023] The signal line is arranged through the gap between the first row and the second row of the second pad group;

[0024] The ground line is located on a side of the second pad group away from the first pad group.

[0025] Optionally, in the second pad group, the address input pad and the address output pad are each adjacent to only one of the other pads in the row;

[0026] The cascade line is located between two adjacent functional units in a column of functional units.

[0027] Optionally, in the second pad group, one of the address input pad and the address output pad is adjacent to only one of the other pads in the row;

[0028] The cascading line is disposed through a gap between a first row and a second row of the second pad group.

[0029] Optionally, in each of the functional units, the extension directions of the first row and the second row of the second pad group are both the second direction.

[0030] Optionally, in each of the functional units, one of the address input pad and the address output pad is located in the first row of the second pad group;

[0031] The cascade line is located between two adjacent functional units in a column of functional units.

[0032] Optionally, in each of the functional units, the at least one ground pad is adjacent to a functional pad located in a first row of the second pad group;

[0033] The ground line is located at a side of the second pad group away from the plurality of first pad groups along the second direction;

[0034] The signal line is disposed through a gap between the first row and the second row of the second pads.

[0035] Optionally, in each of the functional units, the signal pad is adjacent to a functional pad located in the first row of the second pad group;

[0036] The signal line is located on a side of the second pad group away from the plurality of first pad groups along the second direction;

[0037] The grounding line is located in the gap between the first row and the second row of the second pads.

[0038] Optionally, the address line is located on a side of the second type of traces away from the second pad group.

[0039] Optionally, the second pad group includes two ground pads, and the two ground pads are adjacent to each other.

[0040] Optionally, in each of the functional units, the plurality of first pad groups are divided into two categories, and first pad groups of the same category are arranged adjacent to each other;

[0041] The second type of routing includes two power lines, each of which is connected to a type of first pad group in a column of functional units, one of which is located on a side of the multiple first pad groups away from the second pad group, and the other power line is set through the gap between the first sub-pad and the second sub-pad in the first pad group.

[0042] The present disclosure also provides a light-emitting substrate, including any one of the wiring substrates provided in the above technical solutions, and also including a plurality of light-emitting elements connected one-to-one with the first pad group and a plurality of driving elements connected one-to-one with the second pad group.

[0043] The present disclosure also provides a display device, comprising the light-emitting substrate provided in the above technical solution.

[0044] The embodiments of the present disclosure provide a wiring substrate, a display substrate and a display device, wherein the wiring substrate includes a plurality of identical functional units distributed in an array; each functional unit includes a plurality of first pad groups and a second pad group; the plurality of first pad groups are arranged at intervals along a first direction, and the second pad group is located on the same side of the plurality of first pad groups along a second direction; in the second pad group, a plurality of channel pads are sequentially arranged in a first row at intervals along the same direction, and are respectively connected one-to-one with a plurality of first pad groups of the same number in the functional unit in which they are located, so that the traces connected to the first pad group, the traces connected between the first pad group and the second pad group, and the traces connected to the second pad group are sequentially arranged along the second direction without overlapping, which is conducive to making all traces arranged on the same layer; in the second pad group, one of at least two functional pads is located The first row, and the functional pad is only adjacent to one channel pad among the multiple channel pads, that is, a functional pad is set at the end of the first row of the second pad group, and the remaining functional pads of at least two functional pads are arranged in the second row at intervals along the same direction. Compared with the technical solutions in the related art, the number of functional pads in the second pad group is increased, and the positions of the functional pads are adjusted. At the same time, the type of signal received by the functional pad can be adjusted, and the shape and extension direction of the trace connected to the second pad group can be changed. It can be achieved that all traces in the wiring substrate are set on the same layer, and then the functional units on the wiring substrate and the traces connected to the functional units can be single-layered, which can greatly simplify the process of manufacturing the wiring substrate, thereby improving the product yield, and reducing the use of mask plates, greatly reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG1 is a schematic diagram of the connection structure of pads and traces on a light-emitting substrate in the related art;

[0046] FIG2 is a schematic diagram of a connection structure of a functional unit and a wiring in the related art;

[0047] FIG3 is a schematic diagram of the structure of a functional unit and wiring in the related art;

[0048] FIG4 is a cross-sectional view along the cutting line AA′ in FIG3 ;

[0049] FIG5 is a schematic diagram of the structure of functional units and wiring on a wiring substrate provided by an embodiment of the present disclosure;

[0050] FIG6 is a cross-sectional view along the cutting line BB′ in FIG5 ;

[0051] FIG7 is a cross-sectional view of a wiring substrate provided in an embodiment of the present disclosure;

[0052] FIG8 is a schematic diagram of the structure of functional units and wiring on another wiring substrate provided by an embodiment of the present disclosure;

[0053] FIG9 is a schematic diagram showing the connection between a first pad group and a second pad group provided by an embodiment of the present disclosure;

[0054] 10-15 are schematic diagrams of pad arrangements in a functional unit provided by an embodiment of the present disclosure;

[0055] 16 to 29 are schematic diagrams showing connections between a second pad group and a first type of trace provided by an embodiment of the present disclosure;

[0056] FIG30 is a schematic structural diagram of a functional unit and its connected wiring provided by an embodiment of the present disclosure;

[0057] 31-32 are schematic diagrams showing the connection between a first pad group and a second type of trace provided in an embodiment of the present disclosure.

[0058] icon:

[0059] 1-substrate substrate; 2-buffer layer; 3-metal routing layer; 31-functional unit; 311, 3111, 3112, 3113-first pad group; 312-second pad group; 3121-first row; 3122-second row; 32-routing group; 321-connecting routing; 322-first type routing; 323-second type routing; 4-insulating layer; 41-opening. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0061] In the related art, the light-emitting substrate includes a base substrate 01, M1*M2 functional units 02 arranged in an array on the base substrate, M1 address signal lines S, M1 address signal transfer lines Q, M2 data lines D, M2 ground lines G, M2 first power lines Va and M2 second power lines Vb, and multiple pixel units; as shown in Figure 1, a schematic diagram of the connection structure of the light-emitting substrate in an embodiment of the present disclosure is shown, and as shown in Figure 2, a schematic diagram of the connection structure of a functional unit in an embodiment of the present disclosure is shown.

[0062] Among them, multiple functional units 02 are distributed in an array in the first direction F1 and the second direction F2, and the first direction F1 and the second direction F2 intersect with each other. The functional unit 02 includes multiple first pad groups 021 and a second pad group 022. The second pad group 022 includes channel pads CH (for example, CH1, CH2, CH3), data signal pads Da, address pads Uc, and ground pads GND corresponding to the first pad group in the functional unit. The channel pads can be connected to the first pad group 021 one by one through connecting traces 023. The data signal pads Da, address pads Uc, and ground pads GND are functional pads.

[0063] Multiple pixel units 03 are connected to multiple functional units 02 in a one-to-one correspondence. The pixel unit 03 includes multiple light-emitting elements 031 and a driving element 032. The number of pads in the first pad group 021 in the functional unit is the same as the number of pins of the light-emitting element 031. The pins of the light-emitting element 031 are connected to the pads in the first pad group 021 in the functional unit in a one-to-one correspondence. The number of pads in the second pad group 022 in the functional unit is the same as the number of pins of the driving element 032. The pins of the driving element 032 are connected to the pads in the second pad group 022 in the functional unit in a one-to-one correspondence, for driving the light-emitting element 031 to light up.

[0064] It should be noted that the first direction F1 can be the row direction of the multiple functional units arranged in an array, and the second direction F2 can be the column direction of the multiple functional units arranged in an array; alternatively, the first direction F1 can be the column direction of the multiple functional units arranged in an array, and the second direction F2 can be the row direction of the multiple functional units arranged in an array, without limitation. For ease of explanation, in the disclosed embodiment, the first direction F1 is the column direction, and the second direction F2 is the row direction. The value of M1 is equal to the number of rows of functional units, and the value of M2 is equal to the number of columns of functional units.

[0065] Each address signal line Si (0<i≤M1, i is a positive integer) is coupled to an address pad Uc in the second pad group of each functional unit arranged in a row in the second direction F2 to provide address data for the pixel unit.

[0066] Each address signal transfer line Q i (0<i≤M1, i is a positive integer) and the address signal line S i One-to-one correspondence;

[0067] Each data line Dj (0<j≤M2, j is a positive integer) is coupled to the data signal pad Da of each second pad group of a column of functional units arranged in the first direction F1, for providing the pixel unit.

[0068] A ground line Gj (0<j≤M2, j is a positive integer) is coupled to the ground pad GND of each second pad group of a column of functional units arranged in the first direction F1, and is used to provide a ground voltage signal for the pixel unit;

[0069] The first power line Vaj and the second power line Vbj are coupled to a row of first pad groups arranged in the first direction F1; the second sub-pads of each first pad group in the functional unit are respectively coupled to each signal channel pad CH of the second pad group.

[0070] During the driving process of the above-mentioned light-emitting substrate, in the address allocation stage, the address selection information is transmitted to the address pad through each address signal line in turn, and the address selection information includes the address ID of the corresponding pixel row, so that the driving element 032 obtains a specific address ID respectively; in the data signal transmission stage, the data information is transmitted to each pixel column respectively through each data line; the data information includes the address ID and pixel data information corresponding to all driving elements in a certain pixel column. Therefore, each driving element can accurately obtain the pixel data information matching its own address ID, and after parsing and subpackaging the pixel data information, it forms an electrical signal for controlling the connected light-emitting unit respectively, thereby realizing an active addressing driving method.

[0071] The specific wiring structure diagram and cross-sectional view of the area where a functional unit 02 in the above-mentioned light-emitting substrate is located can be shown in Figures 3 and 4 respectively. Figure 4 is a cross-sectional view formed along the cutting line AA' in Figure 3. During the manufacturing process, the light-emitting substrate specifically includes a base substrate 01, a buffer layer 04, a first metal routing layer 05, a first insulating layer 061, a first flat layer 071, a second insulating layer 062, a second metal routing layer 08, a third insulating layer 063, a second flat layer 072 and a fourth insulating layer 064. As shown in Figure 3, the above-mentioned M1 address signal transfer lines Q, M2 data lines D, M2 ground lines G, M2 first power lines Va, M2 second power lines Vb, etc. can belong to the first metal routing layer, and multiple functional units 02, the connecting routing 023, and the M1 address signal line S can belong to the second metal routing layer 08 to form a double-layer routing layer. The various routings in the first metal routing layer 05 are connected to the first pad group 021 and the second pad group 022 of the functional unit in the second metal routing layer 08 through the first through-hole 091 penetrating the first insulating layer 061, the first flat layer 071, and the second insulating layer 062. The light-emitting element can be connected to the first pad group 021 and the second pad group 022 in the functional unit through the second through-hole 092 penetrating the third insulating layer 063, the second flat layer 071, and the fourth insulating layer 064.

[0072] As shown in Figure 3, in the above-mentioned second metal routing layer 08, the various pads in the functional unit 02 and the connected routing are an integrated structure, and each pad is a portion of the second metal routing layer 08 exposed by the second through-hole 092 formed on the third insulating layer 063, the second flat layer 071 and the fourth insulating layer 064, while the routing in the second metal routing layer 08 is a portion covered and protected by the third insulating layer 063, the second flat layer 071 and the fourth insulating layer 064.

[0073] The above-mentioned double-layer metal routing layer structure needs to undergo multiple patterning processes during the manufacturing process, specifically, for example, including: (1) patterning the first metal routing layer 05; (2) patterning the first insulating layer 061 and the first flat layer 071; (3) patterning the second insulating layer 062; (4) patterning the second metal routing layer 08; (5) patterning the third insulating layer 063 and the second flat layer 072; (6) patterning the fourth insulating layer 064. Therefore, it can be seen that the manufacturing process of the double-layer metal routing layer is complex, which may result in low product yield and high cost.

[0074] In order to overcome the above technical problems, an embodiment of the present disclosure provides a wiring substrate, as shown in FIG5 and FIG6 , comprising: a plurality of functional units 31 distributed in an array; each functional unit 31 comprises:

[0075] A plurality of first pad groups 311, wherein the plurality of first pad groups 311 are arranged at intervals along the first direction F1, and each first pad group 311 includes first sub-pads P1 and second sub-pads P2 arranged at intervals along the second direction F2;

[0076] A second pad group 312 is located on one side of the plurality of first pad groups 311 along the second direction F2. The second pad group 312 includes a plurality of channel pads Ch and at least two function pads Gn. The number of pads in the second pad group 312 is an even number and is spaced apart in a 2*N array.

[0077] Among them, multiple channel pads Ch are arranged in sequence along the same direction to form a first row 3121, and are respectively connected one-to-one with the same number of multiple first pad groups 311; one functional pad Gn of at least two functional pads Gn is located in the first row 3121, and the functional pad Gn is only adjacent to one channel pad Ch of the multiple channel pads Ch; the remaining functional pads Gn of at least two functional pads are arranged in the second row 3122 along the same direction.

[0078] The wiring substrate provided by the embodiment of the present disclosure includes a plurality of identical functional units 31 distributed in an array; each functional unit 31 includes a plurality of first pad groups 311 and a second pad group 312; the plurality of first pad groups 311 are arranged at intervals along a first direction F1, and the second pad group 312 is located on the same side of the plurality of first pad groups 311 along a second direction F2; in the second pad group 312, a plurality of channel pads Ch are sequentially arranged in a first row 3121 at intervals along the same direction, and are respectively connected one-to-one with the same number of first pad groups 311 in the functional unit 31 in which they are located, so that the traces connected to the first pad group 311, the traces connected between the first pad group 311 and the second pad group 312, and the traces connected to the second pad group 312 are arranged in sequence along the second direction F2 without overlapping, which is conducive to ensuring that all traces are arranged on the same layer; in the second pad group 312, one of the at least two functional pads Gn is located The first row 3121, and the functional pad Gn is adjacent to only one channel pad Ch among the multiple channel pads Ch, that is, a functional pad Gn is set at the end of the first row 3121 of the second pad group 312, and the remaining functional pads Gn of at least two functional pads Gn are arranged in the same direction to form a second row 3122. Compared with the technical solutions in the related art, the number of functional pads Gn in the second pad group 312 is increased, and the position of the functional pads Gn is adjusted. At the same time, the type of signal received by the functional pad Gn can be adjusted, and the shape and extension direction of the trace connected to the second pad group 312 can be changed, so that all traces in the wiring substrate are set on the same layer, and thus the functional units 31 on the wiring substrate and the traces connected to the functional units 31 can realize single-layer wiring, which can greatly simplify the process of manufacturing the wiring substrate, thereby improving the product yield, and reducing the use of mask plates, greatly reducing the production cost.

[0079] Specifically, as shown in FIG7 , which is a cross-sectional view formed along the cutting line BB' in FIG6 , the wiring substrate includes a base substrate 1, a buffer layer 2, a metal routing layer 3, and an insulating layer 4 stacked in sequence. The manufacturing process of the wiring substrate only requires two mask processes, specifically including: (1) patterning the metal routing layer 3 to form metal routing; (2) patterning the insulating layer 4 to form an opening 41. The opening 41 on the insulating layer 4 can define the pad in the functional unit 31 in the preset area of ​​the metal routing. The pixel unit can be connected to the portion of the metal routing exposed at the opening 41 through the opening 41. The pixel unit can include multiple light-emitting elements and driving elements. The light-emitting element can be connected to the first pad group 311, and the driving element can be connected to the second pad group 312. It can be seen that the structure of the wiring substrate provided in the present disclosure can greatly simplify the process of the wiring substrate.

[0080] In actual applications, the pins of the light-emitting elements are rectangular, with the width of the wide side ranging from 30 to 50 μm and the length of the long side ranging from 50 to 75 μm. The length and width of the first sub-pad P1 and the second sub-pad P2 in the corresponding first pad group 311 are 2 to 30 μm larger than the length and width of the pins of the light-emitting elements, respectively; the pins of the driving elements are rectangular, with the width of the wide side generally ranging from 30 to 50 μm and the length of the long side ranging from 45 to 70 μm. The length and width of the pads in the corresponding second pad group 312 are 2 to 30 μm larger than the length and width of the pins of the driving elements, respectively. The gap width d1 between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311 can be 50 to 200 μm, and the gap width d2 between the two rows in the second pad group 312 can be 50 to 200 μm. Since the position distribution of the first pad group determines the position distribution of the subsequent light-emitting elements, and the position distribution of the light-emitting elements has a decisive influence on the display effect, after the position of the first pad group 311 is determined, the position of the second pad group 312 must not only consider the design requirements of the routing, but also take into account the distance between the second pad group 312 and the first pad group 311. The distance d3 between the second pad group 312 and the first pad group 311 is greater than or equal to 100μm, which can meet the space requirements for repairing the light-emitting elements.

[0081] In the embodiment of the present disclosure, as shown in Figures 5 and 6, the above-mentioned wiring substrate may include a plurality of routing groups 32 arranged along the second direction F2, the number of the plurality of routing groups 32 is the same as the number of columns of the functional units 31, and each routing group 32 is correspondingly connected to a column of functional units 31; specifically, each routing group 32 includes a plurality of connecting lines 321, a first type of routing 322 and a second type of routing 323, the connecting line 321 is used to connect the channel pads Ch in a column of functional units 31 to the second sub-pads P2 respectively in a one-to-one correspondence, the first type of routing 322 is connected to the functional pads Gn in a column of functional units 31, and the second type of routing 323 is connected to the first sub-pad P1 in a column of functional units 31; wherein the first type of routing 322 and the second type of routing 323 are arranged along the second direction F2 and extend along the first direction F1. The first and second types of routings 322 and 323 are extended so as to make the general directions of the first and second types of routings 322 and 323 consistent, avoid the mutual overlap of the first and second types of routings 322 and 323, and facilitate all routings to be arranged on the same layer; at least one routing of the first type of routing 322 passes through the gap between the first row 3121 and the second row 3122 of the second pad group 312 in a column of functional units 31, and at least one routing of the second type of routing 323 passes through the gap between the first sub-pad P1 and the second sub-pad P2 in a column of functional units 31. By passing some of the routings of the first type of routing 322 and the second type of routing 323 through the gaps between the pads, all routings in the routing group 32 can be arranged on the same layer, thereby simplifying the structure of the wiring substrate, reducing the difficulty of production, and thus reducing the production cost.

[0082] In practical applications, as shown in FIG6 , the distance d4 between two adjacent lines in the first-type lines 322 and the second-type lines 323 can be 5 μm to 100 μm, and can be set based on actual conditions. The widths of the first-type lines 322 and the second-type lines 323 vary depending on their functions and require different line widths, and need to be set based on actual conditions, without limitation here.

[0083] In the above disclosed embodiment, the extension direction of the two rows of pads of the second pad group 312 in a functional unit 31 can extend along the first direction F1, as shown in Figures 5 and 6; or, can also extend along the second direction F2, as shown in Figures 8 and 9, that is, the second pad group 312 in Figures 5 and 6 is rotated 90 degrees counterclockwise. According to the extension direction of the two rows of pads in the second pad group 312, it is necessary to adaptively adjust the specific position of each pad in the second pad group 312 and the specific direction of each trace. Those skilled in the art can make adjustments based on actual conditions according to the methods of the embodiments of the present disclosure.

[0084] Specifically, in each functional unit 31, multiple channel pads Ch are arranged along the second direction F2 adjacent to the second sub-pads P2 in the multiple first pad groups 311, so that the connecting lines connecting the second sub-pads P2 and the channel pads Ch are located between the first pad group 311 and the second pad group 312 of the functional unit 31. The arrangement order of the channel pads Ch is coordinated with the arrangement order of the corresponding first pad groups 311, so that the second sub-pads P2 in each group of corresponding first pad groups 311 and the channel pads Ch in the second pad group 312 can be connected in sequence, and each connecting trace 321 can be arranged on the same layer as the first type trace 322 and the second type trace 323, and are insulated from each other without crossing.

[0085] In actual applications, a functional unit 31 may specifically include a first pad group 3111 for connecting to a red light-emitting element, a first pad group 3112 for connecting to a green light-emitting element, and a first pad group 3113 for connecting to a blue light-emitting element. The second pad group 312 of the functional unit 31 includes a first channel pad Ch1 connected to the first pad group 3111, a second channel pad Ch2 connected to the first pad group 3112, and a third channel pad Ch3 connected to the first pad group 3113. As shown in Figure 10, the two rows of the second pad group 312 of the functional unit 31 extend along the first direction F1, and the first row 3121 of the second pad group 312 in the functional unit 31 is located on the side of the second pad group 312 adjacent to the first pad group 311, so that the first channel pad Ch1, the second channel pad Ch2 and the third channel pad Ch3 are arranged adjacent to the first pad group 311, and the first pad group 3111, the first pad group 3112 and the first pad group 3113 are arranged in the first direction F1. The arrangement order of the first channel pad Ch1, the second channel pad Ch2 and the third channel pad Ch3 in the first direction F1 is the same as the arrangement order of the first pad group 3111, the first pad group 3112 and the first pad group 3113 in the first direction F1, which can ensure that the three corresponding connection lines are arranged in sequence, insulated from each other and without crossing. For example, as shown in FIG10 , in a functional unit 31, the first pad group 3111, the first pad group 3112, and the first pad group 3113 are arranged in sequence in the first direction F1, and the first channel pad Ch1, the second channel pad Ch1, and the third channel pad Ch1 in the second pad group 312 are arranged in sequence in the first direction F1; or, as shown in FIG11 , the positions of the first pad group 3111 and the first pad group 3113 in FIG10 are interchanged, and the positions of the corresponding first channel pad Ch1 and the third channel pad Ch3 are also interchanged; or, as shown in FIG12 , the positions of the first channel pad 3112 and the first channel pad 3113 in FIG10 are interchanged, and the positions of the corresponding second channel pad Ch2 and the third channel pad Ch3 are also interchanged; in addition, as shown in FIG13 , the positions of the three channel pads Ch in the first row 3121 of the second pad group 312 and the positions of the functional pads Gn can also be interchanged. Specifically, the arrangement of the plurality of first pad groups 311 and the plurality of channel pads Ch may be determined according to actual conditions.

[0086] Alternatively, as shown in FIG14 , the extension direction of the two rows of pads in the second pad group 312 of the functional unit 31 may also be the second direction F2, and the channel pads Ch in the second pad group 312 may be located in the first row 3121 adjacent to the first pad group 311, and the first pad group 3111, the first pad group 3112, and the first pad group 3113 are arranged sequentially in the first direction F1, and the first channel pad Ch1, the second channel pad Ch1, and the third channel pad Ch1 in the second pad group 312 are arranged sequentially in the second direction F2; alternatively, the order of the three first pad groups can be interchanged, and the positions of the corresponding three channel pads Ch are also interchanged to achieve the purpose of the same arrangement order. In addition, as shown in FIG15 , the upper and lower positions of the first row 3121 and the second row 3122 of the second pad group 312 may also be interchanged, and the positions of the corresponding three channel pads Ch also need to be adjusted accordingly. Specifically, the arrangement of the multiple first pad groups 311 and the multiple channel pads Ch can be determined according to actual conditions.

[0087] In the embodiment of the present disclosure, specifically, in each functional unit 31, as shown in Figure 16, at least two functional pads Gn may include a signal pad Vc, an address input pad D-in, an address output pad D-out and at least one ground pad GND; wherein, any one of the signal pad Vc, the address input pad D-in and the address output pad D-out can be located in the first row 3121 of the second pad group 312, and at least one of the address input pad D-in and the address output pad D-out is only adjacent to one of the other pads in the row, which can facilitate wiring at the end of the second pad group 312, and is conducive to the arrangement of the single-layer metal routing layer 3. In the second pad group 312 of the above-mentioned functional unit 31, the functions of the data signal pad Da and the address pad Uc in the double-layer metal routing layer 3 in the related technology are replaced by the address input pad D-in, the address output pad D-out, and the data signal pad Vc respectively. The functions of the pins of the corresponding driving elements connected to the second pad group 312 also need to be redefined. The setting of the single-layer metal routing layer 3 on the wiring substrate can be realized by adjusting the logic control circuit and function inside the driving element.

[0088] In order to ensure the stability when the second pad group is connected to the driving element, the two rows of pads in the second pad group 312 need to be symmetrically arranged. Therefore, at least one ground pad GND in the second pad group 312 can include two, and the two ground pads GND can be adjacent to each other in the second row 3122 of the second pad group 312 to facilitate connection with the corresponding trace Gd.

[0089] Specifically, as shown in Figure 16, the specific layout structure on the corresponding wiring substrate in Figure 16 can be as shown in Figures 5 and 6. The above-mentioned first-type routing 322 may include: a signal line Vcc, a ground line Gd, multiple cascade lines L, and an address line Addr; wherein, the signal line Vcc is connected to all signal pads Vc in a corresponding column of functional units 31, the ground line Gd is connected to the ground pad GND in a corresponding column of functional units 31, and the multiple cascade lines L are used to cascade every two adjacent functional units 31 in a column of functional units 31, one end of the cascade line L is connected to the address output pad D-out of the previous functional unit 31, and the other end is connected to the address input pad D-in of the next functional unit 31; the address line Addr is connected to the address input pad D-in of the first functional unit 31 in the corresponding column of functional units 31.

[0090] In the above-mentioned disclosed embodiment, the signal line Vcc connected to the signal pad Vc of a column of functional units 31 is used to provide data including address information and luminescence information, and the address line Addr and multiple cascade lines L are used to provide specific address information. By adjusting the function and number of the pads in the functional unit 31 combined with the adjustment of the routing function and layout, it is possible to avoid the need to cross routing with each other, and the first type of routing 322 and the connecting routing 321 can be set on the same layer, thereby realizing single-layer wiring of the wiring substrate.

[0091] Specifically, before the light-emitting substrate with the above-mentioned wiring substrate is powered on and displays normally, specific address information is assigned to the driving element in sequence through the address line Addr and the cascade line L. When it comes to the display stage, the signal transmitted in the signal line Vcc is a power carrier signal, that is, it includes a power supply signal that provides an operating voltage for the driving element, and is also loaded with an address data signal and a light-emitting data signal. Each driving element matches the light-emitting data that is the same as its own address information from the data transmitted by the signal line Vcc, and then undergoes internal processing and calculation of the driving element, and controls the driving element and the light-emitting element through the connecting line to form a signal path, so that the light-emitting element presents a specific grayscale brightness, which is different from the driving method of the light-emitting substrate in the related art.

[0092] In the embodiment of the present disclosure, in each functional unit 31 , the first row 3121 and the second row 3122 of the second pad group 312 may extend in different directions, so that the wiring layout of the wiring substrate obtained is also different.

[0093] Specifically, the extension direction of the first row 3121 and the second row 3122 of the second pad group 312 may both be the first direction F1. In this case, the pads and traces in each functional unit 31 may be arranged in the following structure.

[0094] Among them, as shown in Figure 16, since the channel pad Ch in the second pad group 312 of the functional unit 31 needs to be set adjacent to multiple first pad groups 311, in each functional unit 31, the signal pad Vc can be located in the first row 3121 of the second pad group 312, and is located in the same row as the multiple channel pads Ch; the signal line Vcc can be set through the gap between the first row 3121 and the second row 3122 in the second pad group 312; the ground line Gd can be located on the side of the second pad group 312 away from the first pad group 311, which can avoid interference between the signal line Vcc and the ground line Gd and other wiring, and realize the same layer setting.

[0095] Specifically, as shown in Figure 17, in the first row 3121 of the second pad group 312 of the functional unit 31, the arrangement positions of the signal pad Vc and the multiple channel pads Ch can be exchanged. The specific order of the signal pad Vc and the multiple channel pads Ch is not limited here and can be determined according to actual conditions. The arrangement method of the multiple channel pads Ch can be any of the above-mentioned technical solutions, which is not limited here and can be determined according to actual conditions.

[0096] Optionally, as shown in Figures 16 and 17, in the second pad group 312, the address input pad D-in and the address output pad D-out are only adjacent to one of the other pads in the row, that is, the address input pad D-in and the address output pad D-out are all located at the end of the second row 3122 of the second pad group 312; in this way, the cascade line L can be located between two adjacent functional units 31 in a column of functional units 31 to avoid interference with other routing lines.

[0097] Optionally, as shown in Figure 18, in the second pad group 312, it can also be set that one of the address input pad D-in and the address output pad D-out is only adjacent to one of the other pads in the row, that is, one of the address input pad D-in and the address output pad D-out is located at the end of the second row 3122 of the second pad group 312, and the other is sandwiched between the two pads; in this way, in order to avoid interference between the cascade line L and other routing lines, the cascade line L can be set to pass through the gap between the first row 3121 and the second row 3122 in the second pad group 312.

[0098] In this case, the arrangement layout of each pad in the second pad group 312 of the functional unit 31 can be set not only as shown in FIG. 18 , but also in various other implementations. For example, as shown in Figure 19, the positions of the address input pad D-in and the address output pad D-out in Figure 18 are interchanged; or, as shown in Figure 20, the position of the ground pad GND in Figure 18 is interchanged with the position of the address input pad D-in and the address output pad D-out; or, as shown in Figure 21, the positions of the address input pad D-in and the address output pad D-out in Figure 20 are interchanged; or, as shown in Figure 22, the positions of the multiple channel pads Ch in Figure 20 are interchanged with the position of the signal pad Vc; or, as shown in Figure 23, the positions of the address input pad D-in and the address output pad D-out in Figure 22 are interchanged; or, as shown in Figure 24, the position of the ground pad GND in Figure 22 is interchanged with the position of the address input pad D-in and the address output pad D-out; or, as shown in Figure 25, the positions of the address input pad D-in and the address output pad D-out in Figure 24 are interchanged. Specifically, the arrangement order of the pads in the second pad group 312 of the functional unit 31 may be determined according to actual conditions and is not limited here.

[0099] In the embodiment of the present disclosure, in each functional unit 31, the first row 3121 and the second row 3122 of the second pad group 312 may both extend in the second direction F2. In this case, the pads and traces in each functional unit 31 may be arranged as follows.

[0100] 26 and 27 , the specific layout structure on the wiring substrate corresponding to FIG26 can be as shown in FIG8 and 9 , where, in each functional unit 31, one of the address input pad D-in and the address output pad D-out is located in the first row 3121 of the second pad group 312, that is, one of the address input pad D-in and the address output pad D-out needs to be set at the end of the second pad group 312 away from the first pad group 311; in this way, the other of the address input pad D-in and the address output pad D-out is located in the second row 3122 of the second pad group 312, and the cascade line L can be located between two adjacent functional units 31 in a column of functional units 31, which can avoid interference between the cascade line L and other routings.

[0101] Optionally, as shown in Figures 26 and 27, in each functional unit 31, at least one ground pad GND can be set adjacent to the functional pad Gn located in the first row 3121 of the second pad group 312; in this way, the ground line Gd can be located on the side of the second pad group 312 away from the multiple first pad groups 311 along the second direction F2 to avoid interference with other wirings; the signal line Vcc can be set through the gap between the first row 3121 and the second row 3122 of the second pad to avoid interference with other wirings.

[0102] Specifically, as shown in Figures 26 and 27, the signal pad Vc in the second pad group 312 can be sandwiched between two pads in the second row 3122, and the signal line Vcc can pass through the gap between the first row 3121 and the second row 3122 of the second pad group 312 from the side of the second pad group 312 away from the first pad group 311, so that the cascade line L and the signal line Vcc do not interfere with each other; or, as shown in Figure 28, the signal pad Vc in the second pad group 312 can also be located at the end of the second row 3122, and the signal line Vcc can pass through the gap between the function pad Gn and the channel pad Ch in the first row 3121 of the second pad group 312 and the gap between the second row 3122 and the first row 3121.

[0103] Optionally, as shown in Figure 29, in each functional unit 31, a signal pad Vc can also be set adjacent to the functional pad Gn located in the first row 3121 of the second pad group 312; the signal line Vcc can be located on the side of the second pad group 312 away from the multiple first pad groups 311 along the second direction F2; the ground line Gd can be located in the gap between the first row 3121 and the second row 3122 of the second pad.

[0104] In the embodiment of the present disclosure, as shown in Figures 16, 18 and 26, the above-mentioned address line Addr can be located on the side of the second type of routing 323 away from the second pad group 312, and the address line Addr can be connected to the address input pad D-in of the first functional unit 31 in a column of functional units 31 through a routing located on one side of the functional unit 31 array.

[0105] In actual applications, in order to better realize the functions of each routing, the minimum line width of the above-mentioned cascade line L, address line Addr and signal line Vcc can be 30μm, and the minimum line width of the ground line Gd can be 150μm. For better layout, the ground line Gd can be set on the side of the second pad group 312 away from the first pad group 311 to ensure the line width of the ground line Gd. The minimum line width requirement of the signal line Vcc or the cascade line L is relatively small, so that the signal line Vcc or the cascade line L can be set through the gap between the first row 3121 and the second row 3122 in the second pad group 312. The signal line Vcc and the cascade line L passing through the gap in the second pad group 312 can include a first main body located outside the area where the second pad group 312 is located and a first crossing portion passing through the second pad group 312. Since the gap width between the two rows of pads in the second pad group 312 is limited, the line width of the first crossing portion can be set to be smaller than the line width of the first main body. For example, as shown in Figure 30, the gap between the two rows of pads in the second pad group 312 can be 50 to 200 μm, then the line width d51 of the first main portion of the signal line Vcc or the cascade line L can be set to be greater than or equal to 30 μm, and the line width d52 of the first crossing portion of the signal line Vcc or the cascade line L can be set to be greater than or equal to 5 μm; if the signal line Vcc and the cascade line L are both located between the two rows of gaps in the second pad group 312, then the line spacing between the signal line Vcc and the cascade line L can be 5 to 20 μm, and the specific size can be determined according to the actual process capability.

[0106] In the embodiment of the present disclosure, in each functional unit 31, multiple first pad groups 311 are divided into two categories, and first pad groups 311 of the same category are arranged adjacent to each other. Specifically, as shown in Figures 31 and 32, each functional unit 31 may include a first pad group 3111 for connecting to a red light-emitting element, a first pad group 3112 for connecting to a green light-emitting element, and a first pad group 3113 for connecting to a blue light-emitting element. The light-emitting elements are generally light-emitting diodes (LEDs). In practical applications, the photoelectric characteristics of green and blue LEDs are basically the same, while the photoelectric characteristics of red LEDs are different from those of blue or green LEDs. Therefore, the power supply voltage required to be loaded on the red LED is different from the power supply voltage required to be loaded on the green and blue LEDs. In this case, the first pad group 3111 can be used as a first-category first pad group, and the first pad group 3112 and the first pad group 3113 can be used as a second-category first pad group. The first pad group 3112 and the first pad group 3113 are arranged adjacent to each other.

[0107] Specifically, as shown in Figures 31 and 32, the second type of routing 323 may include two power lines, each power line is connected to a type of first pad group 311 in a column of functional units 31, one of the power lines is located on the side of the multiple first pad groups 311 away from the second pad group 312, and the other power line is set through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311.

[0108] For example, the second type of traces 323 may include a first power line Ve and a second power line Vf, wherein the first power line Ve is connected to the first sub-pad P1 of the first pad group 3111 in a column of functional units 31, and the second power line Vf is connected to the first pad group 3112 and the first pad group 3113 in a column of functional units 31. As shown in FIG31 , the corresponding specific layout structure on the wiring substrate may be as shown in FIG5 and FIG6 , where the first power line Ve is located on a side of the plurality of first pad groups 311 away from the second pad group 312, and the second power line Vf is arranged through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311; or, as shown in FIG32 , the second power line Vf may be located on a side of the plurality of first pad groups 311 away from the second pad group 312, and the first power line Ve is arranged through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311.

[0109] In practical applications, since the voltage recorded on the first power line Ve needs to be greater than the voltage loaded on the second power line Vf, the minimum width of the first power line Ve can be 100 μm, and the minimum width of the second power line Vf can be 50 μm. The power line passing through the gap between the first sub-pad P1 and the second sub-pad P2 can include a second main portion located outside the area where the first pad group 311 is located and a second crossing portion located between the first sub-pad P1 and the second sub-pad P2. Since the gap width between the first sub-pad P1 and the second sub-pad P2 is limited, the line width of the second crossing portion can be set to be smaller than the line width of the first main portion. For example, as shown in FIG30 , the second power line Vf is set to pass through the gap between the first sub-pad P1 and the second sub-pad P2. The line width d61 of the second main portion of the second power line Vf can be 100 μm, and the line width d62 of the second crossing portion of the second power line Vf can be greater than or equal to 20 μm. The specific dimensions are not limited here and are determined according to actual conditions.

[0110] An embodiment of the present disclosure also provides a light-emitting substrate, including any one of the wiring substrates provided in the above technical solutions, and also including a plurality of light-emitting elements connected one-to-one with the first pad group and a plurality of driving elements connected one-to-one with the second pad group.

[0111] In the light-emitting substrate provided by the embodiment of the present disclosure, only one metal routing layer is provided in the wiring substrate, which can simplify the manufacturing process, greatly simplify the manufacturing process, thereby improving the product yield, and can reduce the use of mask plates, thereby significantly reducing the manufacturing cost.

[0112] Specifically, the manufacturing process of the light-emitting substrate may be:

[0113] Step 1: A buffer layer is formed on the substrate by sputtering to reduce the stress of the metal wiring layer on the substrate, thereby reducing the warping of the substrate. The substrate can be a glass substrate.

[0114] Step 2: A metal trace layer is made on top of the buffer layer through a process of sputtering, cleaning, gluing, baking, exposure, developing, hard baking, etching, and stripping. In addition, this metal trace layer can also be completed through an electroplating process;

[0115] Step 3: Make an insulating layer through the process of sputtering, exposure and development;

[0116] Step 4: Perform nickel-gold treatment on the portion of the metal trace layer exposed in the opening on the insulating layer;

[0117] Step 5: Apply white oil on the insulation layer;

[0118] The sixth step is to carry out processes such as die bonding, that is, to connect the light-emitting element and driving element in the pixel unit to the pads in the metal wiring layer through the opening.

[0119] The light-emitting element may be a sub-millimeter light-emitting diode (micro light-emitting diode) or a micro light-emitting diode (Micro LED), which is not limited here. The driving element may be a driving chip, which is set according to actual conditions and is not limited here.

[0120] The present disclosure also provides a display device, comprising the light-emitting substrate provided in the above technical solution.

[0121] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A wiring substrate, wherein: include: Multiple functional units distributed in an array; Each of the functional units comprises: A plurality of first pad groups, wherein the plurality of first pad groups are arranged at intervals along a first direction, and each of the first pad groups includes a first sub-pad and a second sub-pad arranged at intervals along a second direction; A second pad group, the second pad group being located on one side of the plurality of first pad groups along a second direction, the second pad group comprising a plurality of channel pads and at least two functional pads, the number of pads in the second pad group being an even number and being distributed in a 2*N array; Among them, the multiple channel pads are arranged in sequence along the same direction to form a first row, and are respectively connected one-to-one with the same number of multiple first pad groups; one of the at least two functional pads is located in the first row, and the functional pad is only adjacent to one of the multiple channel pads; the remaining functional pads of the at least two functional pads are arranged in the second row along the same direction.

2. The wiring substrate according to claim 1, wherein It also includes a plurality of routing groups arranged along the second direction, the number of the plurality of routing groups is the same as the number of columns of the functional units, and each group of the routing groups is correspondingly connected to a column of functional units; Each of the routing groups includes a plurality of connecting lines, a first type of routing lines, and a second type of routing lines, wherein the plurality of connecting lines are used to connect the channel pads in a column of functional units to the second sub-pads in a one-to-one correspondence, the first type of routing lines are connected to the functional pads in a column of functional units, and the second type of routing lines are connected to the first sub-pads in a column of functional units; Among them, the first type of routing and the second type of routing are arranged along the second direction and extend along the first direction, at least one routing of the first type of routing passes through the gap between the first row and the second row of the second pad group in a column of functional units, and at least one routing of the second type of routing passes through the gap between the first sub-pad and the second sub-pad in a column of functional units, so that each routing in the multiple routing groups is arranged on the same layer.

3. The wiring substrate according to claim 2, wherein In each of the functional units, the plurality of channel pads are arranged adjacent to the second sub-pads in the plurality of first pad groups along the second direction, and an arrangement order of the channel pads matches an arrangement order of the corresponding first pad groups.

4. The wiring substrate according to claim 3, wherein In each of the functional units, the at least two functional pads include a signal pad, an address input pad, an address output pad, and at least one ground pad; Any one of the signal pad, the address input pad and the address output pad is located in the first row of the second pad group, and at least one of the address input pad and the address output pad is adjacent to only one of the other pads in the same row.

5. The wiring substrate according to claim 4, wherein The first type of routing includes: A signal line connected to all signal pads in a corresponding column of functional units; A ground line connected to the ground pad in a corresponding column of functional units; A plurality of cascade lines, wherein the plurality of cascade lines are used to cascade every two adjacent functional units in a column of functional units, one end of the cascade line being connected to the address output pad of the preceding functional unit and the other end being connected to the address input pad of the succeeding functional unit; An address line is connected to an address input pad of a first functional unit in a corresponding column of functional units. The wiring substrate according to claim 5 , wherein: In each of the functional units, the extension directions of the first row and the second row of the second pad group are both in the first direction.

7. The wiring substrate according to claim 6, wherein In each of the functional units, the signal pads are located in the first row of the second pad group; The signal line is arranged through the gap between the first row and the second row of the second pad group; The ground line is located on a side of the second pad group away from the first pad group.

8. The wiring substrate according to claim 7, wherein In the second pad group, the address input pad and the address output pad are each adjacent to only one of the other pads in the row; The cascade line is located between two adjacent functional units in a column of functional units.

9. The wiring substrate according to claim 7, wherein In the second pad group, one of the address input pad and the address output pad is adjacent to only one of the other pads in the same row; The cascading line is disposed through a gap between a first row and a second row of the second pad group.

10. The wiring substrate according to claim 5, wherein In each of the functional units, the extension directions of the first row and the second row of the second pad group are both in the second direction. The wiring substrate according to claim 10 , wherein: In each of the functional units, one of the address input pad and the address output pad is located in the first row of the second pad group; The cascade line is located between two adjacent functional units in a column of functional units.

12. The wiring substrate according to claim 11, wherein In each of the functional units, the at least one ground pad is adjacent to the functional pads located in the first row of the second pad group; The ground line is located at a side of the second pad group away from the plurality of first pad groups along the second direction; The signal line is disposed through a gap between the first row and the second row of the second pads.

13. The wiring substrate according to claim 11, wherein In each of the functional units, the signal pad is adjacent to the functional pad located in the first row of the second pad group; The signal line is located on a side of the second pad group away from the plurality of first pad groups along the second direction; The grounding line is located in the gap between the first row and the second row of the second pads.

14. The wiring substrate according to any one of claims 5 to 13, wherein: The address line is located on a side of the second type of traces away from the second pad group.

15. The wiring substrate according to any one of claims 4 to 14, wherein: The second pad group includes two ground pads, and the two ground pads are adjacent to each other.

16. The wiring substrate according to any one of claims 3 to 15, wherein: In each of the functional units, the plurality of first pad groups are divided into two categories, and the first pad groups of the same category are arranged adjacent to each other; The second type of routing includes two power lines, each of which is connected to a type of first pad group in a column of functional units, one of which is located on a side of the multiple first pad groups away from the second pad group, and the other power line is set through the gap between the first sub-pad and the second sub-pad in the first pad group.

17. A light-emitting substrate, wherein: The wiring substrate comprises the wiring substrate according to any one of claims 1 to 16, further comprising a plurality of light emitting elements connected to the first pad group in a one-to-one correspondence, and a plurality of driving elements connected to the second pad group in a one-to-one correspondence.

18. A display device, wherein: Comprising the light-emitting substrate as claimed in claim 17.

Images