3DIC iJTAG test interconnection structure

Abstract

The invention provides an iJTAG test interconnection structure of a 3DIC, and relates to the technical field of chip testing, and the structure comprises a plurality of bare chips which are vertically stacked; each bare chip comprises a test access port controller; the test access port controllers are connected in series to form a test control path so as to uniformly coordinate test tasks, and the test tasks comprise test of a plurality of bare chips and test of a single bare chip; the chip bare chip at the bottommost layer is provided with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the bare chip to be tested; tDOMUX modules are arranged in part of the chip bare chips, and the selection ends of the modules are controlled by the test access port controllers of the chip bare chips to which the modules belong. According to the application, the resource consumption of the test port and the chip area can be obviously reduced, the single chip test or multi-chip joint test can be efficiently completed, and the flexibility and efficiency of the whole test are improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and particularly to an iJTAG test interconnection structure for 3DICs. Background Art

[0002] With the slowdown of Moore's Law, the integrated circuit has entered the post-Moore era, and new processes, new materials, and new architectures have emerged continuously, promoting the development of integrated circuits. In this context, the technological development trend of the integrated circuit industry emphasizes multi-path innovation in advanced processing, advanced packaging, and architecture innovation.

[0003] Among them, in terms of advanced packaging, 3DIC (Three-Dimensional Integrated Circuit) technology provides an alternative solution. By vertically stacking chips into a packaging device, optimizations in performance, power consumption, size, etc. are achieved. Through this technology, developers can use multiple different manufacturing processes, technology nodes, and even basic technologies, providing stronger flexibility for chip design, and can reuse existing chips without re-designing, reducing costs and increasing yields; by shortening the interconnect length and increasing the communication density, faster data transfer rates and lower latency are achieved, while reducing power consumption; the development of 3DIC technology is driving the integrated circuit technology into a new era, making electronic devices more compact and intelligent.

[0004] In terms of architecture innovation, the test and debug communication standards inside the integrated circuit chip are continuously optimized, and the iJTAG (Internal Joint Test Group) technology is introduced. This technology is extended based on the traditional JTAG (Joint Test Group) standard, aiming to improve the reliability and production efficiency of the chip. This technology follows the IEEE 1687 standard and includes three main parts: a flexible serial TDR (Test Data Register) link, the iJTAG Network Connection Language (ICL), and the iJTAG Program Description Language (PDL). The interoperability of iJTAG is crucial for chip R & D personnel. It ensures that in circuit board design, "IP developed for verifying or testing chip design" has stronger reusability, effectively reducing the cost of chip design. At the same time, the two-way feedback loop between the chip and the circuit board tools means that the entire tool flow has advanced diagnostic capabilities, thus effectively isolating chip or circuit board design problems. At present, this technology is an efficient and standardized solution widely used in integrated circuit testing and debugging.

[0005] In the prior art, a multiplexing logic between an independent test chip and a biased silicon through-hole is used to complete the path switching function for post-stack chip testing. The test data input terminal TDI on the top chip is used to input test data to the corresponding layer before bonding, and the test data is transmitted from the bottom chip to this chip after bonding.

[0006] Each individual chip can be embedded with various DFT (Design for Testability) logics, which are controlled by its TAP (Test Access Port) controller and related test data registers (TDR). The DFT architecture of the solution requires that all stacked chips be equipped with a JTAG interface (TDI (Test Data In), TDO (Test Data Out), TMS (Test Mode Select), TCK (Test Clock), optional TRST (Test Reset)) as a test access mechanism to build a 3D DFT chain, and a TAP controller to build an IEEE 1687 circuit around it: segment insertion bits and related TDRs.

[0007] In the prior art structure, multiple groups of data transmission ports are introduced for each chip. To complete the functional selection of TDI data interaction and parallel transmission between each chip, it leads to the problem of excessive consumption of port numbers. The prior art interconnection structure needs to add multiple MUXs (multiplexing logic) to complete the selection of data paths. All MUXs can be completed through the additional configuration registers proposed in IEEE 1838, or can be optimized using an automatic chip detection mechanism, but are controlled by a static cascaded TAP serial chain.

[0008] Take Figure 1 the TMSMUX in the DIE1 chip in [reference] as an example. The input signal TMS completes the control of the TAP state machine. The TAP controller also has the control authority over the selection terminal of the TMSMUX. The transmission and control of interface protocol data and enable signals do not have an accurate priority order. For different test requirements (a certain specific chip, several specific chips, or all chips), the selection configuration of the multiplexing logic data path in the test stage has greater limitations and implementation difficulties. Summary of the Invention

[0009] In view of the problems in the prior art, the embodiments of the present application provide an iJTAG test interconnection structure for 3DIC, which can solve the problem of how to build an efficient design for testability circuit and an IEEE 1687 interface protocol network structure in 3DIC packaging, so as to reduce test port consumption, chip area overhead, and test configuration complexity, and at the same time improve the flexibility and efficiency of chip testing.

[0010] In a first aspect, the present application provides an iJTAG test interconnection structure for 3DIC, including: multiple chip dies stacked vertically;

[0011] Each of the chip dice includes a test access port controller; the test access port controllers of the respective chip dice form a test control path in series to uniformly coordinate the test tasks of the multiple chip dice, and the test tasks include testing the multiple chip dice and testing a single chip die;

[0012] The bottommost chip die is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing;

[0013] A TDOMUX module is provided in some of the chip dice, and the selection terminal of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs to control the output path of the test data.

[0014] Further, the test access port controller includes a state machine, and the state machine is used to switch the test mode according to the input control signal.

[0015] Further, when testing the multiple chip dice, the test access port controller of each chip die switches to the INTEST mode through the state machine to control its corresponding embedded instrument.

[0016] Further, when testing a single chip die, the test access port controller in the chip die below the chip die to be tested switches to the BYPASS mode through the state machine to enable the test data to be transmitted to the chip die to be tested.

[0017] Further, the chip die further includes: a segment insertion byte and an embedded instrument;

[0018] The segment insertion byte is used to control the access state of the embedded instrument during the test process.

[0019] Further, the chip die further includes: a test data register;

[0020] The test data register is provided between the segment insertion byte and the embedded instrument and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

[0021] Further, each chip die further includes: a local reset module;

[0022] The local reset module is used to perform a reset operation on its corresponding test data register before the test operation to clear the previously configured data state.

[0023] Furthermore, each of the chip dice further includes: a local enable module;

[0024] The local enable module is configured to output an enable signal during the testing process to control data shifting and updating operations of its corresponding test data register.

[0025] Furthermore, the test access port controller complies with the IEEE 1687 standard.

[0026] Furthermore, an embedded instrument is correspondingly provided for each core functional module in the chip dice.

[0027] The present application provides an iJTAG test interconnection structure for 3DICs, including: a plurality of vertically stacked chip dice; each of the chip dice includes a test access port controller; the test access port controllers of each chip die form a test control path in a series connection manner to uniformly coordinate the test tasks of the plurality of chip dice, and the test tasks include testing the plurality of chip dice and testing a single chip die; the bottommost chip die is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing; a TDOMUX module is provided in some of the chip dice, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs to control the output path of the test data. The present application realizes flexible access and test configuration of the embedded instruments in multiple chips while significantly reducing the consumption of test ports and chip area resources, and efficiently completes the individual test or multi-chip joint test of the target chip, thereby improving the flexibility and efficiency of the overall test.

[0028] Among them, the chip integration density is improved by vertical stacking, the interconnection path is shortened, power consumption and latency are reduced, while the computing performance and compactness of the overall system are enhanced; each chip die includes a test access port controller, segment insertion bytes, test data registers, and embedded instruments, which can achieve precise testing and debugging of each chip functional module. The flexibility and coverage of testing are improved through the embedded instruments, and the programmable structure of the segment insertion bytes and test data registers enhances the configurability of the network and module reusability; the bottom chip die is configured with a test data input port and a test data output port, which can simplify the connection between external test equipment and the 3DIC chip system, reduce the number of test ports, and lower the packaging complexity and manufacturing cost; the test access port controllers of each chip die form a test control path in series, which can avoid the area consumption and configuration complexity introduced by multiple input multiplexing logic (MUX) in the traditional parallel test access port (TAP) structure, improve the unity and controllability of test path configuration, and effectively support multi-chip joint testing or selective chip testing; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing, which can improve the coherence and transmission efficiency of the test data stream, realize cross-chip test chain configuration and operation, and support flexible switching of the test range of the target chip; a TDOMUX module is set in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs, which can achieve isolation or bypass of the test data of a specific chip, and effectively improve the flexibility of test data path selection and the accuracy of test operations. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 is a schematic structural diagram of a chip die in the prior art;

[0031] Figure 2 is a schematic structural diagram of the iJTAG test interconnection structure of a 3DIC provided by an embodiment of the present application;

[0032] Figure 3 is a schematic structural diagram of the iJTAG test interconnection structure of a 3DIC provided by an embodiment of the present application. Detailed Embodiments

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer and more understandable, the following further elaborates on the embodiments of this application with reference to the accompanying drawings. Herein, the illustrative embodiments of this application and their descriptions are used to explain this application, but do not limit this application. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be arbitrarily combined with each other.

[0034] Three-dimensional integrated Circuit (3DIC) is an integrated circuit technology that improves performance, reduces power consumption, and increases integration by vertically stacking chip dies and using advanced packaging technologies such as Through Silicon Via (TSV). Among them, TSV is an integrated circuit packaging technology that realizes vertical electrical connections inside or between chips by drilling holes in silicon chips and filling them with conductive materials, thereby improving integration, reducing power consumption, and latency. The Internal Joint Test Action Group (iJTAG) is an integrated circuit testing technology that follows the IEEE 1687 standard and allows for flexible testing and debugging inside the chip. It realizes flexible configuration of the test network by inserting single-bit Segment Insertion Bits (SIBs) into the JTAG link to simplify the chip verification and testing process. SIB is the core component in iJTAG technology, allowing for the realization of any hierarchical structure in the iJTAG network by inserting single-bit Test Data Registers (TDRs), thereby achieving flexible configuration of the iJTAG network. The Test Access Port Controller (TAPController) is the core component in the JTAG interface. It is a finite state machine responsible for controlling the sequence of JTAG test operations, including state transitions and data transmissions.

[0035] Figure 2 is a schematic structural diagram of the iJTAG test interconnection structure of a 3DIC provided by an embodiment of this application. As Figure 2 shown, the iJTAG test interconnection structure of the 3DIC provided by this application includes: a plurality of vertically stacked chip dies;

[0036] Each of the chip dies includes a Test Access Port Controller (TAP Controller); the Test Access Port Controllers of each chip die form a test control path in series to uniformly coordinate the test tasks of the plurality of chip dies. The test tasks include testing the plurality of chip dies and testing a single chip die;

[0037] The bottom - most chip die configures a Test Data Input port (TDI) and a Test Data Output port (TDO); the Test Data Input port receives test data and transmits the test data to the Test Access Port Controller of the chip die under test for processing;

[0038] A TDOMUX module is provided in some of the chip dies, and the selection terminal of the TDOMUX module is controlled by the Test Access Port Controller of the chip die to which it belongs to control the output path of the test data.

[0039] Specifically, Figure 2 The thick black solid lines in represent the iJTAG interconnect network paths, while the dashed lines represent the control relationships between different modules, indicating only functional associations rather than actual circuit connections. For the test requirements of different chips, the configuration of the 1687 interface protocol IP is completed through a cascaded multi - TAP controller.

[0040] To simplify the wiring complexity of the external test interface, the Test Data Input port (TDI) and the Test Data Output port (TDO) are configured on the bottom - most chip die as the unified entry and exit of the test data for the entire system. The test data is input from the TDI port, and the TAP controller selectively performs operations such as enabling, configuring, or bypassing embedded instruments according to the control instructions or status configuration information in the data, thereby realizing full - chip testing or single - chip directed testing.

[0041] To support flexible data output path configuration, a TDOMUX module is provided in the chips other than the top - most chip die ( Figure 2 represented by a trapezoidal symbol in). As the test data output multiplexing logic, the selection terminal of this module is controlled by the TAP controller of the chip to which it belongs, and is used to determine whether the current test data is output from this chip or continues to be passed upward to the upper - layer chip. Through this structural design, the dynamic selection and response output of the test data path can be realized without interrupting the test link.

[0042] Through the above structure, multiple chip dies achieve unified management of test control through a cascaded test access path. It can not only perform joint testing on all chip dies, but also flexibly select specific chip dies for independent testing, with good scalability, reusability, and resource efficiency.

[0043] In one embodiment, Figure 2 The SIB, TDR, and other modules (1687 IP) conforming to the IEEE 1687 interface protocol shown in mainly represent their functional roles. In the specific implementation, a suitable 1687 IP structure will be selected for expansion according to the number of integrated functional modules.

[0044] In one embodiment, the test access port controller includes a state machine for switching test modes according to input control signals.

[0045] Specifically, to support the effective management and status scheduling of the iJTAG test link between multiple chip dies, a state machine is provided in the test access port controller of each chip die. The state machine responds to the control field in the TMS signal line or test data and completes the switching and management of test modes according to the IEEE 1687 standard. The state machine supports modes such as INTEST mode or BYPASS mode, and can achieve the purpose of full chip die testing or individual testing of the target chip die.

[0046] In one embodiment, when testing the multiple chip dies, the test access port controller of each chip die switches to the INTEST mode through the state machine to control its corresponding embedded instrument.

[0047] Specifically, in the scenario of joint testing of multiple chip dies, the state machines of the test access port controllers of each chip die will all switch to the INTEST mode. This mode allows test data to act on the embedded instruments in this chip. When the TAP is in the INTEST state, the segment insertion byte and test data register it controls will be activated to perform operations such as writing test parameters and data sampling on the selected embedded instrument, thereby achieving a complete coverage test of the entire chip system.

[0048] In one embodiment, when testing a single chip die, the test access port controller in the chip die below the chip die to be tested switches to the BYPASS mode through the state machine to enable the test data to be transmitted to the chip die to be tested.

[0049] Specifically, when performing the directed test of the target chip die, to avoid unnecessary intermediate chip test operations and improve the link efficiency, the state machine of the TAP controller of the chip below the target chip is controlled to switch to the BYPASS mode. In this mode, the test data only passes through a 1-bit bypass register in the chip, thereby bypassing the TDR structure of this chip and directly transmitting to the TDI interface of the upper-level chip. This method can effectively reduce the amount of shifted data, improve the link response speed, and isolate the influence of the test logic of non-target chips on the link.

[0050] In one embodiment, the chip die further includes: a segment insertion byte and (SIB) an embedded instrument;

[0051] The segment insertion byte is used to control the access state of the embedded instrument during the test process.

[0052] Specifically, to enhance the control and selection ability of the embedded instrument, the segment insertion byte (SIB) structure selectively enables the target embedded instrument as needed during the test process to control the access state of the embedded instrument. Through the control logic of the SIB, the test chain can flexibly determine whether to activate a certain embedded instrument, thereby forming a tree-like test network and improving the configurability and resource utilization rate of the overall test structure.

[0053] In one embodiment, the chip die further includes: a test data register (TDR);

[0054] The test data register is arranged between the segment insertion byte and the embedded instrument and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

[0055] Specifically, the test data register (TDR) used in conjunction with the segment insertion byte corresponds to the embedded instrument one by one, and can complete the configuration of the test parameters and the transmission of data of the corresponding embedded instrument when the corresponding embedded instrument is enabled. The TDR structure supports the serial shift-in and parallel loading of multiple-bit data, and can exchange signals with the target embedded instrument to perform tasks such as writing initialization parameters, collecting running status, or outputting fault information. It is a key component for realizing highly controllable test interaction.

[0056] In one embodiment, the configuration methods of SIB and TDR for different embedded instruments are consistent, with good generality and consistency.

[0057] In one embodiment, each chip die further includes: a local reset module (LR);

[0058] The local reset module is used to perform a reset operation on its corresponding test data register before the test operation to clear the previously configured data state.

[0059] In one embodiment, each chip die further includes: a local enable module (NIB);

[0060] The local enable module is used to output an enable signal during the test process to control its corresponding test data register to perform data shift and update operations.

[0061] Specifically, as Figure 2As shown, the local reset module LRA is responsible for locally resetting the test data configured in the TDR A; the local enable module NIB A is used to control the local enable signals of the TDR B and TDR C, and cooperate with the global enable signal output by the TAP 0 controller to jointly complete operations such as shifting, updating, and capturing of the relevant TDRs.

[0062] In one embodiment, the test access port controller complies with the IEEE 1687 standard.

[0063] In one embodiment, an embedded instrument is correspondingly provided for each core functional module in the chip die.

[0064] Specifically, the embedded instrument is used to monitor the operating state, perform structural testing, or conduct functional verification on the functional modules (such as processing units, memory interfaces, or other key modules) in the chip. At least one embedded instrument is provided in each chip die, and an embedded instrument is correspondingly provided for each core functional module (such as NPU, DDR, etc.) in the chip die to achieve module-level testing and debugging.

[0065] In one embodiment, as Figure 2 shown, when executing a complete multi-chip test process, the test data is input from the TDI terminal of Die0, and the TAP 0 controller operates in the INTEST mode. In this mode, by enabling the segment insertion byte SIB A, the embedded instrument A included in this test is selected, and the test data register TDR A is used to configure the test parameters of the embedded instrument A.

[0066] After the configuration and testing of the embedded instrument are completed, the test data passes through NIB A and then is output to the TDIS interface of Die0 and the first input port of the test data output multiplexing logic TDOMUX through the TAP 0 controller. Since the complete multi-chip test process is being executed at this time, a certain control signal in the TDI test data stream needs to control the selection terminal of TDOMUX to be set to 0 through the TAP 0 controller to ensure that the data does not come from the TAP 0 controller and to achieve the connection of the multi-chip test link. The TAP 1 controller receives the test data from Die0 through the TDI port of Die1. Similar to Die0, after the internal 1687 IP completes the configuration of the target embedded instrument, the data continues to be transmitted to the subsequent chip die. During this process, the selection terminals of TDOMUX of all chips are set to 0 by their corresponding TAP controllers, so as to ensure the complete output of the final test data at the TDO port of Die0 and achieve the traversal test of all chips.

[0067] In one embodiment, as Figure 3 shown, compared with the complete multi-chip joint test, if Die1 needs to be tested separately, in addition to setting the selection terminal of TDOMUX of Die1, it is also necessary to enable the BYPASS mode for its previous chip Die0. This process completes the mode switch by controlling the state machine of the TAP controller through the TMS port: when the TAP controller works in the BYPASS mode, only a 1-bit bypass register will be inserted between TDI and TDO, so that the shift operation is only completed through this register instead of passing through the entire boundary scan register (BSR). This method effectively isolates Die0, thereby improving the test efficiency of Die1.

[0068] It should be noted that the bypass register is implemented inside the TAP controller. Under this test process, after the TDI test data enters Die0, it is directly passed to the TDI port of Die1 only through the bypass register. After Die1 completes the configuration and testing operations of the embedded instrument, its TAP controller sets the selection terminal of TDOMUX to 1, so that the test response data is directly output to the TDO port of the system.

[0069] The BYPASS operation of the previous chip (such as Die0) is implemented through its TAP controller, and the data bypass of the subsequent chip is completed through the control of TDOMUX of the chip under test (such as Die1). This test structure supports flexible configuration and can efficiently achieve the targeted test operation of any target chip.

[0070] For the 3DIC packaging technology, this application adopts a cascaded multi-TAP controller structure to configure the IEEE 1687 interface protocol network composed of multiple chips. According to the analysis of the design for testability process, compared with the complete scan test (load / unload) time, the time occupied by TDI data configuration in the serial multi-TAP structure is extremely small. Therefore, in this application, the TDI and TDO ports are only set on the bottom-layer chip, and the unified configuration of TDI data is completed through serial input, thus effectively reducing the use of port resources.

[0071] In addition, this application only introduces the TDOMUX module, replacing the multiple interface protocol MUXs (such as test data input multiplexing logic TDIMUX, test clock signal multiplexing logic TCKMUX, test reset signal multiplexing logic TRSTnMUX, and test mode selection signal multiplexing logic TMSMUX) configured for each chip in the traditional structure. With the state machine control of the TAP controller inside each chip, this application significantly reduces the area overhead and configuration complexity while ensuring test flexibility. During the test process, the input test data of any chip can directly act on its TAP controller, and the state machine of the multi-TAP controller is used to select test operations or bypass for different logic modules, so as to achieve individual testing of the target chip or joint testing of multiple chips.

[0072] This application provides an iJTAG test interconnection structure for 3DIC, including: multiple chip dies stacked vertically; each of the chip dies includes a test access port controller; the test access port controllers of each chip die form a test control path in series to uniformly coordinate the test tasks of the multiple chip dies, and the test tasks include testing the multiple chip dies and testing a single chip die; the bottom-layer chip die is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing; a TDOMUX module is set in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs to control the output path of the test data. This application realizes flexible access and test configuration of embedded instruments in multiple chips while significantly reducing the consumption of test ports and chip area resources, efficiently completing individual testing of the target chip or joint testing of multiple chips, thereby improving the flexibility and efficiency of the overall test.

[0073] Among them, the chip integration density is improved by vertical stacking, the interconnection path is shortened, the power consumption and latency are reduced, and at the same time, the computing performance and compactness of the overall system are enhanced; each chip die includes a test access port controller, segment insertion bytes, test data registers, and embedded instrumentation, which can achieve precise testing and debugging of each chip functional module. The flexibility and coverage of testing are improved through the embedded instrumentation, and the programmable structures of the segment insertion bytes and test data registers enhance the configurability of the network and module reusability; the bottom chip die is configured with a test data input port and a test data output port, which can simplify the connection between the external test equipment and the 3DIC chip system, reduce the number of test ports, and lower the packaging complexity and manufacturing cost; the test access port controllers of each chip die form a test control path in series, which can avoid the area consumption and configuration complexity introduced by multiple input multiplexing logic (MUX) in the traditional parallel test access port (TAP) structure, improve the unity and controllability of test path configuration, and effectively support multi-chip joint testing or selective chip testing; the test data input port receives the test data and transmits the test data to the test access port controller of the chip die to be tested for processing, which can improve the coherence and transmission efficiency of the test data stream, realize the test chain configuration and operation across chips, and support flexible switching of the test range of the target chip; a TDOMUX module is provided in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs, which can achieve isolation or bypass of the test data of a specific chip, and effectively enhance the flexibility of test data path selection and the accuracy of test operations.

[0074] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0075] Descriptions with reference to terms such as "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. The order of steps involved in each embodiment is used to schematically illustrate the implementation of the present application, and the order of steps is not limited and can be adjusted appropriately as needed.

[0076] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood through specific circumstances.

[0077] The above specific embodiments further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An iJTAG test interconnect structure of 3DIC, characterized in that: include: Multiple chip dies stacked vertically; Each of the chip dies includes a test access port controller; the test access port controllers of each chip die form a test control path in a serial manner to coordinate the test tasks of the multiple chip dies in a unified manner, and the test tasks include testing the multiple chip dies and testing a single chip die; The bottom-level chip die is configured with a test data input port and a test data output port; The test data input port receives the test data and transmits the test data to the test access port controller of the chip die to be tested for processing; A TDOMUX module is provided in some of the chip dies, and a selection end of the TDOMUX module is controlled by a test access port controller of the chip die to which it belongs, so as to control an output path of test data.

2. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The test access port controller includes a state machine, and the state machine is used to switch the test mode according to an input control signal.

3. The iJTAG test interconnect structure of 3DIC according to claim 2, characterized in that: When the plurality of chip dies are tested, the test access port controller of each chip die is switched to the INTEST mode through the state machine to control the corresponding embedded instrument.

4. The iJTAG test interconnect structure of 3DIC according to claim 2, characterized in that: When testing a single chip die, the test access port controller in the chip die below the chip die to be tested is switched to the BYPASS mode through the state machine so that the test data is transferred to the chip die to be tested.

5. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The chip die further includes: segment insertion bytes and embedded instruments; The segment insertion byte is used to control the access status of the embedded instrument during the test process.

6. The iJTAG test interconnect structure of 3DIC according to claim 5, characterized in that: The chip die further includes: a test data register; The test data register is arranged between the segment insertion byte and the embedded instrument, and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

7. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The chip die further comprises: a local reset module; The local reset module is used to perform a reset operation on the corresponding test data register before the test operation to clear the previously configured data state.

8. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: Each of the chip dies further comprises: a local enabling module; The local enable module is used to output an enable signal during the test process to control the corresponding test data register to perform data shifting and updating operations.

9. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The test access port controller complies with the IEEE 1687 standard.

10. The iJTAG test interconnect structure of 3DIC according to claim 6, characterized in that: Each core functional module in the chip die is correspondingly provided with an embedded instrument.

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