Reliability test system of silicon light emission chip

Abstract

The invention relates to a reliability test system for a silicon light emission chip, and the system comprises a damp-heat test box which is used for adjusting a test environment; the chip mounting plate is placed in the damp heat test box, the mounting surface of the chip mounting plate is provided with a welding spot area, a plurality of chip mounting areas and a plurality of bonding pad areas, each chip mounting area in the plurality of chip mounting areas is used for mounting a silicon light emitting chip needing to be tested, and the bonding pad areas are used for bonding the silicon light emitting chip needing to be tested. Each of the plurality of bonding pad areas is arranged around the corresponding chip mounting area, and each welding spot in the welding spot area is electrically connected with the same pin bonding pad of each silicon light emitting chip to be tested in the plurality of silicon light emitting chips to be tested; the main control board is used for adjusting the working conditions of a plurality of silicon light emitting chips needing to be tested at the same time and carrying out reliability testing under various conditions, so that compatibility and testing reliability can be improved, elements of the main control board are protected, and the main control board is prevented from being directly located in the thermal control box.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon optical emission chip testing, and in particular to a reliability testing system for silicon optical emission chips. Background Art

[0002] Silicon photonics technology uses silicon and silicon-based substrate materials (such as SiGe / Si, SOI, etc.) as optical media, and manufactures corresponding photonic devices and optoelectronic devices (including silicon-based light-emitting devices, modulators, detectors, optical waveguide devices, etc.) through integrated circuit processes. These devices are used for the excitation, processing, and manipulation of photons to achieve their applications in multiple fields such as optical communication, optical interconnection, and optical computing.

[0003] Silicon-based photonic chips are manufactured based on silicon photonics technology. Their core advantages lie in low cost, high integration, and high compatibility with existing semiconductor processes, and are widely used in fields such as optical communication, optical computing, and sensing. However, the testing of silicon photonic devices faces challenges of high precision and high complexity, including coupling loss control, thermal stability, wavelength sensitivity, etc.

[0004] Currently, the existing testing of silicon-based photonic chips is to test silicon optical chips by designing a general-purpose testing device for gyro performance, such as the silicon optical chip and the general-purpose testing device and method for gyro performance described in the publication number CN119104085A. A testing device is formed by combining a gyro measurement and control module, an external light source module, an external phase modulator, an optical fiber loop, a light source module, and a silicon optical chip for testing.

[0005] However, the device of this solution is complex, increasing the cost and weight. The device contains other IC chips and cannot conduct a comprehensive reliability test on the silicon optical chip within a wide temperature range, with poor compatibility. Summary of the Invention

[0006] (I) Technical Problems to be Solved In view of the above-mentioned disadvantages and deficiencies of the prior art, the present invention provides a reliability testing system for silicon optical emission chips, which solves the technical problem of poor compatibility existing in the prior art.

[0007] (II) Technical Solutions In order to achieve the above object, the main technical solutions adopted by the present invention include: An embodiment of the present invention provides a reliability test system for a silicon optical emission chip, including: a damp heat test chamber for adjusting the test environment; a chip mounting board that can be placed inside the damp heat test chamber, and the mounting surface of the chip mounting board is provided with a solder joint area, a plurality of chip mounting areas, and a plurality of pad areas. Each chip mounting area among the plurality of chip mounting areas is used for mounting the silicon optical emission chips to be tested, and each pad area among the plurality of pad areas is arranged around the corresponding chip mounting area. Moreover, each solder joint in the solder joint area is electrically connected to the same pin pad of each silicon optical emission chip to be tested among the plurality of silicon optical emission chips to be tested; a main control board that can be arranged outside the damp heat test chamber and is electrically connected to the chip mounting board, and the main control board is used to adjust the working conditions of the plurality of silicon optical emission chips to be tested simultaneously and perform reliability tests under various working conditions.

[0008] In a possible embodiment, the solder joint area includes at least one of a first solder joint for testing the reverse bias voltage of the silicon optical emission chip to be tested, a second solder joint for testing the supply voltage of the silicon optical emission chip to be tested, a third solder joint for testing the DC performance of the RF port of the silicon optical emission chip to be tested, and a fourth solder joint for testing the current of the monitoring photodiode of the silicon optical emission chip to be tested.

[0009] In a possible embodiment, the mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of fiber optic arrays mounted on the chip mounting board, and each silicon optical emission chip to be tested corresponds to one laser and one fiber optic array; the reliability test includes optoelectronic performance tests. Among them, the main control board is specifically used for: when powering all channels of multiple silicon optical emission chips to be tested, setting the MPD reverse bias voltage of the monitoring photodiode of the silicon optical emission chip to be tested, and coupling the optical power of the laser pulse emitted by its corresponding laser into each MZM channel of the silicon optical emission chip to be tested through the fiber array corresponding to the monitoring photodiode, recording the laser input optical power of the laser corresponding to the monitoring photodiode, the laser output optical power of the laser corresponding to the monitoring photodiode, and the two-way photocurrents of the monitoring photodiode, and calculating and recording the MZM modulator insertion loss of the corresponding channel of the silicon optical emission chip to be tested corresponding to the monitoring photodiode; turning off the laser input optical power and recording the two-way dark currents of the monitoring photodiode; setting the MZM modulator reverse bias voltage of the monitoring photodiode and recording the MZM modulator leakage current of the corresponding channel of the silicon optical emission chip to be tested corresponding to the monitoring photodiode; adjusting its constant current output, testing and recording the internal resistance of the chip of the silicon optical emission chip to be tested corresponding to the monitoring photodiode; when connecting the MZM modulation port of the silicon optical emission chip to be tested corresponding to the monitoring photodiode through a coaxial cable, setting the MZM modulator reverse bias voltage, adjusting the constant current output until the laser output optical power reaches the highest point, then adjusting back to the linear region of the MZM modulator, and performing a bandwidth test with a corresponding vector network analyzer and recording the bandwidth test data; gradually increasing the voltage of the RF port of the MZM modulator to the voltage range related to the reverse bias voltage, and recording the minimum optical power and the maximum optical power at the power output of the laser corresponding to the monitoring photodiode, and calculating the optical power difference between the maximum optical power and the minimum optical power as the optical modulation amplitude; after power-on for a preset time, repeating the above steps to obtain new recorded data after repeated execution, and comparing the new recorded data with the recorded data obtained before repeated execution to obtain the test result of the optoelectronic performance test.

[0010] In a possible embodiment, the reliability test further includes a quality test. Passing the quality test means that the modulator leakage current of the silicon optical emission chip to be tested does not change after changing the test environment, the terminal resistance of the silicon optical emission chip to be tested does not change after changing the test environment, and the dark current of the monitoring photodiode does not change after changing the test environment.

[0011] In a possible embodiment, the main control board includes a main control device and a plurality of slave control devices communicatively connected to the main control device, and each of the plurality of slave control devices is electrically connected through a plurality of multi-channel operational amplifiers and the connection socket of the main control board, and the plurality of slave control devices are used for sampling the monitoring photodiodes of the plurality of silicon optical emission chips to be tested on the chip mounting board and for current regulation of the plurality of silicon optical emission chips to be tested on the chip mounting board.

[0012] In a possible embodiment, the main control board further includes a plurality of second Buck step-down chips, and each slave control device is also electrically connected to the connection socket of the main control board through a second Buck step-down chip. Moreover, each Buck step-down chip among the plurality of second Buck step-down chips is electrically connected to a pad on the main control board between the connection socket of the main control board. The pad on the main control board is used to measure the power supply voltage required by the main control board to supply the chip mounting board and the reverse bias voltage required by the main control board to supply the chip mounting board.

[0013] In a possible embodiment, the main control board further includes a power interface, a first Buck step-down chip, and a low-dropout linear regulator that are electrically connected in sequence. The low-dropout linear regulator is electrically connected to the main control device and each slave control device respectively.

[0014] In a possible embodiment, the main control board further includes a package socket and a plurality of JTAG pin connection interfaces. The package socket is used to burn the firmware for the main control device, and the plurality of JTAG pin connection interfaces are used to burn the firmware for the plurality of slave control devices.

[0015] (III) Beneficial effects The beneficial effects of the present invention are as follows: The embodiment of the present application provides a reliability test system for a silicon optical emission chip. When in use, the silicon optical emission chip to be tested is mounted on a chip mounting board, and the chip mounting board is placed inside a damp heat test chamber with adjustable temperature and humidity. At the same time, the main control board is placed in a conventional environment. And through the control of the main control board by the host computer software, the long-term reliability and performance of the silicon optical emission chip on the chip mounting board under various environments and working conditions can be verified for reliability. Compared with the traditional testing of silicon optical emission chips on a wafer testing system, it can not only test and verify the long-term reliability and performance of silicon optical emission chips under various environments and operating pressure conditions, but also protect the stability of the remaining electronic chips on the main control board. At the same time, the structural volume of the chip mounting board and the main control board is small and easy to carry. The main control board can be adjusted in real time through the host computer, and data can be read and analyzed through the host computer. It can also test different types of silicon optical emission chips, and has good compatibility.

[0016] To make the above objects, features, and advantages to be achieved by the embodiments of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. Description of the drawings

[0017] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0018] Figure 1 Shows a schematic diagram of a reliability test system for a silicon optical emission chip provided by an embodiment of the present application; Figure 2 Shows a schematic diagram of the structure of a chip mounting board provided by an embodiment of the present application; Figure 3 Shows a schematic diagram of the structure of a main control board provided by an embodiment of the present application; Figure 4 Shows a schematic diagram of the power supply structure of a main control board provided by an embodiment of the present application; Figure 5 Shows a schematic diagram of the communication of a master-slave control device provided by an embodiment of the present application; Figure 6 Shows a schematic diagram of a collaborative working principle provided by an embodiment of the present application; Figure 7 Shows a schematic diagram of controlling and adjusting the reverse bias voltage and supply voltage of a control board provided by an embodiment of the present application; Figure 8 Shows a partial structure schematic diagram of the mounting surface of a chip mounting board provided by an embodiment of the present application; Figure 9 Shows a flowchart of a quality test method provided by an embodiment of the present application.

[0019]

Description of the reference numerals

[0020] For better explaining the present invention and facilitating understanding, the present invention will be described in detail below with reference to the accompanying drawings through specific implementation manners.

[0021] Currently, in addition to the method of testing a silicon-based photonic chip by designing a general test device for gyro performance, the existing testing methods for silicon-based photonic chips also include the following two testing methods: One of the testing methods is to move the probe station on the coupling table to make the probe card contact the chip pin pads. It is applicable to the testing of photodiodes (PDs) of multi-channel silicon photonic chips. For example, the silicon photonic chip testing method and device disclosed in the publication number CN119087173A place the silicon photonic emission chip to be tested in the middle of the device coupling table and perform testing through the probe cards on both sides of the coupling table in full contact with the chip. However, this solution has a large volume. Using the probes on the coupling table for contact increases the probe card in the structure, increasing the cost. Moreover, when moving the coupling table, there are high requirements for the contact points between the probe card and the chip pin pads (Pads), and only one silicon photonic chip can be tested at a time, resulting in low efficiency; Another testing method is to perform testing by designing a test device such as an intermediate stage for carrying the chip to be tested. For example, the silicon photonic chip testing device and its testing method disclosed in the publication number CN117191358A complete the testing through an intermediate stage assembly, as well as left and right adjustment modules, an upper vision component, a probe card adjustment component, etc., through a method combining vision and pressure detection. However, this solution has a large structure and complex operation. The stage also includes a water cooling device and a nitrogen purging device, and it can only test the coupling of silicon photonic chips and cannot perform reliability testing on the electrical performance parameters of silicon photonic chips.

[0022] Based on this, the embodiments of the present application provide a reliability test system for a silicon optical emission chip. When in use, the silicon optical emission chip is mounted on a chip mounting board, the chip mounting board is placed inside a damp heat test chamber capable of adjusting temperature, humidity, etc., and the main control board is placed in a conventional environment (i.e., outside the damp heat test chamber). Moreover, it can be connected to the main control board through a connector and a connecting wire on the chip mounting board, and the main control board is controlled by upper computer software, so as to verify the long-term reliability and performance of the silicon optical emission chip on the chip mounting board under various environments and working conditions. For example, temperature cycling, damp heat, low temperature and high temperature storage, and high temperature working tests, including equipment aging and powered damp heat. Also, by comparing the electro-optical performance before and after each stress test, against the pass / fail criteria. Compared with the traditional testing of silicon optical emission chips on a wafer testing system, it can not only test and verify the long-term reliability and performance of the silicon optical emission chip under various environments and operating stress conditions, but also protect the stability of the remaining electrical chips on the main control board. At the same time, due to the small structural volume and easy portability of the chip mounting board and the main control board, the stress conditions can be adjusted in real time through the upper computer, and data can be read and analyzed through the upper computer, and different types of silicon optical emission chips can also be tested, with good compatibility.

[0023] To better understand the above technical solutions, the exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and the scope of the present invention can be fully conveyed to those skilled in the art.

[0024] Please refer to Figure 1 , Figure 1 which shows a schematic diagram of a reliability test system for a silicon optical emission chip provided by the embodiments of the present application. As Figure 1 shown, the reliability test system includes: A damp heat test chamber 100, which is used to adjust the test environment, that is, it can adjust temperature, humidity, etc.; A chip mounting board 200, which can be placed inside the damp heat test chamber 100. The mounting surface of the chip mounting board 200 is provided with a solder joint area, a plurality of chip mounting areas, and a plurality of pad areas. Each chip mounting area in the plurality of chip mounting areas is used to mount a silicon optical emission chip to be tested, and each pad area in the plurality of pad areas is arranged around the corresponding chip mounting area. Moreover, each solder joint in the solder joint area is electrically connected to the same pin pad of each silicon optical emission chip to be tested among the plurality of silicon optical emission chips to be tested. Among them, each chip mounting area corresponds to one pad area; The main control board 300 can be arranged outside the damp heat test chamber 100, and the main control board 300 is electrically connected to the chip mounting board 200. The main control board is used to adjust the working conditions of multiple silicon optical emission chips to be tested simultaneously and perform reliability tests under multiple working conditions (or multiple situations).

[0025] It should be understood that the specific damp heat test chamber can be set according to actual requirements, and the embodiments of the present application are not limited thereto.

[0026] It should also be understood that the specific structure of the chip mounting board 200 can also be set according to actual requirements, and the embodiments of the present application are not limited thereto.

[0027] Specifically, please refer to Figure 2 , Figure 2 which shows a schematic structural diagram of a chip mounting board 200 provided by an embodiment of the present application. As Figure 2 shown, in order to avoid the failure of the electrical chip under the high-temperature and high-humidity pressure test, no other electrical chips are mounted on the chip mounting board 200. Only eight silicon optical emission chips 210 to be tested are mounted on the mounting surface of the chip mounting board 200, and a pad area 220 is arranged around each silicon optical emission chip 210 to be tested. A plurality of pads in the pad area 220 are convenient for wire bonding with the DC pin pads DC Pad of the silicon optical emission chip 210, so as to perform wire routing on the PCB board of the chip mounting board 200, including the phase modulation current pin pads of the silicon optical emission chip 210. And, a solder joint area 230 is further arranged on the mounting surface of the chip mounting board 200. The solder joint area 230 includes at least one of a first solder joint (or called reverse bias voltage Pad) for testing the reverse bias voltage (which may include MPD reverse bias voltage and MZM modulator reverse bias voltage) of the silicon optical emission chip 210 to be tested, a second solder joint (or called supply voltage Pad) for testing the supply voltage of the silicon optical emission chip 210 to be tested, a third solder joint (or called high-speed RF line solder joint RF Pad) for testing the DC performance of the high-speed RF port of the silicon optical emission chip 210 to be tested, and a fourth solder joint (or called monitoring photodiode solder joint MPD Pad) for testing the current of the monitoring photodiode of the silicon optical emission chip 210 to be tested. And, the chip mounting board 200 can also be provided with a connecting line (not shown) and a connector 240 (for example, a right-angle connector) on the chip mounting board that can withstand high temperature and high humidity for connection and interaction with its main control board. Among them, the high-speed RF port can also be called the RF port.

[0028] Moreover, the RF Pad of each silicon optical emission chip 210 can be wire-bonded to pass through the RF Pad solder joint, and the DC performance of the RF port can be tested with a probe; the MPD Pad can either use a probe to contact the solder joint to measure the actual current value, or be connected to the main control board through a trace and the connector 240 on the chip mounting board, and the sampling data can be read by the electrical chip on the main control board; the reverse bias voltage Pad and the power supply voltage Pad can either directly supply the required voltage through an external source meter, or use a multimeter to test the real-time voltage magnitude to determine whether the voltage regulation on the main control board is correctly applied to the reverse bias voltage and the power supply voltage on the chip mounting board through the connector 240 on the chip mounting board; through the voltage regulation on the main control board, the working conditions of the silicon optical emission chips 210 on the mounting board can be controlled at different voltages, so as to better perform corresponding reliability tests on the silicon optical emission chips 210.

[0029] It should be noted here that although Figure 2 it is described by taking eight silicon optical emission chips to be tested, their eight pad areas and three solder joints are provided in the solder joint area as an example, those skilled in the art should understand that the chip mounting board can also be provided with more or fewer pad areas, and the solder joint area can include more or fewer solder joints, so as to be able to perform reliability tests on more or fewer silicon optical emission chips simultaneously.

[0030] It should also be understood that the specific structure of the main control board can also be set according to actual needs, and the embodiments of the present application are not limited thereto.

[0031] Specifically, in order to control, regulate the voltage and sample data of the chip mounting board, the main control board 300 includes: a power interface 310 (for example, a square power socket), a toggle switch 320, a standard USB interface 330, a JTAG (Joint Test Action Group) pin connection interface 340, a package socket 350 (for example, a dual-row straight-through package socket), a first Buck step-down chip 360, a second Buck step-down chip 370, a low-dropout linear regulator 380, a connector 390 on the main control board, etc. For specific details, reference can be made to Figure 3 the relevant content.

[0032] It should be understood that Figure 3Only some devices of the main control board 300 are labeled. For example, the main control board may further include devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Transient Voltage Suppressors (TVSs), control devices (such as single-chip microcomputer MCUs), multi-channel operational amplifiers (OAs), and power protectors. However, these devices are not labeled in Figure 3 this document.

[0033] Furthermore, as Figure 4 shown, the power interface of the main control board is powered on by connecting to a source meter SMU, and the power supply is protected against undervoltage, overvoltage, and reverse power by a toggle switch, a power protector, and a Metal Oxide Semiconductor Field Effect Transistor, so that the voltage provided by the source meter powers the main control board within the set range, and the power supply is indicated by a power indicator.

[0034] In addition, continuing to refer to Figure 4 , the supply voltage is converted into the required power voltage through a first Buck step-down chip (such as a DC-DC Buck power chip, etc.) and a Low dropout regulator (LDO) to power the control device and other devices.

[0035] It should be noted here that although Figure 4 uses a Low dropout regulator as an example for description, those skilled in the art should understand that it can also replace the Low dropout regulator in Figure 4 with other step-down chips according to actual needs, and the embodiments of the present application are not limited to this.

[0036] Furthermore, as Figure 5 shown, the control device of the main control board may include a main control device and two slave control devices, and the main control device can initiate all communications on the I2C bus, provide clocks for all slave control devices, and determine which slave control device to communicate with through address selection.

[0037] It should be understood that although Figure 5 uses two slave control devices as an example for description, those skilled in the art should understand that the control device may include more or fewer slave control devices, and the embodiments of the present application are not limited to this.

[0038] Furthermore, as Figure 6As shown, multiple slave control devices are responsible for providing multiple channels of voltage drive, and constant current output is performed through multiple multi-channel operational amplifiers. The output is input to multiple silicon optical emission chips on the chip mounting board through a connector on the main control board to provide the operating current for the silicon optical emission chips, and the current can be adjusted through the voltage drive adjustment of the slave control devices. The main control device is responsible for the output acquisition of the constant power supply. At the same time, the multiple slave control devices can also sample the monitoring photodiodes MPD of the multiple silicon optical emission chips on the chip mounting board to analyze whether the corresponding monitoring photodiodes MPD are in a normal operating state. Among them, the MPD sampling in this application refers to the main control device converting the constant current output by the multiple multi-channel operational amplifiers into voltage for sampling to determine the situation of the output constant current.

[0039] It should be noted here that Figure 6 each multi-channel drive current in [[]] has a sampling resistor for sampling.

[0040] It should be understood that although Figure 6 in [[]] a single slave control device connecting two multi-channel operational amplifiers is taken as an example for description, those skilled in the art should understand that each slave control device can be connected to more multi-channel operational amplifiers, and the embodiments of this application are not limited thereto.

[0041] Furthermore, as shown in Figure 7 the main control board further includes two second Buck buck converters, and each slave control device is also electrically connected to the connector on the main control board through a second Buck buck converter. Each trace between the multiple second Buck buck converters and the connector on the main control board is also electrically connected to multiple pads. The multiple pads are used to measure the supply voltage required for the main control board to provide to the chip mounting board and the reverse bias voltage required for the main control board to provide to the chip mounting board. Thus, by controlling and adjusting the reverse bias voltage and supply voltage of the multiple silicon optical emission chips, and also inputting to the multiple silicon optical emission chips on the chip mounting board through the connector on the main control board, the magnitudes of the reverse bias voltage and supply voltage can be measured through the multiple pads. Among them, there are measurement pads for the reverse bias voltage and supply voltage on both the main control board and the chip mounting board.

[0042] It should be understood that although Figure 7 in [[]] two second Buck buck converters are taken as an example for description, those skilled in the art should understand that in the case where the control device may include more or fewer slave control devices, the number of the second Buck buck converters can be adjusted accordingly with the number of slave control devices, and the embodiments of this application are not limited thereto.

[0043] Further, the main control board further includes a packaging socket and a plurality of JTAG pin connection interfaces. The packaging socket is used for burning firmware for the main control device, and the plurality of JTAG pin connection interfaces are used for burning firmware for a plurality of slave control devices.

[0044] On the basis that the settings of the main control board before testing can be achieved through the above steps (for example, it is necessary to detect whether the provided voltage is set properly), through the connection between the main control board and the chip mounting board, reliability tests can be performed on a plurality of silicon optical emission chips to be tested, and the reliability tests include optoelectronic performance tests and quality tests. Among them, the optoelectronic performance test is to test the change of the optical performance of the silicon optical emission chip under indoor environmental conditions, including optical output power, backlight current, modulation bandwidth, etc.; the quality test is to test and evaluate the long-term reliability and performance of the silicon optical emission chip under various environmental and operating stress conditions, including temperature cycle (TC), damp-heat storage (DHS), low temperature storage (LTS), high temperature storage (HTS), high temperature operation test of the silicon optical emission chip, and damp-heat power-on test of the silicon optical emission chip, etc.

[0045] In addition, the mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of fiber optic arrays mounted on the chip mounting board, and as Figure 8 shown, each silicon optical emission chip to be tested corresponds to a laser and a fiber optic array.

[0046] Further, the optoelectronic performance test can also be verified through tests under multiple test conditions. For different test conditions, temperature, humidity, supply voltage, etc. can be changed, and it is not limited to performing the optoelectronic performance test under only one test condition.

[0047] In addition, the process of the optoelectronic performance test includes: when power is supplied to all channels of a plurality of silicon optical emission chips to be tested, set the reverse bias voltage of the monitoring photodiode MPD, and couple the optical power of the laser pulse emitted by its corresponding laser into each MZM channel of its corresponding silicon optical emission chip to be tested through the fiber optic array corresponding to the monitoring photodiode, and record the laser input optical power P in of the laser corresponding to the monitoring photodiode, the laser output optical power P out of the laser corresponding to the monitoring photodiode, and the two optical currents of the monitoring photodiode (in the case where the MZM modulator has two branches, the two optical currents are the optical current I pd_a of branch a and the optical current I pd_b), and calculate and record the insertion loss IL of the MZM modulator for the corresponding channel of the silicon optical emission chip to be tested corresponding to the monitoring photodiode MPD. MZM ; Turn off the laser input optical power P. in , and record the two dark currents of the monitoring photodiode (i.e., in the case where the MZM modulator has two branches, the two dark currents are the dark current I of branch a pd_dark_a and the dark current I of branch b pd_dark_b ); Set the reverse bias voltage of the MZM modulator of the monitoring photodiode, and record the leakage current I of the MZM modulator for the corresponding channel of the silicon optical emission chip to be tested corresponding to the monitoring photodiode. Leak ; Adjust the constant current I output of the main control board H , and test and record the internal resistance R of the chip of the silicon optical emission chip to be tested corresponding to the monitoring photodiode. H ; Reopen the optical path of the laser, and record the laser input optical power P through an optical power meter. in , scan the constant current I H , when the output optical power P out changes by one cycle, record the current I H_P after one cycle of change. Since the optical power changes sinusoidally with the input current, record the current magnitude after one cycle of change of the optical power as the reference current for the subsequent constant current input value, which is convenient for referring to the magnitude of the constant current input. Therefore, use this value as the reference value and driving condition in the subsequent high-temperature operation test. With the MZM modulation port of the silicon optical emission chip to be tested corresponding to the monitoring photodiode connected through a coaxial cable, set the reverse bias voltage of the MZM modulator, adjust the constant current I H output until the laser output optical power P out reaches the highest point, then adjust the constant current to return to the linear region of the MZM modulator, and perform a small-signal bandwidth test with a corresponding vector network analyzer, record the bandwidth test data Bandwidth, and use it as a comparison reference; Gradually increase the voltage of the RF port of the MZM modulator to the voltage range related to the reverse bias voltage (for example, this voltage range can be the reverse bias voltage ±1.5V, etc.), and record the minimum optical power P MZM_min and the maximum optical power P MZM_max at the power output of the laser corresponding to the monitoring photodiode (i.e., the laser input optical power), and calculate the maximum optical power P MZM_max and the minimum optical power P MZM_minThe optical power difference is used as the optical modulation amplitude OMA, and this optical modulation amplitude OMA is used as a comparison reference; after a preset power-on time, the above steps are repeatedly executed to obtain new recorded data after repeated execution, and the new recorded data is compared with the recorded data obtained before repeated execution, so as to determine whether the test is passed, and further obtain the test result of the optoelectronic performance test. Among them, it judges whether the optoelectronic performance test is passed by setting a change standard.

[0048] Moreover, the passing of this quality test means that the modulator leakage current of the silicon optical emission chip to be tested does not change after changing the test environment, the terminal resistance (or called Heater resistance) of the silicon optical emission chip to be tested does not change after changing the test environment, and the dark current of the monitoring photodiode (the dark current here refers to the dark current obtained when the laser and the fiber array are not turned on) does not change after changing the test environment.

[0049] For example, a multi-channel digital-to-analog converter DAC can be used to achieve multi-channel different constant current outputs; for the monitoring photodiode MPD sampling, the sampling voltage is fed back to the slave control device through a sampling resistor, and the slave control device displays it to monitor whether the sampling of the monitoring photodiode MPD of the silicon optical chip changes under different working conditions, and is used to judge whether the monitoring photodiode MPD of the silicon optical chip changes; for the terminal resistance of the silicon optical emission chip, by inputting the constant current and sampling voltage conditions, it is used to judge whether the terminal resistance of the silicon optical chip changes.

[0050] It should be understood that the specific process of this quality test can be set according to actual needs, and the embodiments of this application are not limited thereto.

[0051] Specifically, as Figure 9 shown, Figure 9 shows a flowchart of a quality test method provided by an embodiment of this application. Specifically, this quality test method includes: Step S910, power-on test; Step S920, set the supply voltage and reverse bias voltage. And under different test conditions, the supply voltage and reverse bias voltage will change; Step S930, whether the MPD sampling passes; If the constant current of the MPD sampling does not change after adjusting the test environment for a preset time, it is considered that the MPD sampling passes, and step S940 is executed; if the constant current of the MPD sampling changes after adjusting the test environment for a preset time, step S970 is executed; Step S940, whether the test of the terminal resistance of the silicon optical emission chip passes; If the test of the termination resistance of the silicon optical emission chip passes, step S950 is executed; if the test of the termination resistance of the silicon optical emission chip fails, step S970 is executed; Step S950: Check whether the test of the dark current passes; If the test of the dark current passes, step S960 is executed; if the test of the dark current fails, step S970 is executed; Step S960: Determine that the currently tested silicon optical emission chip passes in this working environment, then test the next silicon optical emission chip and perform a power-on test.

[0052] It should be noted here that multiple (for example, eight) silicon optical emission chips on the chip mounting board are sampled and tested simultaneously. After all the silicon optical emission chips are tested, new multiple silicon optical emission chips are replaced on the chip mounting board, and the above test steps are repeated.

[0053] Step S970: The test of the currently tested silicon optical emission chip fails.

[0054] Therefore, with the above technical solution, the chip mounting board with only silicon optical emission chips mounted is placed in a damp heat test chamber (temperature, humidity, etc. can be adjusted), and cooperates with the main control board placed in a conventional environment to perform the reliability test of the silicon optical emission chips. It can not only test and verify the long-term reliability and performance of the silicon optical emission chips under various environments and working conditions, but also ensure that all the electrical chips in the test scheme are in a conventional environment, guarantee the reliability of its electrical chips, and save costs; the system is small in size, simple in structure, can be independently tested and verified, occupies little space, has good portability, is easy to develop, has a short development cycle, and improves the stability of the test system; at the same time, it can also be combined with different types of silicon optical emission chips for testing and verification, and according to the working conditions and test requirements of customers, cooperate with the upper computer software to maximize the role of the main control board and improve the compatibility of the test system; this chip mounting board can mount multiple silicon optical emission chips, and the main control board has functions such as adjustment, control, and sampling of multiple silicon optical emission chips, and can test and verify the reliability performance of multiple silicon optical emission chips at the same time, improve the product test efficiency, and shorten the test time.

[0055] It should be understood that the above reliability test system for silicon optical emission chips is only exemplary. Those skilled in the art can make various deformations according to the above method, and the deformed solutions also fall within the protection scope of this application.

[0056] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0057] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions.

[0058] It should be noted that the words "a" or "an" before a component do not exclude the existence of a plurality of such components. The present invention can be implemented by means of hardware including several different components and by means of a suitably programmed computer. Among the several devices listed, several of these devices can be embodied by the same hardware. The use of the words first, second, third, etc. is only for convenience of expression and does not indicate any order. These words can be understood as part of the component name.

[0059] In addition, it should be noted that in the description of this specification, the description of terms such as "an embodiment", "some embodiments", "embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0060] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications after learning the basic creative concepts. Therefore, the technical solutions should be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0061] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the technical solution of the present invention and its equivalent technologies, the present invention should also cover these modifications and variations.

Claims

1. A reliability test system for a silicon light emitting chip, characterized in that: include: A damp heat test chamber, which is used to adjust the test environment; A chip mounting board, wherein the chip mounting board can be placed in the damp heat test chamber, and the mounting surface of the chip mounting board is provided with a solder point area, a plurality of chip mounting areas and a plurality of pad areas, each of the plurality of chip mounting areas is used for mounting a silicon light emitting chip to be tested, and each of the plurality of pad areas is arranged around a corresponding chip mounting area, and each solder point in the solder point area is electrically connected to the same pin pad of each of the plurality of silicon light emitting chips to be tested; A main control board, which can be arranged outside the damp heat test chamber, and the main control board is electrically connected to the chip mounting board, and the main control board is used to simultaneously adjust the working conditions of multiple silicon light emitting chips that need to be tested, and perform reliability tests under multiple working conditions.

2. The reliability testing system according to claim 1, characterized in that: The solder joint area includes at least one solder joint including a first solder joint for testing the reverse bias voltage of the silicon photonic emission chip to be tested, a second solder joint for testing the power supply voltage of the silicon photonic emission chip to be tested, a third solder joint for testing the DC performance of the RF port of the silicon photonic emission chip to be tested, and a fourth solder joint for testing the current of the monitoring photodiode of the silicon photonic emission chip to be tested.

3. The reliability testing system according to claim 1, characterized in that: The mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of optical fiber arrays mounted on the chip mounting board, and each silicon light emitting chip to be tested corresponds to one of the lasers and one of the optical fiber arrays; the reliability test includes an optoelectronic performance test; Among them, the main control board is specifically used to: when powering all channels of the multiple silicon light emitting chips that need to be tested, set the MPD reverse bias voltage of the monitoring photodiode of the silicon light emitting chip that needs to be tested, and couple the optical power of the laser pulse emitted by the corresponding laser to each MZM channel of the corresponding silicon light emitting chip that needs to be tested through the optical fiber array corresponding to the monitoring photodiode, record the laser input optical power of the laser corresponding to the monitoring photodiode, the laser output optical power of the laser corresponding to the monitoring photodiode and the two-way photocurrent of the monitoring photodiode, and calculate and record the MZM modulator insertion loss of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; turn off the laser input optical power and record the two-way dark current of the monitoring photodiode; set the MZM modulator reverse bias voltage of the monitoring photodiode and record the MZM modulator leakage current of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; adjust its Constant current output, test and record the chip internal resistance of the silicon light emitting chip to be tested corresponding to the monitoring photodiode; when the MZM modulation port of the silicon light emitting chip to be tested corresponding to the monitoring photodiode is connected through a coaxial cable, set the reverse bias voltage of the MZM modulator, adjust the constant current output until the laser output optical power reaches the highest point, and then adjust it back to the linear region of the MZM modulator, and use the corresponding vector network analyzer to perform bandwidth testing and record bandwidth test data; gradually increase the voltage of the RF port of the MZM modulator to a voltage range related to the reverse bias voltage, and record the minimum optical power and maximum optical power at the power output of the laser corresponding to the monitoring photodiode, and calculate the optical power difference between the maximum optical power and the minimum optical power as the optical modulation amplitude; after the preset power-on time, repeat the above steps to obtain new recorded data after repeated execution, and compare the new recorded data with the recorded data obtained before repeated execution to obtain the test result of the photoelectric performance test.

4. The reliability testing system according to claim 3, characterized in that: The reliability test further includes a quality test, and passing the quality test means that after changing the test environment, the modulator leakage current of the silicon light emitting chip to be tested does not change, the terminal resistance of the silicon light emitting chip to be tested does not change after changing the test environment, and the dark current of the monitoring photodiode does not change after changing the test environment.

5. The reliability testing system according to claim 4, characterized in that: The main control board includes a main control device and multiple slave control devices that are communicatively connected to the main control device, and each of the multiple slave control devices is electrically connected to the connection socket of the main control board through multiple multi-way operational amplifiers, and the multiple slave control devices are used to sample the monitoring photodiodes of the multiple silicon light emitting chips that need to be tested on the chip mounting board and to regulate the current of the multiple silicon light emitting chips that need to be tested on the chip mounting board.

6. The reliability testing system according to claim 5, characterized in that: The main control board further includes a plurality of second Buck buck chips, and each of the slave control devices is electrically connected to a connection socket of the main control board via a second Buck buck chip, and each of the plurality of second Buck buck chips and the connection socket of the main control board are electrically connected to pads on the main control board, and the pads on the main control board are used to measure the power supply voltage required by the main control board to provide to the chip mounting board and the reverse bias voltage required by the main control board to provide to the chip mounting board.

7. The reliability testing system according to claim 6, characterized in that: The main control board further includes a power supply interface, a first Buck step-down chip and a low-voltage difference linear regulator which are electrically connected in sequence, and the low-voltage difference linear regulator is electrically connected to the main control device and each of the slave control devices respectively.

8. The reliability testing system according to claim 7, characterized in that: The main control board further includes a packaging socket and a plurality of JTAG pin connection interfaces, wherein the packaging socket is used to burn firmware to the main control device, and the plurality of JTAG pin connection interfaces are used to burn firmware to the plurality of slave control devices.

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