Array substrate and display device

Abstract

The embodiment of the invention provides an array substrate and a display device, relates to the technical field of display, and is used for improving the brightness of a liquid crystal display panel, and the array substrate comprises a substrate, a first semiconductor layer, a first conductive layer and a plurality of touch leads. The first semiconductor layer is located on one side of the substrate. The first conductive layer is located on the side, away from the substrate, of the first semiconductor layer; the first conductive layer includes a plurality of first signal lines. The plurality of touch leads are positioned on one side, close to the first semiconductor layer, of the substrate; the extension direction of the touch lead is parallel to the extension direction of the first signal line. Wherein the orthographic projection of the touch lead on the substrate is overlapped with the orthographic projection of the first signal line on the substrate. The array substrate is used for preparing a liquid crystal display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate and a display device. Background Art

[0002] With the continuous development of touch technologies, touch technologies are increasingly widely applied in electronic products such as mobile phones, tablets, laptop computers, etc. Generally, a touch panel (English: Touch Panel) can be classified into types such as capacitive, electromagnetic, resistive, and optical. A capacitive touch panel can be classified into an add-on mode touch panel (English: Add On Mode Touch Panel), an on-cell touch panel (English: On Cell Touch Panel), and an in-cell touch panel (English: In Cell Touch Panel). The in-cell touch panel can integrate touch electrodes in a display screen, and simultaneously implement the functions of touch and display, thereby effectively reducing the thickness of the entire display device and simplifying the production process. Due to the characteristics of simple structure, light weight, and low cost of the in-cell touch panel, it has gradually become the mainstream in the display field. Summary of the Invention

[0003] On the one hand, an array substrate is provided. The array substrate includes a substrate, a first semiconductor layer, a first conductive layer, and a plurality of touch leads. The first semiconductor layer is located on one side of the substrate. The first conductive layer is located on the side of the first semiconductor layer away from the substrate; the first conductive layer includes a plurality of first signal lines. The plurality of touch leads are located on the side of the substrate close to the first semiconductor layer; the extending direction of the touch leads is parallel to the extending direction of the first signal lines. Wherein, the orthographic projection of the touch leads on the substrate overlaps with the orthographic projection of the first signal lines on the substrate.

[0004] In the above array substrate, the overlapping part of the touch leads and the first signal lines in the orthographic projection does not repeatedly occupy or does not occupy the light-transmitting area of the array substrate, thereby increasing the light-transmitting area of the sub-pixel region, and further improving the brightness of the liquid crystal display panel.

[0005] In some embodiments, the array substrate further includes a second conductive layer, the second conductive layer is located between the substrate and the first semiconductor layer, the touch leads are located on the second conductive layer; the first semiconductor layer further includes a plurality of active layer patterns, and the second conductive layer further includes a plurality of light-shielding blocks, and the orthographic projection of the light-shielding blocks on the substrate overlaps with the orthographic projection of the first active layer pattern on the substrate.

[0006] In some embodiments, the touch leads are connected to the light-shielding blocks.

[0007] In some embodiments, the array substrate further includes a plurality of touch electrodes. The plurality of touch electrodes are located on a side of the first conductive layer away from the substrate; the touch lead includes a connected trace portion and a connection portion; the trace portion extends in a third direction, and the connection portion is located on one side of the trace portion in a fourth direction; the third direction intersects the fourth direction; in a front projection onto the substrate, the trace portion is within the range of the first signal line, at least a part of the connection portion extends beyond the first signal line, and the touch electrode is connected to the part of the connection portion that extends beyond the first signal line.

[0008] In some embodiments, the array substrate further includes a first transfer block, at least one first insulating layer, and at least one second insulating layer. The first transfer block is located between the plurality of touch electrodes and the plurality of touch leads; the at least one first insulating layer is located between the touch electrode and the first transfer block, and the at least one first insulating layer is provided with a second connection hole penetrating through the at least one first insulating layer; the touch electrode extends into the second connection hole to overlap with the first transfer block; the at least one second insulating layer is located between the first transfer block and the touch lead; the at least one second insulating layer is provided with a third connection hole penetrating through the at least one second insulating layer, and the first transfer block extends into the third connection hole to overlap with the part of the connection portion that extends beyond the first signal line.

[0009] In some embodiments, the first transfer block is located in the first conductive layer.

[0010] In some embodiments, the second conductive layer further includes a plurality of second gate lines; the array substrate further includes a second semiconductor layer, and the second semiconductor layer is located between the second conductive layer and the substrate; the second semiconductor layer includes a plurality of second active layer patterns, and a front projection of the second active layer pattern on the substrate overlaps with a front projection of the second gate line on the substrate.

[0011] In some embodiments, the first semiconductor layer includes a plurality of first active layer patterns. The array substrate further includes a source driving circuit, a plurality of pixel electrodes, and a third conductive layer. The source driving circuit is located on a side of the substrate close to the first semiconductor layer; the first signal line is connected to the source driving circuit and the first active layer pattern; the plurality of pixel electrodes are located on a side of the first conductive layer away from the substrate; the third conductive layer is located between the first conductive layer and the plurality of pixel electrodes; the third conductive layer includes a plurality of second transfer blocks; the second transfer block is located between the pixel electrode and the first active layer pattern and connects the pixel electrode and the first active layer pattern; wherein, the touch lead is located in the third conductive layer.

[0012] In some embodiments, the array substrate further includes a plurality of touch electrodes located between the third conductive layer and the plurality of pixel electrodes; the orthographic projection of the touch lead on the substrate is within the range of the orthographic projection of the first signal line on the substrate, and the touch lead is connected to the touch electrode.

[0013] In some embodiments, in the orthographic projection onto the substrate, at least one of the first signal lines is provided between any two adjacent touch leads.

[0014] In some embodiments, in the orthographic projection onto the substrate, a plurality of the first signal lines overlap with a plurality of touch leads in a one-to-one correspondence.

[0015] In some embodiments, the ratio of the resistivity of the touch lead to the thickness of the touch lead is less than or equal to 0.3.

[0016] On the other hand, a display device is provided. The display device includes: an array substrate, a color filter substrate, and a liquid crystal layer as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate; the liquid crystal layer is located between the array substrate and the color filter substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0018] Figure 1 FIG. is a structural diagram of a display device according to some embodiments;

[0019] Figure 2 is Figure 1 a cross-sectional view along section line A-A in;

[0020] Figure 3 FIG. is a structural diagram of an array substrate according to some embodiments;

[0021] Figure 4 is Figure 3 a partial enlarged view of B in;

[0022] Figure 5 is Figure 4 a cross-sectional view along section line C-C in;

[0023] Figure 6 isFigure 4 Another cross-sectional view along section line C-C in

[0024] Figure 7 For Figure 3 Another partial enlarged view of B in

[0025] Figure 8 For Figure 7 Cross-sectional view along section line D-D in

[0026] Figure 9 For Figure 3 Another partial enlarged view of B in

[0027] Figure 10 For Figure 7 Cross-sectional view along section line E-E in

[0028] Figure 11 For Figure 3 Another partial enlarged view of B in

[0029] Figure 12 For Figure 11 Cross-sectional view along section line F-F in

[0030] Figure 13 Another structural diagram of an array substrate according to some embodiments. Detailed implementation manners

[0031] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that a specific feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described above may be included in any one or more embodiments or examples in any suitable manner.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0034] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0035] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0036] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0037] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude a device suitable for or configured to perform additional tasks or steps.

[0038] In addition, the use of "based on" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can, in practice, be based on additional conditions or values beyond those stated.

[0039] As used herein, "substantially" includes the stated value and the average value within an acceptable deviation range of a particular value, where the acceptable deviation range is determined by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0040] As used herein, "parallel", "perpendicular", and "equal" include the stated situations and situations similar to the stated situations, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one of them.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0043] Embodiments of the present disclosure provide a display device 1000, such as Figure 1As shown, the display device 1000 can be any product or component with a display function, such as a laptop, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an Augmented Reality (AR) device, a Virtual Reality (VR) device, a car center control screen, etc.

[0044] The above display device 1000 can be a Liquid Crystal Display (LCD), an Organic Light Emitting Display (OLED), a Quantum Dot Light Emitting Display (QLED), a Mini / Micro Light Emitting Display (MLED), or an Active-Matrix Organic Light Emitting Diode (AMOLED) display device.

[0045] In the following embodiments, the display device 1000 is taken as an LCD as an example to schematically illustrate some embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0046] As Figure 2 shown, the display device 1000 includes a housing 100, a cover plate 200, a liquid crystal display panel 300, a backlight module 400, and a circuit board 500.

[0047] As Figure 2 shown, the longitudinal section of the housing 100 can be U-shaped, for example. The liquid crystal display panel 300, the backlight module 400, and the circuit board 500 are located inside the housing 100, and the cover plate 200 is disposed at the opening of the housing 100. The backlight module 400 is located on the side of the circuit board 500 close to the cover plate 200, and the liquid crystal display panel 300 is located on the side of the backlight module 400 close to the cover plate 200.

[0048] Among them, the backlight module 400 is used to provide backlight for the liquid crystal display panel 300, and the color of the backlight can be blue or white. The embodiments of the present disclosure do not specifically limit the color of the light emitted by the backlight module.

[0049] As Figure 2As shown, the liquid crystal display panel 300 includes an array substrate 10, a color filter substrate 20, a liquid crystal layer 30, and a sealant 40. The array substrate 10 and the color filter substrate 20 are disposed opposite to each other. The liquid crystal layer 30 is located between the array substrate 10 and the color filter substrate 20. The sealant 40 is located between the array substrate 10 and the color filter substrate 20 and surrounds the liquid crystal layer 30. The array substrate 10 and the color filter substrate 20 are bonded by the sealant 40.

[0050] Among them, the color filter substrate 20 may include color filters. When the backlight provided by the backlight module 400 is blue light, the above-mentioned color filters may include a red filter portion, a green filter portion, and a blue filter portion. The red filter portion can only allow red light in the incident light to pass through, the green filter portion can only allow green light in the incident light to pass through, and the blue filter portion can only allow blue light in the incident light to pass through. When the backlight provided by the backlight module 400 is blue light, the above-mentioned color filters may include a red filter portion and a green filter portion.

[0051] As Figure 3 shown, the array substrate 10 has a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. Figure 3 Taking the peripheral area BB surrounding the display area AA as an example. The peripheral area BB can be used, for example, to arrange a scan driving circuit, control signal lines (such as clock signal lines, power supply voltage signal lines, etc.), and a source driver (English: Source Driver, abbreviated as: SD). The function of the peripheral area BB is not limited to this.

[0052] In some embodiments, as Figure 3 , Figure 4 and Figure 5 shown, the array substrate 10 includes a substrate 11, a driving circuit stack 12, and a plurality of touch electrodes 13.

[0053] As Figure 5 shown, the substrate 11 can be a single-layer structure or a multi-layer structure. For example, when the substrate 11 is a multi-layer structure, the substrate 11 may include a substrate 111 and a buffer layer 112 disposed on the substrate 111. The buffer layer 112 is disposed on the substrate 111. The material used for the buffer layer 112 may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON), and silicon oxide (SiOx, x>0). The buffer layer 112 is used to provide a good formation basis for the thin film when the thin film is fabricated on the substrate 11. When the substrate 11 is a single-layer structure, the material of the substrate 11 may include glass, sapphire, or silicon.

[0054] In some embodiments, as Figure 3 , Figure 4 and Figure 5As shown, the driving circuit stack 12 includes a plurality of pixel circuits 121, such as Figure 3 As shown, the plurality of pixel circuits 121 are located in the display area AA. The plurality of pixel circuits 121 are arranged in multiple rows and multiple columns. Each row of pixel circuits 121 includes a plurality of pixel circuits 121 arranged at intervals along the first direction X. The multiple rows of pixel circuits 121 are arranged along the second direction Y. Each column of pixel circuits 121 includes a plurality of pixel circuits 121 arranged along the second direction Y. The multiple columns of pixel circuits 121 are arranged along the first direction X. That is to say, the first direction X is the row direction in which the plurality of pixel circuits 121 are arranged, and the second direction Y is the column direction in which the plurality of pixel circuits 121 are arranged. Among them, the first direction X and the second direction Y intersect. Exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0055] As Figure 3 shown, the driving circuit stack 12 further includes a plurality of data lines 123 and a plurality of first gate lines 124. Among them, the plurality of data lines 123 and the plurality of first gate lines 124 are located in the display area AA. The plurality of data lines 123 extend along the second direction Y and are arranged at intervals along the first direction X. As Figure 5 shown, one data line 123 is connected to one row of pixel circuits 121.

[0056] As Figure 3 shown, the driving circuit stack 12 further includes a source driver circuit 125. The source driver circuit 125 is located in the peripheral area BB and on one side of the display area AA. Exemplarily, the source driver circuit 125 can be located on the upper side, lower side, left side or right side of the display area AA. Figure 3 Taking the source driver circuit 125 located on the upper side of the display area AA as an example. The plurality of data lines 123 (all the data lines 123) are connected to the source driver circuit 125.

[0057] As Figure 3 shown, the plurality of first gate lines 124 extend along the first direction X and are arranged at intervals along the second direction Y. As Figure 5 shown, one first gate line 124 is connected to one column of pixel circuits 121.

[0058] Based on the above structure, as Figure 3 shown, the plurality of data lines 123 and the plurality of first gate lines 124 divide the display area AA into a plurality of sub-pixel areas 110.

[0059] As Figure 3As shown, a plurality of touch electrodes 13 are located in the display area AA and on the side of the driving circuit stack 12 away from the substrate 11. The plurality of touch electrodes 13 are arranged in multiple rows and multiple columns. Each row of touch electrodes 13 includes a plurality of touch electrodes 13 arranged at intervals in the first direction X, and the multiple rows of touch electrodes 13 are arranged in the second direction Y. Each column of touch electrodes 13 includes a plurality of touch electrodes 13 arranged in the second direction Y, and the multiple columns of touch electrodes 13 are arranged in the first direction X.

[0060] As Figure 3 shown, a plurality of sub-pixel regions 110 correspond to one touch electrode 13. For example, five, ten, or twenty pixel electrodes correspond to one touch electrode 13, and the embodiments of the present disclosure will not list them one by one.

[0061] Among them, the correspondence between the plurality of sub-pixel regions 110 and one touch electrode 13 may mean that the plurality of sub-pixel regions 110 are located within the outer boundary of the orthographic projection of one touch electrode 13 on the substrate 11.

[0062] As Figure 3 shown, the array substrate 10 further includes a touch chip 14. The touch chip 14 is disposed on the substrate 11. The touch chip 14 is located in the peripheral area BB and on one side of the display area AA. The touch chip 14 may be located above, below, to the left, or to the right of the display area AA. Figure 3 In the following, the case where the touch chip 14 is located below the display area AA is taken as an example.

[0063] The touch chip 14 is connected to a plurality of touch electrodes 13 (all touch electrodes 13). The touch chip 14 transmits a touch driving signal to the touch electrodes 13, and at the same time receives the feedback signals of the plurality of touch electrodes 13. By analyzing the feedback signals, it is determined whether the touch electrodes 13 are touched to implement the touch function.

[0064] As Figure 3 shown, the array substrate 10 further includes a plurality of touch leads 15. One end of each touch lead 15 is connected to one touch electrode 13, and the other end is connected to the touch chip 14. In this way, the touch chip can apply a touch driving signal to the touch electrodes 13 through the touch leads 15.

[0065] The array substrate 10 further includes a first conductive layer 16. The first conductive layer 16 includes a plurality of first signal lines 161, and the first signal lines 161 are configured to transmit signals (for example, the first signal lines 161 are configured to transmit data signals, scan signals, VDD signals, or VSS signals).

[0066] In the related art, the touch lead and the first signal line are made of the same material and are arranged in the same layer. When the first signal line is configured to transmit a data signal or a scan signal, the touch lead is located in the sub-pixel region, and the touch lead occupies a part of the sub-pixel region, resulting in a reduction in the light-transmitting region of the sub-pixel region, and thus a reduction in the brightness of the liquid crystal display panel. When the first signal line is configured to transmit a VDD signal or a VSS signal, both the touch lead and the first signal line are located in the sub-pixel region, and both the touch lead and the first signal line occupy a part of the sub-pixel region, resulting in a reduction in the light-transmitting region of the sub-pixel region.

[0067] To solve the above technical problems, in some embodiments of the present disclosure, the touch lead 15 is disposed on the substrate 11, and the extending direction of the touch lead 15 is parallel to the extending direction of the first signal line 161. The orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first signal line 161 on the substrate 11.

[0068] With this arrangement, the overlapping portion of the touch lead 15 and the orthographic projection of the first signal line 161 does not repeatedly occupy or does not occupy the region of the sub-pixel region 110, thereby increasing the light-transmitting region of the sub-pixel region 110, and thus increasing the brightness of the liquid crystal display panel 300.

[0069] Exemplarily, the orthographic projection of the touch lead 15 on the substrate 11 is located within the range of the orthographic projection of the first signal line 161 on the substrate 11.

[0070] With this arrangement, the touch lead 15 does not repeatedly occupy or does not occupy the region of the sub-pixel region 110, thereby increasing the light-transmitting region of the sub-pixel region 110, and thus increasing the brightness of the liquid crystal display panel 300.

[0071] In some embodiments, the driving circuit stack 12 includes a first semiconductor layer ACT1, a first conductive layer 16, and a first source-drain conductive layer SD1 that are sequentially arranged in a direction perpendicular to the substrate 11 and away from the substrate 11.

[0072] The first gate line 124 is located in the first conductive layer 16, that is, the first signal line 161 is the first gate line 124, and the data line 123 is located in the first source-drain conductive layer SD1. The touch lead 15 extends along the first direction X, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first gate line 124 on the substrate 11.

[0073] With this arrangement, the overlapping portion of the touch lead 15 and the orthographic projection of the first gate line 124 does not need to occupy the region of the sub-pixel region 110, thereby increasing the light-transmitting region of the sub-pixel region 110, and thus increasing the brightness of the liquid crystal display panel 300.

[0074] It can be understood that the driving circuit stack 12 further includes an insulating film layer located between the first semiconductor layer ACT1, the first conductive layer 16, the first source-drain conductive layer SD1, and the touch electrode 13. For example, the driving circuit stack 12 further includes a second gate insulating layer GI2 located between the first semiconductor layer ACT1 and the first conductive layer 16, a second interlayer dielectric layer ILD2 located between the first conductive layer 16 and the first source-drain conductive layer SD1, and a planarization layer PLN located between the first source-drain conductive layer SD1 and the touch electrode 13.

[0075] In some other embodiments, as Figure 5 shown, the driving circuit stack 12 includes a first semiconductor layer ACT1, a first gate conductive layer GT1, and a first conductive layer 16 sequentially arranged along a direction perpendicular to the substrate 11 and away from the substrate 11.

[0076] The first gate line 124 is located on the first gate conductive layer GT1, and the data line 123 is located on the first conductive layer 16, that is, the first signal line 161 is the data line 123. The touch lead 15 extends along the second direction Y, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the data line 123 on the substrate 11.

[0077] Set in this way, the portion overlapping with the orthographic projection of the data line 123 does not need to occupy the area of the sub-pixel region 110, thereby increasing the light-transmitting area of the sub-pixel region 110, and further improving the brightness of the liquid crystal display panel 300.

[0078] It can be understood that the driving circuit stack 12 further includes an insulating film layer located between the first semiconductor layer ACT1, the first gate conductive layer GT1, the first conductive layer 16, and the touch electrode 13. For example, the driving circuit stack 12 further includes a second gate insulating layer GI2 located between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second interlayer dielectric layer ILD2 located between the first gate conductive layer GT1 and the first conductive layer 16, and a planarization layer PLN located between the first conductive layer 16 and the touch electrode 13.

[0079] In the following embodiments, taking the first signal line 161 as the data line 123 as an example, some embodiments of the present disclosure are schematically described. However, the embodiments of the present disclosure are not limited thereto, and any other signal lines can also be considered as long as the same technical idea is applied.

[0080] In some embodiments, as Figure 5 shown, the array substrate 10 further includes a second conductive layer 17. The second conductive layer 17 is located between the substrate 11 and the first semiconductor layer ACT1. The touch lead 15 is located within the second conductive layer 17.

[0081] Set in this way, the touch lead 15 and the first signal line 161 can be set on different layers. The orthographic projection of the touch lead 15 on the substrate 11 and the orthographic projection of the first signal line 161 on the substrate 11 overlap. The part that overlaps with the orthographic projection of the first signal line 161 does not need to occupy the area of the sub-pixel region 110, thereby increasing the light-transmitting area of the sub-pixel region 110 and further improving the brightness of the liquid crystal display panel 300.

[0082] It can be understood that in order to electrically insulate the second conductive layer 17 and the first gate conductive layer GT1, the driving circuit stack 12 further includes a first interlayer dielectric layer ILD1, and the first interlayer dielectric layer ILD1 is located between the second conductive layer 17 and the first gate conductive layer GT1.

[0083] In some examples, the first semiconductor layer ACT1 further includes a plurality of active layer patterns 1, and the active layer patterns 1 are the active layer patterns of the pixel circuit 121. The second conductive layer 17 further includes a plurality of light-shielding blocks 171, and the orthographic projection of the light-shielding blocks 171 on the substrate 11 overlaps with the orthographic projection of the first active layer pattern 1 on the substrate 11. Set in this way, the problem that light irradiates from the substrate 11 to the active layer pattern 1, resulting in a threshold voltage shift of the first thin-film transistor 1211, can be improved.

[0084] It can be understood that the pixel circuit 121 further includes a first gate 2, a first source 3, and a first drain 4. The above-mentioned first source 3 and first drain 4 can be the same in structure, so the first source 3 and the first drain 4 can be interchanged. A first gate line 124 overlaps with the orthographic projection of the first active layer pattern 1 in a row of first thin-film transistors 1211 on the substrate 11, and the part of the first gate line 124 that overlaps with the orthographic projection of the first active layer pattern 1 forms the first gate 2. A data line 123 overlaps with the orthographic projection of the first active layer pattern 1 in a column of first thin-film transistors 1211 on the substrate 11, and the part of the data line 123 that overlaps with the orthographic projection of the first active layer pattern 1 forms the first source 3.

[0085] Exemplarily, the first thin-film transistor 1211 can be an oxide thin-film transistor, that is, the material of the active layer pattern 1 in the first thin-film transistor 1211 includes an oxide material. For example, the material of the active layer pattern 1 includes indium gallium zinc oxide or indium gallium tin oxide. Or, the first thin-film transistor 1211 can be a low-temperature polycrystalline silicon thin-film transistor, that is, the material of the active layer pattern 1 in the first thin-film transistor 1211 includes a low-temperature polycrystalline silicon material. For example, the material of the active layer pattern 1 includes oxygenated polycrystalline silicon.

[0086] In some embodiments, the touch lead 15 includes a wiring portion 151 and a connection portion 152 that are connected to each other. The wiring portion 151 extends in a third direction, and the connection portion 152 is located on one side of the wiring portion 151 in a fourth direction. In the orthographic projection onto the substrate 11, the wiring portion 151 is within the range of the first signal line 161, and at least a part of the connection portion 152 extends beyond the first signal line 161. The third direction intersects the fourth direction. Exemplarily, the third direction and the fourth direction are perpendicular. As Figure 5 shown, the third direction is substantially parallel to the second direction Y, and the fourth direction is substantially parallel to the first direction X. That is, the wiring portion 151 extends in the second direction Y, and the connection portion 152 is located on one side of the wiring portion 151 in the first direction X. Exemplarily, the connection portion 152 is located on the left or right side of the wiring portion 151. Figure 5 In Figure 5 , the case where the connection portion 152 is located on the left side of the wiring portion 151 is taken as an example.

[0087] Exemplarily, in the orthographic projection onto the substrate 11, the wiring portion 151 completely overlaps with the first signal line 161, and the connection portion 152 completely extends beyond the first signal line 161.

[0088] In some embodiments, as Figure 5 shown, the array substrate 10 further includes a first insulating stack 101. The first insulating stack 101 is located between the plurality of touch electrodes 13 and the plurality of touch leads 15. The first insulating stack 101 is provided with a first connection hole 1011 that penetrates the first insulating stack 101. The touch electrode 13 extends into the first connection hole 1011 and overlaps with the portion of the connection portion 152 that extends beyond the first signal line 161. That is, the touch electrode 13 and the touch lead 15 are connected through the first connection hole 1011.

[0089] When the driving circuit stack 12 includes a first interlayer dielectric layer ILD1, a second gate insulating layer GI2, a second interlayer dielectric layer ILD1, and a planarization layer PLN that are sequentially arranged in a direction perpendicular to the substrate 11 and away from the substrate 11, the first insulating stack 101 includes a first interlayer dielectric layer ILD1, a second gate insulating layer GI2, a second interlayer dielectric layer ILD2, and a planarization layer PLN that are stacked.

[0090] It should be noted that the processes for preparing vias in inorganic insulating layers and organic insulating layers are different. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, and the planarization layer PLN is an organic insulating layer. That is to say, the first insulating stack 101 includes both an organic insulating film layer and an inorganic insulating film layer. Therefore, two punching operations are required on the first insulating stack 101 to form the first connection hole 1011.

[0091] In some other embodiments, as Figure 6As shown, the array substrate 10 further includes a first transfer block 18, at least one first insulating layer 102, and at least one second insulating layer 103. The first transfer block 18 is located between a plurality of touch electrodes 13 and a plurality of touch leads 15.

[0092] At least one first insulating layer 102 (all the first insulating layers 102) is located between the touch electrode 13 and the first transfer block 18. At least one first insulating layer 102 is provided with a second connection hole 1021 penetrating through at least one first insulating layer 102. The touch electrode 13 extends into the second connection hole 1021 to overlap with the first transfer block 18.

[0093] At least one second insulating layer 103 (all the second insulating layers 103) is located between the first transfer block 18 and the touch lead 15. At least one second insulating layer 103 is provided with a third connection hole 1031 penetrating through at least one second insulating layer 103. The first transfer block 18 extends into the third connection hole 1031 to overlap with a portion of the connection portion 152 that extends beyond the first signal line 161.

[0094] With such an arrangement, the first transfer block 18 can reduce the depth of a single via hole when the touch electrode 13 is connected to the touch lead 15, improve the connection stability between the touch electrode 13 and the touch lead 15, and at the same time reduce the process difficulty in the process of fabricating the via hole.

[0095] When the driving circuit stack 12 includes a second conductive layer 17, a first interlayer dielectric layer ILD1, a first semiconductor layer ACT1, a second gate insulating layer GI2, a first gate conductive layer GT1, a second interlayer dielectric layer ILD2, a first conductive layer 16, and a planarization layer PLN that are sequentially arranged in a direction perpendicular to and away from the substrate 11, the first transfer block 18 can be located in the first gate conductive layer GT1 or in the first conductive layer 16.

[0096] In some examples, the first transfer block 18 is located in the first gate conductive layer GT1. In this case, at least one first insulating layer 102 includes the second interlayer dielectric layer ILD2 and the planarization layer PLN. At least one second insulating layer 103 includes the first interlayer dielectric layer ILD1 and the second gate insulating layer GI2.

[0097] It should be noted that the processes for fabricating vias in the inorganic insulating layer and the organic insulating layer are different. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, and the planarization layer PLN is an organic insulating layer. That is to say, at least one first insulating layer 102 includes both an organic insulating film layer and an inorganic insulating film layer. Therefore, two punching operations are required to form the second connection hole 1021 on at least one first insulating layer 102. At least one second insulating layer 103 only includes an inorganic insulating film layer. Therefore, only one punching operation is required to form the third connection hole 1031 on at least one second insulating layer 103.

[0098] In some other examples, as Figure 6 shown, the first adapter block 18 is located on the first conductive layer 16. In this case, at least one first insulating layer 102 includes the planarization layer PLN. At least one second insulating layer 103 includes the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2.

[0099] It should be noted that the processes for fabricating vias in the inorganic insulating layer and the organic insulating layer are different. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, and the planarization layer PLN is an organic insulating layer. That is to say, at least one first insulating layer 102 only includes an organic insulating film layer. Therefore, only one punching operation is required to form the second connection hole 1021 on at least one first insulating layer 102. At least one second insulating layer 103 only includes an inorganic insulating film layer. Therefore, only one punching operation is required to form the third connection hole 1031 on at least one second insulating layer 103.

[0100] As Figure 6 shown, on the basis that the array substrate 10 includes the first adapter block 18, the second connection hole 1021 and the third connection hole 1031 are coaxially arranged. By arranging in this way, the size of the part of the first adapter block 18 exceeding the first signal line 161 can be reduced, so that the area of the sub-pixel region 110 occupied by the first adapter block 18 can be reduced, and the light-transmitting area of the sub-pixel region 110 can be further increased, thereby increasing the brightness of the liquid crystal display panel 300.

[0101] In some embodiments, on the basis that the second conductive layer 17 includes the touch lead 15 and the light-shielding block 171, as Figure 7 and Figure 8 shown, the touch lead 15 is connected to the light-shielding block 171.

[0102] Set in this way, it is possible to improve the problem that the parasitic capacitance between the plurality of light-shielding blocks 171 caused by the floating electrodes of the light-shielding blocks 171 is large, and reduce the risk that the large difference in the parasitic capacitance between the first active layer patterns 1 causes a large difference in the threshold voltage shift of the plurality of first thin-film transistors 1211.

[0103] In some examples, such as Figure 7 and Figure 8 As shown, in the positive projection onto the substrate 11, the connection portion 152 is located on the left side of the routing portion 151, and the pixel circuit 121 corresponding to the routing portion 151 is located on the right side of the routing portion 151. Along the second direction Y, the connection portion 152 and the pixel circuit 121 corresponding to the routing portion 151 are arranged in pairs. Among them, the pixel circuit 121 corresponding to the routing portion 151 refers to the pixel circuit 121 connected to the data line 123 that overlaps with the positive projection of the routing portion 151.

[0104] In this case, the touch lead 15 is connected to the light-shielding block 171, the gap between the touch lead 15 and the light-shielding block 171 can be eliminated, and the pixel circuit 121 can be closer to the data line 123. Without changing the distance between two adjacent data lines 123, the pixel circuit 121 being closer to the data line 123 can increase the distance between the connection portion 152 and the pixel circuit 121 located in the same sub-pixel region 110, thereby increasing the size of the connection portion 152, which is beneficial to increasing the facing area between the connection portion 152 and the touch electrode 13, increasing the contact area between the connection portion 152 and the touch electrode 13, and increasing the connection reliability and stability between the connection portion 152 and the touch electrode 13. Or, without changing the size of the connection portion 152, the pixel circuit 121 being closer to the data line can reduce the distance between two adjacent data lines 123, thereby reducing the size of the sub-pixel region 110 along the second direction Y, and further improving the pixel resolution of the liquid crystal display panel 300.

[0105] In some embodiments, such as Figure 3 and Figure 5 As shown, the driving circuit stack further includes a scan driving circuit 122, and a plurality of first gate lines 124 (all the first gate lines 124) are connected to the scan driving circuit 122.

[0106] Such as Figure 5 As shown, the scan driving circuit 122 is located in the peripheral region BB and on one side of the display region AA. The scan driving circuit 122 can be located on at least one of the upper side, lower side, left side, and right side of the display region AA. Figure 3Taking the case where the middle scan driving circuit 122 is located on the left side of the display area AA as an example. The scan driving circuit 122 includes a second thin film transistor 1221, and the second thin film transistor 1221 includes a second active layer pattern 5, a second gate 6, a second source 7, and a second drain 8. The above-mentioned second source 7 and second drain 8 can be the same in structure, so the second source 7 and the second drain 8 can be interchanged.

[0107] Exemplarily, the second conductive layer 17 further includes a plurality of second gate lines. The driving circuit stack 12 further includes a second semiconductor layer ACT2, and the second semiconductor layer ACT2 is located between the second conductive layer 17 and the substrate 11. The second semiconductor layer includes a plurality of second active layer patterns, and the orthographic projection of the second active layer pattern on the substrate 11 overlaps with the orthographic projection of the second gate line on the substrate. The part of the second gate line that overlaps with the orthographic projection of the second active layer pattern 5 is the second gate 6.

[0108] In some embodiments, as Figure 5 shown, when the driving circuit stack 12 includes a first thin film transistor 1211 and a second thin film transistor 1221, the first thin film transistor 1211 can be an oxide thin film transistor, and the second thin film transistor 1221 can be a low-temperature polycrystalline silicon thin film transistor.

[0109] Based on the advantages of high mobility and fast charging of low-temperature polycrystalline silicon thin film transistors, and the advantage of low leakage current of oxide thin film transistors, integrating low-temperature polycrystalline silicon thin film transistors and oxide thin film transistors on an array substrate 10 to utilize the advantages of both can reduce the power consumption of the array substrate 10 and improve the display quality of the liquid crystal display panel 300.

[0110] In some embodiments, as Figure 9 、 Figure 10 、 Figure 11 and Figure 12 shown, the driving circuit stack 12 further includes a third conductive layer 19, and the third conductive layer 19 is located between the first conductive layer 16 and the plurality of touch electrodes 13. The third conductive layer 19 includes a plurality of second connection blocks 191, and the orthographic projection of the second connection block 191 on the substrate 11 overlaps with the orthographic projection of the first active layer pattern 1 on the substrate 11, and the second connection block 191 is connected to the first active layer pattern 1, that is, the second connection block 191 forms the first drain 4.

[0111] In this case, the distance between the orthographic projection of the second adapter block 191 on the substrate 11 and the orthographic projection of the data line 123 on the substrate 11 can be smaller than the minimum limit value of the exposure process (for example, the exposure accuracy value of the exposure machine, an example exposure accuracy value is 5μm), so that the size of the first active layer pattern 1 between the second adapter block 191 and the data line 123 can be smaller, the size of the first thin film transistor 1211 can be reduced, and the pixel resolution of the liquid crystal display panel 300 can be increased.

[0112] In some embodiments, Figure 10 and Figure 12 As shown, the touch lead 15 is located on the third conductive layer 19 .

[0113] In this way, the touch lead 15 and the first signal line 161 can be arranged in different layers, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first signal line 161 on the substrate 11, thereby improving the brightness of the liquid crystal display panel 300.

[0114] In some embodiments, Figure 12 As shown, on the basis that the touch lead 15 is located on the third conductive layer 19 , the orthographic projection of the touch lead 15 on the substrate 11 is located within the range of the orthographic projection of the first signal line 161 on the substrate 11 , and the touch lead 15 is connected to the touch electrode 13 .

[0115] In this case, the touch lead 15 does not include the connecting portion 152 , which can further increase the light-transmitting area of ​​the sub-pixel area 110 and improve the brightness of the liquid crystal display panel 300 .

[0116] It is understandable that, in order to electrically insulate the first conductive layer 16 from the third conductive layer 19 , the driving circuit stack 12 further includes a third interlayer dielectric layer ILD3 , and the third interlayer dielectric layer ILD3 is located between the first conductive layer 16 and the third conductive layer 19 .

[0117] In some embodiments, Figure 12 As shown, the array substrate 10 also includes at least one third insulating layer 104 (all third insulating layers 104), at least one third insulating layer 104 is located between the touch lead 15 and the touch electrode 13, at least one third insulating layer 104 is provided with a fourth connecting hole 1041 penetrating at least one third insulating layer 104, and the touch electrode 13 extends into the fourth connecting hole 1041 and is connected to the touch lead 15.

[0118] Exemplarily, when the driving circuit stack 12 includes the first conductive layer 16 , the third interlayer dielectric layer ILD2 , the third conductive layer 19 and the planarization layer PLN, the at least one third insulating layer 104 includes the planarization layer PLN.

[0119] It should be noted that the processes for fabricating vias in the inorganic insulating layer and the organic insulating layer are different. The planarization layer PLN is an organic insulating layer, that is, at least one third insulating layer 104 includes only an organic insulating layer. Therefore, the fourth connection hole 1041 can be formed by punching once on at least one third insulating layer 104.

[0120] In some embodiments, a touch electrode 13 can be connected to multiple touch leads 15, or can be connected to one touch lead 15.

[0121] In some examples, a touch electrode 13 is connected to multiple touch leads 15. In this case, even if one of the multiple touch leads 15 connected to a touch electrode 13 fails, the touch chip 14 can still transmit touch signals to the touch electrode 13 through other touch leads 15, which can increase the stability of the touch chip 14 transmitting touch signals to the touch electrode 13.

[0122] In other examples, a touch electrode 13 is connected to one touch lead 15. With this arrangement, the number of touch electrodes 13 can be increased, the size of the touch electrodes 13 can be reduced, and thus the touch performance of the liquid crystal display device can be improved.

[0123] In some embodiments, as Figure 3 shown, in the orthographic projection onto the substrate 11, at least one first signal line 161 is provided between any two adjacent touch leads 15. For example, one, three, or five first signal lines 161 are provided between any two adjacent touch leads 15, and the embodiments of the present disclosure will not list them one by one.

[0124] Exemplarily, in the orthographic projection onto the substrate 11, two first signal lines 161 are provided between any two adjacent touch leads 15.

[0125] In other embodiments, as Figure 13 shown, in the orthographic projection onto the substrate 11, multiple first signal lines 161 overlap with multiple touch leads one by one.

[0126] In this way, the number of touch leads 15 is the same as the number of first signal lines 161, so that the number of touch electrodes 13 can be increased, the size of the touch electrodes 13 can be reduced, and thus the touch performance of the display device 1000 can be improved.

[0127] In some embodiments, the ratio of the resistivity of the touch lead 15 to the thickness of the touch lead 15 is less than or equal to 0.3. With this arrangement, the resistance of the touch lead 15 can be made smaller, and thus the voltage drop of the touch lead 15 can be reduced.

[0128] In some embodiments, the touch electrode 13 is multiplexed as a common electrode. At this time, the touch lead 15 is multiplexed as a common electrode lead. The touch chip 14 can be a Touch and Display Driver Integration (TDDI) chip.

[0129] On this basis, as Figure 3 and Figure 5 shown, the array substrate 10 further includes a plurality of pixel electrodes 22. The plurality of pixel electrodes 22 are located in the display area AA and on the side of the touch electrode 13 away from the substrate 11. The plurality of pixel electrodes 22 are arranged in multiple rows and multiple columns. Each row of pixel electrodes 22 includes a plurality of pixel electrodes 22 arranged at intervals in the first direction X, and the multiple rows of pixel electrodes 22 are arranged in the second direction Y. Each column of pixel electrodes 22 includes a plurality of pixel electrodes 22 arranged in the second direction Y, and the multiple columns of pixel electrodes 22 are arranged in the first direction X.

[0130] Among them, one pixel electrode 22 is located in one sub-pixel area 110 and is connected to the drain of one first thin-film transistor 1211. In this way, the source driver circuit 125 is used to provide a data signal to the pixel electrode 22 through the data line 123.

[0131] As Figure 5 shown, the array substrate 10 further includes a passivation layer PVX. The passivation layer PVX is located between the plurality of pixel electrodes 22 and the plurality of touch electrodes 13. Arranged in this way, the passivation layer PVX can insulate the touch electrode 13 and the pixel electrode 22.

[0132] In the description of this specification, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0133] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, it includes: a substrate; a first semiconductor layer located on one side of the substrate; a first conductive layer located on the side of the first semiconductor layer away from the substrate; the first conductive layer includes a plurality of first signal lines; a plurality of touch leads located on the side of the substrate close to the first semiconductor layer; the extending direction of the touch leads is parallel to the extending direction of the first signal lines; wherein, the orthographic projection of the touch leads on the substrate overlaps with the orthographic projection of the first signal lines on the substrate.

2. The array substrate according to claim 1, characterized in that, it further includes: a second conductive layer located between the substrate and the first semiconductor layer, and the touch leads are located on the second conductive layer; the first semiconductor layer further includes a plurality of active layer patterns, and the second conductive layer further includes a plurality of light-shielding blocks, and the orthographic projection of the light-shielding blocks on the substrate overlaps with the orthographic projection of the first active layer pattern on the substrate.

3. The array substrate according to claim 2, wherein, the touch leads are connected to the light-shielding blocks.

4. The array substrate according to claim 1, characterized in that, it further includes: a plurality of touch electrodes located on the side of the first conductive layer away from the substrate; the touch leads include a connected routing portion and a connecting portion; the routing portion extends along a third direction, and the connecting portion is located on one side of the routing portion along a fourth direction; the third direction intersects with the fourth direction; in the orthographic projection onto the substrate, the routing portion is within the range of the first signal lines, at least a part of the connecting portion extends beyond the first signal lines, and the touch electrodes are connected to the part of the connecting portion that extends beyond the first signal lines.

5. The array substrate according to claim 4, characterized in that, it further includes: a first insulating stack located between the plurality of touch electrodes and the plurality of touch leads, and the first insulating stack is provided with a first connection hole penetrating through the first insulating stack, and the touch electrodes extend into the first connection hole and overlap with the part of the connecting portion that extends beyond the first signal lines.

6. The array substrate according to claim 5, characterized in that, it further includes: a first transfer block located between the plurality of touch electrodes and the plurality of touch leads; at least one first insulating layer located between the touch electrodes and the first transfer block, and the at least one first insulating layer is provided with a second connection hole penetrating through the at least one first insulating layer; the touch electrodes extend into the second connection hole and overlap with the first transfer block; at least one second insulating layer located between the first transfer block and the touch leads; the at least one second insulating layer is provided with a third connection hole penetrating through the at least one second insulating layer, and the first transfer block extends into the third connection hole and overlaps with the part of the connecting portion that extends beyond the first signal lines.

7. The array substrate according to claim 6, characterized in that, the first transfer block is located on the first conductive layer.

8. The array substrate according to any one of claims 1 to 7, characterized in that, the second conductive layer further includes a plurality of second gate lines; the array substrate further includes: A second semiconductor layer, located between the second conductive layer and the substrate; the second semiconductor layer includes a plurality of second active layer patterns, and the orthographic projection of the second active layer pattern on the substrate overlaps with the orthographic projection of the second gate line on the substrate.

9. The array substrate according to claim 1, wherein, the first semiconductor layer includes a plurality of first active layer patterns; the array substrate further includes: a source driving circuit, located on a side of the substrate close to the first semiconductor layer; the first signal line is connected to the source driving circuit and the first active layer pattern; a plurality of pixel electrodes, located on a side of the first conductive layer away from the substrate; a third conductive layer, located between the first conductive layer and the plurality of pixel electrodes; the touch lead is located in the third conductive layer, and the third conductive layer includes a plurality of second transfer blocks; the second transfer block is located between the pixel electrode and the first active layer pattern and connects the pixel electrode and the first active layer pattern.

10. The array substrate according to claim 9, wherein, it further includes: a plurality of touch electrodes, located between the third conductive layer and the plurality of pixel electrodes; the orthographic projection of the touch lead on the substrate is located within the range of the orthographic projection of the first signal line on the substrate, and the touch lead is connected to the touch electrode.

11. The array substrate according to any one of claims 1 to 10, wherein, where, in the orthographic projection onto the substrate, at least one of the first signal lines is provided between any two adjacent touch leads.

12. The array substrate according to claim 11, wherein, in the orthographic projection onto the substrate, two of the first signal lines are provided between any two adjacent touch leads.

13. The array substrate according to any one of claims 1 to 10, wherein, in the orthographic projection onto the substrate, a plurality of the first signal lines overlap with a plurality of touch leads in a one-to-one correspondence.

14. The array substrate according to any one of claims 1 to 10, wherein, the ratio of the resistivity of the touch lead to the thickness of the touch lead is less than or equal to 0.

3.

15. A display device, wherein, it includes: the array substrate according to any one of claims 1 to 14; a color filter substrate, disposed opposite to the array substrate; a liquid crystal layer, located between the array substrate and the color filter substrate.

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