Display substrate, display panel and display device

Abstract

The invention discloses a display substrate, a display panel and a display device. The display substrate comprises a pixel array, a source and drain electrode layer and a plurality of scanning line groups. The source and drain electrode layer comprises a plurality of data lines and a plurality of first touch lines. The pixel array comprises a plurality of pixel groups arranged in the row direction, and each pixel group comprises a first sub-pixel column and a second sub-pixel column which are adjacent to each other. The data lines are arranged between the first sub-pixel columns and the second sub-pixel columns. The first touch lines are arranged between two adjacent pixel groups. And a plurality of adjacent first touch lines are connected in parallel to form a first touch coil. Each scanning line group corresponds to one pixel row and comprises a first scanning line and a second scanning line which are arranged on the two sides of the corresponding pixel row respectively. The first scanning lines and the second scanning lines extend in the row direction, the first scanning lines are connected with pixels, located in the first sub-pixel columns, in the corresponding pixel rows, and the second scanning lines are connected with pixels, located in the second sub-pixel columns, in the corresponding pixel rows.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device. Background Art

[0002] For large and medium-sized display panels, the large size and high resolution mean that more IC channels are required. However, considering the current shortage of driving IC resources and the rising prices of raw materials in the semiconductor industry, it is particularly important to reduce the usage of display driver chips. At the same time, electromagnetic touch technology can also be applied to large and medium-sized display panels to achieve electromagnetic touch by forming built-in electromagnetic coils.

[0003] Therefore, how to improve the display effect of the display panel while effectively realizing electromagnetic touch and reducing the semiconductor manufacturing cost has become an urgent problem to be solved. Summary of the Invention

[0004] The present application discloses a display substrate, which includes: a substrate, a pixel array disposed on the substrate, a source-drain electrode layer, and multiple scanning line groups, wherein the source-drain electrode layer includes multiple data lines and multiple first touch lines;

[0005] The pixel array includes multiple pixel groups arranged in the row direction. Each pixel group includes adjacent first sub-pixel columns and second sub-pixel columns. The data lines are disposed between the first sub-pixel columns and the second sub-pixel columns and are connected to the first sub-pixel columns and the second sub-pixel columns. The first touch lines are disposed between two adjacent pixel groups and extend in the column direction; multiple adjacent first touch lines are connected in parallel to form a first touch coil, and multiple first touch coils are arranged in the row direction;

[0006] Each scanning line group corresponds to a pixel row respectively. The scanning line group includes a first scanning line and a second scanning line respectively disposed on both sides of the corresponding pixel row. The first scanning line and the second scanning line both extend in the row direction. The first scanning line is connected to the pixels in the first sub-pixel columns of the corresponding pixel row, and the second scanning line is connected to the pixels in the second sub-pixel columns of the corresponding pixel row.

[0007] In some embodiments, it further includes:

[0008] A gate layer, disposed on one side of the substrate, includes the multiple scanning line groups and a common electrode line;

[0009] A gate insulating layer, disposed on the side of the gate layer away from the substrate and covering the multiple scanning line groups and the common electrode line;

[0010] The active layer is disposed on a side of the gate insulating layer away from the substrate.

[0011] In some embodiments, it further includes:

[0012] The pixel electrode layer is disposed on a side of the gate insulating layer away from the substrate. The pixel electrode layer includes a plurality of pixel electrodes that are spaced apart from each other. The source-drain electrode layer is disposed on a side of the active layer and the pixel electrode layer away from the substrate;

[0013] The first insulating layer is disposed on a side of the source-drain electrode layer away from the substrate and covers the source-drain electrode layer and the pixel electrode layer;

[0014] The touch control electrode layer is disposed on a side of the first insulating layer away from the substrate. The touch control electrode layer includes a plurality of second touch control lines that extend along the row direction;

[0015] The second insulating layer is disposed on a side of the touch control electrode layer away from the substrate and covers the touch control electrode layer;

[0016] The common electrode layer is disposed on a side of the second insulating layer away from the substrate.

[0017] In some embodiments, the source-drain electrode layer is disposed on a side of the active layer away from the substrate.

[0018] In some embodiments, it further includes:

[0019] The first insulating layer is disposed on a side of the source-drain electrode layer away from the substrate and covers the source-drain electrode layer;

[0020] The touch control electrode layer is disposed on a side of the first insulating layer away from the substrate. The touch control electrode layer includes a plurality of second touch control lines that extend along the row direction.

[0021] In some embodiments, it further includes:

[0022] The second insulating layer is disposed on a side of the touch control electrode layer away from the substrate and covers the touch control electrode layer;

[0023] The pixel electrode layer is disposed on a side of the second insulating layer away from the substrate. The pixel electrode layer includes a plurality of pixel electrodes.

[0024] In some embodiments, it further includes:

[0025] The first insulating layer is disposed on a side of the source-drain electrode layer away from the substrate and covers the source-drain electrode layer;

[0026] An electrode layer is disposed on a side of the first insulating layer away from the substrate. The electrode layer includes a plurality of pixel electrodes and a common electrode, and the common electrode is disposed between adjacent pixel electrodes.

[0027] A second insulating layer is disposed on a side of the electrode layer away from the substrate and covers the pixel electrodes and the common electrode.

[0028] A touch control electrode layer is disposed on a side of the second insulating layer away from the substrate. The touch control electrode layer includes a plurality of second touch control lines that extend in a row direction.

[0029] In some embodiments, within the same first touch control coil, first ends of all the first touch control lines are connected to a first touch control connection line, and second ends of all the first touch control lines are connected to a second touch control connection line.

[0030] In some embodiments, first ends of all the first touch control lines within all the first touch control coils are connected to the same first touch control connection line;

[0031] Second ends of different first touch control coils are connected to different second touch control connection lines.

[0032] In some embodiments, different touch control connection lines are connected to different pins of an electromagnetic induction circuit board.

[0033] In some embodiments, there are further a plurality of second touch control lines that extend in the row direction;

[0034] Adjacent second touch control lines are connected in parallel to form a second touch control coil, and a plurality of second touch control coils are arranged in sequence in a column direction;

[0035] Within the same second touch control coil, first ends of all the second touch control lines are connected to a third touch control connection line, and second ends of all the second touch control lines are connected to a fourth touch control connection line.

[0036] In some embodiments, first ends of all the second touch control lines within all the second touch control coils are connected to the same third touch control connection line;

[0037] Second ends of different second touch control coils are connected to different fourth touch control connection lines.

[0038] In some embodiments, different touch control connection lines are connected to different pins of an electromagnetic induction circuit board.

[0039] This application also discloses a display panel, and the display panel includes the display substrate as described above.

[0040] This application further discloses a display device, and the display device includes the display panel as described above.

[0041] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0043] Figure 1 Schematic structural diagram of an embodiment of a display substrate provided for this application;

[0044] Figure 2 Schematic diagram of a manufacturing process flow of an embodiment of an ADS type display substrate provided for this application;

[0045] Figure 3 Schematic cross-sectional structural diagram of an embodiment of an ADS type display substrate provided for this application;

[0046] Figure 4 Schematic diagram of a manufacturing process flow of an embodiment of a TN type display substrate provided for this application;

[0047] Figure 5 Schematic cross-sectional structural diagram of an embodiment of a TN type display substrate provided for this application;

[0048] Figure 6 Schematic diagram of a manufacturing process flow of an embodiment of an IPS type display substrate provided for this application;

[0049] Figure 7 Schematic cross-sectional structural diagram along the column direction of an embodiment of an IPS type display substrate provided for this application;

[0050] Figure 8 Schematic cross-sectional structural diagram along the row direction of an embodiment of an IPS type display substrate provided for this application;

[0051] Figure 9 Schematic diagram of an embodiment of the connection relationship between multiple first touch lines and a circuit board in a display substrate provided for this application;

[0052] Figure 10 Schematic diagram of an embodiment of the connection relationship between multiple second touch lines and a circuit board in a display substrate provided for this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0054] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in this specification should have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. The terms "first", "second" and similar words used in this specification and the appended claims do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not denote a quantity limitation, but rather denote the presence of one. "Plurality" or "several" means two or more. Unless otherwise indicated, words such as "front", "rear", "lower" and / or "upper" are for convenience of description only and are not limited to one position or a spatial orientation. The words such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The words such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0055] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0056] Please refer to Figure 1 , which shows a schematic structural diagram of an embodiment of a display substrate provided by this application.

[0057] In this embodiment, the display substrate 100 includes a substrate ( Figure 1 not shown in

[0058] The pixel array 10 is formed by arranging a plurality of pixels P in the row direction X and the column direction Y, and includes a plurality of pixel groups 11 arranged in the row direction X. Each pixel group 11 includes an adjacent first sub-pixel column 111 and a second sub-pixel column 112. Data lines S1, S2, …, Sn are disposed between the first sub-pixel column 111 and the second sub-pixel column 112. Each data line S1, S2, …, Sn is connected to two sub-pixel columns 111 and 112 in a pixel group 11. First touch lines Q1, Q2, …, Qn are disposed between two adjacent pixel groups 11. The data lines S1, S2, …, Sn and the first touch lines Q1, Q2, …, Qn both extend in the column direction Y.

[0059] Each scan line group includes a first scan line and a second scan line respectively disposed on both sides of each pixel row. For example Figure 1 in, the scan line group G1 includes a first scan line G11 and a second scan line G12 respectively located on both sides of the first pixel row, the scan line group G2 includes a first scan line G21 and a second scan line G22 respectively located on both sides of the second pixel row, the scan line group G3 includes a first scan line G31 and a second scan line G32 respectively located on both sides of the third pixel row, the scan line group G(m - 1) includes a first scan line G(m - 1)1 and a second scan line G(m - 1)2 located on both sides of the (m - 1)th pixel row, and the scan line group Gm includes a first scan line Gm1 and a second scan line Gm2 located on both sides of the mth pixel row. The first scan lines G11, G21, G31, …, G(m - 1)1, Gm1 extend in the row direction X of the pixel array and are respectively connected to the pixels located in the respective first sub-pixel columns 111 in a corresponding pixel row. The second scan lines G12, G22, G32, …, G(m - 1)2, Gm2 extend in the row direction X of the pixel array and are respectively connected to the pixels located in the respective second sub-pixel columns 112 in a corresponding pixel row.

[0060] In some embodiments, the display substrate 100 further includes thin film transistors (not shown in the figure) corresponding to the pixels P in the pixel array one by one. The gate of each thin film transistor is connected to the first scan lines G11, G21, G31, …, G(m - 1)1, Gm1 or the second scan lines G12, G22, G32, …, G(m - 1)2, Gm2. The first pole of each thin film transistor is connected to a data line S1, S2, …, Sn. The second pole of each thin film transistor is connected to a corresponding pixel (specifically, it can be connected to the pixel electrode of the pixel).

[0061] The display substrate provided in this embodiment adopts a Dual Gate design (where one pixel row is driven by two scan lines). By using one data line to transmit drive signals to two adjacent columns of pixels in a pixel group, the number of data lines can be halved, thereby reducing the number of IC channels. A first touch line is provided between adjacent pixel groups, such that a first touch line extending in the column direction can be provided between every two columns of pixels, which is beneficial to increasing the density and number of the first touch lines and reducing the resistance of the first touch lines. The first touch line and the data line are arranged on the same layer (i.e., the source-drain electrode layer) and can be fabricated using the same mask, which is beneficial to simplifying the manufacturing process. Moreover, both the first touch line and the data line are arranged between adjacent sub-pixel columns, and there is no need to provide the first touch line in the pixel area, so the pixel aperture ratio can be increased, the transmittance of the display substrate can be improved, and high image quality and display effects can be achieved.

[0062] The display substrate provided in this application can be an ADS type display substrate. The structure and manufacturing method of the ADS type display substrate can be as Figures 1 to 3 shown. Among them, Figure 1 can be regarded as a top view schematic diagram of an ADS type display substrate, Figure 2 is a schematic diagram of the manufacturing process of an ADS type display substrate, Figure 3 is a schematic cross-sectional structure diagram of an ADS type display substrate.

[0063] Please refer to Figure 2 and Figure 3 . And when necessary, in combination with Figure 1 , the gate layer 22 can be provided on one surface of the substrate 21 (i.e., the front surface of the substrate 21). The gate layer 22 can include a plurality of scan lines 227, a common electrode line 223, and a plurality of gates 221. The scan lines 227 and the common electrode line 223 are arranged at intervals and both extend in the row direction. The scan lines 227 are similar to or are Figure 1 the first scan lines G11, G21, G31, …, G(m - 1)1, Gm1 and the second scan lines G12, G22, G32, …, G(m - 1)2, Gm2 in

[0064] Since the common electrode line 223 and the scanning line 227 are provided on the same layer, during fabrication, they can be fabricated synchronously, which is beneficial to reducing the fabrication cost. For example, a whole layer of metal material layer (such as copper, aluminum, silver, etc.) can be first formed, and then by etching, some regions of the metal material layer are removed to form a plurality of spaced scanning lines 227 and one or more common electrode lines 223, thereby obtaining the gate layer 22. In some embodiments, the common electrode line 223 can also be fabricated on a different layer from the scanning line 227. The common electrode line 223 can be fabricated using a separate film layer.

[0065] The gate insulating layer 23 can be provided on the side of the gate layer 22 away from the substrate 21 and cover the scanning line 227, the common electrode line 223, and the region of the substrate 21 not covered by the scanning line 227 and the common electrode line 223. The material of the gate insulating layer 23 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0066] The active layer 24 can be provided on the side of the gate insulating layer 23 away from the substrate 21. The active layer 24 can include a source region, a drain region, and a channel located between the source region and the drain region, and is used to form a thin film transistor. The material of the active layer 24 can be single crystal silicon, polycrystalline silicon, or oxide, etc.

[0067] The pixel electrode layer 25 can be provided on the side of the gate insulating layer 23 away from the substrate 21. The pixel electrode layer 25 can be provided at an interval from the active layer 24. The pixel electrode layer 25 can include a plurality of pixel electrodes, and the plurality of pixel electrodes are spaced from each other, and each of the pixel electrodes corresponds to a sub-pixel. The material of the pixel electrode layer 25 can be a transparent metal, such as ITO (indium tin oxide).

[0068] The source-drain electrode layer 26 can be provided on the side of the active layer 24 and the pixel electrode layer 25 away from the substrate 21. The source-drain electrode layer 26 can include a plurality of data lines ( Figure 3 not shown in the figure, please refer to Figure 1 ), and each data line extends along the column direction. The data line covers the surface of the active layer and can be connected to the drain region of the active layer. The source-drain electrode layer 26 can also include a plurality of first touch lines (not shown in the figure), and each first touch line extends along the column direction. The plurality of data lines and the plurality of first touch lines are alternately arranged in the row direction. The source-drain electrode layer 26 is similar to or is Figure 1 the source-drain electrode layer 40 in Figure 1 . The data line is similar to or is Figure 1The first touch lines Q1, Q2, …, Qn therein. The source-drain electrode layer 26 may further include a plurality of source electrodes 265 and a plurality of drain electrodes 267. One end of each source electrode 265 is connected to a data line, and the other end is connected to the source region of the active layer 24; one end of each drain electrode 267 is connected to the drain region of the active layer 24, and the other end of the drain electrode 267 is overlapped with the pixel electrode of the corresponding pixel, thereby realizing the connection between the thin-film transistor and the pixel.

[0069] The first insulating layer 27 may be disposed on a side of the source-drain electrode layer 26 away from the substrate 21, and cover the source-drain electrode layer 26, the pixel electrode layer 25, and the region of the gate insulating layer 23 that is not covered by the source-drain electrode layer 26 and the pixel electrode layer 25. The material of the first insulating layer 27 may be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0070] The touch electrode layer 28 may be disposed on a side of the first insulating layer 27 away from the substrate 21. The touch electrode layer 28 may include a plurality of second touch lines 282, and each second touch line 282 extends along the row direction. The plurality of second touch lines 282 and the plurality of first touch lines are arranged in a crossed manner, and touch points may be formed at the crossing positions thereof. The material of the touch electrode layer 28 may be a metal such as copper, aluminum, silver, etc. The second touch line 282 is similar to or is Figure 1 the second touch lines R1, R2, R3, …, Rm-1, Rm therein. One second touch line 282 may be disposed between adjacent pixel rows, or one second touch line 282 may be disposed between every two pixel rows or more pixel rows.

[0071] The second insulating layer 285 may be disposed on a side of the touch electrode layer 28 away from the substrate 21, and cover the touch electrode layer 28 and the region of the first insulating layer 27 that is not covered by the touch electrode layer 28. The material of the second insulating layer 285 may be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0072] The common electrode layer 29 may be disposed on a side of the second insulating layer 285 away from the substrate 21. The common electrode layer 29 may include a plurality of common electrodes located within the sub-pixels. The common electrodes are slit electrodes so as to form a multi-dimensional electric field with the pixel electrodes, and adjacent common electrodes may be connected through a common electrode line 223. The material of the common electrode layer 29 may be a transparent metal, such as ITO (indium tin oxide). The common electrode layer 29 may form an electric field with the pixel electrode layer 25 for controlling the brightness of each pixel.

[0073] The display substrate provided by this application may also be a TN-type display substrate. The structure and manufacturing method of the TN-type display substrate may be as Figure 4 and Figure 5 and Figure 1 shown. Among them, Figure 1 may be a top view schematic diagram of the TN-type display substrate, Figure 4It is a schematic diagram of the manufacturing process of a TN-type display substrate. Figure 5 It is a schematic cross-sectional structure diagram of a TN-type display substrate.

[0074] Please refer to Figure 4 and Figure 5 , and in combination with Figure 1 if necessary. The gate layer 32 can be disposed on one surface of the substrate 31 (i.e., the front side of the substrate 31). The gate layer 32 can include a plurality of scan lines 321, a plurality of gates 325, and a common electrode line 323. The scan lines 321 and the common electrode line 323 are arranged at intervals and both extend in the row direction. The scan lines 321 are similar to or are Figure 1 the first scan lines G11, G21, G31,..., G(m - 1)1, Gm1 and the second scan lines G12, G22, G32,..., G(m - 1)2, Gm2 in The gates 325 are connected to the corresponding scan lines 321 for receiving electrical signals from the scan lines 321. The gates 325 correspond to the positions of the channels in the active layer and are used to turn on and off the thin film transistors. The common electrode line 323 is used to connect a plurality of common electrodes or all the common electrodes located in another film layer.

[0075] Since the common electrode line 323 and the scan lines 321 are provided on the same layer, during manufacturing, the two can be fabricated synchronously, which is beneficial to reducing the manufacturing cost. For example, a whole layer of metal material layer (such as copper, aluminum, silver, etc.) can be formed first, and then part of the metal material layer is removed by etching to form spaced-apart scan lines 321 and one or more common electrode lines 323, thereby obtaining the gate layer 32. In some embodiments, the common electrode line 323 can also be fabricated on a different layer from the scan lines 321. The common electrode line 323 can be fabricated using a separate film layer.

[0076] The gate insulating layer 33 can be disposed on the side of the gate layer 32 away from the substrate 31 and cover the scan lines 321, the common electrode line 323, and the area of the substrate 31 not covered by the scan lines 321 and the common electrode line 323. The material of the gate insulating layer 33 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0077] The active layer 34 can be disposed on the side of the gate insulating layer 33 away from the substrate 31. The active layer 34 can include a source region, a drain region, and a channel located between the source region and the drain region for forming a thin film transistor. The material of the active layer 34 can be single crystal silicon, polycrystalline silicon, or oxide, etc.

[0078] The source-drain electrode layer 36 can be disposed on the side of the active layer 34 away from the substrate 31. The source-drain electrode layer 36 can include a plurality of data lines ( Figure 5 not shown in Figure 1)With multiple source electrodes 365, each data line extends in the column direction. One end of the source electrode 365 is connected to a corresponding data line, and the other end covers the source region of the active layer 34. The source-drain electrode layer 36 may further include a plurality of first touch lines (not shown in the figure), and each first touch line extends in the column direction. The plurality of data lines and the plurality of first touch lines are alternately arranged in the row direction. The source-drain electrode layer 36 is similar to or is Figure 1 the source-drain electrode layer 40 in Figure 1 The data lines are similar to or are Figure 1 the data lines S1, S2, …, Sn in

[0079] The first insulating layer 371 may be disposed on the side of the source-drain electrode layer 36 away from the substrate 31, and covers the source-drain electrode layer 36 and the region of the gate insulating layer 33 not covered by the source-drain electrode layer 36. The material of the first insulating layer 371 may be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0080] The touch electrode layer 38 may be disposed on the side of the first insulating layer 371 away from the substrate 31. The touch electrode layer 38 may include a plurality of second touch lines 382, and each second touch line 382 extends in the row direction. The plurality of second touch lines 382 and the plurality of first touch lines are cross-arranged, and touch points may be formed at the intersections thereof. The material of the touch electrode layer 38 may be a metal such as copper, aluminum, silver, etc. The second touch line 382 is similar to or is Figure 1 the second touch lines R1, R2, R3, …, Rm-1, Rm in

[0081] The second insulating layer 373 may be disposed on the side of the touch electrode layer 38 away from the substrate 31, and covers the touch electrode layer 38 and the region of the first insulating layer 371 not covered by the touch electrode layer 38. The material of the second insulating layer 373 may be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0082] The pixel electrode layer 39 may be disposed on the side of the second insulating layer 373 away from the substrate 31. The pixel electrode layer 35 may include a plurality of pixel electrodes, and the plurality of pixel electrodes are spaced apart from each other, and each of the pixel electrodes corresponds to a pixel. The material of the pixel electrode layer 35 may be a transparent metal, such as ITO (indium tin oxide). Among them, the pixel electrode may be connected to the drain electrode 367 through a through hole (not marked in the figure), and the through hole sequentially penetrates the second insulating layer 373 and the first insulating layer 371 to expose the data line.

[0083] The display substrate provided by this application can also be an IPS type display substrate. The structure and manufacturing method of the IPS type display substrate can be as Figures 6 to 8 and Figure 1 shown. Among them, Figure 1 can be a top view schematic diagram of the IPS type display substrate, Figure 6 is a schematic diagram of the manufacturing process of the IPS type display substrate, Figure 7 is a schematic cross-sectional structure diagram of the IPS type display substrate along the column direction, Figure 8 is a schematic cross-sectional structure diagram of the IPS type display substrate along the row direction.

[0084] Please refer to Figure 6 and Figure 8 and, if necessary, in combination with Figure 1 , the gate layer 42 can be disposed on a surface of the substrate 41 (i.e., the front side of the substrate 41). The gate layer 42 can include a gate 421, a scan line 427, and a common electrode line 423. The scan line 427 and the common electrode line 423 are arranged at intervals and both extend along the row direction. The scan line 427 is similar to or is Figure 1 the first scan lines G11, G21, G31, …, G(m - 1)1, Gm1 and the second scan lines G12, G22, G32, …, G(m - 1)2, Gm2 in

[0085] . The common electrode line 423 is used to connect multiple common electrodes or all common electrodes located in another film layer. The gate 421 is connected to the corresponding scan line 427 for receiving an electrical signal from the scan line 427. The gate 421 corresponds to the position of the channel in the active layer for turning on or off the thin film transistor.

[0086] Since the common electrode line 423 and the scan line 427 are arranged in the same layer, during manufacturing, the two can be fabricated synchronously, which is beneficial to reducing the manufacturing cost. For example, a whole layer of metal material layer (such as copper, aluminum, silver, etc.) can be first formed, and then part of the metal material layer is removed by etching to form multiple spaced scan lines 427 and one or more common electrode lines 423, thereby obtaining the gate layer 42. In some embodiments, the common electrode line 423 can also be fabricated in a different layer from the scan line 427. The common electrode line 423 can be fabricated using a separate film layer.

[0087] The active layer 44 can be disposed on a side of the gate insulating layer 43 away from the substrate 41. The active layer 44 can include a source region, a drain region, and a channel located between the source region and the drain region, and is used to form a thin film transistor. The material of the active layer 44 can be single crystal silicon, polycrystalline silicon, etc.

[0088] The source-drain electrode layer 46 can be disposed on a side of the active layer 44 away from the substrate 41. The source-drain electrode layer 46 can include a plurality of data lines ( Figure 7 and Figure 8 not shown in the figure) and a plurality of source electrodes 462. Each data line extends along the column direction. The source electrode 462 is connected to a corresponding data line and is used to receive an electrical signal from the data line. The source electrode 462 covers a part of the surface of the active layer 44 and is used to connect the source region of the active layer 44. The source-drain electrode layer 46 can further include a plurality of first touch lines ( Figure 7 and Figure 8 not shown in the figure). Each first touch line extends along the column direction. The plurality of data lines and the plurality of first touch lines are alternately arranged in the row direction. The source-drain electrode layer 46 is similar to or is Figure 1 the source-drain electrode layer 40 in Figure 1 . The data lines are similar to or are Figure 1 the data lines S1, S2,..., Sn in

[0089] The first insulating layer 47 can be disposed on a side of the source-drain electrode layer 46 away from the substrate 41 and covers the source-drain electrode layer 46 and the region of the gate insulating layer 43 not covered by the source-drain electrode layer 46. The material of the first insulating layer 47 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0090] The electrode layer 490 can be disposed on a side of the first insulating layer 47 away from the substrate 41. The electrode layer 490 includes a plurality of pixel electrodes 45. The plurality of pixel electrodes 45 are spaced apart from each other, and each of the pixel electrodes 45 corresponds to a pixel. The electrode layer 490 further includes a common electrode 49. The common electrode 49 can be disposed between adjacent pixel electrodes 45 and is used to cooperate with the corresponding pixel electrode 45 to form an electric field for controlling pixel display. The material of the electrode layer 490 can be a transparent metal, such as ITO (indium tin oxide).

[0091] The second insulating layer 485 can be disposed on a side of the electrode layer 490 away from the substrate 41 and covers the pixel electrodes 45, the common electrode 49, and the region of the first insulating layer 47 not covered by the pixel electrodes 45 and the common electrode 49. The material of the second insulating layer 485 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0092] The touch control electrode layer 48 can be disposed on a side of the second insulating layer 485 away from the substrate 41. The touch control electrode layer 48 can include a plurality of second touch control lines 482, and each second touch control line 482 extends in the row direction. The plurality of second touch control lines 482 are arranged to cross the plurality of first touch control lines, and touch control points can be formed at the intersections of the two. The material of the touch control electrode layer 48 can be a metal such as copper, aluminum, silver, etc. The second touch control line 482 is similar to or is Figure 1 the second touch control lines R1, R2, R3, …, Rm-1, Rm in

[0093] Figure 9 FIG. is a schematic diagram of an embodiment of the connection relationship between a plurality of first touch control lines in the display substrate provided by the present application and a circuit board. Please refer to Figure 9 and, if necessary, in combination with Figure 1 , pixels cover the entire pixel area 85. The area between the outermost edge 83 of the display substrate and the pixel area 85 is the edge area 87. Each of the first touch control lines Q1, Q2, Q3, Q4, …, Qn-1, Qn extends in the column direction. The plurality of first touch control lines Q1, Q2, Q3, Q4, …, Qn-1, Qn cover the pixel area 85 evenly or substantially evenly.

[0094] Adjacent first touch control lines can be connected in parallel to form a first touch control coil X. A plurality of first touch control coils X1, X2, X3, …, X(j-2), X(j-1), Xj are arranged in sequence in the row direction. For example, the first touch control lines Q1, Q2, Q3, Q4 are connected in parallel to form the first touch control coil X1, …, the first touch control lines Qn-3, Qn-2, Qn-1, Qn are connected in parallel to form the first touch control coil Xj. Among them, j can be any integer. For example, k can be 36. That is, the number of groups of the first touch control coil X can be 36.

[0095] The "a plurality of" described in the text includes two and more than two. In some embodiments, every two first touch control lines can be connected in parallel to form a first touch control coil. In some embodiments, every three first touch control lines can be connected in parallel to form a first touch control coil. In some embodiments, every five first touch control lines can be connected in parallel to form a first touch control coil.

[0096] Within the same first touch control coil X, one end of all the first touch control lines is connected to a first touch control connection line 14, and the other end of all the first touch control lines is connected to a second touch control connection line 143. For example, within the first touch control coil X1, the first ends of all the first touch control lines Q1, Q2, Q3, Q4 ( Figure 9The upper ends thereof are connected to the first touch connection line 14, and the second ends of all the first touch lines Q1, Q2, Q3, Q4 ( Figure 9 the lower ends thereof) are connected to the second touch connection line 143.

[0097] In some embodiments, the first ends of all the first touch lines Q1, Q2, Q3, Q4, …, Qn-1, Qn of all the first touch coils X1, X2, X3, …, X(j-2), X(j-1), Xj are connected to the same first touch connection line 14. Thus, the first touch connection line 14 can be referred to as the global touch connection line 14. The second ends of different first touch coils X1, X2, X3, …, X(j-2), X(j-1), Xj are connected to different second touch connection lines 143. Thus, the second touch connection lines 143 can be referred to as local touch connection lines 143).

[0098] The global touch connection line 14 and the multiple local touch connection lines 143 can be respectively connected to different pins 812 of the electromagnetic induction circuit board 81. Both ends of the global touch connection line 14 can be respectively connected to a pin 812 of the electromagnetic induction circuit board 81 through a wire 52, and the multiple local touch connection lines 143 can be connected to other pins 812 of the electromagnetic induction circuit board 81 through other wires 53.

[0099] In some embodiments, the global touch connection line 14, the local touch connection lines 143, and the first touch coils X1, X2, X3, …, X(j-2), X(j-1), Xj can be arranged on the same layer. In some embodiments, the global touch connection line 14 and the local touch connection lines 143 can be arranged on the same layer, but not on the same layer as the first touch coils X1, X2, X3, …, X(j-2), X(j-1), Xj, and they can be connected through metal vias.

[0100] In some embodiments, the global touch connection line 14 can be arranged in the edge area 87. In some embodiments, the electromagnetic induction circuit board 81 can be arranged in the edge area 87. In some embodiments, both the global touch connection line 14 and the local touch connection lines 143 can extend along the row direction. In some embodiments, the electromagnetic induction circuit board 81 can be a flexible printed circuit (FPC) that realizes the touch function by electromagnetic induction.

[0101] In the above embodiments, by arranging the touch connection line 14 that extends along the row direction, touch voltage drift can be prevented. Touch voltage drift easily causes the display greenish phenomenon where the red pixels and blue pixels are darker and the green pixels are brighter.

[0102] Figure 10 It is a schematic diagram of an embodiment of the connection relationship between multiple second touch lines in the display substrate provided by the present application and the circuit board. Please refer toFigure 10 and combine, if necessary, with Figure 1 , the pixels cover the entire pixel area 85. The area between the outermost edge 83 of the display substrate and the pixel area 85 is the edge area 87. Each of the second touch lines R1, R2, R3, R4, …, Rm-3, Rm-2, Rm-1, Rm extends in the row direction. A plurality of second touch lines R1, R2, R3, R4, …, Rm-3, Rm-2, Rm-1, Rm are evenly or substantially evenly distributed over the pixel area 85.

[0103] Adjacent second touch lines can be connected in parallel to form a second touch coil Y. A plurality of second touch coils Y1, Y2, Y3, …, Y(k-2), Y(k-1), Yk are arranged in sequence in the column direction. For example, the second touch lines R1, R2, R3, R4 are connected in parallel to form the second touch coil Y1, …, the second touch lines Rm-3, Rm-2, Rm-1, Rm are connected in parallel to form the second touch coil Yk. Wherein, k can be any positive integer. For example, k can be 23. That is, the number of groups of the second touch coils can be 23.

[0104] The "a plurality" described in the text includes two and more than two. In some embodiments, every two second touch lines can be connected in parallel to form a second touch coil. In some embodiments, every three second touch lines can be connected in parallel to form a second touch coil. In some embodiments, every five second touch lines can be connected in parallel to form a second touch coil.

[0105] Within the same second touch coil Y, one end of all the second touch lines is connected to a third touch connection line 74, and the other end of all the second touch lines is connected to a fourth touch connection line 743. For example, within the second touch coil Y1, the first ends ( Figure 10 the left ends in Figure 10 ) of all the second touch lines R1, R2, R3, R4 are connected to the third touch connection line 74, and the second ends (

[0106] the right ends in

[0107] The global touch connection line 74 and multiple local touch connection lines 743 can be respectively connected to different pins 812 of the electromagnetic induction circuit board 81. One end of the global touch connection line 74 ( Figure 10 the lower end in the figure) can be connected to a pin 812 of the electromagnetic induction circuit board 81 through a wire 52, and multiple local touch connection lines 743 can be connected to other pins 812 of the electromagnetic induction circuit board 81 through other wires 53.

[0108] In some embodiments, the global touch connection line 74 can be arranged in the edge area 87. In some embodiments, the electromagnetic induction circuit board 81 can be arranged in the edge area 87. In some embodiments, both the global touch connection line 74 and the local touch connection lines 743 can extend along the column direction.

[0109] In some embodiments, the global touch connection line 74, the local touch connection lines 743, and the second touch coils Y1, Y2, Y3, …, Y(k - 2), Y(k - 1), Yk can be arranged on the same layer. In some embodiments, the global touch connection line 74 and the local touch connection lines 743 can be arranged on the same layer, but not on the same layer as the second touch coils Y1, Y2, Y3, …, Y(k - 2), Y(k - 1), Yk, and they can be connected through metal vias.

[0110] In some embodiments, the electromagnetic induction circuit board connected to the second touch coils Y1, Y2, Y3, …, Y(k - 2), Y(k - 1), Yk and the electromagnetic induction circuit board connected to the first touch coils X1, X2, X3, …, X(j - 2), X(j - 1), Xj can be the same circuit board. Just connect them to different pins of the circuit board.

[0111] This application also provides a display panel. The display panel may include the display substrate as described above and a color filter substrate disposed opposite to the display substrate.

[0112] This application also provides a display device. The display device can be a liquid crystal display device, such as a mobile phone, and includes the display panel as described above.

[0113] It can be understood that the display device may further include well-known structures such as a backlight, a light guide plate, a liquid crystal layer, a polarizer, and a protective glass located between the display substrate and the color filter substrate, which will not be elaborated here.

[0114] Other embodiments of the present specification will be readily conceived by those skilled in the art after considering the specification and practicing the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present specification, which follow the general principles of the present specification and include known common general knowledge or conventional technical means in the technical field not claimed in the present specification. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present specification are pointed out by the following claims.

[0115] It should be understood that the present specification is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present specification is only limited by the appended claims.

[0116] The above are only the preferred embodiments of the present specification, and are not intended to limit the present specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present specification shall be included within the scope of protection of the present specification.

Claims

1. A display substrate, characterized in that, it includes: a substrate, a pixel array disposed on the substrate, a source-drain electrode layer, and a plurality of scan line groups, wherein the source-drain electrode layer includes a plurality of data lines and a plurality of first touch lines; the pixel array includes a plurality of pixel groups arranged in a row direction, each pixel group includes adjacent first sub-pixel columns and second sub-pixel columns, the data lines are disposed between the first sub-pixel columns and the second sub-pixel columns and are connected to the first sub-pixel columns and the second sub-pixel columns, the first touch line is disposed between two adjacent pixel groups and extends in a column direction; a plurality of adjacent first touch lines are connected in parallel to form a first touch coil, and a plurality of first touch coils are arranged in a row direction; each scan line group corresponds to a pixel row respectively, the scan line group includes a first scan line and a second scan line respectively disposed on two sides of the corresponding pixel row, both the first scan line and the second scan line extend in the row direction, the first scan line is connected to the pixels in each first sub-pixel column in the corresponding pixel row, and the second scan line is connected to the pixels in each second sub-pixel column in the corresponding pixel row.

2. The display substrate according to claim 1, characterized in that, it further includes: a gate layer, disposed on one side of the substrate, including the plurality of scan line groups and a common electrode line; a gate insulating layer, disposed on the side of the gate layer away from the substrate and covering the plurality of scan line groups and the common electrode line; an active layer, disposed on the side of the gate insulating layer away from the substrate.

3. The display substrate according to claim 2, characterized in that, it further includes: a pixel electrode layer, disposed on the side of the gate insulating layer away from the substrate, the pixel electrode layer includes a plurality of pixel electrodes, the plurality of pixel electrodes are spaced apart from each other, and the source-drain electrode layer is disposed on the side of the active layer and the pixel electrode layer away from the substrate; a first insulating layer, disposed on the side of the source-drain electrode layer away from the substrate and covering the source-drain electrode layer and the pixel electrode layer; a touch electrode layer, disposed on the side of the first insulating layer away from the substrate, the touch electrode layer includes a plurality of second touch lines, and the second touch lines extend in the row direction; a second insulating layer, disposed on the side of the touch electrode layer away from the substrate and covering the touch electrode layer; a common electrode layer, disposed on the side of the second insulating layer away from the substrate.

4. The display substrate according to claim 2, characterized in that, the source-drain electrode layer is disposed on the side of the active layer away from the substrate.

5. The display substrate according to claim 4, characterized in that, it further includes: a first insulating layer, disposed on the side of the source-drain electrode layer away from the substrate and covering the source-drain electrode layer; a touch electrode layer, disposed on the side of the first insulating layer away from the substrate, the touch electrode layer includes a plurality of second touch lines, and the second touch lines extend in a row direction.

6. The display substrate according to claim 5, characterized in that, it further includes: A second insulating layer is disposed on a side of the touch control electrode layer away from the substrate and covers the touch control electrode layer; A pixel electrode layer is disposed on a side of the second insulating layer away from the substrate, and the pixel electrode layer includes a plurality of pixel electrodes.

7. The display substrate according to claim 4, wherein, it further includes: A first insulating layer is disposed on a side of the source-drain electrode layer away from the substrate and covers the source-drain electrode layer; An electrode layer is disposed on a side of the first insulating layer away from the substrate, and the electrode layer includes a plurality of pixel electrodes and a common electrode, and the common electrode is disposed between adjacent pixel electrodes; A second insulating layer is disposed on a side of the electrode layer away from the substrate and covers the pixel electrodes and the common electrode; A touch control electrode layer is disposed on a side of the second insulating layer away from the substrate, and the touch control electrode layer includes a plurality of second touch control lines that extend in a row direction.

8. The display substrate according to claim 1, wherein, within the same first touch control coil, the first ends of all the first touch control lines are connected to a first touch control connection line, and the second ends of all the first touch control lines are connected to a second touch control connection line.

9. The display substrate according to claim 8, wherein, the first ends of all the first touch control lines within all the first touch control coils are connected to the same first touch control connection line; the second ends of different first touch control coils are connected to different second touch control connection lines.

10. The display substrate according to claim 8, wherein, different touch control connection lines are connected to different pins of the electromagnetic induction circuit board.

11. The display substrate according to claim 1, wherein, it further includes a plurality of second touch control lines that extend in the row direction; adjacent second touch control lines are connected in parallel to form a second touch control coil, and a plurality of second touch control coils are arranged in sequence in a column direction; within the same second touch control coil, the first ends of all the second touch control lines are connected to a third touch control connection line, and the second ends of all the second touch control lines are connected to a fourth touch control connection line.

12. The display substrate according to claim 11, wherein, the first ends of all the second touch control lines within all the second touch control coils are connected to the same third touch control connection line; the second ends of different second touch control coils are connected to different fourth touch control connection lines.

13. The display substrate according to claim 11, wherein, different touch control connection lines are connected to different pins of the electromagnetic induction circuit board.

14. A display panel, wherein, it includes the display substrate according to any one of claims 1 - 13.

15. A display device, wherein, it includes the display panel according to claim 14.

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