Reset isolation method and memory for server baseboard management controller chip

Abstract

The present invention relates to the technical field of baseboard management controllers, and specifically to a reset isolation method and memory for a server baseboard management controller chip, comprising: when a host computer or an internal processor reads or writes memory, first adding the read / write data to a cache, and then sending the read / write data via the cache; when the host computer or the internal processor triggers a reset operation, maintaining the read / write operation based on the cache, and isolating the memory reset instruction. In view of the problem that a baseboard management controller chip in the prior art may cause memory data loss and transmission interruption when a reset operation occurs, a cache mechanism is introduced to cache the read / write data of the host computer and the internal processor to maintain data transmission during the reset process, and at the same time isolate the reset host computer or internal processor to avoid memory data loss during the reset process, which may affect the normal operation of the internal processor or host computer on the other side.

Description

Technical Field

[0001] The present invention relates to the technical field of baseboard management controllers, and in particular to a reset isolation method and a memory of a server baseboard management controller chip. Background Art

[0002] The Baseboard Management Controller (BMC) chip is a controller designed specifically for server monitoring and management. The BMC chip is responsible for device information management, server status monitoring, remote control management, and maintenance management, ensuring stable and efficient server operation. It operates independently of the server's main system, running a small operating system on an integrated ARM processor with its own memory and flash memory. In current technology, the BMC chip communicates with the host computer (server) via PCIe. Multiple modules within the BMC chip are controlled by the BMC's CPU, while the display controller is controlled and driven by the host computer. The host computer and the BMC chip system share a shared memory space to read and write data.

[0003] For example, Chinese patent CN202311112118.9 discloses a server management board and server. The server management board includes: a BMC chip, a DDR memory stick, a CPLD chip, a serial port, an interface chip, a CPU slot, and a PCIe switch chip; the BMC chip is electrically connected to the DDR memory stick, the CPLD chip, and the CPU slot; the serial port is electrically connected to the CPLD chip via the interface chip, and the interface chip is used to convert the output level of the serial port to a level compatible with the BMC chip; the CPU slot is electrically connected to the first end of the PCIe switch chip, and the multiple second ends of the PCIe switch chip are used to connect to multiple computing boards.

[0004] However, since the DDR memory space is shared, when the host computer or baseboard management controller chip is reset, the reset side will reset the memory, resulting in memory data loss and data interruption on the opposite side. Summary of the Invention

[0005] In view of the above problems existing in the prior art, a reset isolation method and a memory of a server baseboard management controller chip are provided.

[0006] The specific technical solution is as follows: A reset isolation method for a server baseboard management controller chip, wherein the server baseboard management controller chip includes an internal processor and a bus, and the baseboard management controller chip is connected to a host computer and a memory; the host computer and the internal processor read and write the memory through the bus respectively; the reset isolation method includes: step S1: when the host computer or the internal processor reads and writes the memory, the read and write data is first added to the cache, and then the read and write data is sent through the cache; step S2: monitoring the host computer or the internal processor, and when the host computer or the internal processor triggers a reset operation, going to step S3; step S3: maintaining read and write operations based on the cache, and isolating the memory reset instructions output to the memory by the host computer or the internal processor that is being reset.

[0007] On the other hand, the step S1 includes: step S11: reading and identifying the operation instructions input into the bus by the host computer or the internal processor, and going to step S12 when it is determined to be a read-write instruction; step S12: when the read-write instruction is a read operation, obtaining read data from the memory and writing it into the cache, and, when the read-write instruction is a write operation, writing the write data into the cache in sequence; step S13: transmitting the read data from the cache to the host computer or the internal processor in sequence according to the read-write order, or, writing the write data into the memory in sequence according to the read-write order.

[0008] On the other hand, when executing step S12, a monitor is also created, and the monitor is used to monitor the internal processor or the host computer in step S2.

[0009] On the other hand, in the step S12, when the read and write instructions are executed, a corresponding cache index is constructed for the read data or the write data; in the step S13, a first-in-first-out operation is performed according to the cache index.

[0010] On the other hand, the step S2 includes: collecting, by the monitor, operation instructions issued by the internal processor or the host computer to the bus, and determining whether a reset operation occurs.

[0011] On the other hand, the step S3 includes: step S31: isolating the memory reset instruction and determining whether the currently executed operation is a read operation; if so, going to step S32; if not, going to step S33; step S32: waiting for the host computer or the internal processor to complete the reset, and continuing to send the read data to the host computer or the internal processor in accordance with the read-write order; step S33: continuing to send the write data to the memory in accordance with the read-write order, and continuing to write to the cache after the host computer or the internal processor completes the reset.

[0012] On the other hand, before executing step S32 or step S33, it also includes: step A31: in the cache, each data of the read and write operations is marked separately, and a read and write timer is started at each transmission operation; step A32: when the read and write timer times out, it is considered that the host computer or the internal processor is being reset.

[0013] On the other hand, when executing step S32 or step S33, the interruption point is determined according to the operation flag, and the read / write data is resent.

[0014] On the other hand, the process of executing step S3 further includes: step A4: when the internal processor on the other side or the host computer issues a read / write instruction, the bus operates the memory and obtains the read / write data.

[0015] A memory includes computer instructions. When a computer device runs the computer instructions, the reset isolation method is executed.

[0016] The above technical solution has the following advantages or beneficial effects: In response to the problem in the prior art that the server baseboard management controller chip will cause memory data loss and transmission interruption when a reset operation occurs, this embodiment introduces a cache mechanism on the bus side. By caching the read and write data of the host computer and the internal processor, the data transmission during the reset process is maintained. At the same time, the reset host computer or internal processor is isolated to avoid the problem of memory data loss during the reset process, which affects the normal operation of the internal processor or host computer on the other side. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0018] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the architecture of the server baseboard management controller chip;

[0020] Figure 3 Schematic diagram of the architecture of a server baseboard management controller chip in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of step S1 in an embodiment of the present invention;

[0022] Figure 5 Schematic diagram of step S3 in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0027] The present invention includes: a reset isolation method for a server baseboard management controller chip, such as Figure 1 、 Figure 2 As shown, the baseboard management controller chip U4 includes an internal processor U7 and a bus U6. The baseboard management controller chip U4 is connected to the host computer U1 and the memory U9; the host computer U1 and the internal processor U7 read and write to the memory U9 through the bus U6 respectively; the reset isolation method includes: step S1: when the host computer or the internal processor reads and writes to the memory, the read and write data are first added to the cache, and then the read and write data are sent through the cache; step S2: the host computer or the internal processor is monitored, and when the host computer or the internal processor triggers a reset operation, go to step S3; step S3: maintain the read and write operations based on the cache, and isolate the memory reset instructions output to the memory by the host computer or the internal processor that is being reset.

[0028] Specifically, in response to the problem in the prior art that the server baseboard management controller chip will cause memory data loss and transmission interruption when a reset operation occurs, this embodiment introduces a cache mechanism on the bus side. By caching the read and write data of the host computer and the internal processor, the data transmission during the reset process is maintained. At the same time, the reset host computer or internal processor is isolated to avoid the problem of memory data loss during the reset process, which affects the normal operation of the internal processor or host computer on the other side.

[0029] Specifically, Figure 2 The figure shows a typical system architecture of a server baseboard management controller chip. In this system, the server baseboard management controller chip U4 has a built-in internal processor U7; the internal processor U7 is usually a central processing unit, which is used to run the specific operating system of the baseboard management controller chip U4, mainly used to realize the monitoring of various system resources in the server, that is, the host computer U1, as well as the triggering of scheduled tasks, data display and other functions.

[0030] The internal processor U7 is connected to the DDR controller U8 via the bus U6 built into the baseboard management controller chip U4. The DDR controller U8 is used to control external devices of the DDR protocol, such as the memory U9.

[0031] Memory U9 stores some data corresponding to the server's baseboard management controller chip U4, such as data corresponding to the server's operating status collected by relevant software. The baseboard management controller chip U4 reads and writes data in memory U9 via bus U6 and DDR controller U8.

[0032] The server baseboard management controller chip U4 also has a built-in display controller U5, which is used to provide a display for the host computer U1, such as monitoring data display. The host computer U1, as a server, needs to access the baseboard management controller chip U4, usually based on the PCIe bus.

[0033] Specifically, the host computer U1 first accesses the PCIe host U2 through the PCIe bus, and then the PCIe host U2 interacts with the PCIe slave U3 in the server baseboard management controller chip U4 to build a data channel, so that the host computer U1 can access the display controller U5 through the PCIe slave U3 and perform read and write operations on the video memory data.

[0034] Among them, the video memory data is stored in the memory U9, and the display controller U5 is connected to the DDR controller U8 through the bus U6 according to the read and write requirements of the host computer U1, thereby performing read and write operations on the data in the memory U9 through the bus U6, DDR controller U8, and the channel to the memory U9.

[0035] Normally, the host computer U1 and the internal processor U7 work together to read and write data. The memory U9 stores data from both sides and performs parallel read and write operations.

[0036] When the host computer U1 or the internal processor U7 performs a reset operation, for a single-sided branch, it is usually the host computer U1 or the internal processor U7 that performs the reset and issues a memory reset instruction. The memory reset instruction is sent to the DDR controller U8 via the bus U6, and the memory U9 is reset by the DDR controller U8.

[0037] However, when the host computer U1 and internal processor U7 on both sides operate in parallel, it is easy to see that when the DDR controller U8 performs a memory reset operation on the memory U9, the memory reset action may cause the loss of other data stored in the memory U9, that is, the data that the host computer U1 or internal processor U7 on the other side needs to read or write. If the memory is not reset, the data read and write operations originally performed by the host computer U1 or internal processor U7 being reset will be interrupted.

[0038] To address the above issues, the technical means adopted in this solution include: Figure 3 As shown, on one side of the bus U6, a virtual logic controller is introduced mainly between the display controller U5 and the bus U6, and between the internal processor U7 and the bus U6. The virtual logic controller is used to provide virtualized read and write operation logic for the display controller U5 and the internal processor U7.

[0039] Specifically, it will be manifested as a combination of a cache and a monitor. The monitor is used to monitor the read and write operations issued by the display controller U5 and the internal processor U7, and forward the same read and write operations and read and write data to the bus U6. The subsequent interaction logic between the bus U6, DDR controller U8 and the memory is the same as when the virtual logic controller is not added.

[0040] However, when the memory U9 returns the corresponding read and write data through the bus U6, this part of the read and write data will be added to a cache in the virtual logic controller, and then forwarded to the display controller U5 and the internal processor U7 for subsequent operations.

[0041] In addition, when the host computer U1 and the internal processor U7 trigger the corresponding reset operation and issue a memory reset instruction, the instruction will be isolated by the virtual logic controller after being monitored by the virtual logic controller, and the corresponding process of the virtualized memory reset operation will be provided, but it will not be actually forwarded to the bus U6.

[0042] This step can effectively isolate the branch being reset, avoiding the problem of resetting memory U9 affecting the reading and writing of the other side, ensuring that data transmission is not interrupted during the reset process and the system can run stably.

[0043] Based on the above architectural adjustments, during actual control, when the host computer or internal processor reads and writes the memory, the read and write data will first be added to the cache, and then the read and write data will be sent through the cache. This step is performed in parallel on the host computers or internal processors on both sides.

[0044] At the same time, the host computer or internal processor is monitored to determine whether a reset operation is triggered. This step does not affect the corresponding read and write operations. Only when the reset operation is triggered, the memory reset instructions output to the memory by the host computer or internal processor being reset are isolated, and the corresponding read and write operations are continued based on the cache.

[0045] In one embodiment, Figure 4 As shown, step S1 includes: step S11: reading and identifying the operation instruction of the host computer or internal processor input bus, and turning to step S12 when it is determined to be a read-write instruction; step S12: when the read-write instruction is a read operation, obtaining read data from the memory and writing it into the cache, and, when the read-write instruction is a write operation, writing the write data into the cache in sequence; step S13: transmitting the read data from the cache to the host computer or internal processor in sequence according to the read-write order, or, writing the write data into the memory in sequence according to the read-write order.

[0046] Specifically, in order to replace the original operation logic, in this embodiment, the operation instructions of the host computer or internal processor input bus are first read and judged. When it is determined to be a read or write instruction, the instruction is further judged to be a read instruction or a write instruction.

[0047] When the read / write instruction is a read operation, the read data is retrieved from the memory and written to the cache. During the read process, the data at the corresponding address in the memory is first obtained through the DDR controller and bus. For each group of data entries, it is stored in the cache in sequence and the corresponding cache index is established. The data in the cache is then sent to the corresponding host computer display controller or internal processor in a first-in, first-out order.

[0048] When the read / write instruction is a write operation, the write data is obtained from the display controller or internal processor of the host computer and written into the cache. During the write process, each set of data entries is stored in the cache in sequence and a corresponding cache index is established. The data in the cache is then forwarded to the DDR controller via the bus in a first-in, first-out order and then written into the memory.

[0049] It should be noted that the above execution subject is executed by the virtual logic controller. When the host computer and the internal processor perform read and write operations at the same time, the virtual logic controllers on both sides perform independent parallel operations respectively.

[0050] In one embodiment, when executing step S12, a monitor is also created, and the monitor is used to monitor the internal processor or the host computer in step S2.

[0051] Specifically, to achieve effective monitoring of read and write operations of the internal processor or host computer, in this embodiment, each time a corresponding read and write operation is triggered, a monitor is configured for the read and write operation to achieve monitoring of the internal processor or host computer.

[0052] In one embodiment, in step S12, when a read or write instruction is executed, a corresponding cache index is constructed for the read data or the write data; in step S13, a first-in-first-out operation is performed according to the cache index.

[0053] Specifically, to achieve better control over the read and write processes, this embodiment builds a corresponding cache index for each triggered read or write instruction, respectively, for the read or write data. The cache index is created based on the data entry and refreshed in real time based on the data emitted from the cache. When the cache is emitted, a first-in, first-out operation is performed based on the cache index.

[0054] When the read / write instruction is a read operation, the read data is retrieved from the memory and written to the cache. During the read process, the data at the corresponding address in the memory is first obtained through the DDR controller and bus. For each group of data entries, it is stored in the cache in sequence and the corresponding cache index is established. The data in the cache is then sent to the corresponding host computer display controller or internal processor in a first-in, first-out order.

[0055] When the read / write instruction is a write operation, the write data is obtained from the display controller or internal processor of the host computer and written into the cache. During the write process, each set of data entries is stored in the cache in sequence and a corresponding cache index is established. The data in the cache is then forwarded to the DDR controller via the bus in a first-in, first-out order and then written into the memory.

[0056] In one embodiment, step S2 includes: collecting, through a monitor, operation instructions issued by an internal processor or a host computer to the bus, and determining whether a reset operation occurs.

[0057] Specifically, in order to achieve effective monitoring of the read and write operations of the internal processor or the host computer, in this embodiment, each time the corresponding read and write operation is triggered, a monitor is first configured for the read and write operation. The monitor is used to monitor the instructions issued by the internal processor or the host computer, and first judge the corresponding instructions to determine whether a reset operation occurs. If so, the instructions are isolated.

[0058] In one embodiment, Figure 5 As shown, step S3 includes: step S31: isolating the memory reset instruction and determining whether the currently executed operation is a read operation; if so, going to step S32; if not, going to step S33; step S32: waiting for the host computer or internal processor to complete the reset, and continuing to send read data to the host computer or internal processor in the read-write order; step S33: continuing to send write data to the memory in the read-write order, and continuing to write to the cache after the host computer or internal processor completes the reset.

[0059] Specifically, to avoid memory data loss caused by a reset operation, in this embodiment, when a memory reset instruction is detected, the memory reset instruction is first isolated, and then it is determined whether the currently executed operation is a read operation or a write operation.

[0060] For read operations, since the corresponding data content has been read from the memory in advance and stored in the cache, this part of the data is retained in the cache and the memory continues to send the corresponding read data to the cache until the DDR controller completes the sending.

[0061] Then, after waiting for the host computer or internal processor to complete the reset, it continues to send read data to the host computer or internal processor in the read and write order, and then processes the remaining data in the memory according to the relevant reset requirements, thereby completing the data transmission process.

[0062] For write operations, since the data to be sent by the host computer or internal processor has been written to the cache, the cache continues to write to the DDR controller in sequence according to the data entries in the cache after isolating the host computer or internal processor, thereby completing the memory write operation.

[0063] If there is data that has not been written before the reset, the data will continue to be written to the cache after the reset of the host computer or the internal processor is completed, and the subsequent memory writing process will continue.

[0064] In one embodiment, before executing step S32 or step S33, the following steps are also included: Step A31: In the cache, each piece of data for the read and write operations is marked separately, and a read and write timer is started for each transmission operation; Step A32: When the read and write timer times out, it is considered that the host computer or the internal processor is being reset.

[0065] Specifically, to achieve better transmission continuity, in this embodiment, when the isolation operation is triggered and the read and write operation process relying on the cache is entered, the operation mark is performed for each data for the read and write operation, and the read and write timer is started for each transmission operation.

[0066] The operation tag is used to record the corresponding node of the current read and write operation, and the read and write timer is used to determine whether the read and write operation is abnormal.

[0067] When the read / write timer times out, it indicates that an abnormality has occurred in the read / write operation, which is usually caused by an interruption caused by a reset operation.

[0068] Then, in executing step S32 or step S33, the interruption point is determined according to the operation mark, and the read and write data are resent to implement the process of breakpoint resume.

[0069] In one embodiment, the process of executing step S3 further includes: step A4: when the internal processor or host computer on the other side issues a read / write instruction, the bus operates the memory and obtains the read / write data.

[0070] Specifically, based on the above settings, since the read and write operations of the host computer and the internal processor are isolated by the virtual logic controller, a better parallel processing effect can be achieved. When the host computer or internal processor on one side is being reset, if the internal processor or host computer on the other side issues a read and write instruction, the bus can still operate on the memory and obtain the read and write data, and maintain the data from being lost.

[0071] A memory includes computer instructions. When a computer device runs the computer instructions, the reset isolation method is executed.

[0072] Those skilled in the art will appreciate that various aspects of the present invention, or possible implementations of various aspects, may be embodied as systems, methods, or computer program products. Thus, various aspects of the present invention, or possible implementations of various aspects, may take the form of complete hardware embodiments, complete software embodiments (including firmware, resident software, etc.), or embodiments combining software and hardware aspects, all collectively referred to herein as "circuits," "modules," or "systems." Furthermore, various aspects of the present invention, or possible implementations of various aspects, may take the form of computer program products, which refer to computer instructions stored in a memory.

[0073] The memory may be a computer-readable signal medium or a computer-readable storage medium. Computer-readable storage media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination thereof, such as random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, and portable read-only memory (CD-ROM).

[0074] The processor in the computer reads the computer instructions stored in the memory, so that the processor can perform the functional actions specified in each step or the combination of steps in the flowchart; and generate a device that implements the functional actions specified in each block or the combination of blocks in the block diagram.

[0075] It should be understood that the processor in the computer can be understood as one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components implemented to execute the aforementioned computer instructions.

[0076] Computer instructions can be executed entirely on the user's local computer, partially on the user's local computer, as a separate software package, partially on the user's local computer and partially on a remote computer, or entirely on a remote computer or server. It should also be noted that in certain alternative embodiments, the functions noted in each step of the flow chart or each block in the block diagram may not occur in the order noted in the figure. For example, depending on the functions involved, two steps or two blocks shown in succession may actually be executed approximately simultaneously, or the blocks may sometimes be executed in reverse order.

[0077] In practice, the various components in a computer system are coupled together via a bus system. It is understood that the bus system is used to enable communication between these components. In addition to the data bus, the bus system also includes a power bus, a control bus, and a status signal bus.

[0078] Although the present application includes many specific implementation details, these should not be interpreted as limiting the scope of any disclosure or the scope of protection claimed, but are mainly used to describe the features of the specific disclosed embodiments. Certain features described in multiple embodiments of the present application can also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment can also be implemented separately in multiple embodiments or implemented in any suitable sub-combination. In addition, although features can work in some combinations as described and even initially claim protection, one or more features from the claimed combination can be removed from the combination in some cases, and the claimed combination can point to a variation of a sub-combination or a sub-combination.

[0079] Similarly, although configurations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these configurations be performed in the particular order shown or sequentially, or that all illustrated configurations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0080] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A reset isolation method for a server baseboard management controller chip, wherein the baseboard management controller chip includes an internal processor and a bus, and the baseboard management controller chip is connected to a host computer and a memory; The host computer and the internal processor read and write the memory through the bus respectively; The host computer is connected to the display controller of the baseboard management controller chip; A virtual logic controller is provided between the display controller and the bus, and between the internal processor and the bus respectively; Characterized in that, the reset isolation method includes: Step S1: When the host computer or the internal processor reads or writes the memory, the read or write data is first added to the cache, and then the read or write data is sent via the cache; Step S2: monitoring the host computer or the internal processor, and turning to step S3 when the host computer or the internal processor triggers a reset operation; Step S3: maintaining read and write operations based on the cache, and isolating the memory reset instruction output by the host computer or the internal processor being reset to the memory; When the host computer and the internal processor perform read and write operations simultaneously, the virtual logic controllers on both sides perform independent parallel operations respectively; The isolation operation includes providing a corresponding process of a virtualized memory reset operation to the host computer or the internal processor that triggers the memory reset instruction, but not forwarding the memory reset instruction to the bus.

2. The reset isolation method according to claim 1, characterized in that: The step S1 comprises: Step S11: reading and identifying the operation instruction inputted into the bus by the host computer or the internal processor, and turning to step S12 when it is determined to be a read / write instruction; Step S12: when the read / write instruction is a read operation, obtaining read data from the memory and writing the data into the cache; and, when the read / write instruction is a write operation, writing the data into the cache in sequence; Step S13: transmitting the read data from the cache to the host computer or the internal processor in sequence according to the read and write order, or writing the write data into the memory in sequence according to the read and write order.

3. The reset isolation method according to claim 2, characterized in that: When executing step S12, a monitor is also created, and the monitor is used to monitor the internal processor or the host computer in step S2.

4. The reset isolation method according to claim 2, wherein: In step S12, when the read / write instruction is executed, a corresponding cache index is constructed for the read data or the write data; In step S13, a first-in-first-out operation is performed according to the cache index.

5. The reset isolation method according to claim 3, characterized in that: The step S2 comprises: The monitor collects the operation instructions issued by the internal processor or the host computer to the bus, and determines whether a reset operation occurs.

6. The reset isolation method according to claim 2, characterized in that: The step S3 comprises: Step S31: Isolate the memory reset instruction and determine whether the currently executed operation is a read operation; If yes, go to step S32; If not, go to step S33; Step S32: After waiting for the host computer or the internal processor to complete reset, continue to send the read data to the host computer or the internal processor according to the read and write sequence; Step S33: Continue to send the write data to the memory according to the read and write sequence, and continue to write to the cache after the host computer or the internal processor is reset.

7. The reset isolation method according to claim 6, characterized in that: Before executing step S32 or step S33, the method further includes: Step A31: in the cache, marking each piece of data to be read or written, and starting a read / write timer for each data transfer operation; Step A32: When the read / write timer times out, it is considered that the host computer or the internal processor is being reset.

8. The reset isolation method according to claim 7, characterized in that: In executing step S32 or step S33, an interruption point is determined according to the operation mark, and the read / write data is resent.

9. The reset isolation method according to claim 1, wherein: The process of executing step S3 further includes: Step A4: When the internal processor on the other side or the host computer issues a read / write instruction, the bus operates the memory and obtains the read / write data.

10. A memory comprising computer instructions, characterized in that When the computer device runs the computer instructions, the reset isolation method according to any one of claims 1 to 9 is executed.

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