Method and device for burning mirror image package by system-on-chip, chip and electronic equipment

Abstract

The embodiment of the invention provides a method and a device for burning a mirror image package by a system-on-chip, a chip and electronic equipment, the method comprises the following steps: N central processing units (CPUs), M CPUs in the N CPUs participate in burning work, M is less than or equal to N, and M is an integer greater than 1; the CPU is allocated with one or more of preset burning work, and the preset burning work at least comprises data receiving, data burning and data checking; a plurality of mirror image packets to be burnt, wherein each mirror image packet is a complete mirror image packet comprising complete mirror image data or partial data of a split complete mirror image packet; the burning method comprises the steps that in response to burning starting operation of an upper computer, a first CPU receives a first mirror image package from the upper computer; and under the condition that the first CPU is only allocated with the burning work of the received data, is also allocated with the burning work of the burning data or is also allocated with the burning work of the burning data and the verification data, executing the corresponding burning work.

Description

Technical Field

[0001] This application relates to the field of chips, and particularly to a method, device, chip, and electronic device for a system-on-chip to burn an image package. Background Art

[0002] In the field of microelectronics manufacturing technology, burning is a key process in the manufacturing of semiconductor devices. Burning refers to the process of burning data or programs into semiconductor devices, such as solid-state drives, flash memories, etc.

[0003] In the existing technology, the burning of a system-on-chip is usually responsible by a single core. Since a single core needs to wait for the previous step to complete before starting the next step, during this process, a large amount of data needs to be written into the semiconductor device, which results in a long time consumption for the entire burning process and limits the improvement of burning efficiency.

[0004] In order to improve the burning speed, the existing technology uses a faster burner or improves the design of the burner to increase its data transmission rate. However, the improvement of the burning speed is still very limited, which increases the production and debugging time consumption and is not conducive to industrial development. Summary of the Invention

[0005] In view of this, the embodiments of this application propose a method, device, chip, and electronic device for a system-on-chip to burn an image package to solve the following problems of the existing technology: The existing technology uses a faster burner or improves the design of the burner to increase its data transmission rate. However, the improvement of the burning speed is still very limited, which increases the production and debugging time consumption and is not conducive to industrial development.

[0006] On the one hand, an embodiment of the present application provides a method for burning an image package by a system-on-chip, including: N central processing units (CPUs), and M of the N CPUs participate in the burning work, where M is less than or equal to N and M is an integer greater than 1; the CPU is assigned one or more of the predetermined burning tasks, and the predetermined burning tasks at least include: receiving data, writing data, and verifying data; a plurality of image packages to be burned, each of the image packages being a complete image package including complete image data or partial data of the split complete image package; the burning method includes: in response to a burning start operation of the host computer, the first CPU receives a first image package from the host computer; in the case where the first CPU is only assigned the burning task of receiving data, in response to an operation of the first CPU feeding back a receiving result to the host computer, the second CPU performs a writing operation on the first image package saved to the first address; in the case where the writing operation is completed, the second CPU feeds back a writing result to the host computer; in response to an operation of the second CPU feeding back the writing result, the second CPU or the third CPU performs a verification operation on the first image package written to the second address; in the case where the verification operation is completed, the second CPU or the third CPU feeds back a verification result to the host computer; in the case where the first CPU is also assigned the burning task of writing data, in response to an operation of the first CPU feeding back a receiving result to the host computer, the first CPU performs a writing operation on the first image package saved to the first address; in the case where the writing operation is completed, the first CPU feeds back a writing result to the host computer; in response to an operation of the first CPU feeding back the writing result, the second CPU performs a verification operation on the first image package written to the second address; in the case where the verification operation is completed, the second CPU feeds back a verification result to the host computer; in the case where the first CPU is also assigned the burning tasks of writing data and verifying data, the second CPU receives a second image package from the host computer and feeds back a receiving result to the host computer after the reception is completed; the first CPU performs a writing operation and a verification operation on the first image package, and the second CPU performs a writing operation and a verification operation on the second image package.

[0007] In some embodiments, the first CPU performs a flashing operation and a verification operation on the first image package, including: in response to an operation of feeding back the reception result, the first CPU performs a flashing operation on the first image package saved to the first address; after the flashing operation is completed, the first CPU feeds back a flashing result to the host computer; in response to an operation of feeding back the flashing result, the first CPU performs a verification operation on the first image package flashed to the second address; after the verification operation is completed, the first CPU feeds back a verification result to the host computer.

[0008] In some embodiments, after the first CPU feeds back a verification result to the host computer after the verification operation is completed, it further includes: the first CPU obtains a third image package according to the reception time of each image package saved in the first address, so as to perform a flashing operation on the third image package.

[0009] In some embodiments, when the second CPU is only assigned the flashing work of the flashing data, after the second CPU feeds back a flashing result to the host computer after the flashing operation is completed, it further includes: the second CPU obtains a fourth image package according to the reception time of each image package saved by the first CPU in the first address, so as to perform a flashing operation on the fourth image package.

[0010] In some embodiments, when the first image package and the second image package are partial data of a split complete image package, the second CPU receives the second image package from the host computer, including: in response to an operation of the first CPU feeding back a reception result to the host computer, the second CPU receives the second image package from the host computer.

[0011] In some embodiments, when both the first image package and the second image package are the complete image package, the first CPU and the second CPU receive the image package from the host computer simultaneously.

[0012] In some embodiments, the second address is the address of an internal storage device of the system-on-chip or an external storage device of the system-on-chip.

[0013] On the other hand, an embodiment of the present application provides a system-on-chip device for burning an image package, including: N central processing units (CPUs), and M of the N CPUs participate in the burning work, where M is less than or equal to N and M is an integer greater than 1; the CPU is assigned one or more of the predetermined burning tasks, and the predetermined burning tasks at least include: receiving data, writing data, and verifying data; a plurality of image packages to be burned, each of the image packages being a complete image package including complete image data or partial data of the split complete image package; the burning device includes: a first execution module, configured to, in response to a burning start operation of the host computer, receive a first image package from the host computer through the first CPU; a second execution module, configured to, when the first CPU is only assigned the burning task of receiving data, in response to an operation of the first CPU feeding back a receiving result to the host computer, perform a writing operation on the first image package saved to the first address through the second CPU; in the case of completing the writing operation, feed back a writing result to the host computer through the second CPU; in response to an operation of the second CPU feeding back the writing result, perform a verification operation on the first image package written to the second address through the second CPU or the third CPU; in the case of completing the verification operation, feed back a verification result to the host computer through the second CPU or the third CPU; a third execution module, configured to, when the first CPU is also assigned the burning task of writing data, in response to an operation of the first CPU feeding back a receiving result to the host computer, perform a writing operation on the first image package saved to the first address through the first CPU; in the case of completing the writing operation, feed back a writing result to the host computer through the first CPU; in response to an operation of the first CPU feeding back the writing result, perform a verification operation on the first image package written to the second address through the second CPU; in the case of completing the verification operation, feed back a verification result to the host computer through the second CPU; a fourth execution module, configured to, when the first CPU is also assigned the burning tasks of writing data and verifying data, receive a second image package from the host computer through the second CPU, and feed back a receiving result to the host computer after receiving; perform a writing operation and a verification operation on the first image package through the first CPU, and perform a writing operation and a verification operation on the second image package through the second CPU.

[0014] On the other hand, an embodiment of the present application provides a chip storing a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0015] On the other hand, an embodiment of the present application provides an electronic device, which at least includes a memory and a processor. A computer program is stored on the memory, and when the processor executes the computer program on the memory, the steps of the above method are implemented.

[0016] The embodiment of the present application makes full use of the resources of the multi-core processor of the system-on-chip. Multiple CPUs in the system-on-chip participate in the programming work, and the programming efficiency is relatively high; each CPU can be configured to execute all the programming work, and then the programming work of each image package can be independently completed by each CPU respectively; different stages of programming work can also be assigned to the CPUs, and the CPUs assigned with different stages of programming work work serially to form a complete programming process. The embodiment of the present application can greatly improve the programming speed. Especially for the programming of large image packages with a large amount of data, it can be split and programmed by multiple CPUs in cooperation, and the programming speed is very fast. For the fields of microelectronics manufacturing process and semiconductor device manufacturing, making full use of the resources of the multi-core processor can greatly improve production efficiency and reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a flowchart of the method for programming an image package by the system-on-chip provided in the first embodiment of the present application;

[0019] Figure 2 It is a schematic diagram of the programming process provided in the first embodiment of the present application Figure 1 ;

[0020] Figure 3 It is a schematic diagram of the programming process provided in the first embodiment of the present application Figure 2 ;

[0021] Figure 4 It is a schematic diagram of the programming process provided in the first embodiment of the present application Figure 3 ;

[0022] Figure 5 It is a schematic diagram of the programming process provided in the first embodiment of the present application Figure 4 ;

[0023] Figure 6 It is a schematic structural diagram of the device for programming an image package by the system-on-chip provided in the second embodiment of the present application;

[0024] Figure 7Schematic diagram of the electronic device provided in the third embodiment of the present application. Detailed implementation manners

[0025] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the ordinary meanings understood by those of ordinary skill in the art to which the present application pertains. The "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0027] To keep the following description of the embodiments of the present application clear and concise, detailed descriptions of known functions and known components are omitted in the present application.

[0028] Program burning is a key operation, which is usually used to write data (such as program code and configuration information) into non-volatile storage devices so that program files can be read from the storage devices and executed when the chip starts up, and at the same time, relevant configuration information is processed. This process is crucial for various electronic devices, especially embedded systems and microcontrollers. The prior art uses a faster programmer or improves the design of the programmer to increase its data transfer rate. However, the improvement in burning speed is still very limited, increasing the production and debugging time, which is not conducive to industrial development.

[0029] To solve the problems in the prior art, the first embodiment of the present application provides a method for burning an image package by a system-on-chip, including: N central processing units (CPUs), and M of the N CPUs participate in the burning work, where M is less than or equal to N and M is an integer greater than 1; the CPUs are assigned one or more of the predetermined burning tasks, and the predetermined burning tasks at least include: receiving data, writing data, and verifying data; a plurality of image packages to be burned, each image package being a complete image package including complete image data or partial data of a split complete image package; the flow of the burning method is as Figure 1 shown, including steps S101 to S104:

[0030] S101, in response to the burning start operation of the host computer, the first CPU receives the first image package from the host computer.

[0031] In the embodiments of the present application, all N CPUs of the system-on-chip may participate in the burning work, or several CPUs among the N CPUs may be selected to participate in the burning work. The speed of multiple CPUs participating in the burning work is significantly higher than that of the existing method of a single CPU performing the burning work.

[0032] In the embodiments of the present application, the way of multiple CPUs participating in the burning work is very flexible. The burning work includes but is not limited to the three most basic burning processes of receiving data, writing data, and verifying data. The CPUs in the embodiments of the present application can be configured with only one burning task, or two burning tasks, or all of the above three burning tasks. The above three complete burning processes can be completed by one CPU, or two CPUs, or three CPUs. As long as the CPU is idle, it can make full use of the CPU to participate in the burning work, and the burning speed and efficiency can be maximized according to the actual needs of the system-on-chip. Those skilled in the art allocate CPUs to participate in the burning work according to the actual types of the burning work. The above three most basic burning tasks are only an example and do not limit the present application. For more types of burning work, the allocation method of the above three burning tasks can be referred to, and details are not described here.

[0033] S102, in the case where the first CPU is only assigned the burning task of receiving data, in response to the operation of the first CPU feeding back the receiving result to the host computer, the second CPU performs a writing operation on the first image package saved to the first address; in the case of completing the writing operation, the second CPU feeds back the writing result to the host computer; in response to the operation of the second CPU feeding back the writing result, the second CPU or the third CPU performs a verification operation on the first image package written to the second address; in the case of completing the verification operation, the second CPU or the third CPU feeds back the verification result to the host computer.

[0034] In this process, the second CPU may be assigned two types of programming tasks, namely, the programming tasks of writing data and verifying data, or the second CPU may only be assigned the programming task of writing data, while the third CPU performs the programming task of verifying data. This is not limited here.

[0035] In the case where the second CPU is only assigned the programming task of writing data, after the writing operation is completed and the second CPU feeds back the writing result to the host computer, the second CPU obtains the next fourth image package to be programmed according to the receiving time of each image package saved by the first CPU in the first address, so as to perform the writing operation on the fourth image package.

[0036] S103. In the case where the first CPU is also assigned the programming task of writing data, in response to the operation of the first CPU feeding back the receiving result to the host computer, the first CPU performs the writing operation on the first image package saved to the first address; after the writing operation is completed, the first CPU feeds back the writing result to the host computer; in response to the operation of the first CPU feeding back the writing result, the second CPU performs the verification operation on the first image package programmed to the second address; after the verification operation is completed, the second CPU feeds back the verification result to the host computer.

[0037] S104. In the case where the first CPU is also assigned the programming tasks of writing data and verifying data, the second CPU receives the second image package from the host computer and feeds back the receiving result to the host computer after the reception is completed; the first CPU performs the writing operation and the verification operation on the first image package, and the second CPU performs the writing operation and the verification operation on the second image package.

[0038] In the case where the first image package and the second image package are partial data of a split complete image package, preferably, after the first CPU feeds back the receiving result to the host computer, the second CPU receives the second image package from the host computer in response to the operation of the first CPU feeding back the receiving result to the host computer.

[0039] In the case where both the first image package and the second image package are complete image packages, the first CPU and the second CPU receive the image packages from the host computer simultaneously. However, the host computer needs to send one image package and then send the next one. Therefore, usually, the first image package is sent first and then the second image package is sent.

[0040] In specific implementation, the first CPU performs the burning operation and verification operation on the first image package in the same way as a single CPU performing all the burning work, that is, it includes the following processes: in response to the operation of feedback receiving result, the first CPU performs the burning operation on the first image package saved to the first address; in the case of completing the burning operation, the first CPU feeds back the burning result to the host computer; in response to the operation of feedback burning result, the first CPU performs the verification operation on the first image package burned to the second address; in the case of completing the verification operation, the first CPU feeds back the verification result to the host computer.

[0041] In the case of the first CPU completing the verification operation, the first CPU feeds back the verification result to the host computer. Subsequently, the first CPU can obtain the third image package according to the receiving time of each image package saved in the first address to perform the burning operation on the third image package.

[0042] Figure 2 Shows the process of the system-on-chip burning data serially using three CPUs (the three CPUs are only an example). In Figure 2 this case, CPU1, CPU2, and CPU3 respectively perform a burning task, thus forming a serial burning process. In this process, the system is initialized. After the system-on-chip is started, it interacts with the host computer and starts the burning program of the main core CPU1. The main core burning program starts the burning programs of other cores. The main core creates a main task and is responsible for interacting with the host computer. Other tasks are created on other cores according to whether they are blocked. For example, a task of burning data is created on the second core, and a task of reading back and verifying data is created on the third core. Because if these tasks are only processed on the same core, it is necessary to wait for the previous task to complete before the next task can be carried out, which greatly increases the time-consuming of burning. Through the multi-core serial burning method of the embodiments of the present application, the time-consuming of the burning process can be greatly reduced. Start the burning tool to start burning. During the burning process, each CPU will continuously perform its respective tasks, similar to the working mode of an assembly line operation, until all the image packages are burned.

[0043] As Figure 3 shown, during the serial burning process, CPU1 continuously receives the blocks to be burned (i.e., the image packages to be burned), CPU2 sequentially burns the image packages to the internal storage device according to the receiving time of the image packages received by CPU1, and CPU3 sequentially performs the verification operation on the burned image packages according to the burning time. The above-mentioned second address to which it is burned can be the address of the internal storage device of the system-on-chip or the external storage device of the system-on-chip. Figure 4 Shows a schematic diagram of burning the image package to the external storage device. The burning process is similar to Figure 3 this, and will not be elaborated here.

[0044] Figure 5The process of separately programming data for a system-on-chip using three CPUs is shown. As can be seen from the figure, each CPU can complete all the programming tasks, that is, receive data, write data, and verify data. Each CPU works independently and does not interact with other CPUs. During the entire programming process, after any one CPU completes the programming task, it is in an idle state, and the host computer can then issue the next programming task to this CPU. The independent participation of multiple CPUs in the programming work is not limited by CPU cooperation. If one CPU is blocked, it does not affect the work of other CPUs, and the programming efficiency is relatively high.

[0045] The embodiments of the present application make full use of the resources of the multi-core processor of the system-on-chip. Multiple CPUs in the system-on-chip participate in the programming work, and the programming efficiency is relatively high; each CPU can be configured to execute all the programming work, and thus the programming work of each image package can be independently completed by each CPU respectively; or different stages of the programming work can be assigned to the CPUs, and the CPUs assigned different stages of the programming work work serially to form a complete programming process. The embodiments of the present application can greatly improve the programming speed. Especially for the programming of large image packages with a large amount of data, they can be split and programmed by multiple CPUs in cooperation, and the programming speed is very fast. For the microelectronics manufacturing process and the semiconductor device manufacturing field, making full use of the resources of the multi-core processor can greatly improve production efficiency and reduce production costs.

[0046] The second embodiment of the present application provides a device for programming an image package for a system-on-chip, including:

[0047] N central processing units (CPUs), M of the N CPUs participate in the programming work, where M is less than or equal to N and M is an integer greater than 1; the CPUs are assigned one or more of the predetermined programming tasks, and the predetermined programming tasks at least include: receiving data, writing data, and verifying data; multiple image packages to be programmed, each image package being a complete image package including complete image data or a partial data of a split complete image package; the structural schematic diagram of the programming device is as Figure 6 shown, including:

[0048] The first execution module 10 is configured to receive a first image package from the host computer through the first CPU in response to a programming start operation of the host computer; the second execution module 20 is coupled to the first execution module 10 and is configured to, when the first CPU is only assigned the programming task of receiving data, in response to an operation of the first CPU feeding back a reception result to the host computer, execute a programming operation on the first image package saved at the first address through the second CPU; in the case of completing the programming operation, feed back a programming result to the host computer through the second CPU; in response to an operation of the second CPU feeding back the programming result, perform a verification operation on the first image package programmed to the second address through the second CPU or the third CPU; in the case of completing the verification operation, feed back a verification result to the host computer through the second CPU or the third CPU; the third execution module 30 is coupled to the first execution module 10 and is configured to, when the first CPU is also assigned the programming task of programming data, in response to an operation of the first CPU feeding back a reception result to the host computer, execute a programming operation on the first image package saved at the first address through the first CPU; in the case of completing the programming operation, feed back a programming result to the host computer through the first CPU; in response to an operation of the first CPU feeding back the programming result, perform a verification operation on the first image package programmed to the second address through the second CPU; in the case of completing the verification operation, feed back a verification result to the host computer through the second CPU; the fourth execution module 40 is coupled to the first execution module 10 and is configured to, when the first CPU is also assigned the programming tasks of programming data and verifying data, receive a second image package from the host computer through the second CPU, and feed back a reception result to the host computer after the reception is completed; execute a programming operation and a verification operation on the first image package through the first CPU, and execute a programming operation and a verification operation on the second image package through the second CPU.

[0049] In the system-on-chip according to the embodiment of the present application, N CPUs can all participate in the programming work, or several CPUs among the N CPUs can be selected to participate in the programming work. The programming speed with multiple CPUs participating in the programming work is significantly higher than the programming speed of the existing single CPU performing the programming work.

[0050] In the embodiments of the present application, the manner in which multiple CPUs participate in the programming work is very flexible. The programming work includes, but is not limited to, three most basic programming processes: receiving data, writing data, and verifying data. The CPU in the embodiments of the present application can be configured with only one programming work, or two programming works, or all of the above three programming works. All of the above three complete programming processes can be completed by one CPU, or two CPUs, or three CPUs. As long as there is idle CPU, it can be fully utilized to participate in the programming work, and the programming speed and efficiency can be maximized according to the actual needs of the system-on-chip. Those skilled in the art allocate CPUs to participate in the programming work according to the actual types of the programming work. The above three most basic programming works are only an example and do not limit the present application. For more types of programming work, the allocation method of the above three programming works can be referred to, which will not be elaborated here.

[0051] When the second execution module 20 is working, it can be that the second CPU is allocated two programming works, that is, the programming works of writing data and verifying data, or it can be that the second CPU is only allocated the programming work of writing data, and at the same time the third CPU executes the programming work of verifying data, which is not limited here.

[0052] In the case where the second CPU is only allocated the programming work of writing data, after the second CPU feeds back the writing result to the host computer after completing the writing operation, the second execution module 20 is further configured to obtain the fourth image packet according to the reception time of each image packet saved by the first CPU in the first address through the second CPU, so as to perform a writing operation on the fourth image packet.

[0053] In the case where the first image packet and the second image packet are partial data of a split complete image packet, preferably, after the first CPU feeds back the reception result to the host computer, the second CPU receives the second image packet from the host computer in response to the operation of the first CPU feeding back the reception result to the host computer.

[0054] In the case where both the first image packet and the second image packet are complete image packets, the first CPU and the second CPU receive the image packets from the host computer at the same time. However, the host computer needs to send one image packet and then send the next one. Therefore, usually, the first image packet is sent first and then the second image packet is sent.

[0055] In specific implementation, the first CPU performs the writing operation and verification operation on the first image package in the same manner as a single CPU performing all the burning operations, that is, when the fourth execution module 40 performs the writing operation and verification operation on the first image package through the first CPU, it is specifically used for: in response to the operation of receiving the feedback result, performing the writing operation on the first image package saved at the first address through the first CPU; in the case of completing the writing operation, feeding back the writing result to the host computer through the first CPU; in response to the operation of feeding back the writing result, performing the verification operation on the first image package written to the second address through the first CPU; in the case of completing the verification operation, feeding back the verification result to the host computer through the first CPU.

[0056] In the case of completing the verification operation, after the first execution module 10 feeds back the verification result to the host computer through the first CPU, it is further used to obtain the third image package through the first CPU according to the receiving time of each image package saved in the first address, so as to perform the writing operation on the third image package.

[0057] The above-mentioned second address written to can be the address of the internal storage device or the external storage device of the system-on-chip, and the embodiments of the present application do not make any limitations.

[0058] The embodiments of the present application make full use of the resources of the multi-core processor of the system-on-chip. Multiple CPUs in the system-on-chip participate in the burning work, and the burning efficiency is relatively high; each CPU can be configured to perform all the burning work, and thus the burning work of each image package can be independently completed by each CPU respectively; or different stages of the burning work can be allocated to the CPUs, and the CPUs allocated with different stages of the burning work work serially to form a complete burning process. The embodiments of the present application can greatly improve the burning speed. Especially for the burning of large image packages with a large amount of data, they can be split and burned by multiple CPUs in cooperation, and the burning speed is very fast. For the microelectronics manufacturing process and the semiconductor device manufacturing field, making full use of the resources of the multi-core processor can greatly improve the production efficiency and reduce the production cost.

[0059] The third embodiment of the present application provides a chip, which is a system-on-chip storing a computer program. The system-on-chip includes N central processing units (CPUs), and M of the N CPUs participate in the burning work, where M is less than or equal to N and M is an integer greater than 1; the CPU is allocated one or more of the predetermined burning work, and the predetermined burning work at least includes: receiving data, writing data, and verifying data; multiple image packages to be burned, and each image package is a complete image package including complete image data or partial data of a split complete image package; when the computer program is executed by the processor, it implements the method provided in any embodiment of the present application, including the following steps S11 to S14:

[0060] S11. In response to the programming start operation of the host computer, the first CPU receives a first image package from the host computer;

[0061] S12. When the first CPU is only assigned the programming task of receiving data, in response to the operation of the first CPU feeding back the reception result to the host computer, the second CPU performs a writing operation on the first image package saved at the first address; after the writing operation is completed, the second CPU feeds back the writing result to the host computer; in response to the operation of the second CPU feeding back the writing result, the second CPU or the third CPU performs a verification operation on the first image package written to the second address; after the verification operation is completed, the second CPU or the third CPU feeds back the verification result to the host computer;

[0062] S13. When the first CPU is also assigned the programming task of writing data, in response to the operation of the first CPU feeding back the reception result to the host computer, the first CPU performs a writing operation on the first image package saved at the first address; after the writing operation is completed, the first CPU feeds back the writing result to the host computer; in response to the operation of the first CPU feeding back the writing result, the second CPU performs a verification operation on the first image package written to the second address; after the verification operation is completed, the second CPU feeds back the verification result to the host computer;

[0063] S14. When the first CPU is also assigned the programming tasks of writing data and verifying data, the second CPU receives a second image package from the host computer and feeds back the reception result to the host computer after the reception is completed; the first CPU performs a writing operation and a verification operation on the first image package, and the second CPU performs a writing operation and a verification operation on the second image package.

[0064] When the computer program is executed by the processor and the first CPU performs a writing operation and a verification operation on the first image package, the processor specifically executes the following steps: in response to the operation of feeding back the reception result, the first CPU performs a writing operation on the first image package saved at the first address; after the writing operation is completed, the first CPU feeds back the writing result to the host computer; in response to the operation of feeding back the writing result, the first CPU performs a verification operation on the first image package written to the second address; after the verification operation is completed, the first CPU feeds back the verification result to the host computer.

[0065] After the computer program is executed by the processor and the first CPU feeds back the verification result to the host computer after the verification operation is completed, the processor further executes the following steps: the first CPU obtains a third image package according to the reception time of each image package saved in the first address to perform a writing operation on the third image package.

[0066] In the case where the second CPU is only assigned the programming work of programming data, after the programming operation is completed and the second CPU feeds back the programming result to the host computer, the following steps are further executed by the processor: The second CPU obtains the fourth image package according to the reception time of each image package saved by the first CPU in the first address, so as to perform a programming operation on the fourth image package.

[0067] In the case where the first image package and the second image package are partial data of a split complete image package, when the computer program is executed by the processor and the second CPU receives the second image package from the host computer, the following steps are specifically executed by the processor: In response to the operation of the first CPU feeding back the reception result to the host computer, the second CPU receives the second image package from the host computer.

[0068] In the case where both the first image package and the second image package are complete image packages, the first CPU and the second CPU receive the image packages from the host computer simultaneously.

[0069] The above second address is the address of an internal storage device of the system-on-chip or an external storage device of the system-on-chip.

[0070] The embodiments of the present application make full use of the resources of the multi-core processor of the system-on-chip. Multiple CPUs in the system-on-chip participate in the programming work, and the programming efficiency is relatively high; each CPU can be configured to execute all the programming work, and then the programming work of each image package can be independently completed by each CPU respectively; different stages of the programming work can also be assigned to the CPUs, and the CPUs assigned different stages of the programming work work serially to form a complete programming process. The embodiments of the present application can greatly improve the programming speed. Especially for the programming of large image packages with a large amount of data, they can be split and programmed by multiple CPUs in cooperation, and the programming speed is very fast. For the microelectronics manufacturing process and the semiconductor device manufacturing field, making full use of the resources of the multi-core processor can greatly improve the production efficiency and reduce the production cost.

[0071] Optionally, in this embodiment, the above computer program product may include, but is not limited to: various media that can store program codes such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), external hard drives, magnetic disks, or optical discs. Optionally, in this embodiment, the processor executes the method steps described in the above embodiment according to the program codes stored in the computer program product. Optionally, for the specific examples in this embodiment, reference may be made to the examples described in the above embodiment and the optional implementation manners, and details are not described herein again. Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a sequence different from that here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0072] The fourth embodiment of the present application provides an electronic device. The structural schematic diagram of the computer device may be as Figure 7 shown, and at least includes a memory 901 and a processor 902. A computer program is stored on the memory 901, and the processor 902 implements the method provided in any embodiment of the present application when executing the computer program on the memory 901. Exemplarily, the system-on-chip includes N central processing units (CPUs), and M of the N CPUs participate in the burning operation, where M is less than or equal to N and M is an integer greater than 1; the CPUs are assigned one or more of the predetermined burning operations, and the predetermined burning operations at least include: receiving data, writing data, and verifying data; multiple mirror packages to be burned, and each mirror package is a complete mirror package including complete mirror data or partial data of a split complete mirror package; the computer program steps of the computer device are as follows S21 to S24:

[0073] S21, in response to the burning start operation of the host computer, the first CPU receives the first mirror package from the host computer;

[0074] S22. When the first CPU is only assigned the burning task of receiving data, in response to the operation of the first CPU feeding back the reception result to the host computer, the second CPU performs a burning operation on the first image package saved to the first address; after the burning operation is completed, the second CPU feeds back the burning result to the host computer; in response to the operation of the second CPU feeding back the burning result, the second CPU or the third CPU performs a verification operation on the first image package burned to the second address; after the verification operation is completed, the second CPU or the third CPU feeds back the verification result to the host computer.

[0075] S23. When the first CPU is also assigned the burning task of burning data, in response to the operation of the first CPU feeding back the reception result to the host computer, the first CPU performs a burning operation on the first image package saved to the first address; after the burning operation is completed, the first CPU feeds back the burning result to the host computer; in response to the operation of the first CPU feeding back the burning result, the second CPU performs a verification operation on the first image package burned to the second address; after the verification operation is completed, the second CPU feeds back the verification result to the host computer.

[0076] S24. When the first CPU is also assigned the burning tasks of burning data and verifying data, the second CPU receives the second image package from the host computer and feeds back the reception result to the host computer after the reception is completed; the first CPU performs a burning operation and a verification operation on the first image package, and the second CPU performs a burning operation and a verification operation on the second image package.

[0077] When the processor executes the computer program in which the first CPU performs a burning operation and a verification operation on the first image package stored in the memory, it specifically executes the following computer program: in response to the operation of feeding back the reception result, the first CPU performs a burning operation on the first image package saved to the first address; after the burning operation is completed, the first CPU feeds back the burning result to the host computer; in response to the operation of feeding back the burning result, the first CPU performs a verification operation on the first image package burned to the second address; after the verification operation is completed, the first CPU feeds back the verification result to the host computer.

[0078] After the verification operation is completed, after the processor executes the computer program in which the first CPU feeds back the verification result to the host computer stored in the memory, it also executes the following computer program: the first CPU obtains the third image package according to the reception time of each image package saved in the first address to perform a burning operation on the third image package.

[0079] In the case where the second CPU is only assigned the programming work of programming data, after the programming operation is completed, after the processor executes the computer program in which the second CPU stored in the memory feeds back the programming result to the host computer, the following computer program is further executed: The second CPU obtains the fourth image package according to the reception time of each image package saved by the first CPU in the first address, so as to perform a programming operation on the fourth image package.

[0080] In the case where the first image package and the second image package are partial data of a split complete image package, when the processor executes the computer program in which the second CPU stored in the memory receives the second image package from the host computer, the following computer program is specifically executed: In response to the operation of the first CPU feeding back the reception result to the host computer, the second CPU receives the second image package from the host computer.

[0081] In the case where both the first image package and the second image package are complete image packages, the first CPU and the second CPU simultaneously receive the image package from the host computer.

[0082] The above second address is the address of the internal storage device of the system-on-chip or the external storage device of the system-on-chip.

[0083] The embodiments of the present application make full use of the resources of the multi-core processor of the system-on-chip. Multiple CPUs in the system-on-chip participate in the programming work, and the programming efficiency is relatively high; each CPU can be configured to execute all the programming work, and then the programming work of each image package can be independently completed by each CPU respectively; different stages of programming work can also be assigned to the CPU, and the CPUs assigned with different stages of programming work work serially to form a complete programming process. The embodiments of the present application can greatly improve the programming speed. Especially for the programming of large image packages with a large amount of data, they can be split and programmed by multiple CPUs in cooperation, and the programming speed is very fast. For the microelectronics manufacturing process and the semiconductor device manufacturing field, making full use of the resources of the multi-core processor can greatly improve the production efficiency and reduce the production cost.

[0084] In addition, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present application having equivalent elements, modifications, omissions, combinations (e.g., solutions that cross various embodiments), adaptations or changes. The elements in the claims will be broadly interpreted based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of the present application, and the examples will be interpreted as non-exclusive. Therefore, this specification and the examples are only to be considered as examples, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.

[0085] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. For example, those of ordinary skill in the art may use other embodiments when reading the above description. Additionally, in the above detailed description, various features may be grouped together to simplify the present application. This should not be construed as an intention that an unclaimed disclosed feature is necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description by way of example or illustration, where each claim stands on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the appended claims and the full scope of equivalents to which those claims are entitled.

[0086] The above has described in detail multiple embodiments of the present application, but the present application is not limited to these specific embodiments. Those skilled in the art, based on the concept of the present application, can make various variations and modifications to the embodiments, and these variations and modifications should all fall within the scope claimed by the present application.

Claims

1. A method for burning a mirror package of a system-level chip, characterized in that: include: N central processing units (CPUs), M of the N CPUs participate in the burning work, wherein M is less than or equal to N and is an integer greater than 1; the CPUs are assigned one or more of the predetermined burning work, and the predetermined burning work at least includes: receiving data, burning data, and verifying data; A plurality of image packages to be burned, each of which is a complete image package including complete image data or a partial data of a split complete image package; The burning method comprises: In response to the burning start operation of the host computer, the first CPU receives a first image packet from the host computer; In the case where the first CPU is only assigned the burning work of the received data, in response to the operation of the first CPU feeding back the receiving result to the host computer, the second CPU performs a burning operation on the first mirror package saved to the first address; when the burning operation is completed, the second CPU feeds back the burning result to the host computer; in response to the operation of the second CPU feeding back the burning result, the second CPU or the third CPU performs a verification operation on the first mirror package burned to the second address; when the verification operation is completed, the second CPU or the third CPU feeds back the verification result to the host computer; In the case where the first CPU is also assigned the burning work of the burning data, in response to the operation of the first CPU feeding back the receiving result to the host computer, the first CPU performs a burning operation on the first mirror package saved to the first address; in the case of completing the burning operation, the first CPU feeds back the burning result to the host computer; in response to the operation of the first CPU feeding back the burning result, the second CPU performs a verification operation on the first mirror package burned to the second address; in the case of completing the verification operation, the second CPU feeds back the verification result to the host computer; In the case where the first CPU is also assigned the burning work of the burning data and the verification data, the second CPU receives the second mirror package from the host computer and feeds back the receiving result to the host computer after the receiving is completed; the first CPU performs the burning operation and the verification operation on the first mirror package, and the second CPU performs the burning operation and the verification operation on the second mirror package.

2. The method according to claim 1, characterized in that The first CPU performs a burning operation and a verification operation on the first mirror package, including: In response to the operation of feeding back the receiving result, the first CPU performs a burning operation on the first mirror package saved to the first address; When the burning operation is completed, the first CPU feeds back the burning result to the host computer; In response to the operation of feeding back the programming result, the first CPU performs a verification operation on the first mirror package programmed to the second address; When the verification operation is completed, the first CPU feeds back the verification result to the host computer.

3. The method according to claim 2, characterized in that When the verification operation is completed, after the first CPU feeds back the verification result to the host computer, the method further includes: The first CPU obtains the third mirror package according to the receiving time of each mirror package stored in the first address, so as to perform a burning operation on the third mirror package.

4. The method according to claim 1, characterized in that In the case where the second CPU is only assigned to the burning work of burning data, after completing the burning operation, the second CPU feeds back the burning result to the host computer, and further includes: The second CPU obtains the fourth mirror package according to the reception time of each mirror package saved by the first CPU in the first address, so as to perform a burning operation on the fourth mirror package.

5. The method according to claim 1, characterized in that In the case where the first mirror package and the second mirror package are partial data of a split complete mirror package, the second CPU receives the second mirror package from the host computer, including: In response to the operation of the first CPU feeding back a reception result to the host computer, the second CPU receives the second mirror packet from the host computer.

6. The method according to claim 1, characterized in that In the case that both the first mirror package and the second mirror package are the complete mirror packages, the first CPU and the second CPU simultaneously receive the mirror package from the host computer.

7. The method according to any one of claims 1 to 6, characterized in that The second address is an address of a storage device inside the SoC or a storage device outside the SoC.

8. A system-on-chip image package burning device, characterized in that: include: N central processing units (CPUs), M of the N CPUs participate in the burning work, wherein M is less than or equal to N and is an integer greater than 1; the CPUs are assigned one or more of the predetermined burning work, and the predetermined burning work at least includes: receiving data, burning data, and verifying data; A plurality of image packages to be burned, each of which is a complete image package including complete image data or a partial data of a split complete image package; The burning device comprises: A first execution module, configured to respond to a burning start operation of the host computer and receive a first image packet from the host computer through a first CPU; A second execution module is used for, when the first CPU is only assigned the burning work of the received data, in response to the operation of the first CPU feeding back the receiving result to the host computer, performing a burning operation on the first mirror package saved to the first address through the second CPU; when the burning operation is completed, feeding back the burning result to the host computer through the second CPU; in response to the operation of the second CPU feeding back the burning result, performing a verification operation on the first mirror package burned to the second address through the second CPU or the third CPU; when the verification operation is completed, feeding back the verification result to the host computer through the second CPU or the third CPU; A third execution module is used for, when the first CPU is also assigned the burning work of the burning data, in response to the operation of the first CPU feeding back the receiving result to the host computer, performing a burning operation on the first mirror package saved to the first address through the first CPU; when the burning operation is completed, feeding back the burning result to the host computer through the first CPU; in response to the operation of the first CPU feeding back the burning result, performing a verification operation on the first mirror package burned to the second address through the second CPU; when the verification operation is completed, feeding back the verification result to the host computer through the second CPU; The fourth execution module is used to receive the second mirror package from the host computer through the second CPU when the first CPU is also assigned the burning work of the burning data and the verification data, and to feedback the receiving result to the host computer after the receiving is completed; perform the burning operation and the verification operation on the first mirror package through the first CPU, and perform the burning operation and the verification operation on the second mirror package through the second CPU.

9. A chip storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. An electronic device, comprising at least a memory and a processor, wherein a computer program is stored in the memory, wherein: The processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program on the memory.

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