Miniature display delay measuring equipment based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of measurement, and provides a miniature display delay measurement device based on an FPGA (Field Programmable Gate Array). The device is composed of an output module, a detection module and a processing module. The processing module comprises an operation and signal generation unit, the operation and signal generation unit can calculate the time difference of the electric signals, and the signal generation unit generates variable-frequency pulse electric signals. The detection module converts optical signals into electric signals and outputs the electric signals through noise reduction and filtering; the output module is responsible for converting electric signal formats and outputting image signals. During operation, one signal generated by the signal generation unit is output, and the other signal is transmitted to a first acquisition end of the arithmetic unit; signals generated by the detection module are transmitted to the second acquisition end, and the arithmetic unit calculates time difference and feeds back the time difference to the output module. In addition, the arithmetic unit can measure and calculate the extreme value and the mean value of the time difference for many times. The equipment adopts the high-integration FPGA chip, and the PCB is of a two-layer stacked structure, so that the equipment is small in size, low in cost and convenient to use, and has a wide market prospect.

Description

Technical Field

[0001] The invention relates to the field of measurement technology, in particular to the field of electronic measurement, and provides a micro display delay measurement device based on FPGA. Background Art

[0002] In today's gaming world, especially for players who are keen on FPS (first-person shooter), action and real-time strategy games, monitor latency has become a key factor affecting gaming performance. Low-latency monitors allow players to perceive screen changes faster in the game, so they can respond more promptly, significantly improving the gaming experience and competitive level. At the same time, in professional monitor evaluation work, monitor latency measurement is also an indispensable and important part, and accurate latency data is crucial for a comprehensive evaluation of monitor performance.

[0003] However, there are many problems with the existing monitor delay measuring instruments on the market. First, they are generally expensive, which makes it difficult for ordinary users, especially gamers, to measure the monitor delay independently due to cost factors. Second, the existing measuring instruments are large in size, inconvenient to carry and use daily, which limits their application scenarios. This situation leads to the fact that ordinary users often lack effective detection methods when facing monitor delay problems, and cannot timely understand the delay status of their own monitors, which in turn affects the gaming experience or lacks key data references when purchasing monitors.

[0004] In view of the above problems, an innovative solution is urgently needed to reduce the cost and size of display delay measurement equipment. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a micro display delay measurement device based on FPGA, aiming to solve the problems of high cost and large size of the existing display delay measurement device.

[0006] In order to achieve the above-mentioned object, the present invention provides a micro display delay measurement device based on FPGA, comprising: an output module, a detection module and a processing module;

[0007] The processing module includes a computing unit and a signal generating unit;

[0008] The signal generating unit is capable of generating a pulse electrical signal with a variable frequency;

[0009] The computing unit is provided with a first acquisition terminal and a second acquisition terminal, and can receive the electrical signals inputted through the first acquisition terminal and the second acquisition terminal, and calculate the time difference between the two groups of signals;

[0010] The output module is responsible for receiving electrical signals, converting them into a format suitable for the display device, and outputting image signals through a specific interface to ensure accurate transmission of image information to the display device;

[0011] The detection module is used to receive optical signals and output them in the form of electrical signals after processing;

[0012] The processing module uses a highly integrated FPGA chip to achieve high - efficiency signal processing and computing capabilities in a compact volume.

[0013] Furthermore, the arithmetic unit is also provided with a first feedback terminal;

[0014] The detection module includes a signal detection unit and a signal feedback unit;

[0015] The detection unit receives optical signals and converts them into electrical signals;

[0016] The signal feedback unit performs noise reduction and filtering processing on the input electrical signals and then outputs them.

[0017] Furthermore, the signal generation unit generates a pulsed electrical signal one with a variable frequency. While being output through the output module, it is sent to the first acquisition terminal;

[0018] The signal detection unit receives optical signals, converts them into electrical signals two, and then sends them to the second acquisition terminal through the signal feedback unit;

[0019] The arithmetic unit receives the electrical signal one input through the first acquisition terminal and the electrical signal two input through the second acquisition terminal, calculates the time difference between the two groups of electrical signals, and sends this time difference to the output module through the first feedback terminal.

[0020] Furthermore, the processing module also includes a storage unit;

[0021] The arithmetic unit is also provided with a second feedback terminal;

[0022] The arithmetic unit can measure the time difference between the electrical signal one and the electrical signal two multiple times within a set period and store the data in the storage unit through the second feedback terminal.

[0023] Furthermore, the arithmetic unit processes the data stored in the storage unit, obtains the maximum value, minimum value, and average value of the time difference, and then sends them to the output module through the first feedback terminal.

[0024] Furthermore, the signal generation unit uses the LVDS IO of the FPGA to simulate the output as an HDMI signal. The output image includes squares that flash at a fixed frequency for measuring latency and an area for displaying the final measurement result.

[0025] Further, the PCB of the device is designed as a two-layer stacked structure to reduce the product volume.

[0026] Further, it further includes a control module, which is electrically connected to the output module, the detection module and the processing module, and is used to control the start or stop of each module.

[0027] Further, the control module adopts the form of a physical button. After pressing the physical button, the signal generation unit outputs a flashing square at 10 Hz. The detection module receives the flashing signal and converts it into a level signal. The arithmetic unit calculates the time difference between the input and output levels and displays it through the output module.

[0028] Further, the control module further includes a self-closed loop unit. The input end of the self-closed loop unit is connected to the output module, and the output end is connected to the detection module; it is used to detect the internal delay of the device and provide calibration data.

[0029] By adopting a highly integrated FPGA chip and a two-layer stacked PCB structure, the present invention reduces the cost and the volume of the device, making it convenient to carry and use anytime and anywhere. The FPGA-based micro display delay measurement device provided by the present invention is extremely convenient to operate. The user only needs to press the physical button, and the device can automatically complete the measurement process. At the same time, the measurement result will be intuitively displayed in a specific area of the output image, without complex interpretation, and ordinary users can easily obtain the display delay data, effectively solving the problems of high price, large volume, complex operation and unintuitive results of existing measurement devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a schematic structural diagram of the FPGA-based micro display delay measurement device provided by the present invention;

[0032] Figure 2 It is a schematic diagram of the operation of the FPGA-based micro display delay measurement device provided by the present invention Figure 1 ;

[0033] Figure 3 It is a schematic diagram of the operation of the FPGA-based micro display delay measurement device provided by the present invention Figure 2 ;

[0034] Figure 4Schematic diagram of the operation of the FPGA-based micro display delay measurement device provided by the present invention Figure 3 。

[0035] Reference numerals:

[0036] 100. Output module, 200. Detection module, 210. Signal detection unit, 220. Signal feedback unit, 300. Processing module, 310. Arithmetic unit, 320. Signal generation unit, 330 Storage unit, 311. First acquisition end, 312. Second acquisition end, 313. First feedback end, 314, Second feedback end, 400. Control module, 410. Self-closed loop unit. Detailed implementation manners

[0037] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of this application.

[0038] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application. Therefore, they do not have any technical essence. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed in this application without affecting the effects that this application can produce and the purposes that can be achieved.

[0039] HDMI, full name High-Definition Multimedia Interface, is a high-definition multimedia interface.

[0040] USB, full name Universal Serial Bus, is a universal serial bus; it is a two-way serial interface standard for fast synchronous transmission, used to standardize the connection and communication between computers, mobile devices, etc. and external devices.

[0041] FPGA, full name Field-Programmable Gate Array, that is, a field-programmable gate array. It is an integrated circuit chip that contains a large number of programmable logic units, look-up tables (LUTs), flip-flops and programmable wiring resources. FPGA is used in the design of digital systems to standardize the implementation of internal logic functions and the interface connection with other external digital devices, and to implement the customized digital circuit system required by users.

[0042] LVDS, which stands for Low-Voltage Differential Signaling, is low-voltage differential signaling. It is a technical standard for electrical signal transmission. LVDS is mainly used to standardize the connection and signal transmission between high-speed data devices (such as displays) and signal sources, ensuring signal quality and transmission efficiency.

[0043] Example 1

[0044] The existing display delay measurement devices use complex and expensive hardware components and multi-layer circuit boards, which are costly and bulky. They are unaffordable for ordinary consumers and inconvenient to carry, with limited usage scenarios.

[0045] Refer to Figure 1 and Figure 2 As shown, this embodiment provides a micro display delay measurement device based on FPGA, including: an output module 100, a detection module 200, and a processing module 300;

[0046] The processing module 300 includes an arithmetic unit 310 and a signal generation unit 320;

[0047] The signal generation unit 320 is capable of generating pulsed electrical signals with variable frequencies;

[0048] The arithmetic unit 310 is provided with a first acquisition end 311 and a second acquisition end 312, which can receive the electrical signals input through the first acquisition end 311 and the second acquisition end 312, and calculate the time difference between the two groups of signals;

[0049] The output module 100 is responsible for receiving the electrical signal, converting it into a format suitable for the display device, and outputting the image signal through a specific interface to ensure the accurate transmission of image information to the display device;

[0050] The detection module 200 is used to receive the optical signal and output it in the form of an electrical signal after processing;

[0051] The processing module uses a highly integrated FPGA chip to achieve high-efficiency signal processing and computing capabilities in a compact volume.

[0052] It should be noted that in this embodiment, by utilizing the programmable logic function of the highly integrated FPGA chip, the production cost and space occupation are reduced. From the perspective of cost control, the highly integrated FPGA chip adopted by the processing module 300, with its powerful programmable logic function, can achieve complex signal processing and operation functions at a relatively low cost. This enables the device not to rely on a large number of complex and expensive hardware components as in the prior art, thus significantly reducing the production cost of the device. The FPGA-based micro display delay measurement device of this embodiment is only one-tenth of the price of products with the same parameters. In this way, ordinary consumers can easily afford the device price, greatly improving the market competitiveness and popularity of the product. In terms of volume, the highly integrated FPGA chip itself has the advantage of small size. This characteristic enables the device to be miniaturized while ensuring the integrity of functions, expanding the usage scenarios of the device, and meeting the needs of users for display delay measurement in different environments.

[0053] Embodiment 2

[0054] The results output by the display delay measurement device of the prior art are not intuitive enough, and users need to spend a lot of time and energy analyzing and interpreting them.

[0055] Refer to Figure 1 and Figure 2 As shown, this embodiment provides an FPGA-based micro display delay measurement device, including: an output module 100, a detection module 200, and a processing module 300;

[0056] The processing module 300 includes an arithmetic unit 310 and a signal generation unit 320;

[0057] The signal generation unit 320 can generate pulsed electrical signals with variable frequencies;

[0058] The arithmetic unit 310 is provided with a first acquisition end 311 and a second acquisition end 312, and can receive the electrical signals input through the first acquisition end 311 and the second acquisition end 312, and calculate the time difference between the two groups of signals;

[0059] The output module 100 is responsible for receiving the electrical signal, converting it into a format adapted to the display device, and outputting the image signal through a specific interface to ensure the accurate transmission of image information to the display device;

[0060] The detection module 200 is used to receive the optical signal and output it in the form of an electrical signal after processing;

[0061] The processing module adopts a highly integrated FPGA chip to achieve high-efficiency signal processing and operation capabilities with a compact volume.

[0062] The arithmetic unit 310 is further provided with a first feedback end 313;

[0063] The detection module 200 includes a signal detection unit 210 and a signal feedback unit 220;

[0064] The detection unit 210 receives an optical signal and converts it into an electrical signal;

[0065] The signal feedback unit 220 performs noise reduction and filtering processing on the input electrical signal and then outputs it.

[0066] The signal generation unit 320 generates a pulsed electrical signal one with a variable frequency. While outputting through the output module 100, it is sent to the first acquisition end 311;

[0067] After the signal detection unit 210 receives the optical signal and converts it into an electrical signal two, it is sent to the second acquisition end 312 through the signal feedback unit 220;

[0068] The operation unit 310 receives the electrical signal one input through the first acquisition end 311 and the electrical signal two input through the second acquisition end 312, calculates the time difference between the two sets of electrical signals, and sends the time difference to the output module 100 through the first feedback end 313.

[0069] The processing module 300 further includes a storage unit 330;

[0070] The operation unit 310 is further provided with a second feedback end 314;

[0071] The operation unit 310 can measure the time difference between the electrical signal one and the electrical signal two multiple times within a set period, and store the data in the storage unit 330 through the second feedback end 314.

[0072] The operation unit 310 processes the data stored in the storage unit 330, obtains the maximum value, minimum value and average value of the time difference, and then sends them to the output module 100 through the first feedback end 313.

[0073] The signal generation unit 320 uses the LVDS IO of the FPGA to simulate and output as an HDMI signal. The output image includes a square that flashes at a fixed frequency for measuring the delay and a region for displaying the final measurement result.

[0074] It should be noted that in this embodiment, when using the FPGA-based micro display delay measurement device of the present invention, first connect the device to the micro display to be tested through a video cable and ensure that the line is stable. The signal generation unit 320 generates a variable-frequency pulsed electrical signal 1. After the format of this signal is converted by the output module 100, an image with a fixed-frequency flicker is output on the micro display for measuring the delay. At the same time, another signal is transmitted to the first acquisition end 311 of the operation unit 310. The signal detection unit 210 of the detection module 200 receives the screen optical signal of the micro display and converts it into an electrical signal 2. After noise reduction and filtering processing by the signal feedback unit 220, it is transmitted to the second acquisition end 312 of the operation unit 310. The operation unit 310 calculates the time difference between the two groups of electrical signals based on this. Within a set period, the operation unit 310 repeats the measurement multiple times, stores the time difference data in the storage unit 330, and then processes these data to obtain the maximum value, minimum value, and average value, and then sends them to the output module 100 through the first feedback end 313. The output module 100 superimposes and displays these data in a dedicated area of the micro display, and the user can directly read the measurement result.

[0075] In the image output by the HDMI signal, the number of squares flickering at a fixed frequency is preferably 3, and the fixed frequency is preferably 1 flash per 100 ms. The detection module 200 is preferably a photodiode. In terms of signal processing and output, the signal generation unit 320 uses the LVDS IO of the FPGA to simulate the output of the HDMI signal, which can ensure the stability and high quality of the output signal. The output image not only contains squares flickering at a fixed frequency for measuring the delay, providing a reliable basis for accurate measurement, but also has a dedicated area for displaying the final measurement result, facilitating the user to directly obtain the data. With the high computing power of the FPGA chip, the processing module 300 can quickly and accurately calculate the signal time difference, greatly improving the measurement efficiency and reducing the user's waiting time.

[0076] The device of the present invention presents the measurement results in a clear and intuitive manner, enabling the user to obtain the key data of the display delay at a glance, thus providing convenient and powerful data support for display performance evaluation, game experience optimization, and display selection, etc.

[0077] Embodiment 3

[0078] The display delay measurement device of the prior art is large in size and inconvenient to carry, and its usage scenarios are limited.

[0079] Refer to Figure 1 and Figure 2 As shown, this embodiment provides an FPGA-based micro display delay measurement device, including: an output module 100, a detection module 200, and a processing module 300;

[0080] The processing module 300 includes an arithmetic unit 310 and a signal generation unit 320;

[0081] The signal generation unit 320 is capable of generating a pulsed electrical signal with a variable frequency;

[0082] The arithmetic unit 310 is provided with a first acquisition terminal 311 and a second acquisition terminal 312, which can receive the electrical signals input through the first acquisition terminal 311 and the second acquisition terminal 312, and calculate the time difference between the two groups of signals;

[0083] The output module 100 is responsible for receiving the electrical signal, converting it into a format adapted to the display device, and outputting the image signal through a specific interface to ensure the accurate transmission of the image information to the display device;

[0084] The detection module 200 is used to receive the optical signal and output it in the form of an electrical signal after processing;

[0085] The processing module uses a highly integrated FPGA chip to achieve efficient signal processing and computing capabilities with a compact volume.

[0086] The PCB of the device is designed as a two-layer stacked structure for reducing the product volume.

[0087] It should be noted that in this embodiment, due to the use of double-layer stacking, the volume of the circuit board is greatly reduced, directly driving a qualitative reduction in the volume of the entire device. The device becomes small and achieves miniaturization. The FPGA-based micro display delay measurement device of this embodiment has the entire device volume extremely compressed to within 2x2x2 cm. Compared with the existing large-sized display delay measurement instruments, this device can be easily placed in a pocket, backpack, etc. Whether it is carried for daily office work or moved between different e-sports competition venues, there is no burden. This further expands the usage scenarios of the device and meets the user's demand for display delay measurement in more environments.

[0088] Embodiment 4

[0089] The operation of the existing display delay measurement device is complex and the learning cost is relatively high.

[0090] Refer to Figure 1 and Figure 2 As shown, this embodiment provides an FPGA-based micro display delay measurement device, including: an output module 100, a detection module 200, and a processing module 300;

[0091] The processing module 300 includes an arithmetic unit 310 and a signal generation unit 320;

[0092] The signal generation unit 320 is capable of generating a pulsed electrical signal with a variable frequency;

[0093] The operation unit 310 is provided with a first acquisition end 311 and a second acquisition end 312, and can receive the electrical signals input through the first acquisition end 311 and the second acquisition end 312, and calculate the time difference between the two groups of signals;

[0094] The output module 100 is responsible for receiving the electrical signal, converting it into a format adapted to the display device, and outputting the image signal through a specific interface to ensure the accurate transmission of the image information to the display device;

[0095] The detection module 200 is used for receiving the optical signal and outputting it in the form of an electrical signal after processing;

[0096] The processing module adopts a highly integrated FPGA chip to achieve high-efficiency signal processing and operation capabilities with a compact volume.

[0097] Refer to Figure 1 and Figure 3 As shown, it further includes a control module 400. The control module 400 is electrically connected to the output module 100, the detection module 200 and the processing module 300, and is used to control the start or stop of each module.

[0098] The control module 400 is in the form of a physical button. After pressing the physical button, the signal generation unit 320 outputs a flashing square at 10 Hz. The detection module 200 receives the flashing signal and converts it into a level signal. The operation unit 310 calculates the time difference between the input and output levels and displays it through the output module 100.

[0099] It should be noted that in this embodiment, the operation of the device is extremely simple. Compared with the complex operation and high learning cost of the prior art, through the physical button design of the control module 400, the operation threshold is greatly reduced. The user only needs to press the physical button, and the device will start immediately. The signal generation unit 320 continuously outputs a flashing square at 10 Hz. The detection module 200 continuously receives the flashing signal and converts it into a level signal. The operation unit 310 continuously calculates the time difference between the input and output levels, and the output module 100 continuously and clearly displays the measurement results. By moving the device and aligning the detection module 200 with different positions of the flashing square on the screen and pressing the button, the display delay data of different screen positions can be obtained. No professional knowledge or complex operation is required throughout the process. Ordinary users, such as game players and office workers, can easily get started and continuously obtain the display delay data, effectively solving the problem of complex operation in the prior art and greatly improving the practicality of the device and the user experience.

[0100] Embodiment Five

[0101] The existing display delay measurement device cannot measure the delay generated by the device itself.

[0102] Refer toFigure 1 and Figure 2 As shown in Figure 2 , this embodiment provides a microdisplay delay measurement device based on FPGA, including: an output module 100, a detection module 200, and a processing module 300;

[0103] The processing module 300 includes an arithmetic unit 310 and a signal generation unit 320;

[0104] The signal generation unit 320 can generate a pulsed electrical signal with a variable frequency;

[0105] The arithmetic unit 310 is provided with a first acquisition end 311 and a second acquisition end 312, and can receive the electrical signals input through the first acquisition end 311 and the second acquisition end 312, and calculate the time difference between the two groups of signals;

[0106] The output module 100 is responsible for receiving the electrical signal, converting it into a format adapted to the display device, and outputting an image signal through a specific interface to ensure accurate transmission of the image information to the display device;

[0107] The detection module 200 is used to receive the optical signal and output it in the form of an electrical signal after processing;

[0108] The processing module uses a highly integrated FPGA chip to achieve high-efficiency signal processing and computing capabilities with a compact volume.

[0109] Refer to Figure 1 and Figure 3 As shown in Figure 3 , it further includes a control module 400, and the control module 400 is electrically connected to the output module 100, the detection module 200, and the processing module 300, and is used to control the start or stop of each module.

[0110] Refer to Figure 1 and Figure 4 As shown in Figure 4 , the control module 400 further includes a self-closed loop unit 410. The input end of the self-closed loop unit 410 is connected to the output module 100, and the output end is connected to the detection module 200; it is used to detect the internal delay of the device and provide calibration data.

[0111] It should be noted that in this embodiment, the self-closed loop inspection process is as follows: After the device is powered on, each module starts smoothly. At this time, the self-closed loop unit 410 is activated by the control module 400. Then, the output module 100 outputs according to the signal generated by the signal generating unit 320, and the signal reaches the detection module 200 through the self-closed loop unit 410. The signal processed by the detection module 200 and the original signal are respectively input to the two acquisition ends of the operation unit 310. The operation unit 310 accurately calculates the time difference between the two sets of signals, generates calibration data through multi-cycle measurement and statistical analysis, and stores it in the storage unit 330. This calibration data is specifically used to detect the internal delay of the device, and can be corrected accordingly when the delay measurement of the external display is performed later. It is worth emphasizing that the delay time of the self-closed loop unit 410 itself must be much smaller than the display delay time to ensure the accuracy of the measurement.

[0112] Compared with existing technologies, the significant advantage of this device is that it can accurately detect its own delay status and effectively correct the external display delay measurement results, greatly improving the accuracy of the measurement and providing users with highly reliable data.

[0113] The FPGA-based micro-display delay measurement device of the present invention, with the help of highly integrated FPGA chips, gets rid of expensive components, cooperates with double-layer PCB design, reduces costs and achieves miniaturization, is easy to carry and expands usage scenarios; uses FPGA to simulate HDMI signal output, combined with chip computing power, quickly and accurately calculates delays, and reduces waiting time; through physical buttons, the device automatically completes the measurement process, is easy to operate, does not require professional knowledge, and meets the needs of various users; clearly displays key time difference data in a specific area of ​​the display, and the measurement results are intuitive, helping users evaluate display performance, optimize gaming experience and purchase.

[0114] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A micro display delay measurement device based on FPGA, characterized in that: include: An output module (100), a detection module (200) and a processing module (300); The processing module (300) comprises a computing unit (310) and a signal generating unit (320); The signal generating unit (320) is capable of generating a pulse electrical signal with a variable frequency; The operation unit (310) is provided with a first acquisition terminal (311) and a second acquisition terminal (312), and can receive electrical signals input through the first acquisition terminal (311) and the second acquisition terminal (312), and calculate the time difference between the two groups of signals; The output module (100) is responsible for receiving the electrical signal, converting it into a format suitable for the display device, and outputting the image signal through a specific interface to ensure that the image information is accurately transmitted to the display device; The detection module (200) is used to receive the optical signal and output it in the form of an electrical signal after processing; The processing module (300) adopts a highly integrated FPGA chip to achieve efficient signal processing and computing capabilities in a compact size.

2. The FPGA-based microdisplay delay measurement device as claimed in claim 1, characterized in that: The operation unit (310) is also provided with a first feedback terminal (313); The detection module (200) comprises a signal detection unit (210) and a signal feedback unit (220); The detection unit (210) receives the optical signal and converts it into an electrical signal; The signal feedback unit (220) performs noise reduction and filtering processing on the input electrical signal and then outputs the signal.

3. The FPGA-based microdisplay delay measurement device as claimed in claim 2, characterized in that: The signal generating unit (320) generates a pulse electrical signal with a variable frequency, which is output through the output module (100) and sent to the first acquisition terminal (311); The signal detection unit (210) receives the optical signal, converts it into an electrical signal, and then sends it to the second collection end (312) via the signal feedback unit (220); The operation unit (310) receives an electrical signal 1 input via the first acquisition terminal (311) and an electrical signal 2 input via the second acquisition terminal (312), calculates a time difference between the two groups of electrical signals, and sends the time difference to the output module (100) via the first feedback terminal (313).

4. The FPGA-based microdisplay delay measurement device as claimed in claim 3, characterized in that: The processing module (300) further includes a storage unit (330); The operation unit (310) is also provided with a second feedback terminal (314); The operation unit (310) can measure the time difference between the first electrical signal and the second electrical signal multiple times within a set period, and store the data in the storage unit (330) through the second feedback terminal (314).

5. The FPGA-based microdisplay delay measurement device as claimed in claim 4, characterized in that: The operation unit (310) processes the data stored in the storage unit (330) to obtain the maximum value, minimum value and average value of the time difference, and then sends the data to the output module (100) via the first feedback terminal (313).

6. The FPGA-based microdisplay delay measurement device according to claim 1, characterized in that: The signal generating unit (320) uses the LVDS IO of the FPGA to simulate the HDMI signal output, and the output image includes a square flashing at a fixed frequency for measuring the delay and an area for displaying the final measurement result.

7. The FPGA-based microdisplay delay measurement device according to claim 1, characterized in that: The PCB design of the device is a two-layer stacked structure to reduce the product size.

8. The FPGA-based microdisplay delay measurement device according to any one of claims 1 to 7, characterized in that: It also includes a control module (400), which is electrically connected to the output module (100), the detection module (200) and the processing module (300) and is used to control each module to start or stop working.

9. The FPGA-based microdisplay delay measurement device as claimed in claim 8, characterized in that: The control module (400) is in the form of a physical key. When the physical key is pressed, the signal generating unit (320) outputs a 10 Hz flashing square. The detection module (200) receives the flashing signal and converts it into a level signal. The operation unit (310) calculates the input and output level time difference and displays it through the output module (100).

10. The FPGA-based microdisplay delay measurement device according to claim 8, characterized in that: The control module (400) further comprises a self-closed loop unit (410), the input end of the self-closed loop unit (410) being connected to the output module (100) and the output end being connected to the detection module (200); and being used for detecting internal delay of the device and providing calibration data.

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