Debugging device and method suitable for FPGA, terminal and storage medium

Abstract

The invention belongs to the technical field of electronic equipment debugging, and particularly relates to a debugging device and method suitable for an FPGA, a terminal and a storage medium, and the device comprises a to-be-tested data collection module which is arranged in the FPGA and is used for collecting to-be-tested data in the FPGA; the expansion module is arranged outside the FPGA, is connected to the to-be-tested data acquisition module through an optical port, and is used for receiving, analyzing, storing and processing acquired data from the to-be-tested data acquisition module; and the upper computer is connected to the expansion module through the Ethernet, and is used for setting trigger information of the to-be-tested data acquisition module, generating a waveform trigger message according to the set trigger information and issuing the waveform trigger message, and receiving and displaying the processed acquisition data transmitted by the expansion module. Through the design of the external expansion module, more data sets are dynamically collected under the condition that a large number of internal RAM resources of the FPGA are not occupied.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic device debugging, and particularly relates to a debugging device, method, terminal and storage medium applicable to FPGA. Background Art

[0002] FPGA (Field Programmable Gate Array), that is, Field Programmable Gate Array, is an integrated circuit with great flexibility and reconfigurability. Its unique programmable feature enables designers to configure it into a specific circuit structure according to actual requirements, thus avoiding the limitations of relying entirely on ASIC chips designed and manufactured by chip manufacturers. This feature of FPGA has been widely applied in many fields such as prototype verification, communication, automotive electronics, industrial control, aerospace, and data centers.

[0003] However, the debugging process of FPGA is a complex and crucial link. Traditional debugging means mainly rely on external logic analyzers or internal embedded logic analyzers. Although external logic analyzers have powerful functions, they are expensive and require a large number of FPGA pins, which is undoubtedly a heavy burden for FPGAs with limited pin resources. While internal embedded logic analyzers save pin resources, they occupy valuable RAM resources inside the FPGA, and the number of signals that can be analyzed and the dwell time are limited by the size of the internal RAM of the FPGA, and usually cannot meet complex debugging requirements.

[0004] In view of the above problems, finding a more efficient and adaptable FPGA debugging means has become an urgent need for developers. This debugging means not only needs to have sufficient signal capture and analysis capabilities, but also needs to minimize the occupation of FPGA resources to ensure the efficiency and accuracy of the debugging process. Summary of the Invention

[0005] Aiming at the defects in the prior art that external logic analyzers are expensive and require a large number of FPGA pins, while internal embedded logic analyzers save pin resources but occupy valuable RAM resources inside the FPGA, and the number of signals that can be analyzed and the dwell time are limited by the size of the internal RAM of the FPGA, and usually cannot meet complex debugging requirements, the present invention provides a debugging device, method, terminal and storage medium applicable to FPGA to solve the above technical problems.

[0006] In a first aspect, the present invention provides a debugging device applicable to FPGA, including: A to-be-tested data acquisition module, arranged inside the FPGA, for acquiring data to be tested inside the FPGA; An expansion module, which is set outside the FPGA and connected to the data acquisition module under test through an optical port, and is used to receive, parse, store, and process the acquisition data from the data acquisition module under test; A host computer, which is connected to the expansion module through Ethernet, is used to set the trigger information of the data acquisition module under test, generate and send a waveform trigger message according to the set trigger information, and is used to receive and display the processed acquisition data transmitted by the expansion module.

[0007] A further improvement of this technical solution is that the data acquisition module under test includes: A first optical port unit, which is used to communicate with the expansion module through an optical fiber; A first message parsing unit, which is used to receive and parse the waveform trigger message sent by the host computer; A data acquisition trigger unit, which is used to acquire target data from the unit under test in the FPGA according to the trigger information parsed by the first message parsing unit; A first data packing unit, which is used to pack the target data acquired by the data acquisition trigger unit according to a preset format and transmit it to the expansion module through the first optical port unit.

[0008] A further improvement of this technical solution is that the expansion module includes: A PL unit, which is used to parse the packed data from the data acquisition module under test and generate corresponding DDR addresses according to the parsed data; A double data rate synchronous dynamic random access memory DDR, which is set in the expansion module and is used to store the parsed data according to the DDR addresses generated by the PL unit; An AXI bus, which is used to download the waveform trigger message sent by the host computer and is used to upload the real-time parsed data or historical parsed data stored in the double data rate synchronous dynamic random access memory DDR according to the selection command sent by the host computer; A PS unit, which is used to convert the data format of the real-time parsed data or historical parsed data uploaded by the double data rate synchronous dynamic random access memory DDR and transmit the parsed data after data conversion to the host computer through Ethernet for display.

[0009] A further improvement of this technical solution is that the PL unit includes: A second optical port sub-unit, which is used to communicate with the data acquisition module under test through an optical fiber; A second message parsing sub-unit, which is used to parse the packed data from the data acquisition module under test; An address control sub-unit, which is used to generate corresponding DDR addresses according to the parsed data; A register control sub-unit, which is used to manage the read and write operations of the register according to the selection command sent by the host computer; A DDR controller, which is used to control the reading and writing of data parsed by a second message parsing unit from a double data rate synchronous dynamic random access memory (DDR) according to the DDR address generated by an address control subunit and the register read / write instruction generated by a register control subunit.

[0010] A further improvement of this technical solution is that the PS unit includes: A data format conversion subunit, which is used to convert the data parsed by the second message parsing unit read from the double data rate synchronous dynamic random access memory (DDR) into the VCD format; A second data packing subunit, which is used to pack the waveform trigger message from the host computer and to pack the VCD format data generated by the data format conversion subunit according to a preset format; A media access control (MAC), which is used to transmit the packed VCD format data to the host computer through Ethernet for display.

[0011] A further improvement of this technical solution is that the trigger information includes a trigger condition, a trigger type, trigger parameters, a collection target, and collection parameters.

[0012] A further improvement of this technical solution is that the collection parameters include a collection time, a sampling rate, and a data format.

[0013] In a second aspect, the present invention provides a debugging method applicable to an FPGA debugging device based on any one of the above, including: Setting the trigger information of a data acquisition module to be tested through a host computer, generating a waveform trigger message according to the set trigger information, and sending it down; The second data packing subunit of the expansion module packs the waveform trigger message sent down by the host computer and transmits it to the data acquisition module to be tested through an optical fiber; The first message parsing unit of the data acquisition module to be tested receives the waveform trigger message packed and sent down by the expansion module and parses it; The data acquisition trigger unit of the data acquisition module to be tested acquires target data from the unit to be tested in the FPGA according to the trigger information parsed by the first message parsing unit; The first data packing unit of the data acquisition module to be tested packs the target data acquired by the data acquisition trigger unit according to a preset format and transmits it to the expansion module through a first optical port unit; The second message parsing subunit of the expansion module parses the packed data from the data acquisition module to be tested; The address control subunit of the expansion module generates a corresponding DDR address according to the parsed data; The DDR controller of the expansion module controls the reading and writing of data from the double data rate synchronous dynamic random access memory (DDR) parsed by the second message parsing unit according to the DDR address generated by the address control subunit and the register read / write instruction generated by the register control subunit; and uploads the data parsed by the second message parsing unit read to the data format conversion subunit; The data format conversion subunit of the expansion module converts the data parsed by the second message parsing unit read from the double data rate synchronous dynamic random access memory (DDR) into the VCD format; The second data packing subunit of the expansion module packs the VCD format data generated by the data format conversion subunit according to a preset format, and transmits the packed VCD format data to the host computer for display via Ethernet through the media access control (MAC) of the expansion module.

[0014] Thirdly, a terminal is provided, including: A processor and a memory, wherein, The memory is used to store a computer program, The processor is used to call and run the computer program from the memory, so that the terminal executes the method of the above terminal.

[0015] Fourthly, a computer storage medium is provided. Instructions are stored in the computer-readable storage medium. When it runs on a computer, the computer is made to execute the methods described in the above aspects.

[0016] The beneficial effects of the present invention are as follows: Efficient resource utilization: Through the design of the external expansion module, the present invention realizes dynamically collecting more data sets without occupying a large amount of internal RAM resources of the FPGA. This greatly reduces the resource burden of the FPGA during the debugging process, enabling designers to focus more on circuit design and function verification.

[0017] Full signal visibility: The double data rate synchronous dynamic random access memory (DDR) in the expansion module provides a large-capacity external storage, capable of storing more waveform data. Combining the settings and trigger information of the host computer, the present invention realizes full signal capture and visibility of the device under test (DUT) inside the FPGA, overcoming the problem of limited signal visibility in traditional debugging means.

[0018] Flexible debugging ability: The debugging device of the present invention supports multiple trigger conditions and trigger types, which can be flexibly set according to the actual needs of designers. At the same time, through the Ethernet connection between the host computer and the expansion module, remote debugging and data transmission are realized, improving the debugging efficiency and convenience.

[0019] Data Format Conversion and Display: The data processing unit (PS unit) in the expansion module can convert the collected data into the VCD format and transmit it to the host computer via Ethernet for display. This not only facilitates the designers' analysis and processing of data but also improves the intuitiveness and readability of the debugging results.

[0020] In addition, the design principle of the present invention is reliable, the structure is simple, and it has a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic block diagram of the device according to an embodiment of the present invention.

[0023] Figure 2 It is a schematic flowchart of the method according to an embodiment of the present invention.

[0024] Figure 3 It is a schematic structural diagram of a terminal provided by an embodiment of the present invention.

[0025] 110 is the module for collecting data to be measured, 111 is the first optical port unit, 112 is the first packet parsing unit, 113 is the data collection trigger unit, 114 is the first data packing unit, 115 is the unit to be measured, 120 is the expansion module, 121 is the PL unit, 1211 is the second optical port sub-unit, 1212 is the second packet parsing sub-unit, 1213 is the address control sub-unit, 1214 is the register control sub-unit, 1215 is the DDR controller, 122 is the double data rate synchronous dynamic random access memory DDR, 123 is the AXI bus, 124 is the PS unit, 1241 is the data format conversion sub-unit, 1242 is the second data packing sub-unit, 1243 is the media access control MAC, and 130 is the host computer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] In order to make the objectives, features, and advantages of the present invention more obvious and understandable, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the specific embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in this patent, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this patent.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention.

[0028] The following explains the key terms that appear in the present invention.

[0029] PL, the full English name is Programmable Logic, and the Chinese meaning is programmable logic; it can be customized and is used to implement specific logic functions.

[0030] DDR, the full English name is Double Data Rate Synchronous Dynamic Random Access Memory, and the Chinese meaning is double data rate synchronous dynamic random access memory; DDR is developed on the basis of SDRAM (synchronous dynamic random access memory). It achieves a double data transfer rate by performing two data transfers within one clock cycle (i.e., transferring data once on both the rising edge and the falling edge of the clock). The frequency of DDR memory can be expressed in two ways: the working frequency and the equivalent frequency. The working frequency is the actual working frequency of the memory chip. However, since DDR memory can transfer data on both the rising and falling edges of the pulse, the equivalent frequency of data transfer is twice the working frequency.

[0031] AXI bus, the full English name is Advanced eXtensible Interface, and the Chinese meaning is advanced extensible interface; it is proposed by ARM Corporation and is a high-performance, high-bandwidth, low-latency on-chip bus that has been widely used in designs such as FPGA. The AXI bus supports a multi-Master and multi-Slave topology structure, has efficient data transfer capabilities and flexible configuration options, and can meet the requirements of various complex systems.

[0032] PS, the full English name is Processing System, and the Chinese meaning is processing system; it is the ARM's SOC (System on Chip) part that has nothing to do with FPGA. This part is usually packaged at the factory and includes hardware resources such as a processor and memory, and is used to execute tasks such as operating systems and application programs.

[0033] VCD, the full English name is Video Compact Disc, and the Chinese meaning is video compact disc, which can also be called audio and video optical disc. It is a standard for storing video information on an optical disc (Compact Disk) and can be played on a personal computer, a VCD player, and most DVD players.

[0034] MAC, the full English name is Media Access Control Address, and its Chinese meaning is Media Access Control Address, also known as the LAN address or physical address. Application scenario: In the field of computer networks, it is used to uniquely identify the location of network devices (such as network cards) in a local area network.

[0035] As Figure 1 As shown, the present invention provides a debugging device applicable to an FPGA, including a data acquisition module to be tested, an expansion module, and a host computer; among them, the data acquisition module to be tested is arranged inside the FPGA and is used to acquire the data to be tested inside the FPGA; the expansion module is arranged outside the FPGA and is connected to the data acquisition module to be tested through an optical port, and is used to receive, parse, store, and process the acquisition data from the data acquisition module to be tested; the host computer is connected to the expansion module through Ethernet, and is used to set the trigger information of the data acquisition module to be tested, generate a waveform trigger message according to the set trigger information and send it down, and is also used to receive and display the processed acquisition data transmitted by the expansion module.

[0036] During the FPGA debugging process, the accuracy and integrity of the trigger information are crucial for ensuring the correctness of the debugging results. Therefore, the trigger information in the present invention includes trigger conditions, trigger types, trigger parameters, acquisition targets, and acquisition parameters.

[0037] Among them, the acquisition parameters are parameters related to data acquisition, including acquisition time, sampling rate, data format, etc.; the acquisition target is the specific module or signal (unit to be tested) inside the FPGA that needs to be acquired or processed after triggering; the trigger parameters are specific parameters related to triggering, such as trigger delay, trigger window size, etc.; the trigger type is to determine whether the trigger is an edge trigger or a level trigger, and the edge trigger may include a rising edge trigger or a falling edge trigger; the trigger conditions include specific times, data changes, external signals, etc. For example, when a certain data value reaches a preset threshold, the acquisition is triggered. The debugging device of the present invention supports a variety of trigger conditions and trigger types, and can be flexibly set according to the actual needs of designers. At the same time, through the Ethernet connection between the host computer and the expansion module, remote debugging and data transmission are realized, improving the debugging efficiency and convenience.

[0038] Specifically, the data acquisition module to be measured includes a first optical port unit, a first packet parsing unit, a data acquisition trigger unit, and a first data packing unit. Among them, the first optical port unit is used to communicate with the expansion module through an optical fiber; the first packet parsing unit is used to receive and parse the waveform trigger packet sent by the host computer; the data acquisition trigger unit is used to collect target data from the unit to be tested in the FPGA according to the trigger information parsed by the first packet parsing unit; the first data packing unit is used to pack the target data collected by the data acquisition trigger unit according to a preset format and transmit it to the expansion module through the first optical port unit.

[0039] In addition, the expansion module includes a PL unit, a double data rate synchronous dynamic random access memory (DDR), an AXI bus, and a PS unit. Among them, the PL unit is used to parse the packed data from the data acquisition module to be measured and generate corresponding DDR addresses according to the parsed data; the double data rate synchronous dynamic random access memory (DDR) is provided in the expansion module and is used to store the parsed data according to the DDR addresses generated by the PL unit; the AXI bus is used to download the waveform trigger packet sent by the host computer and upload the real-time parsed data or historical parsed data stored in the double data rate synchronous dynamic random access memory (DDR) according to the selection command sent by the host computer; the PS unit is used to perform data format conversion on the real-time parsed data or historical parsed data uploaded by the double data rate synchronous dynamic random access memory (DDR) and transmit the parsed data after data conversion to the host computer through Ethernet for display. The double data rate synchronous dynamic random access memory (DDR) in the expansion module provides a large-capacity external storage and can store more waveform data. Combining the settings and trigger information of the host computer, the present invention realizes the full-signal capture and visibility of the unit to be tested (DUT) inside the FPGA, overcoming the problem of limited signal visibility in traditional debugging means.

[0040] Further, the PL unit includes a second optical port sub-unit, a second packet parsing sub-unit, an address control sub-unit, a register control sub-unit, and a DDR controller. Among them, the second optical port sub-unit is used to communicate with the data acquisition module to be measured through an optical fiber; the second packet parsing sub-unit is used to parse the packed data from the data acquisition module to be measured; the address control sub-unit is used to generate corresponding DDR addresses according to the parsed data; the register control sub-unit is used to manage the read and write operations of the register according to the selection command sent by the host computer; the DDR controller is used to control the double data rate synchronous dynamic random access memory (DDR) to read and write the data parsed by the second packet parsing sub-unit according to the DDR addresses generated by the address control sub-unit and the register read and write instructions generated by the register control sub-unit.

[0041] In addition, the PS unit includes a data format conversion subunit, a second data packing subunit, and a Media Access Control (MAC); among them, the data format conversion subunit is used to convert the data parsed by the second message parsing subunit read from the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) into the VCD format; the second data packing subunit is used to pack the waveform trigger message from the host computer and to pack the VCD format data generated by the data format conversion subunit according to a preset format; the Media Access Control (MAC) is used to transmit the packed VCD format data to the host computer through Ethernet for display. The data processing unit (PS unit) in the expansion module can convert the collected data into the VCD format and transmit it to the host computer through Ethernet for display. This not only facilitates the designers' analysis and processing of the data, but also improves the intuitiveness and readability of the debugging results.

[0042] As Figure 2 shown, the present invention provides a debugging method applicable to an FPGA debugging device based on any one of the above, including: Step 210, setting the trigger information of the data acquisition module to be tested through the host computer, generating a waveform trigger message according to the set trigger information, and sending it down; Step 220, the second data packing subunit of the expansion module packs the waveform trigger message sent down by the host computer and transmits it to the data acquisition module to be tested through an optical fiber; Step 230, the first message parsing unit of the data acquisition module to be tested receives the waveform trigger message packed and sent down by the expansion module and parses it; Step 240, the data acquisition trigger unit of the data acquisition module to be tested acquires target data from the unit to be tested in the FPGA according to the trigger information parsed by the first message parsing unit; Step 250, the first data packing unit of the data acquisition module to be tested packs the target data acquired by the data acquisition trigger unit according to a preset format and transmits it to the expansion module through the first optical port unit; Step 260, the second message parsing subunit of the expansion module parses the packed data from the data acquisition module to be tested; Step 270, the address control subunit of the expansion module generates corresponding DDR addresses according to the parsed data; the DDR controller of the expansion module controls the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) to read and write the data parsed by the second message parsing subunit according to the DDR addresses generated by the address control subunit and the register read / write instructions generated by the register control subunit; and uploads the data read from the data parsed by the second message parsing subunit to the data format conversion subunit; Step 280, the data format conversion subunit of the expansion module converts the data parsed by the second message parsing subunit read from the double data rate synchronous dynamic random access memory (DDR) into the VCD format; Step 290, the second data packing subunit of the expansion module packs the VCD format data generated by the data format conversion subunit according to a preset format, and transmits the packed VCD format data to the host computer for display via Ethernet through the media access control (MAC) of the expansion module.

[0043] Specifically, first, a data acquisition module to be tested as shown in Figure 1 is set inside the FPGA to be tested. The data acquisition module to be tested is connected to the unit to be tested through a data interface, and the executable file of the FPGA is downloaded into the FPGA to be tested. On the other hand, an expansion module based on MPSOC (Multi-Processors System-on-Chip) is designed outside the FPGA to be tested and connected to the host computer through a network port. During normal operation, the expansion module is connected to the FPGA to be tested through an optical port to achieve high-speed communication, and the host computer is connected to the expansion module through a network port for waveform acquisition and display.

[0044] When the entire device is running, first, the host computer sets the trigger information of the acquisition module, including the acquisition time, generates a trigger message with this information and sends it to the expansion module through the network port. The PS unit of the expansion module packs the trigger message through the message packing module and sends it to the PL unit through the AXI bus. The PL unit sends it to the data acquisition module to be tested in the FPGA to be tested through the optical port. On the one hand, this module parses the message and generates response data to return to the host computer. On the other hand, it selects the internal data of the unit to be tested that needs to be acquired and triggered according to the message data, packs this data according to a certain format, and transmits it to the expansion module through the optical port. The expansion module parses the data, and the address control subunit generates corresponding DDR addresses according to the differences in the data. Thus, the data is transmitted to the external large-capacity DDR through the DDR controller and performs the next operation according to the selection command issued by the host computer. If the selection command issued by the host computer is to display the acquired data waveform in real time, at this time, the DDR can be regarded as a FIFO with a huge depth. After storing less data, it is sent to the PS unit through the AXI bus. The PS unit converts the data into the VCD format through the data format conversion subunit, and sends the waveform file with the format changed to the host computer through the network port for real-time display; if the selection command issued by the host computer is to view the historical waveform, the viewing time needs to be set on the host computer, and all waveforms during this time period are stored in the external DDR, and then the data is transmitted from the PS unit to the host computer through the network port for display.

[0045] Through the design of an external expansion module, the present invention realizes the dynamic acquisition of more data sets without occupying a large amount of internal RAM resources of the FPGA. This greatly reduces the resource burden of the FPGA during the debugging process, enabling designers to focus more on circuit design and function verification.

[0046] Figure 3 FIG. 4 is a schematic structural diagram of a terminal 300 provided by an embodiment of the present invention, and the terminal 300 can be used to execute the FPGA debugging method provided by the embodiment of the present invention.

[0047] Among them, the terminal 300 may include: a processor 310, a memory 320, and a communication module 330. These components communicate through one or more buses. Those skilled in the art can understand that the structure of the server shown in the figure does not constitute a limitation to the present invention. It can be a bus structure, a star structure, and may also include more or fewer components than shown in the figure, or combine some components, or different component arrangements.

[0048] Among them, the memory 320 can be used to store the execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the terminal 300 can execute some or all of the steps in the above method embodiments.

[0049] The processor 310 is the control center of the storage terminal, connecting various parts of the entire electronic terminal through various interfaces and lines. By running or executing software programs and / or modules stored in the memory 320, and calling the data stored in the memory, it executes various functions and / or processes data of the electronic terminal. The processor may be composed of an integrated circuit (IC), for example, it may be composed of a single packaged IC, or may be composed of multiple packaged ICs with the same or different functions connected. For example, the processor 310 may only include a central processing unit (CPU). In the embodiment of the present invention, the CPU may be a single arithmetic core or may include multiple arithmetic cores.

[0050] The communication module 330 is used to establish a communication channel, so that the storage terminal can communicate with other terminals. Receive user data sent by other terminals or send user data to other terminals.

[0051] The present invention also provides a computer storage medium. The computer storage medium can store a program which, when executed, can include some or all of the steps in the various embodiments provided by the present invention. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), or the like.

[0052] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solutions in the embodiments of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program codes, and includes several instructions to enable a computer terminal (which can be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0053] For the same or similar parts among the various embodiments in this specification, reference can be made to each other. In particular, for the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference can be made to the descriptions in the method embodiments for the relevant parts.

[0054] In the several embodiments provided by the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the system embodiments described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there can be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling, direct coupling, or communication connection can be through some interfaces. The indirect coupling or communication connection of the system or module can be in an electrical, mechanical, or other form.

[0055] The modules described as separate components may or may not be physically separated. The components displayed as modules may or may not be physical modules, that is, they can be located in one place, or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0056] In addition, in each embodiment of the present invention, each functional module may be integrated into one processing module, may exist physically alone for each module, or two or more modules may be integrated into one module.

[0057] Although the present invention has been described in detail by referring to the accompanying drawings and in conjunction with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions should all be within the scope of the present invention / Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention.

Claims

1. A debugging device suitable for FPGA, characterized in that: include: The test data acquisition module is arranged inside the FPGA and is used to collect the test data inside the FPGA; The expansion module is arranged outside the FPGA and connected to the data acquisition module to be tested through an optical port, and is used for receiving, analyzing, storing and processing the collected data from the data acquisition module to be tested; The host computer is connected to the expansion module via Ethernet, and is used to set the trigger information of the data acquisition module to be tested, generate and send waveform trigger messages according to the set trigger information, and receive and display the processed acquisition data transmitted by the expansion module.

2. The debugging device suitable for FPGA according to claim 1, characterized in that: The data acquisition modules to be tested include: A first optical port unit, used for communicating with the extension module via an optical fiber; The first message parsing unit is used to receive and parse the waveform trigger message sent by the host computer; A data acquisition trigger unit, used to acquire target data from the unit to be tested in the FPGA according to the trigger information parsed by the first message parsing unit; The first data packaging unit is used to package the target data collected by the data collection trigger unit according to a preset format, and transmit the package to the expansion module through the first optical port unit.

3. The debugging device suitable for FPGA according to claim 2, characterized in that: Extension modules include: The PL unit is used to parse the packaged data from the data acquisition module to be tested and generate the corresponding DDR address according to the parsed data; Double rate synchronous dynamic random access memory DDR, located in the expansion module, is used to store parsed data according to the DDR address generated by the PL unit; AXI bus, used to download the waveform trigger message sent by the host computer, and to upload the real-time analysis data or historical analysis data stored in the double-rate synchronous dynamic random access memory DDR according to the selection command sent by the host computer; The PS unit is used to convert the data format of the real-time parsing data or historical parsing data uploaded by the double-rate synchronous dynamic random access memory DDR, and transmit the parsing data after the data conversion to the host computer through Ethernet for display.

4. The debugging device suitable for FPGA according to claim 3, characterized in that: The PL unit includes: The second optical port subunit is used to communicate with the data acquisition module to be tested through the optical fiber; The second message parsing subunit is used to parse the packaged data from the data acquisition module to be tested; An address control subunit, used to generate a corresponding DDR address according to the parsed data; The register control subunit is used to manage the read and write operations of the register according to the selection command issued by the host computer; The DDR controller is used to control the double rate synchronous dynamic random access memory DDR to read and write the data parsed by the second message parsing subunit according to the DDR address generated by the address control subunit and the register read and write instructions generated by the register control subunit.

5. The debugging device suitable for FPGA according to claim 4, characterized in that: The PS unit includes: A data format conversion subunit, used for converting the data parsed by the second message parsing subunit read from the double rate synchronous dynamic random access memory DDR into a VCD format; The second data packaging subunit is used to package the waveform trigger message from the host computer, and to package the VCD format data generated by the data format conversion subunit according to a preset format; Media access control MAC is used to transmit the packaged VCD format data to the host computer via Ethernet for display.

6. The debugging device suitable for FPGA according to claim 1, characterized in that: The trigger information includes trigger conditions, trigger types, trigger parameters, acquisition targets and acquisition parameters.

7. The debugging device suitable for FPGA according to claim 6, characterized in that: Acquisition parameters include acquisition time, sampling rate and data format.

8. A debugging method applicable to an FPGA debugging device based on any one of claims 1 to 7, characterized in that: include: The trigger information of the data acquisition module to be tested is set through the host computer, and a waveform trigger message is generated and sent according to the set trigger information; The second data packaging subunit of the extension module packages the waveform trigger message sent by the host computer and transmits it to the data acquisition module to be tested through the optical fiber; The first message parsing unit of the data acquisition module to be tested receives and parses the waveform trigger message packaged and sent by the extension module; The data acquisition trigger unit of the data acquisition module to be tested acquires target data from the unit to be tested in the FPGA according to the trigger information parsed by the first message parsing unit; The first data packaging unit of the data acquisition module to be tested packages the target data collected by the data acquisition trigger unit according to a preset format, and transmits it to the expansion module through the first optical port unit; The second message parsing subunit of the extension module parses the packaged data from the data acquisition module to be tested; The address control subunit of the expansion module generates a corresponding DDR address according to the parsed data; The DDR controller of the expansion module controls the double rate synchronous dynamic random access memory DDR to read and write the data parsed by the second message parsing subunit according to the DDR address generated by the address control subunit and the register read and write instruction generated by the register control subunit; and uploads the parsed data of the second message parsing subunit to the data format conversion subunit; The data format conversion subunit of the expansion module converts the data parsed by the second message parsing subunit read from the double rate synchronous dynamic random access memory DDR into a VCD format; The second data packaging subunit of the extension module packages the VCD format data generated by the data format conversion subunit according to a preset format, and transmits the packaged VCD format data to the host computer via Ethernet through the media access control MAC of the extension module for display.

9. A terminal, characterized in that: include: processor; A memory for storing execution instructions of the processor; Wherein, the processor is configured to execute the method of claim 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the program is executed by a processor, the method according to claim 8 is implemented.

Images